From d5b3ecc3ef646b0cdf72bfddc3745faac2042fef Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=89der=20Ferreira=20Zulian?= Date: Wed, 20 May 2015 13:02:11 +0200 Subject: [PATCH] Some about address mapping in README, but I'm still working on it. --- README.md | 191 ++-- docs/images/am_ddr4.svg | 1835 +++++++++++++++++++++++++++++++++++++ docs/images/am_wideio.svg | 1792 ++++++++++++++++++++++++++++++++++++ 3 files changed, 3721 insertions(+), 97 deletions(-) create mode 100644 docs/images/am_ddr4.svg create mode 100644 docs/images/am_wideio.svg diff --git a/README.md b/README.md index bac9ac77..61f094aa 100644 --- a/README.md +++ b/README.md @@ -3,7 +3,7 @@ de.uni-kl.ems.dram.vp.system Generic DRAM controller simulator and debug tools related to it. -# Basic Setup +## Basic Setup In a terminal window execute the commands that follow. @@ -21,31 +21,30 @@ $ mkdir projects Clone the repository. +``` +$ git clone --recursive https://@git.rhrk.uni-kl.de/EIT-Wehn/dram.vp.system.git +``` + +The *--recursive* flag tells git to initialize all submodules within the +repository. **DRAMPower** and **tinyxml** are examples third party +repositories that were embedded within the source tree as submodules. + It is possible that you will work with a **fork** of the official codebase. A fork is a copy of a repository. In that case, after pushing changes into your copy you should create a **pull request** in order to your supervisor check and possibly bring your changes to the official codebase. -In case of doubts about which repository you should clone ask your supervisor. - ``` -$ git clone https://@git.rhrk.uni-kl.de//dram.vp.system.git +$ git clone --recursive https://@git.rhrk.uni-kl.de//dram.vp.system.git ``` -Go to the project directory. +After cloning go to the project directory. ``` $ cd dram.vp.system ``` -Execute the script below. - -``` -$ ./install_prerequisites.sh -``` - - -## With QTCreator +### With QTCreator Execute the *QTCreator*. ``` @@ -64,7 +63,7 @@ Repeat the procedure above and build the trace analyser project. **File -> Open Project -> dram.vp.sys/analyser/analyser/traceAnalizer.pro** -## Without QTCreator +### Without QTCreator In case you prefer a command line interface to the QTCreator GUI you can also use **qmake** to generate a Makefile and then compile the project. @@ -83,116 +82,114 @@ The **dramSys** executable supports one argument which is a XML file that contains configurable aspects of the desired simulation. If no argument is passed through the command line a default configuration file will be loaded. -The XML code below shows a typical simulation configuration: +The XML code below shows a typic configuration: ``` - - - - - - - - - - - - - - - - - voco2.stl - - + + + + + + + + + + + + + Multiple address mappings + + + + + Multiple mem. configs + + + + + voco2.stl + + + ``` Some configuration fields reference other XML files which contain more -specialized chunks of the configuration, e.g. memory specification and address -mapping. +specialized chunks of the configuration like memory specification, address +mapping and memory configurations. The XML configuration files are parsed by the program and the configuration details extracted are assigned to the correspondent attributes of the internal configuration structure. - #### Configuration File Sections The main configuration file is divided into self-contained sections, each of these sections is a set of logically related configuration aspects for the simulation. -The list below, which is not intended to be exhaustive, present the -configuration sections and possible configuration fields. +Below are listed the configuration sections and configuration fields. -- Simulator configuration - - Database recording - - Power analysis - - Debug mode +- **Simulator configuration** + - *Debug* (boolean) + - "1": Enables debug output on console + - "0": Disables debug output + - *DatabaseRecording* (boolean) + - "1": Enables trace file recording for the trace analyser tool + - "0": Disables trace file recording + - *PowerAnalysis* (boolean) + - "1": Enables live power analysis with the DRAMPower tool + - "0": Disables power analysis -- Memory specification - - Memory ID: JEDEC_256Mb_WIDEIO_SDR-200_128bit, - MICRON_4Gb_DDR4-2400_8bit_A, ... - - Memory type: WIDEIO_SD, DDR4, ... +- **Memory specification** -- Memory Architecture Specification - - Width - - Number of Banks - - Number of Ranks - - Number of Columns - - Number of Rows - - Data Rate - - Burst Length + A file with memory specifications. Usually, this information comes from + datasheet and does not change. -- Memory Timing Specification (memory dependent) - - Clock in MHz - - RC - - RCD - - RL - - RP - - RFC - - RAS - - WL - - AL - - DQSCK - - RTP - - WR - - XP - - XPDLL - - XS - - XSDLL - - REFI - - CL - - TAW - - RRD - - CCD - - WTR - - CKE - - CKESR +- **Address Mapping** -- Memory Power Specification + XML files describe the address mapping to be used in the simulation. -- Address Mapping - - Length: address length in bits - - Row: bits used for the row - - Bank: bits used for the bank - - Column: bits used for the column + "dram/resources/configs/amconfigs/am_wideio.xml" + + ``` + + + + + + + + ``` -- Memory Configuration - - Bankwise Logic - - Open Page Policy - - Maximum Number of Transactions - - Scheduler - - Capacitor size - - Powerdown Mode - - Powerdown Timeout - - Chip seed - - CSV file - - Storage Mode value + ![WideIO Address Mapping Sample](docs/images/am_wideio.svg) + "dram/resources/configs/amconfigs/am_ddr4.xml" + + ``` + + + + + + + + + + + ``` + + ![DDR4 Address Mapping Sample](docs/images/am_ddr4.svg) + +- **Memory Configuration** + + Multiple mem. configs --> repeat for all... + +- **Trace setups** + + voco2.stl Some attributes are self-explanatory while others require some previous knowhow of memory technologies or some knowledge of the simulator source code. diff --git a/docs/images/am_ddr4.svg b/docs/images/am_ddr4.svg new file mode 100644 index 00000000..3d6ced5d --- /dev/null +++ b/docs/images/am_ddr4.svg @@ -0,0 +1,1835 @@ + + + +image/svg+xml + + + + + + + +R8 + +R7 + +R6 + +R5 + +R4 + +R3 + +R2 + +R1 + +R0 + + +C6 + +C5 + +C4 + +C3 + +C2 + +C1 + +C0 + +B2 + +B1 + +B0 + + + + + +R12 +R11 +R10 +R9 +C7 +C8 +C9 +B3 + \ No newline at end of file diff --git a/docs/images/am_wideio.svg b/docs/images/am_wideio.svg new file mode 100644 index 00000000..e22032a9 --- /dev/null +++ b/docs/images/am_wideio.svg @@ -0,0 +1,1792 @@ + + + +image/svg+xml + + + +R12 + +R11 + +R10 + +R9 + +R8 + +R7 + +R6 + +R5 + +R4 + +R3 + +R2 + +R1 + +R0 + +ch0 + +C6 + +C5 + +C4 + +C3 + +C2 + +C1 + +C0 + +B2 + +B1 + +B0 + +b3 + +b2 + +b1 + +b0 + +ch1 + \ No newline at end of file