From ff265a8a95a8b954c75550f9d5ed558b0b21aaff Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Wed, 19 May 2021 14:03:13 +0200 Subject: [PATCH 1/6] Trigger power down interruption outside of refresh manager. --- DRAMSys/library/src/controller/Controller.cpp | 23 ++--- .../powerdown/PowerDownManagerStaggered.cpp | 96 +++++++++---------- .../refresh/RefreshManagerAllBank.cpp | 96 ++++++++++--------- .../refresh/RefreshManagerPerBank.cpp | 83 ++++++++-------- .../refresh/RefreshManagerSameBank.cpp | 84 ++++++++-------- 5 files changed, 196 insertions(+), 186 deletions(-) diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index c9c93f05..b9092b81 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -261,20 +261,21 @@ void Controller::controllerMethod() commandTuple = powerDownManagers[rankID]->getNextCommand(); if (std::get(commandTuple) != Command::NOP) readyCommands.emplace_back(commandTuple); - else + + // (4.2) Check for refresh commands (PREA/PRE or REFA/REFB) + commandTuple = refreshManagers[rankID]->getNextCommand(); + if (std::get(commandTuple) != Command::NOP) { - // (4.2) Check for refresh commands (PREA/PRE or REFA/REFB) - commandTuple = refreshManagers[rankID]->getNextCommand(); + readyCommands.emplace_back(commandTuple); + powerDownManagers[rankID]->triggerInterruption(); + } + + // (4.3) Check for bank commands (PRE, ACT, RD/RDA or WR/WRA) + for (auto it : bankMachinesOnRank[rankID]) + { + commandTuple = it->getNextCommand(); if (std::get(commandTuple) != Command::NOP) readyCommands.emplace_back(commandTuple); - - // (4.3) Check for bank commands (PRE, ACT, RD/RDA or WR/WRA) - for (auto it : bankMachinesOnRank[rankID]) - { - commandTuple = it->getNextCommand(); - if (std::get(commandTuple) != Command::NOP) - readyCommands.emplace_back(commandTuple); - } } } diff --git a/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.cpp b/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.cpp index 13532fd0..4ae2a175 100644 --- a/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.cpp +++ b/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.cpp @@ -114,55 +114,55 @@ void PowerDownManagerStaggered::updateState(Command command) { switch (command) { - case Command::ACT: - activatedBanks++; - break; - case Command::PRE: - activatedBanks--; - break; - case Command::PREA: - activatedBanks = 0; - break; - case Command::PDEA: - state = State::ActivePdn; - entryTriggered = false; - break; - case Command::PDEP: - state = State::PrechargePdn; - entryTriggered = false; - break; - case Command::SREFEN: - state = State::SelfRefresh; - entryTriggered = false; - enterSelfRefresh = false; - break; - case Command::PDXA: - state = State::Idle; - exitTriggered = false; - break; - case Command::PDXP: - state = State::Idle; - exitTriggered = false; - if (controllerIdle) - enterSelfRefresh = true; - break; - case Command::SREFEX: - state = State::ExtraRefresh; - break; - case Command::REFA: - if (state == State::ExtraRefresh) - { + case Command::ACT: + activatedBanks++; + break; + case Command::PRE: + activatedBanks--; + break; + case Command::PREA: + activatedBanks = 0; + break; + case Command::PDEA: + state = State::ActivePdn; + entryTriggered = false; + break; + case Command::PDEP: + state = State::PrechargePdn; + entryTriggered = false; + break; + case Command::SREFEN: + state = State::SelfRefresh; + entryTriggered = false; + enterSelfRefresh = false; + break; + case Command::PDXA: state = State::Idle; exitTriggered = false; - } - else if (controllerIdle) - entryTriggered = true; - break; - case Command::REFB: - if (controllerIdle) - entryTriggered = true; - break; - default: - break; + break; + case Command::PDXP: + state = State::Idle; + exitTriggered = false; + if (controllerIdle) + enterSelfRefresh = true; + break; + case Command::SREFEX: + state = State::ExtraRefresh; + break; + case Command::REFA: + if (state == State::ExtraRefresh) + { + state = State::Idle; + exitTriggered = false; + } + else if (controllerIdle) + entryTriggered = true; + break; + case Command::REFB: + if (controllerIdle) + entryTriggered = true; + break; + default: + break; } } diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerAllBank.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerAllBank.cpp index e6e66b18..d9c86544 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerAllBank.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerAllBank.cpp @@ -66,9 +66,9 @@ sc_time RefreshManagerAllBank::start() if (sc_time_stamp() >= timeForNextTrigger) { - powerDownManager->triggerInterruption(); - if (sleeping) - return timeToSchedule; +// powerDownManager->triggerInterruption(); +// if (sleeping) +// return timeToSchedule; if (sc_time_stamp() >= timeForNextTrigger + memSpec->getRefreshIntervalAB()) { @@ -107,7 +107,9 @@ sc_time RefreshManagerAllBank::start() nextCommand = Command::PREA; else nextCommand = Command::REFA; - timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, BankGroup(0), Bank(0)); + + if (!sleeping) + timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, BankGroup(0), Bank(0)); return timeToSchedule; } else // if (state == RmState::Pulledin) @@ -131,7 +133,9 @@ sc_time RefreshManagerAllBank::start() else { nextCommand = Command::REFA; - timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, BankGroup(0), Bank(0)); + + if (!sleeping) + timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, BankGroup(0), Bank(0)); return timeToSchedule; } } @@ -144,48 +148,48 @@ void RefreshManagerAllBank::updateState(Command command) { switch (command) { - case Command::ACT: - activatedBanks++; - break; - case Command::PRE: case Command::RDA: case Command::WRA: - activatedBanks--; - break; - case Command::PREA: - activatedBanks = 0; - break; - case Command::REFA: - if (sleeping) - { - // Refresh command after SREFEX - state = State::Regular; // TODO: check if this assignment is necessary - timeForNextTrigger = sc_time_stamp() + memSpec->getRefreshIntervalAB(); - sleeping = false; - } - else - { - if (state == State::Pulledin) - flexibilityCounter--; - else - state = State::Pulledin; - - if (flexibilityCounter == maxPulledin) + case Command::ACT: + activatedBanks++; + break; + case Command::PRE: case Command::RDA: case Command::WRA: + activatedBanks--; + break; + case Command::PREA: + activatedBanks = 0; + break; + case Command::REFA: + if (sleeping) { - state = State::Regular; - timeForNextTrigger += memSpec->getRefreshIntervalAB(); + // Refresh command after SREFEX + state = State::Regular; // TODO: check if this assignment is necessary + timeForNextTrigger = sc_time_stamp() + memSpec->getRefreshIntervalAB(); + sleeping = false; } - } - break; - case Command::PDEA: case Command::PDEP: - sleeping = true; - break; - case Command::SREFEN: - sleeping = true; - timeForNextTrigger = sc_max_time(); - break; - case Command::PDXA: case Command::PDXP: - sleeping = false; - break; - default: - break; + else + { + if (state == State::Pulledin) + flexibilityCounter--; + else + state = State::Pulledin; + + if (flexibilityCounter == maxPulledin) + { + state = State::Regular; + timeForNextTrigger += memSpec->getRefreshIntervalAB(); + } + } + break; + case Command::PDEA: case Command::PDEP: + sleeping = true; + break; + case Command::SREFEN: + sleeping = true; + timeForNextTrigger = sc_max_time(); + break; + case Command::PDXA: case Command::PDXP: + sleeping = false; + break; + default: + break; } } diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerPerBank.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerPerBank.cpp index 59991d6b..fc264031 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerPerBank.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerPerBank.cpp @@ -76,9 +76,9 @@ sc_time RefreshManagerPerBank::start() if (sc_time_stamp() >= timeForNextTrigger) { - powerDownManager->triggerInterruption(); - if (sleeping) - return timeToSchedule; +// powerDownManager->triggerInterruption(); +// if (sleeping) +// return timeToSchedule; if (sc_time_stamp() >= timeForNextTrigger + memSpec->getRefreshIntervalPB()) { @@ -129,8 +129,9 @@ sc_time RefreshManagerPerBank::start() } } - timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, - currentBankMachine->getBankGroup(), currentBankMachine->getBank()); + if (!sleeping) + timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, + currentBankMachine->getBankGroup(), currentBankMachine->getBank()); return timeToSchedule; } } @@ -161,8 +162,10 @@ sc_time RefreshManagerPerBank::start() nextCommand = Command::PRE; else nextCommand = Command::REFB; - timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, - currentBankMachine->getBankGroup(), currentBankMachine->getBank()); + + if (!sleeping) + timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, + currentBankMachine->getBankGroup(), currentBankMachine->getBank()); return timeToSchedule; } } @@ -175,40 +178,40 @@ void RefreshManagerPerBank::updateState(Command command) { switch (command) { - case Command::REFB: - skipSelection = false; - remainingBankMachines.erase(currentIterator); - if (remainingBankMachines.empty()) - remainingBankMachines = allBankMachines; + case Command::REFB: + skipSelection = false; + remainingBankMachines.erase(currentIterator); + if (remainingBankMachines.empty()) + remainingBankMachines = allBankMachines; - if (state == State::Pulledin) - flexibilityCounter--; - else - state = State::Pulledin; + if (state == State::Pulledin) + flexibilityCounter--; + else + state = State::Pulledin; - if (flexibilityCounter == maxPulledin) - { - state = State::Regular; - timeForNextTrigger += memSpec->getRefreshIntervalPB(); - } - break; - case Command::REFA: - // Refresh command after SREFEX - state = State::Regular; // TODO: check if this assignment is necessary - timeForNextTrigger = sc_time_stamp() + memSpec->getRefreshIntervalPB(); - sleeping = false; - break; - case Command::PDEA: case Command::PDEP: - sleeping = true; - break; - case Command::SREFEN: - sleeping = true; - timeForNextTrigger = sc_max_time(); - break; - case Command::PDXA: case Command::PDXP: - sleeping = false; - break; - default: - break; + if (flexibilityCounter == maxPulledin) + { + state = State::Regular; + timeForNextTrigger += memSpec->getRefreshIntervalPB(); + } + break; + case Command::REFA: + // Refresh command after SREFEX + state = State::Regular; // TODO: check if this assignment is necessary + timeForNextTrigger = sc_time_stamp() + memSpec->getRefreshIntervalPB(); + sleeping = false; + break; + case Command::PDEA: case Command::PDEP: + sleeping = true; + break; + case Command::SREFEN: + sleeping = true; + timeForNextTrigger = sc_max_time(); + break; + case Command::PDXA: case Command::PDXP: + sleeping = false; + break; + default: + break; } } diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerSameBank.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerSameBank.cpp index 9e144c4c..e0b3388b 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerSameBank.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerSameBank.cpp @@ -85,9 +85,9 @@ sc_time RefreshManagerSameBank::start() if (sc_time_stamp() >= timeForNextTrigger) { - powerDownManager->triggerInterruption(); - if (sleeping) - return timeToSchedule; +// powerDownManager->triggerInterruption(); +// if (sleeping) +// return timeToSchedule; if (sc_time_stamp() >= timeForNextTrigger + memSpec->getRefreshIntervalSB()) { @@ -148,8 +148,9 @@ sc_time RefreshManagerSameBank::start() skipSelection = true; } - timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, - currentIterator->front()->getBankGroup(), currentIterator->front()->getBank()); + if (!sleeping) + timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, + currentIterator->front()->getBankGroup(), currentIterator->front()->getBank()); return timeToSchedule; } } @@ -195,8 +196,9 @@ sc_time RefreshManagerSameBank::start() } } - timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, - currentIterator->front()->getBankGroup(), currentIterator->front()->getBank()); + if (!sleeping) + timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, + currentIterator->front()->getBankGroup(), currentIterator->front()->getBank()); return timeToSchedule; } } @@ -209,41 +211,41 @@ void RefreshManagerSameBank::updateState(Command command) { switch (command) { - case Command::REFSB: - skipSelection = false; - remainingBankMachines.erase(currentIterator); - if (remainingBankMachines.empty()) - remainingBankMachines = allBankMachines; - currentIterator = remainingBankMachines.begin(); + case Command::REFSB: + skipSelection = false; + remainingBankMachines.erase(currentIterator); + if (remainingBankMachines.empty()) + remainingBankMachines = allBankMachines; + currentIterator = remainingBankMachines.begin(); - if (state == State::Pulledin) - flexibilityCounter--; - else - state = State::Pulledin; + if (state == State::Pulledin) + flexibilityCounter--; + else + state = State::Pulledin; - if (flexibilityCounter == maxPulledin) - { - state = State::Regular; - timeForNextTrigger += memSpec->getRefreshIntervalSB(); - } - break; - case Command::REFA: - // Refresh command after SREFEX - state = State::Regular; // TODO: check if this assignment is necessary - timeForNextTrigger = sc_time_stamp() + memSpec->getRefreshIntervalSB(); - sleeping = false; - break; - case Command::PDEA: case Command::PDEP: - sleeping = true; - break; - case Command::SREFEN: - sleeping = true; - timeForNextTrigger = sc_max_time(); - break; - case Command::PDXA: case Command::PDXP: - sleeping = false; - break; - default: - break; + if (flexibilityCounter == maxPulledin) + { + state = State::Regular; + timeForNextTrigger += memSpec->getRefreshIntervalSB(); + } + break; + case Command::REFA: + // Refresh command after SREFEX + state = State::Regular; // TODO: check if this assignment is necessary + timeForNextTrigger = sc_time_stamp() + memSpec->getRefreshIntervalSB(); + sleeping = false; + break; + case Command::PDEA: case Command::PDEP: + sleeping = true; + break; + case Command::SREFEN: + sleeping = true; + timeForNextTrigger = sc_max_time(); + break; + case Command::PDXA: case Command::PDXP: + sleeping = false; + break; + default: + break; } } From dda39ac4ef78268f500f23d69b6156b905e67372 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Wed, 19 May 2021 15:34:14 +0200 Subject: [PATCH 2/6] Revert changes from previous commit. --- DRAMSys/library/src/controller/Controller.cpp | 23 +++++++++---------- .../refresh/RefreshManagerAllBank.cpp | 13 ++++------- .../refresh/RefreshManagerPerBank.cpp | 16 ++++++------- .../refresh/RefreshManagerSameBank.cpp | 16 ++++++------- 4 files changed, 30 insertions(+), 38 deletions(-) diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index b9092b81..c9c93f05 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -261,21 +261,20 @@ void Controller::controllerMethod() commandTuple = powerDownManagers[rankID]->getNextCommand(); if (std::get(commandTuple) != Command::NOP) readyCommands.emplace_back(commandTuple); - - // (4.2) Check for refresh commands (PREA/PRE or REFA/REFB) - commandTuple = refreshManagers[rankID]->getNextCommand(); - if (std::get(commandTuple) != Command::NOP) + else { - readyCommands.emplace_back(commandTuple); - powerDownManagers[rankID]->triggerInterruption(); - } - - // (4.3) Check for bank commands (PRE, ACT, RD/RDA or WR/WRA) - for (auto it : bankMachinesOnRank[rankID]) - { - commandTuple = it->getNextCommand(); + // (4.2) Check for refresh commands (PREA/PRE or REFA/REFB) + commandTuple = refreshManagers[rankID]->getNextCommand(); if (std::get(commandTuple) != Command::NOP) readyCommands.emplace_back(commandTuple); + + // (4.3) Check for bank commands (PRE, ACT, RD/RDA or WR/WRA) + for (auto it : bankMachinesOnRank[rankID]) + { + commandTuple = it->getNextCommand(); + if (std::get(commandTuple) != Command::NOP) + readyCommands.emplace_back(commandTuple); + } } } diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerAllBank.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerAllBank.cpp index d9c86544..44c97ea1 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerAllBank.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerAllBank.cpp @@ -66,9 +66,9 @@ sc_time RefreshManagerAllBank::start() if (sc_time_stamp() >= timeForNextTrigger) { -// powerDownManager->triggerInterruption(); -// if (sleeping) -// return timeToSchedule; + powerDownManager->triggerInterruption(); + if (sleeping) + return timeToSchedule; if (sc_time_stamp() >= timeForNextTrigger + memSpec->getRefreshIntervalAB()) { @@ -108,8 +108,7 @@ sc_time RefreshManagerAllBank::start() else nextCommand = Command::REFA; - if (!sleeping) - timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, BankGroup(0), Bank(0)); + timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, BankGroup(0), Bank(0)); return timeToSchedule; } else // if (state == RmState::Pulledin) @@ -133,9 +132,7 @@ sc_time RefreshManagerAllBank::start() else { nextCommand = Command::REFA; - - if (!sleeping) - timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, BankGroup(0), Bank(0)); + timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, BankGroup(0), Bank(0)); return timeToSchedule; } } diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerPerBank.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerPerBank.cpp index fc264031..1b2fe232 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerPerBank.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerPerBank.cpp @@ -76,9 +76,9 @@ sc_time RefreshManagerPerBank::start() if (sc_time_stamp() >= timeForNextTrigger) { -// powerDownManager->triggerInterruption(); -// if (sleeping) -// return timeToSchedule; + powerDownManager->triggerInterruption(); + if (sleeping) + return timeToSchedule; if (sc_time_stamp() >= timeForNextTrigger + memSpec->getRefreshIntervalPB()) { @@ -129,9 +129,8 @@ sc_time RefreshManagerPerBank::start() } } - if (!sleeping) - timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, - currentBankMachine->getBankGroup(), currentBankMachine->getBank()); + timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, + currentBankMachine->getBankGroup(), currentBankMachine->getBank()); return timeToSchedule; } } @@ -163,9 +162,8 @@ sc_time RefreshManagerPerBank::start() else nextCommand = Command::REFB; - if (!sleeping) - timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, - currentBankMachine->getBankGroup(), currentBankMachine->getBank()); + timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, + currentBankMachine->getBankGroup(), currentBankMachine->getBank()); return timeToSchedule; } } diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerSameBank.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerSameBank.cpp index e0b3388b..484d652b 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerSameBank.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerSameBank.cpp @@ -85,9 +85,9 @@ sc_time RefreshManagerSameBank::start() if (sc_time_stamp() >= timeForNextTrigger) { -// powerDownManager->triggerInterruption(); -// if (sleeping) -// return timeToSchedule; + powerDownManager->triggerInterruption(); + if (sleeping) + return timeToSchedule; if (sc_time_stamp() >= timeForNextTrigger + memSpec->getRefreshIntervalSB()) { @@ -148,9 +148,8 @@ sc_time RefreshManagerSameBank::start() skipSelection = true; } - if (!sleeping) - timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, - currentIterator->front()->getBankGroup(), currentIterator->front()->getBank()); + timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, + currentIterator->front()->getBankGroup(), currentIterator->front()->getBank()); return timeToSchedule; } } @@ -196,9 +195,8 @@ sc_time RefreshManagerSameBank::start() } } - if (!sleeping) - timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, - currentIterator->front()->getBankGroup(), currentIterator->front()->getBank()); + timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, + currentIterator->front()->getBankGroup(), currentIterator->front()->getBank()); return timeToSchedule; } } From 1b58c916b077f266c9b39e5d4a2b5db086b7f582 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Thu, 20 May 2021 15:56:41 +0200 Subject: [PATCH 3/6] Code refactoring. --- DRAMSys/library/src/common/dramExtensions.cpp | 42 +-- DRAMSys/library/src/common/dramExtensions.h | 8 +- DRAMSys/library/src/common/utils.cpp | 4 +- DRAMSys/library/src/common/utils.h | 2 +- .../library/src/controller/BankMachine.cpp | 27 +- DRAMSys/library/src/controller/BankMachine.h | 22 +- DRAMSys/library/src/controller/Controller.cpp | 4 +- DRAMSys/library/src/controller/Controller.h | 10 +- DRAMSys/library/src/controller/ControllerIF.h | 2 +- .../src/controller/ControllerRecordable.cpp | 4 +- .../src/controller/ControllerRecordable.h | 18 +- .../src/controller/checker/CheckerDDR3.cpp | 12 +- .../src/controller/checker/CheckerDDR3.h | 5 +- .../src/controller/checker/CheckerDDR4.cpp | 30 +- .../src/controller/checker/CheckerDDR4.h | 5 +- .../src/controller/checker/CheckerDDR5.cpp | 258 +++++++++--------- .../src/controller/checker/CheckerDDR5.h | 5 +- .../src/controller/checker/CheckerGDDR5.cpp | 32 ++- .../src/controller/checker/CheckerGDDR5.h | 5 +- .../src/controller/checker/CheckerGDDR5X.cpp | 32 ++- .../src/controller/checker/CheckerGDDR5X.h | 5 +- .../src/controller/checker/CheckerGDDR6.cpp | 32 ++- .../src/controller/checker/CheckerGDDR6.h | 5 +- .../src/controller/checker/CheckerHBM2.cpp | 32 ++- .../src/controller/checker/CheckerHBM2.h | 5 +- .../src/controller/checker/CheckerIF.h | 5 +- .../src/controller/checker/CheckerLPDDR4.cpp | 12 +- .../src/controller/checker/CheckerLPDDR4.h | 5 +- .../src/controller/checker/CheckerSTTMRAM.cpp | 12 +- .../src/controller/checker/CheckerSTTMRAM.h | 5 +- .../src/controller/checker/CheckerWideIO.cpp | 12 +- .../src/controller/checker/CheckerWideIO.h | 5 +- .../src/controller/checker/CheckerWideIO2.cpp | 12 +- .../src/controller/checker/CheckerWideIO2.h | 5 +- .../powerdown/PowerDownManagerStaggered.cpp | 6 +- .../refresh/RefreshManagerAllBank.cpp | 9 +- .../refresh/RefreshManagerAllBank.h | 7 +- .../controller/refresh/RefreshManagerDummy.h | 6 +- .../src/controller/refresh/RefreshManagerIF.h | 4 +- .../refresh/RefreshManagerPerBank.cpp | 14 +- .../refresh/RefreshManagerPerBank.h | 8 +- .../refresh/RefreshManagerSameBank.cpp | 19 +- .../refresh/RefreshManagerSameBank.h | 8 +- 43 files changed, 418 insertions(+), 342 deletions(-) diff --git a/DRAMSys/library/src/common/dramExtensions.cpp b/DRAMSys/library/src/common/dramExtensions.cpp index 44910e22..286e57f0 100644 --- a/DRAMSys/library/src/common/dramExtensions.cpp +++ b/DRAMSys/library/src/common/dramExtensions.cpp @@ -43,23 +43,23 @@ using namespace tlm; DramExtension::DramExtension() : - thread(0), channel(0), rank(0), bankgroup(0), bank(0), - row(0), column(0), burstLength(0), - threadPayloadID(0), channelPayloadID(0) {} + thread(0), channel(0), rank(0), bankGroup(0), bank(0), + row(0), column(0), burstLength(0), + threadPayloadID(0), channelPayloadID(0) {} DramExtension::DramExtension(Thread thread, Channel channel, Rank rank, - BankGroup bankgroup, Bank bank, Row row, + BankGroup bankGroup, Bank bank, Row row, Column column, unsigned int burstLength, uint64_t threadPayloadID, uint64_t channelPayloadID) : - thread(thread), channel(channel), rank(rank), bankgroup(bankgroup), bank(bank), - row(row), column(column), burstLength(burstLength), - threadPayloadID(threadPayloadID), channelPayloadID(channelPayloadID) {} + thread(thread), channel(channel), rank(rank), bankGroup(bankGroup), bank(bank), + row(row), column(column), burstLength(burstLength), + threadPayloadID(threadPayloadID), channelPayloadID(channelPayloadID) {} void DramExtension::setExtension(tlm::tlm_generic_payload *payload, - Thread thread, Channel channel, Rank rank, - BankGroup bankgroup, Bank bank, Row row, - Column column, unsigned int burstLength, - uint64_t threadPayloadID, uint64_t channelPayloadID) + Thread thread, Channel channel, Rank rank, + BankGroup bankGroup, Bank bank, Row row, + Column column, unsigned int burstLength, + uint64_t threadPayloadID, uint64_t channelPayloadID) { DramExtension *extension = nullptr; payload->get_extension(extension); @@ -69,7 +69,7 @@ void DramExtension::setExtension(tlm::tlm_generic_payload *payload, extension->thread = thread; extension->channel = channel; extension->rank = rank; - extension->bankgroup = bankgroup; + extension->bankGroup = bankGroup; extension->bank = bank; extension->row = row; extension->column = column; @@ -79,7 +79,7 @@ void DramExtension::setExtension(tlm::tlm_generic_payload *payload, } else { - extension = new DramExtension(thread, channel, rank, bankgroup, + extension = new DramExtension(thread, channel, rank, bankGroup, bank, row, column, burstLength, threadPayloadID, channelPayloadID); payload->set_auto_extension(extension); @@ -87,12 +87,12 @@ void DramExtension::setExtension(tlm::tlm_generic_payload *payload, } void DramExtension::setExtension(tlm::tlm_generic_payload &payload, - Thread thread, Channel channel, Rank rank, - BankGroup bankgroup, Bank bank, Row row, - Column column, unsigned int burstLength, - uint64_t threadPayloadID, uint64_t channelPayloadID) + Thread thread, Channel channel, Rank rank, + BankGroup bankGroup, Bank bank, Row row, + Column column, unsigned int burstLength, + uint64_t threadPayloadID, uint64_t channelPayloadID) { - setExtension(&payload, thread, channel, rank, bankgroup, + setExtension(&payload, thread, channel, rank, bankGroup, bank, row, column, burstLength, threadPayloadID, channelPayloadID); } @@ -226,7 +226,7 @@ uint64_t DramExtension::getChannelPayloadID(const tlm_generic_payload &payload) tlm_extension_base *DramExtension::clone() const { - return new DramExtension(thread, channel, rank, bankgroup, bank, row, column, + return new DramExtension(thread, channel, rank, bankGroup, bank, row, column, burstLength, threadPayloadID, channelPayloadID); } @@ -236,7 +236,7 @@ void DramExtension::copy_from(const tlm_extension_base &ext) thread = cpyFrom.thread; channel = cpyFrom.channel; rank = cpyFrom.rank; - bankgroup = cpyFrom.bankgroup; + bankGroup = cpyFrom.bankGroup; bank = cpyFrom.bank; row = cpyFrom.row; column = cpyFrom.column; @@ -260,7 +260,7 @@ Rank DramExtension::getRank() const BankGroup DramExtension::getBankGroup() const { - return bankgroup; + return bankGroup; } Bank DramExtension::getBank() const diff --git a/DRAMSys/library/src/common/dramExtensions.h b/DRAMSys/library/src/common/dramExtensions.h index 462a61a8..0898cb49 100644 --- a/DRAMSys/library/src/common/dramExtensions.h +++ b/DRAMSys/library/src/common/dramExtensions.h @@ -164,7 +164,7 @@ class DramExtension : public tlm::tlm_extension public: DramExtension(); DramExtension(Thread thread, Channel channel, Rank rank, - BankGroup bankgroup, Bank bank, Row row, + BankGroup bankGroup, Bank bank, Row row, Column column, unsigned int burstLength, uint64_t threadPayloadID, uint64_t channelPayloadID); @@ -173,12 +173,12 @@ public: static void setExtension(tlm::tlm_generic_payload *payload, Thread thread, Channel channel, Rank rank, - BankGroup bankgroup, Bank bank, Row row, + BankGroup bankGroup, Bank bank, Row row, Column column, unsigned int burstLength, uint64_t threadPayloadID, uint64_t channelPayloadID); static void setExtension(tlm::tlm_generic_payload &payload, Thread thread, Channel channel, Rank rank, - BankGroup bankgroup, Bank bank, Row row, + BankGroup bankGroup, Bank bank, Row row, Column column, unsigned int burstLength, uint64_t threadPayloadID, uint64_t channelPayloadID); @@ -229,7 +229,7 @@ private: Thread thread; Channel channel; Rank rank; - BankGroup bankgroup; + BankGroup bankGroup; Bank bank; Row row; Column column; diff --git a/DRAMSys/library/src/common/utils.cpp b/DRAMSys/library/src/common/utils.cpp index e0230736..a8c2d649 100644 --- a/DRAMSys/library/src/common/utils.cpp +++ b/DRAMSys/library/src/common/utils.cpp @@ -139,7 +139,7 @@ std::string parseString(json &obj, std::string name) throw std::invalid_argument("Parameter '" + name + "' does not exist."); } -void setUpDummy(tlm_generic_payload &payload, uint64_t channelPayloadID, Rank rank, BankGroup bankgroup, Bank bank) +void setUpDummy(tlm_generic_payload &payload, uint64_t channelPayloadID, Rank rank, BankGroup bankGroup, Bank bank) { payload.set_address(bank.getStartAddress()); payload.set_command(TLM_READ_COMMAND); @@ -148,7 +148,7 @@ void setUpDummy(tlm_generic_payload &payload, uint64_t channelPayloadID, Rank ra payload.set_dmi_allowed(false); payload.set_byte_enable_length(0); payload.set_streaming_width(0); - payload.set_extension(new DramExtension(Thread(UINT_MAX), Channel(0), rank, bankgroup, + payload.set_extension(new DramExtension(Thread(UINT_MAX), Channel(0), rank, bankGroup, bank, Row(0), Column(0), 0, 0, channelPayloadID)); payload.set_extension(new GenerationExtension(SC_ZERO_TIME)); } diff --git a/DRAMSys/library/src/common/utils.h b/DRAMSys/library/src/common/utils.h index e29a430d..e98fde2d 100644 --- a/DRAMSys/library/src/common/utils.h +++ b/DRAMSys/library/src/common/utils.h @@ -74,7 +74,7 @@ double parseUdouble(nlohmann::json &obj, std::string name); std::string parseString(nlohmann::json &obj, std::string name); void setUpDummy(tlm::tlm_generic_payload &payload, uint64_t channelPayloadID, - Rank rank = Rank(0), BankGroup bankgroup = BankGroup(0), Bank bank = Bank(0)); + Rank rank = Rank(0), BankGroup bankGroup = BankGroup(0), Bank bank = Bank(0)); #endif // UTILS_H diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index 4fdecbb1..d94ffd03 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -47,8 +47,7 @@ BankMachine::BankMachine(SchedulerIF *scheduler, CheckerIF *checker, Bank bank) CommandTuple::Type BankMachine::getNextCommand() { - return CommandTuple::Type(nextCommand, currentPayload, - std::max(timeToSchedule, sc_time_stamp())); + return {nextCommand, currentPayload, std::max(timeToSchedule, sc_time_stamp())}; } void BankMachine::updateState(Command command) @@ -89,32 +88,32 @@ void BankMachine::block() blocked = true; } -Rank BankMachine::getRank() +Rank BankMachine::getRank() const { return rank; } -BankGroup BankMachine::getBankGroup() +BankGroup BankMachine::getBankGroup() const { return bankgroup; } -Bank BankMachine::getBank() +Bank BankMachine::getBank() const { return bank; } -Row BankMachine::getOpenRow() +Row BankMachine::getOpenRow() const { return openRow; } -BankMachine::State BankMachine::getState() +BankMachine::State BankMachine::getState() const { return state; } -bool BankMachine::isIdle() +bool BankMachine::isIdle() const { return (currentPayload == nullptr); } @@ -148,8 +147,7 @@ sc_time BankMachineOpen::start() else // row miss nextCommand = Command::PRE; } - timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, - bankgroup, bank, DramExtension::getBurstLength(currentPayload)); + timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, currentPayload); } } return timeToSchedule; @@ -179,8 +177,7 @@ sc_time BankMachineClosed::start() else SC_REPORT_FATAL("BankMachine", "Wrong TLM command"); } - timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, - bankgroup, bank, DramExtension::getBurstLength(currentPayload)); + timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, currentPayload); } } return timeToSchedule; @@ -227,8 +224,7 @@ sc_time BankMachineOpenAdaptive::start() else // row miss nextCommand = Command::PRE; } - timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, - bankgroup, bank, DramExtension::getBurstLength(currentPayload)); + timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, currentPayload); } } return timeToSchedule; @@ -275,8 +271,7 @@ sc_time BankMachineClosedAdaptive::start() else // row miss, should never happen SC_REPORT_FATAL("BankMachine", "Should never be reached for this policy"); } - timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, - bankgroup, bank, DramExtension::getBurstLength(currentPayload)); + timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, currentPayload); } } return timeToSchedule; diff --git a/DRAMSys/library/src/controller/BankMachine.h b/DRAMSys/library/src/controller/BankMachine.h index 508ed46d..fc409123 100644 --- a/DRAMSys/library/src/controller/BankMachine.h +++ b/DRAMSys/library/src/controller/BankMachine.h @@ -46,7 +46,7 @@ class BankMachine { public: - virtual ~BankMachine() {} + virtual ~BankMachine() = default; virtual sc_time start() = 0; CommandTuple::Type getNextCommand(); void updateState(Command); @@ -54,12 +54,12 @@ public: enum class State {Precharged, Activated}; - Rank getRank(); - BankGroup getBankGroup(); - Bank getBank(); - Row getOpenRow(); - State getState(); - bool isIdle(); + Rank getRank() const; + BankGroup getBankGroup() const; + Bank getBank() const; + Row getOpenRow() const; + State getState() const; + bool isIdle() const; protected: BankMachine(SchedulerIF *, CheckerIF *, Bank); @@ -81,28 +81,28 @@ class BankMachineOpen final : public BankMachine { public: BankMachineOpen(SchedulerIF *, CheckerIF *, Bank); - sc_time start(); + sc_time start() override; }; class BankMachineClosed final : public BankMachine { public: BankMachineClosed(SchedulerIF *, CheckerIF *, Bank); - sc_time start(); + sc_time start() override; }; class BankMachineOpenAdaptive final : public BankMachine { public: BankMachineOpenAdaptive(SchedulerIF *, CheckerIF *, Bank); - sc_time start(); + sc_time start() override; }; class BankMachineClosedAdaptive final : public BankMachine { public: BankMachineClosedAdaptive(SchedulerIF *, CheckerIF *, Bank); - sc_time start(); + sc_time start() override; }; #endif // BANKMACHINE_H diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index c9c93f05..ce9e5426 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -64,7 +64,7 @@ using namespace tlm; -Controller::Controller(sc_module_name name) : +Controller::Controller(const sc_module_name &name) : ControllerIF(name) { SC_METHOD(controllerMethod); @@ -308,7 +308,7 @@ void Controller::controllerMethod() refreshManagers[rank.ID()]->updateState(command); powerDownManagers[rank.ID()]->updateState(command); - checker->insert(command, rank, bankgroup, bank, burstLength); + checker->insert(command, payload); if (isCasCommand(command)) { diff --git a/DRAMSys/library/src/controller/Controller.h b/DRAMSys/library/src/controller/Controller.h index 8a45ef48..b2e3aef6 100644 --- a/DRAMSys/library/src/controller/Controller.h +++ b/DRAMSys/library/src/controller/Controller.h @@ -60,14 +60,14 @@ class PowerDownManagerStaggered; class Controller : public ControllerIF { public: - Controller(sc_module_name); + explicit Controller(const sc_module_name &name); SC_HAS_PROCESS(Controller); - virtual ~Controller() override; + ~Controller() override; protected: - virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &, tlm::tlm_phase &, sc_time &) override; - virtual tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &, tlm::tlm_phase &, sc_time &) override; - virtual unsigned int transport_dbg(tlm::tlm_generic_payload &) override; + tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &, tlm::tlm_phase &, sc_time &) override; + tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &, tlm::tlm_phase &, sc_time &) override; + unsigned int transport_dbg(tlm::tlm_generic_payload &) override; virtual void sendToFrontend(tlm::tlm_generic_payload *, tlm::tlm_phase, sc_time); virtual void sendToDram(Command, tlm::tlm_generic_payload *, sc_time); diff --git a/DRAMSys/library/src/controller/ControllerIF.h b/DRAMSys/library/src/controller/ControllerIF.h index aebae208..ce9a191a 100644 --- a/DRAMSys/library/src/controller/ControllerIF.h +++ b/DRAMSys/library/src/controller/ControllerIF.h @@ -93,7 +93,7 @@ public: protected: // Bind sockets with virtual functions - ControllerIF(sc_module_name name) : + ControllerIF(const sc_module_name &name) : sc_module(name), tSocket("tSocket"), iSocket("iSocket") { tSocket.register_nb_transport_fw(this, &ControllerIF::nb_transport_fw); diff --git a/DRAMSys/library/src/controller/ControllerRecordable.cpp b/DRAMSys/library/src/controller/ControllerRecordable.cpp index 34350af4..1a320d96 100644 --- a/DRAMSys/library/src/controller/ControllerRecordable.cpp +++ b/DRAMSys/library/src/controller/ControllerRecordable.cpp @@ -37,7 +37,7 @@ using namespace tlm; -ControllerRecordable::ControllerRecordable(sc_module_name name, TlmRecorder *tlmRecorder) +ControllerRecordable::ControllerRecordable(const sc_module_name &name, TlmRecorder *tlmRecorder) : Controller(name), tlmRecorder(tlmRecorder) { if (Configuration::getInstance().enableWindowing) @@ -132,7 +132,7 @@ void ControllerRecordable::controllerMethod() uint64_t windowNumberOfBeatsServed = numberOfBeatsServed - lastNumberOfBeatsServed; lastNumberOfBeatsServed = numberOfBeatsServed; - sc_time windowActiveTime = windowNumberOfBeatsServed * activeTimeMultiplier; + sc_time windowActiveTime = activeTimeMultiplier * static_cast(windowNumberOfBeatsServed); double windowAverageBandwidth = windowActiveTime / windowSizeTime; tlmRecorder->recordBandwidth(sc_time_stamp().to_seconds(), windowAverageBandwidth); } diff --git a/DRAMSys/library/src/controller/ControllerRecordable.h b/DRAMSys/library/src/controller/ControllerRecordable.h index 9459cd12..38bf80fc 100644 --- a/DRAMSys/library/src/controller/ControllerRecordable.h +++ b/DRAMSys/library/src/controller/ControllerRecordable.h @@ -41,19 +41,19 @@ class ControllerRecordable final : public Controller { public: - ControllerRecordable(sc_module_name name, TlmRecorder *tlmRecorder); - virtual ~ControllerRecordable() override {} + ControllerRecordable(const sc_module_name &name, TlmRecorder *tlmRecorder); + ~ControllerRecordable() override = default; protected: - virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &trans, - tlm::tlm_phase &phase, sc_time &delay) override; - virtual tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &trans, - tlm::tlm_phase &phase, sc_time &delay) override; + tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &trans, + tlm::tlm_phase &phase, sc_time &delay) override; + tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &trans, + tlm::tlm_phase &phase, sc_time &delay) override; - virtual void sendToFrontend(tlm::tlm_generic_payload *, tlm::tlm_phase, sc_time) override; - virtual void sendToDram(Command, tlm::tlm_generic_payload *, sc_time) override; + void sendToFrontend(tlm::tlm_generic_payload *, tlm::tlm_phase, sc_time) override; + void sendToDram(Command, tlm::tlm_generic_payload *, sc_time) override; - virtual void controllerMethod() override; + void controllerMethod() override; private: void recordPhase(tlm::tlm_generic_payload &trans, tlm::tlm_phase phase, sc_time delay); diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp index 089a753b..784c9a77 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp @@ -34,6 +34,8 @@ #include "CheckerDDR3.h" +using namespace tlm; + CheckerDDR3::CheckerDDR3() { Configuration &config = Configuration::getInstance(); @@ -60,8 +62,11 @@ CheckerDDR3::CheckerDDR3() tWRAPDEN = memSpec->tWL + tBURST + memSpec->tWR + memSpec->tCK; } -sc_time CheckerDDR3::timeToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank, unsigned) const +sc_time CheckerDDR3::timeToSatisfyConstraints(Command command, tlm_generic_payload *payload) const { + Rank rank = DramExtension::getRank(payload); + Bank bank = DramExtension::getBank(payload); + sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); @@ -412,8 +417,11 @@ sc_time CheckerDDR3::timeToSatisfyConstraints(Command command, Rank rank, BankGr return earliestTimeToStart; } -void CheckerDDR3::insert(Command command, Rank rank, BankGroup, Bank bank, unsigned) +void CheckerDDR3::insert(Command command, tlm_generic_payload *payload) { + Rank rank = DramExtension::getRank(payload); + Bank bank = DramExtension::getBank(payload); + PRINTDEBUGMESSAGE("CheckerDDR3", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + commandToString(command)); diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.h b/DRAMSys/library/src/controller/checker/CheckerDDR3.h index 1eed6b48..ab3bb6ec 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.h +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.h @@ -45,9 +45,8 @@ class CheckerDDR3 final : public CheckerIF { public: CheckerDDR3(); - virtual sc_time timeToSatisfyConstraints(Command, Rank = Rank(0), - BankGroup = BankGroup(0), Bank = Bank(0), unsigned burstLength = 0) const override; - virtual void insert(Command, Rank, BankGroup, Bank, unsigned) override; + virtual sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; + virtual void insert(Command command, tlm::tlm_generic_payload *payload) override; private: const MemSpecDDR3 *memSpec; diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp index 3dda147b..b38d48b0 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp @@ -34,6 +34,8 @@ #include "CheckerDDR4.h" +using namespace tlm; + CheckerDDR4::CheckerDDR4() { Configuration &config = Configuration::getInstance(); @@ -63,8 +65,12 @@ CheckerDDR4::CheckerDDR4() tWRAPDEN = memSpec->tWL + tBURST + memSpec->tCK + memSpec->tWR; } -sc_time CheckerDDR4::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank, unsigned) const +sc_time CheckerDDR4::timeToSatisfyConstraints(Command command, tlm_generic_payload *payload) const { + Rank rank = DramExtension::getRank(payload); + BankGroup bankGroup = DramExtension::getBankGroup(payload); + Bank bank = DramExtension::getBank(payload); + sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); @@ -74,7 +80,7 @@ sc_time CheckerDDR4::timeToSatisfyConstraints(Command command, Rank rank, BankGr if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD - memSpec->tAL); - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L); @@ -86,7 +92,7 @@ sc_time CheckerDDR4::timeToSatisfyConstraints(Command command, Rank rank, BankGr if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST + memSpec->tRTRS); - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L); @@ -105,7 +111,7 @@ sc_time CheckerDDR4::timeToSatisfyConstraints(Command command, Rank rank, BankGr earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE - memSpec->tRTP - memSpec->tAL); } - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_L); @@ -117,7 +123,7 @@ sc_time CheckerDDR4::timeToSatisfyConstraints(Command command, Rank rank, BankGr if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_R); - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_L); @@ -159,7 +165,7 @@ sc_time CheckerDDR4::timeToSatisfyConstraints(Command command, Rank rank, BankGr if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR_R); - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L); @@ -171,7 +177,7 @@ sc_time CheckerDDR4::timeToSatisfyConstraints(Command command, Rank rank, BankGr if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST + memSpec->tRTRS); - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L); @@ -197,7 +203,7 @@ sc_time CheckerDDR4::timeToSatisfyConstraints(Command command, Rank rank, BankGr if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC); - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::ACT][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::ACT][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRD_L); @@ -443,13 +449,17 @@ sc_time CheckerDDR4::timeToSatisfyConstraints(Command command, Rank rank, BankGr return earliestTimeToStart; } -void CheckerDDR4::insert(Command command, Rank rank, BankGroup bankgroup, Bank bank, unsigned) +void CheckerDDR4::insert(Command command, tlm_generic_payload *payload) { + Rank rank = DramExtension::getRank(payload); + BankGroup bankGroup = DramExtension::getBankGroup(payload); + Bank bank = DramExtension::getBank(payload); + PRINTDEBUGMESSAGE("CheckerDDR4", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + commandToString(command)); lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp(); - lastScheduledByCommandAndBankGroup[command][bankgroup.ID()] = sc_time_stamp(); + lastScheduledByCommandAndBankGroup[command][bankGroup.ID()] = sc_time_stamp(); lastScheduledByCommandAndRank[command][rank.ID()] = sc_time_stamp(); lastScheduledByCommand[command] = sc_time_stamp(); lastCommandOnBus = sc_time_stamp(); diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR4.h b/DRAMSys/library/src/controller/checker/CheckerDDR4.h index d2befee3..46c891d0 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR4.h +++ b/DRAMSys/library/src/controller/checker/CheckerDDR4.h @@ -45,9 +45,8 @@ class CheckerDDR4 final : public CheckerIF { public: CheckerDDR4(); - virtual sc_time timeToSatisfyConstraints(Command, Rank = Rank(0), - BankGroup = BankGroup(0), Bank = Bank(0), unsigned burstLength = 0) const override; - virtual void insert(Command, Rank, BankGroup, Bank, unsigned) override; + virtual sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; + virtual void insert(Command command, tlm::tlm_generic_payload *payload) override; private: const MemSpecDDR4 *memSpec; diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR5.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR5.cpp index 775008aa..cc0555ed 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR5.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR5.cpp @@ -34,6 +34,8 @@ #include "CheckerDDR5.h" +using namespace tlm; + CheckerDDR5::CheckerDDR5() { Configuration &config = Configuration::getInstance(); @@ -111,47 +113,48 @@ CheckerDDR5::CheckerDDR5() tWRAPDEN = memSpec->tWL + tBURST16 + memSpec->tWR + cmdLengthDiff; } -sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank, - unsigned burstLength) const +sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, tlm_generic_payload *payload) const { + Rank logicalRank = DramExtension::getRank(payload); + Rank physicalRank = Rank(logicalRank.ID() / memSpec->logicalRanksPerPhysicalRank); + Rank dimmRank = Rank(physicalRank.ID() / memSpec->physicalRanksPerDIMMRank); + BankGroup bankGroup = DramExtension::getBankGroup(payload); + Bank bank = DramExtension::getBank(payload); + Bank bankInGroup = Bank(logicalRank.ID() * memSpec->banksPerGroup + bank.ID() % memSpec->banksPerGroup); + unsigned burstLength = DramExtension::getBurstLength(payload); + sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); - Rank logicalrank = rank; - Rank physicalrank = Rank(logicalrank.ID() / memSpec->logicalRanksPerPhysicalRank); - Rank dimmrank = Rank(physicalrank.ID() / memSpec->physicalRanksPerDIMMRank); - - Bank bankInGroup = Bank(rank.ID() * memSpec->banksPerGroup + bank.ID() % memSpec->banksPerGroup); - if (command == Command::RD || command == Command::RDA) { lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD); - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L_slr); - lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::RD][logicalrank.ID()]; + lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::RD][logicalRank.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_S_slr); - lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::RD][physicalrank.ID()]; + lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::RD][physicalRank.ID()]; if (lastCommandStart != sc_max_time()) { - if (lastBurstLengthByCommandAndPhysicalRank[Command::RD][physicalrank.ID()] == 32) + if (lastBurstLengthByCommandAndPhysicalRank[Command::RD][physicalRank.ID()] == 32) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST32); earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_dlr); } lastCommandStart = lastScheduledByCommand[Command::RD]; - if (lastCommandStart != lastScheduledByCommandAndPhysicalRank[Command::RD][physicalrank.ID()]) // different physical rank + if (lastCommandStart != lastScheduledByCommandAndPhysicalRank[Command::RD][physicalRank.ID()]) // different physical rank { - if (lastCommandStart == lastScheduledByCommandAndDimmRank[Command::RD][dimmrank.ID()]) // same DIMM + if (lastCommandStart == lastScheduledByCommandAndDimmRank[Command::RD][dimmRank.ID()]) // same DIMM { - if (lastBurstLengthByCommandAndDimmRank[Command::RD][dimmrank.ID()] == 32) + if (lastBurstLengthByCommandAndDimmRank[Command::RD][dimmRank.ID()] == 32) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDRD_dpr + tBURST16); else earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDRD_dpr); @@ -165,29 +168,29 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr } } - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L_slr); - lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::RDA][logicalrank.ID()]; + lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::RDA][logicalRank.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_S_slr); - lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::RDA][physicalrank.ID()]; + lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::RDA][physicalRank.ID()]; if (lastCommandStart != sc_max_time()) { - if (lastBurstLengthByCommandAndPhysicalRank[Command::RDA][physicalrank.ID()] == 32) + if (lastBurstLengthByCommandAndPhysicalRank[Command::RDA][physicalRank.ID()] == 32) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST32); earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_dlr); } lastCommandStart = lastScheduledByCommand[Command::RDA]; - if (lastCommandStart != lastScheduledByCommandAndPhysicalRank[Command::RDA][physicalrank.ID()]) // different physical rank + if (lastCommandStart != lastScheduledByCommandAndPhysicalRank[Command::RDA][physicalRank.ID()]) // different physical rank { - if (lastCommandStart == lastScheduledByCommandAndDimmRank[Command::RDA][dimmrank.ID()]) // same DIMM + if (lastCommandStart == lastScheduledByCommandAndDimmRank[Command::RDA][dimmRank.ID()]) // same DIMM { - if (lastBurstLengthByCommandAndDimmRank[Command::RDA][dimmrank.ID()] == 32) + if (lastBurstLengthByCommandAndDimmRank[Command::RDA][dimmRank.ID()] == 32) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDRD_dpr + tBURST16); else earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDRD_dpr); @@ -213,39 +216,39 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr } } - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) { - if (lastBurstLengthByCommandAndBankGroup[Command::WR][bankgroup.ID()] == 32) + if (lastBurstLengthByCommandAndBankGroup[Command::WR][bankGroup.ID()] == 32) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_WTR_slr + tBURST16); else earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_WTR_slr); } - lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::WR][logicalrank.ID()]; + lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::WR][logicalRank.ID()]; if (lastCommandStart != sc_max_time()) { - if (lastBurstLengthByCommandAndLogicalRank[Command::WR][logicalrank.ID()] == 32) + if (lastBurstLengthByCommandAndLogicalRank[Command::WR][logicalRank.ID()] == 32) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_S_WTR_slr + tBURST16); else earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_S_WTR_slr); } - lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::WR][physicalrank.ID()]; + lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::WR][physicalRank.ID()]; if (lastCommandStart != sc_max_time()) { - if (lastBurstLengthByCommandAndPhysicalRank[Command::WR][physicalrank.ID()] == 32) + if (lastBurstLengthByCommandAndPhysicalRank[Command::WR][physicalRank.ID()] == 32) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_WTR_dlr + tBURST16); else earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_WTR_dlr); } lastCommandStart = lastScheduledByCommand[Command::WR]; - if (lastCommandStart != lastScheduledByCommandAndPhysicalRank[Command::WR][physicalrank.ID()]) // different physical rank + if (lastCommandStart != lastScheduledByCommandAndPhysicalRank[Command::WR][physicalRank.ID()]) // different physical rank { - if (lastCommandStart == lastScheduledByCommandAndDimmRank[Command::WR][dimmrank.ID()]) // same DIMM + if (lastCommandStart == lastScheduledByCommandAndDimmRank[Command::WR][dimmRank.ID()]) // same DIMM { - if (lastBurstLengthByCommandAndDimmRank[Command::WR][dimmrank.ID()] == 32) + if (lastBurstLengthByCommandAndDimmRank[Command::WR][dimmRank.ID()] == 32) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_dpr + tBURST16); else earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_dpr); @@ -259,39 +262,39 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr } } - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) { - if (lastBurstLengthByCommandAndBankGroup[Command::WRA][bankgroup.ID()] == 32) + if (lastBurstLengthByCommandAndBankGroup[Command::WRA][bankGroup.ID()] == 32) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_WTR_slr + tBURST16); else earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_WTR_slr); } - lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::WRA][logicalrank.ID()]; + lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::WRA][logicalRank.ID()]; if (lastCommandStart != sc_max_time()) { - if (lastBurstLengthByCommandAndLogicalRank[Command::WRA][logicalrank.ID()] == 32) + if (lastBurstLengthByCommandAndLogicalRank[Command::WRA][logicalRank.ID()] == 32) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_S_WTR_slr + tBURST16); else earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_S_WTR_slr); } - lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::WRA][physicalrank.ID()]; + lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::WRA][physicalRank.ID()]; if (lastCommandStart != sc_max_time()) { - if (lastBurstLengthByCommandAndPhysicalRank[Command::WRA][physicalrank.ID()] == 32) + if (lastBurstLengthByCommandAndPhysicalRank[Command::WRA][physicalRank.ID()] == 32) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_WTR_dlr + tBURST16); else earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_WTR_dlr); } lastCommandStart = lastScheduledByCommand[Command::WRA]; - if (lastCommandStart != lastScheduledByCommandAndPhysicalRank[Command::WRA][physicalrank.ID()]) // different physical rank + if (lastCommandStart != lastScheduledByCommandAndPhysicalRank[Command::WRA][physicalRank.ID()]) // different physical rank { - if (lastCommandStart == lastScheduledByCommandAndDimmRank[Command::WRA][dimmrank.ID()]) // same DIMM + if (lastCommandStart == lastScheduledByCommandAndDimmRank[Command::WRA][dimmRank.ID()]) // same DIMM { - if (lastBurstLengthByCommandAndDimmRank[Command::WRA][dimmrank.ID()] == 32) + if (lastBurstLengthByCommandAndDimmRank[Command::WRA][dimmRank.ID()] == 32) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_dpr + tBURST16); else earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_dpr); @@ -311,39 +314,39 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD); - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) { - if (lastBurstLengthByCommandAndBankGroup[Command::RD][bankgroup.ID()] == 32) + if (lastBurstLengthByCommandAndBankGroup[Command::RD][bankGroup.ID()] == 32) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_RTW_slr + tBURST16); else earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_RTW_slr); } - lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::RD][logicalrank.ID()]; + lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::RD][logicalRank.ID()]; if (lastCommandStart != sc_max_time()) { - if (lastBurstLengthByCommandAndLogicalRank[Command::RD][logicalrank.ID()] == 32) + if (lastBurstLengthByCommandAndLogicalRank[Command::RD][logicalRank.ID()] == 32) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_S_RTW_slr + tBURST16); else earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_S_RTW_slr); } - lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::RD][physicalrank.ID()]; + lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::RD][physicalRank.ID()]; if (lastCommandStart != sc_max_time()) { - if (lastBurstLengthByCommandAndPhysicalRank[Command::RD][physicalrank.ID()] == 32) + if (lastBurstLengthByCommandAndPhysicalRank[Command::RD][physicalRank.ID()] == 32) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_RTW_dlr + tBURST16); else earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_RTW_dlr); } lastCommandStart = lastScheduledByCommand[Command::RD]; - if (lastCommandStart != lastScheduledByCommandAndPhysicalRank[Command::RD][physicalrank.ID()]) // different physical rank + if (lastCommandStart != lastScheduledByCommandAndPhysicalRank[Command::RD][physicalRank.ID()]) // different physical rank { - if (lastCommandStart == lastScheduledByCommandAndDimmRank[Command::RD][dimmrank.ID()]) // same DIMM + if (lastCommandStart == lastScheduledByCommandAndDimmRank[Command::RD][dimmRank.ID()]) // same DIMM { - if (lastBurstLengthByCommandAndDimmRank[Command::RD][dimmrank.ID()] == 32) + if (lastBurstLengthByCommandAndDimmRank[Command::RD][dimmRank.ID()] == 32) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR_dpr + tBURST16); else earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR_dpr); @@ -357,39 +360,39 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr } } - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) { - if (lastBurstLengthByCommandAndBankGroup[Command::RDA][bankgroup.ID()] == 32) + if (lastBurstLengthByCommandAndBankGroup[Command::RDA][bankGroup.ID()] == 32) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_RTW_slr + tBURST16); else earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_RTW_slr); } - lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::RDA][logicalrank.ID()]; + lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::RDA][logicalRank.ID()]; if (lastCommandStart != sc_max_time()) { - if (lastBurstLengthByCommandAndLogicalRank[Command::RDA][logicalrank.ID()] == 32) + if (lastBurstLengthByCommandAndLogicalRank[Command::RDA][logicalRank.ID()] == 32) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_S_RTW_slr + tBURST16); else earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_S_RTW_slr); } - lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::RDA][physicalrank.ID()]; + lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::RDA][physicalRank.ID()]; if (lastCommandStart != sc_max_time()) { - if (lastBurstLengthByCommandAndPhysicalRank[Command::RDA][physicalrank.ID()] == 32) + if (lastBurstLengthByCommandAndPhysicalRank[Command::RDA][physicalRank.ID()] == 32) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_RTW_dlr + tBURST16); else earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_RTW_dlr); } lastCommandStart = lastScheduledByCommand[Command::RDA]; - if (lastCommandStart != lastScheduledByCommandAndPhysicalRank[Command::RDA][physicalrank.ID()]) // different physical rank + if (lastCommandStart != lastScheduledByCommandAndPhysicalRank[Command::RDA][physicalRank.ID()]) // different physical rank { - if (lastCommandStart == lastScheduledByCommandAndDimmRank[Command::RDA][dimmrank.ID()]) // same DIMM + if (lastCommandStart == lastScheduledByCommandAndDimmRank[Command::RDA][dimmRank.ID()]) // same DIMM { - if (lastBurstLengthByCommandAndDimmRank[Command::RDA][dimmrank.ID()] == 32) + if (lastBurstLengthByCommandAndDimmRank[Command::RDA][dimmRank.ID()] == 32) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR_dpr + tBURST16); else earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR_dpr); @@ -403,10 +406,10 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr } } - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) { - if (lastBurstLengthByCommandAndBankGroup[Command::WR][bankgroup.ID()] == 32) + if (lastBurstLengthByCommandAndBankGroup[Command::WR][bankGroup.ID()] == 32) { if (burstLength == 16 && memSpec->bitWidth == 4) // second WR requires RMW earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST16 + memSpec->tCCD_L_WR_slr); @@ -422,25 +425,25 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr } } - lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::WR][logicalrank.ID()]; + lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::WR][logicalRank.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_S_WR_slr); - lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::WR][physicalrank.ID()]; + lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::WR][physicalRank.ID()]; if (lastCommandStart != sc_max_time()) { - if (lastBurstLengthByCommandAndPhysicalRank[Command::WR][physicalrank.ID()] == 32) + if (lastBurstLengthByCommandAndPhysicalRank[Command::WR][physicalRank.ID()] == 32) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST32); earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_WR_dlr); } lastCommandStart = lastScheduledByCommand[Command::WR]; - if (lastCommandStart != lastScheduledByCommandAndPhysicalRank[Command::WR][physicalrank.ID()]) // different physical rank + if (lastCommandStart != lastScheduledByCommandAndPhysicalRank[Command::WR][physicalRank.ID()]) // different physical rank { - if (lastCommandStart == lastScheduledByCommandAndDimmRank[Command::WR][dimmrank.ID()]) // same DIMM + if (lastCommandStart == lastScheduledByCommandAndDimmRank[Command::WR][dimmRank.ID()]) // same DIMM { - if (lastBurstLengthByCommandAndDimmRank[Command::WR][dimmrank.ID()] == 32) + if (lastBurstLengthByCommandAndDimmRank[Command::WR][dimmRank.ID()] == 32) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRWR_dpr + tBURST16); else earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRWR_dpr); @@ -454,10 +457,10 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr } } - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) { - if (lastBurstLengthByCommandAndBankGroup[Command::WRA][bankgroup.ID()] == 32) + if (lastBurstLengthByCommandAndBankGroup[Command::WRA][bankGroup.ID()] == 32) { if (burstLength == 16 && memSpec->bitWidth == 4) // second WR requires RMW earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST16 + memSpec->tCCD_L_WR_slr); @@ -473,25 +476,25 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr } } - lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::WRA][logicalrank.ID()]; + lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::WRA][logicalRank.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_S_WR_slr); - lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::WRA][physicalrank.ID()]; + lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::WRA][physicalRank.ID()]; if (lastCommandStart != sc_max_time()) { - if (lastBurstLengthByCommandAndPhysicalRank[Command::WRA][physicalrank.ID()] == 32) + if (lastBurstLengthByCommandAndPhysicalRank[Command::WRA][physicalRank.ID()] == 32) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST32); earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_WR_dlr); } lastCommandStart = lastScheduledByCommand[Command::WRA]; - if (lastCommandStart != lastScheduledByCommandAndPhysicalRank[Command::WRA][physicalrank.ID()]) // different physical rank + if (lastCommandStart != lastScheduledByCommandAndPhysicalRank[Command::WRA][physicalRank.ID()]) // different physical rank { - if (lastCommandStart == lastScheduledByCommandAndDimmRank[Command::WRA][dimmrank.ID()]) // same DIMM + if (lastCommandStart == lastScheduledByCommandAndDimmRank[Command::WRA][dimmRank.ID()]) // same DIMM { - if (lastBurstLengthByCommandAndDimmRank[Command::WRA][dimmrank.ID()] == 32) + if (lastBurstLengthByCommandAndDimmRank[Command::WRA][dimmRank.ID()] == 32) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRWR_dpr + tBURST16); else earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRWR_dpr); @@ -511,15 +514,15 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC); - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::ACT][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::ACT][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRD_L_slr); - lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::ACT][logicalrank.ID()]; + lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::ACT][logicalRank.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRD_S_slr); - lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::ACT][physicalrank.ID()]; + lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::ACT][physicalRank.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRD_dlr); @@ -540,7 +543,7 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP - cmdLengthDiff); - lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::PREA][logicalrank.ID()]; + lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::PREA][logicalRank.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP - cmdLengthDiff); @@ -548,7 +551,7 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP - cmdLengthDiff); - lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::REFA][logicalrank.ID()]; + lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::REFA][logicalRank.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC_slr - cmdLengthDiff); @@ -560,20 +563,20 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr // TODO: No tRFCsb_dlr between REFSB and ACT? - lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::REFSB][logicalrank.ID()]; + lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::REFSB][logicalRank.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tREFSBRD_slr - cmdLengthDiff); - lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::REFSB][physicalrank.ID()]; + lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::REFSB][physicalRank.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tREFSBRD_dlr - cmdLengthDiff); - if (last4ActivatesLogical[logicalrank.ID()].size() >= 4) - earliestTimeToStart = std::max(earliestTimeToStart, last4ActivatesLogical[logicalrank.ID()].front() + if (last4ActivatesLogical[logicalRank.ID()].size() >= 4) + earliestTimeToStart = std::max(earliestTimeToStart, last4ActivatesLogical[logicalRank.ID()].front() + memSpec->tFAW_slr - memSpec->longCmdOffset); - if (last4ActivatesPhysical[physicalrank.ID()].size() >= 4) - earliestTimeToStart = std::max(earliestTimeToStart, last4ActivatesPhysical[physicalrank.ID()].front() + if (last4ActivatesPhysical[physicalRank.ID()].size() >= 4) + earliestTimeToStart = std::max(earliestTimeToStart, last4ActivatesPhysical[physicalRank.ID()].front() + memSpec->tFAW_dlr - memSpec->longCmdOffset); } else if (command == Command::PRE) @@ -595,55 +598,55 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + cmdLengthDiff); } - lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::PRE][physicalrank.ID()]; + lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::PRE][physicalRank.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPPD); - lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::PREA][physicalrank.ID()]; + lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::PREA][physicalRank.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPPD); - lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::PRESB][physicalrank.ID()]; + lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::PRESB][physicalRank.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPPD); } else if (command == Command::PREA) { - lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::ACT][logicalrank.ID()]; + lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::ACT][logicalRank.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + cmdLengthDiff); - lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::RD][logicalrank.ID()]; + lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::RD][logicalRank.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + cmdLengthDiff); - lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::RDA][logicalrank.ID()]; + lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::RDA][logicalRank.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + cmdLengthDiff); - lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::WR][logicalrank.ID()]; + lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::WR][logicalRank.ID()]; if (lastCommandStart != sc_max_time()) { - if (lastBurstLengthByCommandAndLogicalRank[Command::WR][logicalrank.ID()] == 32) + if (lastBurstLengthByCommandAndLogicalRank[Command::WR][logicalRank.ID()] == 32) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + tBURST16 + cmdLengthDiff); else earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + cmdLengthDiff); } - lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::WRA][logicalrank.ID()]; + lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::WRA][logicalRank.ID()]; if (lastCommandStart != sc_max_time()) { - if (lastBurstLengthByCommandAndLogicalRank[Command::WRA][logicalrank.ID()]) + if (lastBurstLengthByCommandAndLogicalRank[Command::WRA][logicalRank.ID()]) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + tBURST16 + cmdLengthDiff); else earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + cmdLengthDiff); } - lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::PRE][physicalrank.ID()]; + lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::PRE][physicalRank.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPPD); - lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::PREA][physicalrank.ID()]; + lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::PREA][physicalRank.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPPD); @@ -681,52 +684,52 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + cmdLengthDiff); } - lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::PRE][physicalrank.ID()]; + lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::PRE][physicalRank.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPPD); // PREA tRP - lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::PRESB][physicalrank.ID()]; + lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::PRESB][physicalRank.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPPD); } else if (command == Command::REFA) { - lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::ACT][logicalrank.ID()]; + lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::ACT][logicalRank.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC + cmdLengthDiff); - lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::RDA][physicalrank.ID()]; + lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::RDA][physicalRank.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDAACT + cmdLengthDiff); - lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::WRA][logicalrank.ID()]; + lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::WRA][logicalRank.ID()]; if (lastCommandStart != sc_max_time()) { - if (lastBurstLengthByCommandAndLogicalRank[Command::WRA][logicalrank.ID()] == 32) + if (lastBurstLengthByCommandAndLogicalRank[Command::WRA][logicalRank.ID()] == 32) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + tBURST16 + memSpec->tRP + cmdLengthDiff); else earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tRP + cmdLengthDiff); } - lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::PRE][logicalrank.ID()]; + lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::PRE][logicalRank.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); - lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::PREA][logicalrank.ID()]; + lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::PREA][logicalRank.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); - lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::REFA][logicalrank.ID()]; + lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::REFA][logicalRank.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC_slr); - lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::REFA][physicalrank.ID()]; + lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::REFA][physicalRank.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC_dlr); - lastCommandStart = lastScheduledByCommandAndDimmRank[Command::REFA][dimmrank.ID()]; + lastCommandStart = lastScheduledByCommandAndDimmRank[Command::REFA][dimmRank.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC_dpr); @@ -739,7 +742,7 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC + cmdLengthDiff); - lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::ACT][logicalrank.ID()]; + lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::ACT][logicalRank.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRD_L_slr + cmdLengthDiff); @@ -766,34 +769,34 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); - lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::REFA][logicalrank.ID()]; + lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::REFA][logicalRank.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC_slr); // TODO: check this - lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::REFA][physicalrank.ID()]; + lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::REFA][physicalRank.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC_dlr); // TODO: check this - lastCommandStart = lastScheduledByCommandAndDimmRank[Command::REFA][dimmrank.ID()]; + lastCommandStart = lastScheduledByCommandAndDimmRank[Command::REFA][dimmRank.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC_dpr); - lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::REFSB][logicalrank.ID()]; + lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::REFSB][logicalRank.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCsb_slr); - lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::REFSB][physicalrank.ID()]; + lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::REFSB][physicalRank.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCsb_dlr); - if (last4ActivatesLogical[logicalrank.ID()].size() >= 4) - earliestTimeToStart = std::max(earliestTimeToStart, last4ActivatesLogical[logicalrank.ID()].front() + if (last4ActivatesLogical[logicalRank.ID()].size() >= 4) + earliestTimeToStart = std::max(earliestTimeToStart, last4ActivatesLogical[logicalRank.ID()].front() + memSpec->tFAW_slr - memSpec->shortCmdOffset); - if (last4ActivatesPhysical[physicalrank.ID()].size() >= 4) - earliestTimeToStart = std::max(earliestTimeToStart, last4ActivatesPhysical[physicalrank.ID()].front() + if (last4ActivatesPhysical[physicalRank.ID()].size() >= 4) + earliestTimeToStart = std::max(earliestTimeToStart, last4ActivatesPhysical[physicalRank.ID()].front() + memSpec->tFAW_dlr - memSpec->shortCmdOffset); } else @@ -813,20 +816,23 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr return earliestTimeToStart; } -void CheckerDDR5::insert(Command command, Rank rank, BankGroup bankgroup, Bank bank, unsigned burstLength) +void CheckerDDR5::insert(Command command, tlm_generic_payload *payload) { - PRINTDEBUGMESSAGE("CheckerDDR5", "Changing state on bank " + std::to_string(bank.ID()) - + " command is " + commandToString(command)); - - Rank logicalRank = rank; + Rank logicalRank = DramExtension::getRank(payload); Rank physicalRank = Rank(logicalRank.ID() / memSpec->logicalRanksPerPhysicalRank); Rank dimmRank = Rank(physicalRank.ID() / memSpec->physicalRanksPerDIMMRank); - Bank bankInGroup = Bank(rank.ID() * memSpec->banksPerGroup + bank.ID() % memSpec->banksPerGroup); + BankGroup bankGroup = DramExtension::getBankGroup(payload); + Bank bank = DramExtension::getBank(payload); + Bank bankInGroup = Bank(logicalRank.ID() * memSpec->banksPerGroup + bank.ID() % memSpec->banksPerGroup); + unsigned burstLength = DramExtension::getBurstLength(payload); + + PRINTDEBUGMESSAGE("CheckerDDR5", "Changing state on bank " + std::to_string(bank.ID()) + + " command is " + commandToString(command)); lastScheduledByCommandAndDimmRank[command][dimmRank.ID()] = sc_time_stamp(); lastScheduledByCommandAndPhysicalRank[command][physicalRank.ID()] = sc_time_stamp(); lastScheduledByCommandAndLogicalRank[command][logicalRank.ID()] = sc_time_stamp(); - lastScheduledByCommandAndBankGroup[command][bankgroup.ID()] = sc_time_stamp(); + lastScheduledByCommandAndBankGroup[command][bankGroup.ID()] = sc_time_stamp(); lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp(); lastScheduledByCommand[command] = sc_time_stamp(); lastScheduledByCommandAndBankInGroup[command][bankInGroup.ID()] = sc_time_stamp(); @@ -836,7 +842,7 @@ void CheckerDDR5::insert(Command command, Rank rank, BankGroup bankgroup, Bank b lastBurstLengthByCommandAndDimmRank[command][dimmRank.ID()] = burstLength; lastBurstLengthByCommandAndPhysicalRank[command][physicalRank.ID()] = burstLength; lastBurstLengthByCommandAndLogicalRank[command][logicalRank.ID()] = burstLength; - lastBurstLengthByCommandAndBankGroup[command][bankgroup.ID()] = burstLength; + lastBurstLengthByCommandAndBankGroup[command][bankGroup.ID()] = burstLength; lastBurstLengthByCommandAndBank[command][bank.ID()] = burstLength; lastBurstLengthByCommand[command] = burstLength; lastBurstLengthByCommandAndBankInGroup[command][bankInGroup.ID()] = burstLength; diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR5.h b/DRAMSys/library/src/controller/checker/CheckerDDR5.h index 7717b052..a71ee310 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR5.h +++ b/DRAMSys/library/src/controller/checker/CheckerDDR5.h @@ -46,9 +46,8 @@ class CheckerDDR5 final : public CheckerIF { public: CheckerDDR5(); - virtual sc_time timeToSatisfyConstraints(Command, Rank = Rank(0), - BankGroup = BankGroup(0), Bank = Bank(0), unsigned burstLength = 0) const override; - virtual void insert(Command, Rank, BankGroup, Bank, unsigned) override; + virtual sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; + virtual void insert(Command command, tlm::tlm_generic_payload *payload) override; private: const MemSpecDDR5 *memSpec; diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp b/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp index a32251f1..48ec6cb6 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp @@ -34,6 +34,8 @@ #include "CheckerGDDR5.h" +using namespace tlm; + CheckerGDDR5::CheckerGDDR5() { Configuration &config = Configuration::getInstance(); @@ -64,8 +66,12 @@ CheckerGDDR5::CheckerGDDR5() tWRPRE = memSpec->tWL + tBURST + memSpec->tWR; } -sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank, unsigned) const +sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, tlm_generic_payload *payload) const { + Rank rank = DramExtension::getRank(payload); + BankGroup bankGroup = DramExtension::getBankGroup(payload); + Bank bank = DramExtension::getBank(payload); + sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); @@ -75,7 +81,7 @@ sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankG if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDRD); - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); @@ -87,7 +93,7 @@ sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankG if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST + memSpec->tRTRS); - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); @@ -106,7 +112,7 @@ sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankG earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE - memSpec->tRTP); } - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_L); @@ -118,7 +124,7 @@ sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankG if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_R); - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_L); @@ -160,7 +166,7 @@ sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankG if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR_R); - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); @@ -172,7 +178,7 @@ sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankG if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST + memSpec->tRTRS); - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); @@ -198,7 +204,7 @@ sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankG if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC); - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::ACT][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::ACT][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDL); @@ -352,7 +358,7 @@ sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankG if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC); - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::ACT][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::ACT][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDL); @@ -525,13 +531,17 @@ sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankG return earliestTimeToStart; } -void CheckerGDDR5::insert(Command command, Rank rank, BankGroup bankgroup, Bank bank, unsigned) +void CheckerGDDR5::insert(Command command, tlm_generic_payload *payload) { + Rank rank = DramExtension::getRank(payload); + BankGroup bankGroup = DramExtension::getBankGroup(payload); + Bank bank = DramExtension::getBank(payload); + PRINTDEBUGMESSAGE("CheckerGDDR5", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + commandToString(command)); lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp(); - lastScheduledByCommandAndBankGroup[command][bankgroup.ID()] = sc_time_stamp(); + lastScheduledByCommandAndBankGroup[command][bankGroup.ID()] = sc_time_stamp(); lastScheduledByCommandAndRank[command][rank.ID()] = sc_time_stamp(); lastScheduledByCommand[command] = sc_time_stamp(); lastCommandOnBus = sc_time_stamp(); diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR5.h b/DRAMSys/library/src/controller/checker/CheckerGDDR5.h index 30ab9287..86352aac 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR5.h +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR5.h @@ -45,9 +45,8 @@ class CheckerGDDR5 final : public CheckerIF { public: CheckerGDDR5(); - virtual sc_time timeToSatisfyConstraints(Command, Rank = Rank(0), - BankGroup = BankGroup(0), Bank = Bank(0), unsigned burstLength = 0) const override; - virtual void insert(Command, Rank, BankGroup, Bank, unsigned) override; + virtual sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; + virtual void insert(Command command, tlm::tlm_generic_payload *payload) override; private: const MemSpecGDDR5 *memSpec; diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp b/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp index 487184a0..7ccd85a0 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp @@ -34,6 +34,8 @@ #include "CheckerGDDR5X.h" +using namespace tlm; + CheckerGDDR5X::CheckerGDDR5X() { Configuration &config = Configuration::getInstance(); @@ -64,8 +66,12 @@ CheckerGDDR5X::CheckerGDDR5X() tWRPRE = memSpec->tWL + tBURST + memSpec->tWR; } -sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank, unsigned) const +sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, tlm_generic_payload *payload) const { + Rank rank = DramExtension::getRank(payload); + BankGroup bankGroup = DramExtension::getBankGroup(payload); + Bank bank = DramExtension::getBank(payload); + sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); @@ -75,7 +81,7 @@ sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, Rank rank, Bank if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDRD); - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); @@ -87,7 +93,7 @@ sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, Rank rank, Bank if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST + memSpec->tRTRS); - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); @@ -106,7 +112,7 @@ sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, Rank rank, Bank earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE - memSpec->tRTP); } - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_L); @@ -118,7 +124,7 @@ sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, Rank rank, Bank if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_R); - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_L); @@ -160,7 +166,7 @@ sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, Rank rank, Bank if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR_R); - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); @@ -172,7 +178,7 @@ sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, Rank rank, Bank if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST + memSpec->tRTRS); - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); @@ -198,7 +204,7 @@ sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, Rank rank, Bank if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC); - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::ACT][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::ACT][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDL); @@ -352,7 +358,7 @@ sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, Rank rank, Bank if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC); - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::ACT][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::ACT][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDL); @@ -525,13 +531,17 @@ sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, Rank rank, Bank return earliestTimeToStart; } -void CheckerGDDR5X::insert(Command command, Rank rank, BankGroup bankgroup, Bank bank, unsigned) +void CheckerGDDR5X::insert(Command command, tlm_generic_payload *payload) { + Rank rank = DramExtension::getRank(payload); + BankGroup bankGroup = DramExtension::getBankGroup(payload); + Bank bank = DramExtension::getBank(payload); + PRINTDEBUGMESSAGE("CheckerGDDR5X", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + commandToString(command)); lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp(); - lastScheduledByCommandAndBankGroup[command][bankgroup.ID()] = sc_time_stamp(); + lastScheduledByCommandAndBankGroup[command][bankGroup.ID()] = sc_time_stamp(); lastScheduledByCommandAndRank[command][rank.ID()] = sc_time_stamp(); lastScheduledByCommand[command] = sc_time_stamp(); lastCommandOnBus = sc_time_stamp(); diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR5X.h b/DRAMSys/library/src/controller/checker/CheckerGDDR5X.h index 652de82b..18f63ecd 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR5X.h +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR5X.h @@ -45,9 +45,8 @@ class CheckerGDDR5X final : public CheckerIF { public: CheckerGDDR5X(); - virtual sc_time timeToSatisfyConstraints(Command, Rank = Rank(0), - BankGroup = BankGroup(0), Bank = Bank(0), unsigned burstLength = 0) const override; - virtual void insert(Command, Rank, BankGroup, Bank, unsigned) override; + virtual sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; + virtual void insert(Command command, tlm::tlm_generic_payload *payload) override; private: const MemSpecGDDR5X *memSpec; diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp b/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp index f50504e6..4d8efdf2 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp @@ -34,6 +34,8 @@ #include "CheckerGDDR6.h" +using namespace tlm; + CheckerGDDR6::CheckerGDDR6() { Configuration &config = Configuration::getInstance(); @@ -63,8 +65,12 @@ CheckerGDDR6::CheckerGDDR6() tWRPRE = memSpec->tWL + tBURST + memSpec->tWR; } -sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank, unsigned) const +sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, tlm_generic_payload *payload) const { + Rank rank = DramExtension::getRank(payload); + BankGroup bankGroup = DramExtension::getBankGroup(payload); + Bank bank = DramExtension::getBank(payload); + sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); @@ -74,7 +80,7 @@ sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, Rank rank, BankG if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDRD); - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); @@ -86,7 +92,7 @@ sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, Rank rank, BankG if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST + memSpec->tRTRS); - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); @@ -105,7 +111,7 @@ sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, Rank rank, BankG earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE - memSpec->tRTP); } - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_L); @@ -117,7 +123,7 @@ sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, Rank rank, BankG if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_R); - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_L); @@ -159,7 +165,7 @@ sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, Rank rank, BankG if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR_R); - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); @@ -171,7 +177,7 @@ sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, Rank rank, BankG if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST + memSpec->tRTRS); - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); @@ -197,7 +203,7 @@ sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, Rank rank, BankG if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC); - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::ACT][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::ACT][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDL); @@ -348,7 +354,7 @@ sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, Rank rank, BankG if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC); - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::ACT][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::ACT][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDL); @@ -546,13 +552,17 @@ sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, Rank rank, BankG return earliestTimeToStart; } -void CheckerGDDR6::insert(Command command, Rank rank, BankGroup bankgroup, Bank bank, unsigned) +void CheckerGDDR6::insert(Command command, tlm_generic_payload *payload) { + Rank rank = DramExtension::getRank(payload); + BankGroup bankGroup = DramExtension::getBankGroup(payload); + Bank bank = DramExtension::getBank(payload); + PRINTDEBUGMESSAGE("CheckerGDDR6", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + commandToString(command)); lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp(); - lastScheduledByCommandAndBankGroup[command][bankgroup.ID()] = sc_time_stamp(); + lastScheduledByCommandAndBankGroup[command][bankGroup.ID()] = sc_time_stamp(); lastScheduledByCommandAndRank[command][rank.ID()] = sc_time_stamp(); lastScheduledByCommand[command] = sc_time_stamp(); lastCommandOnBus = sc_time_stamp(); diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR6.h b/DRAMSys/library/src/controller/checker/CheckerGDDR6.h index edd78a7c..cf60d503 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR6.h +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR6.h @@ -45,9 +45,8 @@ class CheckerGDDR6 final : public CheckerIF { public: CheckerGDDR6(); - virtual sc_time timeToSatisfyConstraints(Command, Rank = Rank(0), - BankGroup = BankGroup(0), Bank = Bank(0), unsigned burstLength = 0) const override; - virtual void insert(Command, Rank, BankGroup, Bank, unsigned) override; + virtual sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; + virtual void insert(Command command, tlm::tlm_generic_payload *payload) override; private: const MemSpecGDDR6 *memSpec; diff --git a/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp b/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp index 7472d0ad..e2167770 100644 --- a/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp @@ -34,6 +34,8 @@ #include "CheckerHBM2.h" +using namespace tlm; + CheckerHBM2::CheckerHBM2() { Configuration &config = Configuration::getInstance(); @@ -64,8 +66,12 @@ CheckerHBM2::CheckerHBM2() tWRRDL = memSpec->tWL + tBURST + memSpec->tWTRL; } -sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank, unsigned) const +sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, tlm_generic_payload *payload) const { + Rank rank = DramExtension::getRank(payload); + BankGroup bankGroup = DramExtension::getBankGroup(payload); + Bank bank = DramExtension::getBank(payload); + sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); @@ -75,7 +81,7 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, Rank rank, BankGr if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDRD + memSpec->tCK); - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); @@ -83,7 +89,7 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, Rank rank, BankGr if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); @@ -98,7 +104,7 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, Rank rank, BankGr earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE - memSpec->tRTP); } - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRDL); @@ -106,7 +112,7 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, Rank rank, BankGr if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRDS); - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRDL); @@ -134,7 +140,7 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, Rank rank, BankGr if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW); - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); @@ -142,7 +148,7 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, Rank rank, BankGr if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); @@ -162,7 +168,7 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, Rank rank, BankGr if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC); - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::ACT][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::ACT][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDL); @@ -313,7 +319,7 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, Rank rank, BankGr if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC + memSpec->tCK); - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::ACT][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::ACT][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDL + memSpec->tCK); @@ -500,13 +506,17 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, Rank rank, BankGr return earliestTimeToStart; } -void CheckerHBM2::insert(Command command, Rank rank, BankGroup bankgroup, Bank bank, unsigned) +void CheckerHBM2::insert(Command command, tlm_generic_payload *payload) { + Rank rank = DramExtension::getRank(payload); + BankGroup bankGroup = DramExtension::getBankGroup(payload); + Bank bank = DramExtension::getBank(payload); + PRINTDEBUGMESSAGE("CheckerHBM2", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + commandToString(command)); lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp(); - lastScheduledByCommandAndBankGroup[command][bankgroup.ID()] = sc_time_stamp(); + lastScheduledByCommandAndBankGroup[command][bankGroup.ID()] = sc_time_stamp(); lastScheduledByCommandAndRank[command][rank.ID()] = sc_time_stamp(); lastScheduledByCommand[command] = sc_time_stamp(); diff --git a/DRAMSys/library/src/controller/checker/CheckerHBM2.h b/DRAMSys/library/src/controller/checker/CheckerHBM2.h index a68a5f86..22fd6980 100644 --- a/DRAMSys/library/src/controller/checker/CheckerHBM2.h +++ b/DRAMSys/library/src/controller/checker/CheckerHBM2.h @@ -45,9 +45,8 @@ class CheckerHBM2 final : public CheckerIF { public: CheckerHBM2(); - virtual sc_time timeToSatisfyConstraints(Command, Rank = Rank(0), - BankGroup = BankGroup(0), Bank = Bank(0), unsigned burstLength = 0) const override; - virtual void insert(Command, Rank, BankGroup, Bank, unsigned) override; + virtual sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; + virtual void insert(Command command, tlm::tlm_generic_payload *payload) override; private: const MemSpecHBM2 *memSpec; diff --git a/DRAMSys/library/src/controller/checker/CheckerIF.h b/DRAMSys/library/src/controller/checker/CheckerIF.h index a930d797..9ca75c13 100644 --- a/DRAMSys/library/src/controller/checker/CheckerIF.h +++ b/DRAMSys/library/src/controller/checker/CheckerIF.h @@ -46,9 +46,8 @@ class CheckerIF public: virtual ~CheckerIF() {} - virtual sc_time timeToSatisfyConstraints(Command, Rank = Rank(0), - BankGroup = BankGroup(0), Bank = Bank(0), unsigned burstLength = 0) const = 0; - virtual void insert(Command, Rank, BankGroup, Bank, unsigned) = 0; + virtual sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const = 0; + virtual void insert(Command command, tlm::tlm_generic_payload *payload) = 0; }; #endif // CHECKERIF_H diff --git a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp index 2dfc9456..6acee003 100644 --- a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp @@ -34,6 +34,8 @@ #include "CheckerLPDDR4.h" +using namespace tlm; + CheckerLPDDR4::CheckerLPDDR4() { Configuration &config = Configuration::getInstance(); @@ -66,8 +68,11 @@ CheckerLPDDR4::CheckerLPDDR4() tREFPDEN = memSpec->tCK + memSpec->tCMDCKE; } -sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank, unsigned) const +sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, tlm_generic_payload *payload) const { + Rank rank = DramExtension::getRank(payload); + Bank bank = DramExtension::getBank(payload); + sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); @@ -496,8 +501,11 @@ sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, Rank rank, Bank return earliestTimeToStart; } -void CheckerLPDDR4::insert(Command command, Rank rank, BankGroup, Bank bank, unsigned) +void CheckerLPDDR4::insert(Command command, tlm_generic_payload *payload) { + Rank rank = DramExtension::getRank(payload); + Bank bank = DramExtension::getBank(payload); + PRINTDEBUGMESSAGE("CheckerLPDDR4", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + commandToString(command)); diff --git a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h index 3fe5e506..7cb40a13 100644 --- a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h +++ b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h @@ -45,9 +45,8 @@ class CheckerLPDDR4 final : public CheckerIF { public: CheckerLPDDR4(); - virtual sc_time timeToSatisfyConstraints(Command, Rank = Rank(0), - BankGroup = BankGroup(0), Bank = Bank(0), unsigned burstLength = 0) const override; - virtual void insert(Command, Rank, BankGroup, Bank, unsigned) override; + virtual sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; + virtual void insert(Command command, tlm::tlm_generic_payload *payload) override; private: const MemSpecLPDDR4 *memSpec; diff --git a/DRAMSys/library/src/controller/checker/CheckerSTTMRAM.cpp b/DRAMSys/library/src/controller/checker/CheckerSTTMRAM.cpp index bb157ee7..7c8438e6 100644 --- a/DRAMSys/library/src/controller/checker/CheckerSTTMRAM.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerSTTMRAM.cpp @@ -34,6 +34,8 @@ #include "CheckerSTTMRAM.h" +using namespace tlm; + CheckerSTTMRAM::CheckerSTTMRAM() { Configuration &config = Configuration::getInstance(); @@ -60,8 +62,11 @@ CheckerSTTMRAM::CheckerSTTMRAM() tWRAPDEN = memSpec->tWL + tBURST + memSpec->tWR + memSpec->tCK; } -sc_time CheckerSTTMRAM::timeToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank, unsigned) const +sc_time CheckerSTTMRAM::timeToSatisfyConstraints(Command command, tlm_generic_payload *payload) const { + Rank rank = DramExtension::getRank(payload); + Bank bank = DramExtension::getBank(payload); + sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); @@ -368,8 +373,11 @@ sc_time CheckerSTTMRAM::timeToSatisfyConstraints(Command command, Rank rank, Ban return earliestTimeToStart; } -void CheckerSTTMRAM::insert(Command command, Rank rank, BankGroup, Bank bank, unsigned) +void CheckerSTTMRAM::insert(Command command, tlm_generic_payload *payload) { + Rank rank = DramExtension::getRank(payload); + Bank bank = DramExtension::getBank(payload); + PRINTDEBUGMESSAGE("CheckerSTTMRAM", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + commandToString(command)); diff --git a/DRAMSys/library/src/controller/checker/CheckerSTTMRAM.h b/DRAMSys/library/src/controller/checker/CheckerSTTMRAM.h index 50d48d53..34f18db6 100644 --- a/DRAMSys/library/src/controller/checker/CheckerSTTMRAM.h +++ b/DRAMSys/library/src/controller/checker/CheckerSTTMRAM.h @@ -45,9 +45,8 @@ class CheckerSTTMRAM final : public CheckerIF { public: CheckerSTTMRAM(); - virtual sc_time timeToSatisfyConstraints(Command, Rank = Rank(0), - BankGroup = BankGroup(0), Bank = Bank(0), unsigned burstLength = 0) const override; - virtual void insert(Command, Rank, BankGroup, Bank, unsigned) override; + virtual sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; + virtual void insert(Command command, tlm::tlm_generic_payload *payload) override; private: const MemSpecSTTMRAM *memSpec; diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp b/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp index 16985f5d..bde72d2b 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp @@ -34,6 +34,8 @@ #include "CheckerWideIO.h" +using namespace tlm; + CheckerWideIO::CheckerWideIO() { Configuration &config = Configuration::getInstance(); @@ -60,8 +62,11 @@ CheckerWideIO::CheckerWideIO() tWRAPDEN = memSpec->tWL + tBURST + memSpec->tWR; // + memSpec->tCK; ?? } -sc_time CheckerWideIO::timeToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank, unsigned) const +sc_time CheckerWideIO::timeToSatisfyConstraints(Command command, tlm_generic_payload *payload) const { + Rank rank = DramExtension::getRank(payload); + Bank bank = DramExtension::getBank(payload); + sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); @@ -385,8 +390,11 @@ sc_time CheckerWideIO::timeToSatisfyConstraints(Command command, Rank rank, Bank return earliestTimeToStart; } -void CheckerWideIO::insert(Command command, Rank rank, BankGroup, Bank bank, unsigned) +void CheckerWideIO::insert(Command command, tlm_generic_payload *payload) { + Rank rank = DramExtension::getRank(payload); + Bank bank = DramExtension::getBank(payload); + PRINTDEBUGMESSAGE("CheckerWideIO", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + commandToString(command)); diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO.h b/DRAMSys/library/src/controller/checker/CheckerWideIO.h index c8b145a6..8e626bf3 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO.h +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO.h @@ -45,9 +45,8 @@ class CheckerWideIO final : public CheckerIF { public: CheckerWideIO(); - virtual sc_time timeToSatisfyConstraints(Command, Rank = Rank(0), - BankGroup = BankGroup(0), Bank = Bank(0), unsigned burstLength = 0) const override; - virtual void insert(Command, Rank, BankGroup, Bank, unsigned) override; + virtual sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; + virtual void insert(Command command, tlm::tlm_generic_payload *payload) override; private: const MemSpecWideIO *memSpec; diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp b/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp index 10e75682..bcf0518e 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp @@ -34,6 +34,8 @@ #include "CheckerWideIO2.h" +using namespace tlm; + CheckerWideIO2::CheckerWideIO2() { Configuration &config = Configuration::getInstance(); @@ -61,8 +63,11 @@ CheckerWideIO2::CheckerWideIO2() tWRRD_R = memSpec->tWL + memSpec->tCK + tBURST + memSpec->tRTRS - memSpec->tRL; } -sc_time CheckerWideIO2::timeToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank, unsigned) const +sc_time CheckerWideIO2::timeToSatisfyConstraints(Command command, tlm_generic_payload *payload) const { + Rank rank = DramExtension::getRank(payload); + Bank bank = DramExtension::getBank(payload); + sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); @@ -463,8 +468,11 @@ sc_time CheckerWideIO2::timeToSatisfyConstraints(Command command, Rank rank, Ban return earliestTimeToStart; } -void CheckerWideIO2::insert(Command command, Rank rank, BankGroup, Bank bank, unsigned) +void CheckerWideIO2::insert(Command command, tlm_generic_payload *payload) { + Rank rank = DramExtension::getRank(payload); + Bank bank = DramExtension::getBank(payload); + PRINTDEBUGMESSAGE("CheckerWideIO2", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + commandToString(command)); diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO2.h b/DRAMSys/library/src/controller/checker/CheckerWideIO2.h index a1e32636..851811af 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO2.h +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO2.h @@ -45,9 +45,8 @@ class CheckerWideIO2 final : public CheckerIF { public: CheckerWideIO2(); - virtual sc_time timeToSatisfyConstraints(Command, Rank = Rank(0), - BankGroup = BankGroup(0), Bank = Bank(0), unsigned burstLength = 0) const override; - virtual void insert(Command, Rank, BankGroup, Bank, unsigned) override; + virtual sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; + virtual void insert(Command command, tlm::tlm_generic_payload *payload) override; private: const MemSpecWideIO2 *memSpec; diff --git a/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.cpp b/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.cpp index 4ae2a175..80ce14b7 100644 --- a/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.cpp +++ b/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.cpp @@ -90,7 +90,7 @@ sc_time PowerDownManagerStaggered::start() else if (state == State::ExtraRefresh) nextCommand = Command::REFA; - timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, BankGroup(0), Bank(0)); + timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, &powerDownPayload); } else if (entryTriggered) { @@ -99,12 +99,12 @@ sc_time PowerDownManagerStaggered::start() else nextCommand = Command::PDEP; - timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, BankGroup(0), Bank(0)); + timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, &powerDownPayload); } else if (enterSelfRefresh) { nextCommand = Command::SREFEN; - timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, BankGroup(0), Bank(0)); + timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, &powerDownPayload); } return timeToSchedule; diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerAllBank.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerAllBank.cpp index 44c97ea1..11978b82 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerAllBank.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerAllBank.cpp @@ -41,7 +41,7 @@ using namespace tlm; RefreshManagerAllBank::RefreshManagerAllBank(std::vector &bankMachinesOnRank, PowerDownManagerIF *powerDownManager, Rank rank, CheckerIF *checker) - : bankMachinesOnRank(bankMachinesOnRank), powerDownManager(powerDownManager), rank(rank), checker(checker) + : bankMachinesOnRank(bankMachinesOnRank), powerDownManager(powerDownManager), checker(checker) { Configuration &config = Configuration::getInstance(); memSpec = config.memSpec; @@ -55,8 +55,7 @@ RefreshManagerAllBank::RefreshManagerAllBank(std::vector &bankMac CommandTuple::Type RefreshManagerAllBank::getNextCommand() { - return CommandTuple::Type(nextCommand, &refreshPayload, - std::max(timeToSchedule, sc_time_stamp())); + return {nextCommand, &refreshPayload, std::max(timeToSchedule, sc_time_stamp())}; } sc_time RefreshManagerAllBank::start() @@ -108,7 +107,7 @@ sc_time RefreshManagerAllBank::start() else nextCommand = Command::REFA; - timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, BankGroup(0), Bank(0)); + timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, &refreshPayload); return timeToSchedule; } else // if (state == RmState::Pulledin) @@ -132,7 +131,7 @@ sc_time RefreshManagerAllBank::start() else { nextCommand = Command::REFA; - timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, BankGroup(0), Bank(0)); + timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, &refreshPayload); return timeToSchedule; } } diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerAllBank.h b/DRAMSys/library/src/controller/refresh/RefreshManagerAllBank.h index 8474e688..a9605e87 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerAllBank.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerAllBank.h @@ -46,9 +46,9 @@ class RefreshManagerAllBank final : public RefreshManagerIF public: RefreshManagerAllBank(std::vector &, PowerDownManagerIF *, Rank, CheckerIF *); - virtual CommandTuple::Type getNextCommand() override; - virtual sc_time start() override; - virtual void updateState(Command) override; + CommandTuple::Type getNextCommand() override; + sc_time start() override; + void updateState(Command) override; private: enum class State {Regular, Pulledin} state = State::Regular; @@ -58,7 +58,6 @@ private: tlm::tlm_generic_payload refreshPayload; sc_time timeForNextTrigger = sc_max_time(); sc_time timeToSchedule = sc_max_time(); - Rank rank; CheckerIF *checker; Command nextCommand = Command::NOP; diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h b/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h index d0df2806..5b585700 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h @@ -44,9 +44,9 @@ class RefreshManagerDummy final : public RefreshManagerIF { public: - virtual CommandTuple::Type getNextCommand() override; - virtual sc_time start() override; - virtual void updateState(Command) override {} + CommandTuple::Type getNextCommand() override; + sc_time start() override; + void updateState(Command) override {} }; #endif // REFRESHMANAGERDUMMY_H diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerIF.h b/DRAMSys/library/src/controller/refresh/RefreshManagerIF.h index 3f6684f8..a8d56538 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerIF.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerIF.h @@ -44,14 +44,14 @@ class RefreshManagerIF { public: - virtual ~RefreshManagerIF() {} + virtual ~RefreshManagerIF() = default; virtual CommandTuple::Type getNextCommand() = 0; virtual sc_time start() = 0; virtual void updateState(Command) = 0; protected: - sc_time getTimeForFirstTrigger(sc_time refreshInterval, Rank rank, unsigned numberOfRanks) + static sc_time getTimeForFirstTrigger(sc_time refreshInterval, Rank rank, unsigned numberOfRanks) { // Calculate bit-reversal rank ID unsigned rankID = rank.ID(); diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerPerBank.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerPerBank.cpp index 1b2fe232..0c692f0d 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerPerBank.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerPerBank.cpp @@ -41,7 +41,7 @@ using namespace tlm; RefreshManagerPerBank::RefreshManagerPerBank(std::vector &bankMachinesOnRank, PowerDownManagerIF *powerDownManager, Rank rank, CheckerIF *checker) - : bankMachinesOnRank(bankMachinesOnRank), powerDownManager(powerDownManager), rank(rank), checker(checker) + : powerDownManager(powerDownManager), checker(checker) { Configuration &config = Configuration::getInstance(); memSpec = config.memSpec; @@ -64,9 +64,9 @@ RefreshManagerPerBank::RefreshManagerPerBank(std::vector &bankMac CommandTuple::Type RefreshManagerPerBank::getNextCommand() { - return CommandTuple::Type(nextCommand, + return {nextCommand, &refreshPayloads[currentBankMachine->getBank().ID() % memSpec->banksPerRank], - std::max(timeToSchedule, sc_time_stamp())); + std::max(timeToSchedule, sc_time_stamp())}; } sc_time RefreshManagerPerBank::start() @@ -129,8 +129,8 @@ sc_time RefreshManagerPerBank::start() } } - timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, - currentBankMachine->getBankGroup(), currentBankMachine->getBank()); + timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, + &refreshPayloads[currentBankMachine->getBank().ID()]); return timeToSchedule; } } @@ -162,8 +162,8 @@ sc_time RefreshManagerPerBank::start() else nextCommand = Command::REFB; - timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, - currentBankMachine->getBankGroup(), currentBankMachine->getBank()); + timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, + &refreshPayloads[currentBankMachine->getBank().ID()]); return timeToSchedule; } } diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerPerBank.h b/DRAMSys/library/src/controller/refresh/RefreshManagerPerBank.h index b8fabcd1..a0b619ee 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerPerBank.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerPerBank.h @@ -48,19 +48,17 @@ class RefreshManagerPerBank final : public RefreshManagerIF public: RefreshManagerPerBank(std::vector &, PowerDownManagerIF *, Rank, CheckerIF *); - virtual CommandTuple::Type getNextCommand() override; - virtual sc_time start() override; - virtual void updateState(Command) override; + CommandTuple::Type getNextCommand() override; + sc_time start() override; + void updateState(Command) override; private: enum class State {Regular, Pulledin} state = State::Regular; const MemSpec *memSpec; - std::vector &bankMachinesOnRank; PowerDownManagerIF *powerDownManager; std::vector refreshPayloads; sc_time timeForNextTrigger = sc_max_time(); sc_time timeToSchedule = sc_max_time(); - Rank rank; CheckerIF *checker; Command nextCommand = Command::NOP; diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerSameBank.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerSameBank.cpp index 484d652b..54c27299 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerSameBank.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerSameBank.cpp @@ -41,21 +41,24 @@ using namespace tlm; RefreshManagerSameBank::RefreshManagerSameBank(std::vector &bankMachinesOnRank, PowerDownManagerIF *powerDownManager, Rank rank, CheckerIF *checker) - : bankMachinesOnRank(bankMachinesOnRank), powerDownManager(powerDownManager), rank(rank), checker(checker) + : powerDownManager(powerDownManager), checker(checker) { Configuration &config = Configuration::getInstance(); memSpec = config.memSpec; timeForNextTrigger = getTimeForFirstTrigger(memSpec->getRefreshIntervalSB(), rank, memSpec->numberOfRanks); + // each same-bank group has one payload (e.g. 0-4-8-12-16-20-24-28) refreshPayloads = std::vector(memSpec->banksPerGroup); for (unsigned bankID = 0; bankID < memSpec->banksPerGroup; bankID++) { + // rank 0: bank group 0, bank 0 - 3; rank 1: bank group 8, bank 32 - 35 setUpDummy(refreshPayloads[bankID], 0, rank, bankMachinesOnRank[bankID]->getBankGroup(), bankMachinesOnRank[bankID]->getBank()); - allBankMachines.push_back(std::vector(memSpec->groupsPerRank)); + allBankMachines.emplace_back(std::vector(memSpec->groupsPerRank)); } + // allBankMachines: ((0-4-8-12-16-20-24-28), (1-5-9-13-17-21-25-29), ...) std::list>::iterator it = allBankMachines.begin(); for (unsigned bankID = 0; bankID < memSpec->banksPerGroup; bankID++) { @@ -73,9 +76,9 @@ RefreshManagerSameBank::RefreshManagerSameBank(std::vector &bankM CommandTuple::Type RefreshManagerSameBank::getNextCommand() { - return CommandTuple::Type(nextCommand, + return {nextCommand, &refreshPayloads[currentIterator->front()->getBank().ID() % memSpec->banksPerGroup], - std::max(timeToSchedule, sc_time_stamp())); + std::max(timeToSchedule, sc_time_stamp())}; } sc_time RefreshManagerSameBank::start() @@ -148,8 +151,8 @@ sc_time RefreshManagerSameBank::start() skipSelection = true; } - timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, - currentIterator->front()->getBankGroup(), currentIterator->front()->getBank()); + timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, + &refreshPayloads[currentIterator->front()->getBank().ID() % memSpec->banksPerGroup]); return timeToSchedule; } } @@ -195,8 +198,8 @@ sc_time RefreshManagerSameBank::start() } } - timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, - currentIterator->front()->getBankGroup(), currentIterator->front()->getBank()); + timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, + &refreshPayloads[currentIterator->front()->getBank().ID() % memSpec->banksPerGroup]); return timeToSchedule; } } diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerSameBank.h b/DRAMSys/library/src/controller/refresh/RefreshManagerSameBank.h index 062ae8ee..7260242f 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerSameBank.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerSameBank.h @@ -48,19 +48,17 @@ class RefreshManagerSameBank final : public RefreshManagerIF public: RefreshManagerSameBank(std::vector &, PowerDownManagerIF *, Rank, CheckerIF *); - virtual CommandTuple::Type getNextCommand() override; - virtual sc_time start() override; - virtual void updateState(Command) override; + CommandTuple::Type getNextCommand() override; + sc_time start() override; + void updateState(Command) override; private: enum class State {Regular, Pulledin} state = State::Regular; const MemSpec *memSpec; - std::vector &bankMachinesOnRank; PowerDownManagerIF *powerDownManager; std::vector refreshPayloads; sc_time timeForNextTrigger = sc_max_time(); sc_time timeToSchedule = sc_max_time(); - Rank rank; CheckerIF *checker; Command nextCommand = Command::NOP; From 2256d03c5871df2be0becaec960985c930f43b18 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Thu, 20 May 2021 16:19:31 +0200 Subject: [PATCH 4/6] Code refactoring. --- .../library/src/controller/checker/CheckerDDR3.h | 4 ++-- .../library/src/controller/checker/CheckerDDR4.h | 4 ++-- .../library/src/controller/checker/CheckerDDR5.h | 4 ++-- .../src/controller/checker/CheckerGDDR5.h | 4 ++-- .../src/controller/checker/CheckerGDDR5X.h | 4 ++-- .../src/controller/checker/CheckerGDDR6.h | 4 ++-- .../library/src/controller/checker/CheckerHBM2.h | 4 ++-- .../library/src/controller/checker/CheckerIF.h | 2 +- .../src/controller/checker/CheckerLPDDR4.h | 4 ++-- .../src/controller/checker/CheckerSTTMRAM.h | 4 ++-- .../src/controller/checker/CheckerWideIO.h | 4 ++-- .../src/controller/checker/CheckerWideIO2.h | 4 ++-- DRAMSys/library/src/controller/cmdmux/CmdMuxIF.h | 2 +- .../src/controller/cmdmux/CmdMuxOldest.cpp | 4 ++-- .../library/src/controller/cmdmux/CmdMuxOldest.h | 4 ++-- .../src/controller/cmdmux/CmdMuxStrict.cpp | 4 ++-- .../library/src/controller/cmdmux/CmdMuxStrict.h | 4 ++-- .../powerdown/PowerDownManagerDummy.cpp | 2 +- .../controller/powerdown/PowerDownManagerDummy.h | 14 +++++++------- .../controller/powerdown/PowerDownManagerIF.h | 2 +- .../powerdown/PowerDownManagerStaggered.cpp | 2 +- .../powerdown/PowerDownManagerStaggered.h | 12 ++++++------ .../src/controller/respqueue/RespQueueFifo.h | 6 +++--- .../src/controller/respqueue/RespQueueIF.h | 2 +- .../src/controller/respqueue/RespQueueReorder.h | 6 +++--- .../controller/scheduler/BufferCounterBankwise.h | 8 ++++---- .../scheduler/BufferCounterReadWrite.h | 10 +++++----- .../controller/scheduler/BufferCounterShared.h | 10 +++++----- .../src/controller/scheduler/SchedulerFifo.h | 16 ++++++++-------- .../src/controller/scheduler/SchedulerFrFcfs.cpp | 10 +++++----- .../src/controller/scheduler/SchedulerFrFcfs.h | 16 ++++++++-------- .../controller/scheduler/SchedulerFrFcfsGrp.cpp | 6 +++--- .../controller/scheduler/SchedulerFrFcfsGrp.h | 16 ++++++++-------- 33 files changed, 101 insertions(+), 101 deletions(-) diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.h b/DRAMSys/library/src/controller/checker/CheckerDDR3.h index ab3bb6ec..30eba198 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.h +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.h @@ -45,8 +45,8 @@ class CheckerDDR3 final : public CheckerIF { public: CheckerDDR3(); - virtual sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; - virtual void insert(Command command, tlm::tlm_generic_payload *payload) override; + sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; + void insert(Command command, tlm::tlm_generic_payload *payload) override; private: const MemSpecDDR3 *memSpec; diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR4.h b/DRAMSys/library/src/controller/checker/CheckerDDR4.h index 46c891d0..967849ae 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR4.h +++ b/DRAMSys/library/src/controller/checker/CheckerDDR4.h @@ -45,8 +45,8 @@ class CheckerDDR4 final : public CheckerIF { public: CheckerDDR4(); - virtual sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; - virtual void insert(Command command, tlm::tlm_generic_payload *payload) override; + sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; + void insert(Command command, tlm::tlm_generic_payload *payload) override; private: const MemSpecDDR4 *memSpec; diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR5.h b/DRAMSys/library/src/controller/checker/CheckerDDR5.h index a71ee310..5a15b314 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR5.h +++ b/DRAMSys/library/src/controller/checker/CheckerDDR5.h @@ -46,8 +46,8 @@ class CheckerDDR5 final : public CheckerIF { public: CheckerDDR5(); - virtual sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; - virtual void insert(Command command, tlm::tlm_generic_payload *payload) override; + sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; + void insert(Command command, tlm::tlm_generic_payload *payload) override; private: const MemSpecDDR5 *memSpec; diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR5.h b/DRAMSys/library/src/controller/checker/CheckerGDDR5.h index 86352aac..1cf50e9a 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR5.h +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR5.h @@ -45,8 +45,8 @@ class CheckerGDDR5 final : public CheckerIF { public: CheckerGDDR5(); - virtual sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; - virtual void insert(Command command, tlm::tlm_generic_payload *payload) override; + sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; + void insert(Command command, tlm::tlm_generic_payload *payload) override; private: const MemSpecGDDR5 *memSpec; diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR5X.h b/DRAMSys/library/src/controller/checker/CheckerGDDR5X.h index 18f63ecd..1ff2c756 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR5X.h +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR5X.h @@ -45,8 +45,8 @@ class CheckerGDDR5X final : public CheckerIF { public: CheckerGDDR5X(); - virtual sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; - virtual void insert(Command command, tlm::tlm_generic_payload *payload) override; + sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; + void insert(Command command, tlm::tlm_generic_payload *payload) override; private: const MemSpecGDDR5X *memSpec; diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR6.h b/DRAMSys/library/src/controller/checker/CheckerGDDR6.h index cf60d503..16d89bd4 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR6.h +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR6.h @@ -45,8 +45,8 @@ class CheckerGDDR6 final : public CheckerIF { public: CheckerGDDR6(); - virtual sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; - virtual void insert(Command command, tlm::tlm_generic_payload *payload) override; + sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; + void insert(Command command, tlm::tlm_generic_payload *payload) override; private: const MemSpecGDDR6 *memSpec; diff --git a/DRAMSys/library/src/controller/checker/CheckerHBM2.h b/DRAMSys/library/src/controller/checker/CheckerHBM2.h index 22fd6980..674b69a4 100644 --- a/DRAMSys/library/src/controller/checker/CheckerHBM2.h +++ b/DRAMSys/library/src/controller/checker/CheckerHBM2.h @@ -45,8 +45,8 @@ class CheckerHBM2 final : public CheckerIF { public: CheckerHBM2(); - virtual sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; - virtual void insert(Command command, tlm::tlm_generic_payload *payload) override; + sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; + void insert(Command command, tlm::tlm_generic_payload *payload) override; private: const MemSpecHBM2 *memSpec; diff --git a/DRAMSys/library/src/controller/checker/CheckerIF.h b/DRAMSys/library/src/controller/checker/CheckerIF.h index 9ca75c13..7b3e5eb7 100644 --- a/DRAMSys/library/src/controller/checker/CheckerIF.h +++ b/DRAMSys/library/src/controller/checker/CheckerIF.h @@ -44,7 +44,7 @@ class CheckerIF { public: - virtual ~CheckerIF() {} + virtual ~CheckerIF() = default; virtual sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const = 0; virtual void insert(Command command, tlm::tlm_generic_payload *payload) = 0; diff --git a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h index 7cb40a13..d952162a 100644 --- a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h +++ b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h @@ -45,8 +45,8 @@ class CheckerLPDDR4 final : public CheckerIF { public: CheckerLPDDR4(); - virtual sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; - virtual void insert(Command command, tlm::tlm_generic_payload *payload) override; + sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; + void insert(Command command, tlm::tlm_generic_payload *payload) override; private: const MemSpecLPDDR4 *memSpec; diff --git a/DRAMSys/library/src/controller/checker/CheckerSTTMRAM.h b/DRAMSys/library/src/controller/checker/CheckerSTTMRAM.h index 34f18db6..08a3d20c 100644 --- a/DRAMSys/library/src/controller/checker/CheckerSTTMRAM.h +++ b/DRAMSys/library/src/controller/checker/CheckerSTTMRAM.h @@ -45,8 +45,8 @@ class CheckerSTTMRAM final : public CheckerIF { public: CheckerSTTMRAM(); - virtual sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; - virtual void insert(Command command, tlm::tlm_generic_payload *payload) override; + sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; + void insert(Command command, tlm::tlm_generic_payload *payload) override; private: const MemSpecSTTMRAM *memSpec; diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO.h b/DRAMSys/library/src/controller/checker/CheckerWideIO.h index 8e626bf3..22f0e85f 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO.h +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO.h @@ -45,8 +45,8 @@ class CheckerWideIO final : public CheckerIF { public: CheckerWideIO(); - virtual sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; - virtual void insert(Command command, tlm::tlm_generic_payload *payload) override; + sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; + void insert(Command command, tlm::tlm_generic_payload *payload) override; private: const MemSpecWideIO *memSpec; diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO2.h b/DRAMSys/library/src/controller/checker/CheckerWideIO2.h index 851811af..d7d31998 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO2.h +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO2.h @@ -45,8 +45,8 @@ class CheckerWideIO2 final : public CheckerIF { public: CheckerWideIO2(); - virtual sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; - virtual void insert(Command command, tlm::tlm_generic_payload *payload) override; + sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; + void insert(Command command, tlm::tlm_generic_payload *payload) override; private: const MemSpecWideIO2 *memSpec; diff --git a/DRAMSys/library/src/controller/cmdmux/CmdMuxIF.h b/DRAMSys/library/src/controller/cmdmux/CmdMuxIF.h index 7134f3cb..4e58935b 100644 --- a/DRAMSys/library/src/controller/cmdmux/CmdMuxIF.h +++ b/DRAMSys/library/src/controller/cmdmux/CmdMuxIF.h @@ -44,7 +44,7 @@ class CmdMuxIF { public: - virtual ~CmdMuxIF() {} + virtual ~CmdMuxIF() = default; virtual CommandTuple::Type selectCommand(const ReadyCommands &) = 0; }; diff --git a/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.cpp b/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.cpp index a64bde58..46e82a44 100644 --- a/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.cpp +++ b/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.cpp @@ -71,7 +71,7 @@ CommandTuple::Type CmdMuxOldest::selectCommand(const ReadyCommands &readyCommand std::get(*result) == sc_time_stamp()) return *result; else - return CommandTuple::Type(Command::NOP, nullptr, sc_max_time()); + return {Command::NOP, nullptr, sc_max_time()}; } @@ -177,5 +177,5 @@ CommandTuple::Type CmdMuxOldestRasCas::selectCommand(const ReadyCommands &readyC std::get(*result) == sc_time_stamp()) return *result; else - return CommandTuple::Type(Command::NOP, nullptr, sc_max_time()); + return {Command::NOP, nullptr, sc_max_time()}; } diff --git a/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.h b/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.h index 5f8ce661..0ab8a715 100644 --- a/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.h +++ b/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.h @@ -42,7 +42,7 @@ class CmdMuxOldest : public CmdMuxIF { public: CmdMuxOldest(); - virtual CommandTuple::Type selectCommand(const ReadyCommands &) override; + CommandTuple::Type selectCommand(const ReadyCommands &) override; private: const MemSpec *memSpec; @@ -53,7 +53,7 @@ class CmdMuxOldestRasCas : public CmdMuxIF { public: CmdMuxOldestRasCas(); - virtual CommandTuple::Type selectCommand(const ReadyCommands &) override; + CommandTuple::Type selectCommand(const ReadyCommands &) override; private: const MemSpec *memSpec; diff --git a/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp b/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp index ce9e97d6..c2517fe2 100644 --- a/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp +++ b/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp @@ -81,7 +81,7 @@ CommandTuple::Type CmdMuxStrict::selectCommand(const ReadyCommands &readyCommand return *result; } else - return CommandTuple::Type(Command::NOP, nullptr, sc_max_time()); + return {Command::NOP, nullptr, sc_max_time()}; } @@ -180,5 +180,5 @@ CommandTuple::Type CmdMuxStrictRasCas::selectCommand(const ReadyCommands &readyC return *result; } else - return CommandTuple::Type(Command::NOP, nullptr, sc_max_time()); + return {Command::NOP, nullptr, sc_max_time()}; } diff --git a/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.h b/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.h index f7c42380..e8a07d6c 100644 --- a/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.h +++ b/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.h @@ -42,7 +42,7 @@ class CmdMuxStrict : public CmdMuxIF { public: CmdMuxStrict(); - virtual CommandTuple::Type selectCommand(const ReadyCommands &) override; + CommandTuple::Type selectCommand(const ReadyCommands &) override; private: uint64_t nextPayloadID = 1; @@ -53,7 +53,7 @@ class CmdMuxStrictRasCas : public CmdMuxIF { public: CmdMuxStrictRasCas(); - virtual CommandTuple::Type selectCommand(const ReadyCommands &) override; + CommandTuple::Type selectCommand(const ReadyCommands &) override; private: uint64_t nextPayloadID = 1; diff --git a/DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.cpp b/DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.cpp index b496e973..8fcbe479 100644 --- a/DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.cpp +++ b/DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.cpp @@ -38,7 +38,7 @@ using namespace tlm; CommandTuple::Type PowerDownManagerDummy::getNextCommand() { - return CommandTuple::Type(Command::NOP, nullptr, sc_max_time()); + return {Command::NOP, nullptr, sc_max_time()}; } sc_time PowerDownManagerDummy::start() diff --git a/DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.h b/DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.h index 854ecc1a..e8408dea 100644 --- a/DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.h +++ b/DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.h @@ -40,15 +40,15 @@ class PowerDownManagerDummy final : public PowerDownManagerIF { public: - PowerDownManagerDummy() {} + PowerDownManagerDummy() = default; - virtual void triggerEntry() override {} - virtual void triggerExit() override {} - virtual void triggerInterruption() override {} + void triggerEntry() override {} + void triggerExit() override {} + void triggerInterruption() override {} - virtual CommandTuple::Type getNextCommand() override; - virtual void updateState(Command) override {} - virtual sc_time start() override; + CommandTuple::Type getNextCommand() override; + void updateState(Command) override {} + sc_time start() override; }; #endif // POWERDOWNMANAGERDUMMY_H diff --git a/DRAMSys/library/src/controller/powerdown/PowerDownManagerIF.h b/DRAMSys/library/src/controller/powerdown/PowerDownManagerIF.h index 39dd314e..fd038495 100644 --- a/DRAMSys/library/src/controller/powerdown/PowerDownManagerIF.h +++ b/DRAMSys/library/src/controller/powerdown/PowerDownManagerIF.h @@ -43,7 +43,7 @@ class PowerDownManagerIF { public: - virtual ~PowerDownManagerIF() {} + virtual ~PowerDownManagerIF() = default; virtual void triggerEntry() = 0; virtual void triggerExit() = 0; diff --git a/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.cpp b/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.cpp index 80ce14b7..17f8ea4e 100644 --- a/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.cpp +++ b/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.cpp @@ -71,7 +71,7 @@ void PowerDownManagerStaggered::triggerInterruption() CommandTuple::Type PowerDownManagerStaggered::getNextCommand() { - return CommandTuple::Type(nextCommand, &powerDownPayload, std::max(timeToSchedule, sc_time_stamp())); + return {nextCommand, &powerDownPayload, std::max(timeToSchedule, sc_time_stamp())}; } sc_time PowerDownManagerStaggered::start() diff --git a/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.h b/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.h index eaa6cf77..f9d88bc7 100644 --- a/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.h +++ b/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.h @@ -44,13 +44,13 @@ class PowerDownManagerStaggered final : public PowerDownManagerIF public: PowerDownManagerStaggered(Rank, CheckerIF *); - virtual void triggerEntry() override; - virtual void triggerExit() override; - virtual void triggerInterruption() override; + void triggerEntry() override; + void triggerExit() override; + void triggerInterruption() override; - virtual CommandTuple::Type getNextCommand() override; - virtual void updateState(Command) override; - virtual sc_time start() override; + CommandTuple::Type getNextCommand() override; + void updateState(Command) override; + sc_time start() override; private: enum class State {Idle, ActivePdn, PrechargePdn, SelfRefresh, ExtraRefresh} state = State::Idle; diff --git a/DRAMSys/library/src/controller/respqueue/RespQueueFifo.h b/DRAMSys/library/src/controller/respqueue/RespQueueFifo.h index 4a07fb92..82846be9 100644 --- a/DRAMSys/library/src/controller/respqueue/RespQueueFifo.h +++ b/DRAMSys/library/src/controller/respqueue/RespQueueFifo.h @@ -44,9 +44,9 @@ class RespQueueFifo final : public RespQueueIF { public: - virtual void insertPayload(tlm::tlm_generic_payload *, sc_time) override; - virtual tlm::tlm_generic_payload *nextPayload() override; - virtual sc_time getTriggerTime() const override; + void insertPayload(tlm::tlm_generic_payload *, sc_time) override; + tlm::tlm_generic_payload *nextPayload() override; + sc_time getTriggerTime() const override; private: std::queue> buffer; diff --git a/DRAMSys/library/src/controller/respqueue/RespQueueIF.h b/DRAMSys/library/src/controller/respqueue/RespQueueIF.h index 551fcb8f..53cb3c04 100644 --- a/DRAMSys/library/src/controller/respqueue/RespQueueIF.h +++ b/DRAMSys/library/src/controller/respqueue/RespQueueIF.h @@ -44,7 +44,7 @@ public: virtual void insertPayload(tlm::tlm_generic_payload *, sc_time) = 0; virtual tlm::tlm_generic_payload *nextPayload() = 0; virtual sc_time getTriggerTime() const = 0; - virtual ~RespQueueIF() {} + virtual ~RespQueueIF() = default; }; #endif // RESPQUEUEIF_H diff --git a/DRAMSys/library/src/controller/respqueue/RespQueueReorder.h b/DRAMSys/library/src/controller/respqueue/RespQueueReorder.h index 89d8c81a..26ffa730 100644 --- a/DRAMSys/library/src/controller/respqueue/RespQueueReorder.h +++ b/DRAMSys/library/src/controller/respqueue/RespQueueReorder.h @@ -43,9 +43,9 @@ class RespQueueReorder final : public RespQueueIF { public: - virtual void insertPayload(tlm::tlm_generic_payload *, sc_time) override; - virtual tlm::tlm_generic_payload *nextPayload() override; - virtual sc_time getTriggerTime() const override; + void insertPayload(tlm::tlm_generic_payload *, sc_time) override; + tlm::tlm_generic_payload *nextPayload() override; + sc_time getTriggerTime() const override; private: uint64_t nextPayloadID = 1; diff --git a/DRAMSys/library/src/controller/scheduler/BufferCounterBankwise.h b/DRAMSys/library/src/controller/scheduler/BufferCounterBankwise.h index 1591cd80..079bb4c8 100644 --- a/DRAMSys/library/src/controller/scheduler/BufferCounterBankwise.h +++ b/DRAMSys/library/src/controller/scheduler/BufferCounterBankwise.h @@ -43,10 +43,10 @@ class BufferCounterBankwise final : public BufferCounterIF { public: BufferCounterBankwise(unsigned requestBufferSize, unsigned numberOfBanks); - virtual bool hasBufferSpace() const override; - virtual void storeRequest(tlm::tlm_generic_payload *payload) override; - virtual void removeRequest(tlm::tlm_generic_payload *payload) override; - virtual const std::vector &getBufferDepth() const override; + bool hasBufferSpace() const override; + void storeRequest(tlm::tlm_generic_payload *payload) override; + void removeRequest(tlm::tlm_generic_payload *payload) override; + const std::vector &getBufferDepth() const override; private: const unsigned requestBufferSize; diff --git a/DRAMSys/library/src/controller/scheduler/BufferCounterReadWrite.h b/DRAMSys/library/src/controller/scheduler/BufferCounterReadWrite.h index a99716b9..f12ebd7d 100644 --- a/DRAMSys/library/src/controller/scheduler/BufferCounterReadWrite.h +++ b/DRAMSys/library/src/controller/scheduler/BufferCounterReadWrite.h @@ -40,11 +40,11 @@ class BufferCounterReadWrite final : public BufferCounterIF { public: - BufferCounterReadWrite(unsigned requestBufferSize); - virtual bool hasBufferSpace() const override; - virtual void storeRequest(tlm::tlm_generic_payload *payload) override; - virtual void removeRequest(tlm::tlm_generic_payload *payload) override; - virtual const std::vector &getBufferDepth() const override; + explicit BufferCounterReadWrite(unsigned requestBufferSize); + bool hasBufferSpace() const override; + void storeRequest(tlm::tlm_generic_payload *payload) override; + void removeRequest(tlm::tlm_generic_payload *payload) override; + const std::vector &getBufferDepth() const override; private: const unsigned requestBufferSize; diff --git a/DRAMSys/library/src/controller/scheduler/BufferCounterShared.h b/DRAMSys/library/src/controller/scheduler/BufferCounterShared.h index aefd20ad..dbfb0c7a 100644 --- a/DRAMSys/library/src/controller/scheduler/BufferCounterShared.h +++ b/DRAMSys/library/src/controller/scheduler/BufferCounterShared.h @@ -40,11 +40,11 @@ class BufferCounterShared final : public BufferCounterIF { public: - BufferCounterShared(unsigned requestBufferSize); - virtual bool hasBufferSpace() const override; - virtual void storeRequest(tlm::tlm_generic_payload *payload) override; - virtual void removeRequest(tlm::tlm_generic_payload *payload) override; - virtual const std::vector &getBufferDepth() const override; + explicit BufferCounterShared(unsigned requestBufferSize); + bool hasBufferSpace() const override; + void storeRequest(tlm::tlm_generic_payload *payload) override; + void removeRequest(tlm::tlm_generic_payload *payload) override; + const std::vector &getBufferDepth() const override; private: const unsigned requestBufferSize; diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFifo.h b/DRAMSys/library/src/controller/scheduler/SchedulerFifo.h index ae06ac48..6cdeac00 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFifo.h +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFifo.h @@ -48,14 +48,14 @@ class SchedulerFifo final : public SchedulerIF { public: SchedulerFifo(); - virtual ~SchedulerFifo() override; - virtual bool hasBufferSpace() const override; - virtual void storeRequest(tlm::tlm_generic_payload *) override; - virtual void removeRequest(tlm::tlm_generic_payload *) override; - virtual tlm::tlm_generic_payload *getNextRequest(BankMachine *) const override; - virtual bool hasFurtherRowHit(Bank, Row) const override; - virtual bool hasFurtherRequest(Bank) const override; - virtual const std::vector &getBufferDepth() const override; + ~SchedulerFifo() override; + bool hasBufferSpace() const override; + void storeRequest(tlm::tlm_generic_payload *) override; + void removeRequest(tlm::tlm_generic_payload *) override; + tlm::tlm_generic_payload *getNextRequest(BankMachine *) const override; + bool hasFurtherRowHit(Bank, Row) const override; + bool hasFurtherRequest(Bank) const override; + const std::vector &getBufferDepth() const override; private: std::vector> buffer; diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp index a15dc6f2..273a1e99 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp @@ -92,10 +92,10 @@ tlm_generic_payload *SchedulerFrFcfs::getNextRequest(BankMachine *bankMachine) c { // Search for row hit Row openRow = bankMachine->getOpenRow(); - for (auto it = buffer[bankID].begin(); it != buffer[bankID].end(); it++) + for (auto it : buffer[bankID]) { - if (DramExtension::getRow(*it) == openRow) - return *it; + if (DramExtension::getRow(it) == openRow) + return it; } } // No row hit found or bank precharged @@ -107,9 +107,9 @@ tlm_generic_payload *SchedulerFrFcfs::getNextRequest(BankMachine *bankMachine) c bool SchedulerFrFcfs::hasFurtherRowHit(Bank bank, Row row) const { unsigned rowHitCounter = 0; - for (auto it = buffer[bank.ID()].begin(); it != buffer[bank.ID()].end(); it++) + for (auto it : buffer[bank.ID()]) { - if (DramExtension::getRow(*it) == row) + if (DramExtension::getRow(it) == row) { rowHitCounter++; if (rowHitCounter == 2) diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.h b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.h index 15633b51..c8a182c8 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.h +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.h @@ -48,14 +48,14 @@ class SchedulerFrFcfs final : public SchedulerIF { public: SchedulerFrFcfs(); - virtual ~SchedulerFrFcfs() override; - virtual bool hasBufferSpace() const override; - virtual void storeRequest(tlm::tlm_generic_payload *) override; - virtual void removeRequest(tlm::tlm_generic_payload *) override; - virtual tlm::tlm_generic_payload *getNextRequest(BankMachine *) const override; - virtual bool hasFurtherRowHit(Bank, Row) const override; - virtual bool hasFurtherRequest(Bank) const override; - virtual const std::vector &getBufferDepth() const override; + ~SchedulerFrFcfs() override; + bool hasBufferSpace() const override; + void storeRequest(tlm::tlm_generic_payload *) override; + void removeRequest(tlm::tlm_generic_payload *) override; + tlm::tlm_generic_payload *getNextRequest(BankMachine *) const override; + bool hasFurtherRowHit(Bank, Row) const override; + bool hasFurtherRequest(Bank) const override; + const std::vector &getBufferDepth() const override; private: std::vector> buffer; diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.cpp b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.cpp index a1510123..3ee1c46a 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.cpp +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.cpp @@ -94,10 +94,10 @@ tlm_generic_payload *SchedulerFrFcfsGrp::getNextRequest(BankMachine *bankMachine // Filter all row hits Row openRow = bankMachine->getOpenRow(); std::list rowHits; - for (auto it = buffer[bankID].begin(); it != buffer[bankID].end(); it++) + for (auto it : buffer[bankID]) { - if (DramExtension::getRow(*it) == openRow) - rowHits.push_back(*it); + if (DramExtension::getRow(it) == openRow) + rowHits.push_back(it); } if (!rowHits.empty()) diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.h b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.h index b6f67e1c..11cd2dae 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.h +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.h @@ -48,14 +48,14 @@ class SchedulerFrFcfsGrp final : public SchedulerIF { public: SchedulerFrFcfsGrp(); - virtual ~SchedulerFrFcfsGrp() override; - virtual bool hasBufferSpace() const override; - virtual void storeRequest(tlm::tlm_generic_payload *) override; - virtual void removeRequest(tlm::tlm_generic_payload *) override; - virtual tlm::tlm_generic_payload *getNextRequest(BankMachine *) const override; - virtual bool hasFurtherRowHit(Bank, Row) const override; - virtual bool hasFurtherRequest(Bank) const override; - virtual const std::vector &getBufferDepth() const override; + ~SchedulerFrFcfsGrp() override; + bool hasBufferSpace() const override; + void storeRequest(tlm::tlm_generic_payload *) override; + void removeRequest(tlm::tlm_generic_payload *) override; + tlm::tlm_generic_payload *getNextRequest(BankMachine *) const override; + bool hasFurtherRowHit(Bank, Row) const override; + bool hasFurtherRequest(Bank) const override; + const std::vector &getBufferDepth() const override; private: std::vector> buffer; From c015a73e916707e01f8d1def4cf3d0f6abc5a47c Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Thu, 20 May 2021 17:42:12 +0200 Subject: [PATCH 5/6] Code refactoring. --- DRAMSys/library/src/common/TlmRecorder.cpp | 89 +++++++++---------- DRAMSys/library/src/common/TlmRecorder.h | 31 ++++--- DRAMSys/library/src/common/utils.cpp | 16 ++-- DRAMSys/library/src/common/utils.h | 16 ++-- .../src/configuration/Configuration.cpp | 12 +-- .../library/src/configuration/Configuration.h | 8 +- .../src/simulation/DRAMSysRecordable.cpp | 4 +- 7 files changed, 84 insertions(+), 92 deletions(-) diff --git a/DRAMSys/library/src/common/TlmRecorder.cpp b/DRAMSys/library/src/common/TlmRecorder.cpp index ca347381..8a42044d 100644 --- a/DRAMSys/library/src/common/TlmRecorder.cpp +++ b/DRAMSys/library/src/common/TlmRecorder.cpp @@ -46,13 +46,12 @@ using namespace tlm; -TlmRecorder::TlmRecorder(std::string name, std::string dbname) : - dbName(dbname), name(name), - totalNumTransactions(1), simulationTimeCoveredByRecording(SC_ZERO_TIME) +TlmRecorder::TlmRecorder(const std::string &name, const std::string &dbName) : + name(name), totalNumTransactions(1), simulationTimeCoveredByRecording(SC_ZERO_TIME) { recordedData.reserve(transactionCommitRate); setUpTransactionTerminatingPhases(); - openDB(TlmRecorder::dbName.c_str()); + openDB(dbName); char *sErrMsg; sqlite3_exec(db, "PRAGMA main.page_size = 4096", nullptr, nullptr, &sErrMsg); sqlite3_exec(db, "PRAGMA main.cache_size=10000", nullptr, nullptr, &sErrMsg); @@ -110,7 +109,7 @@ void TlmRecorder::recordBandwidth(double timeInSeconds, double averageBandwidth) } void TlmRecorder::recordPhase(tlm_generic_payload &trans, - tlm_phase phase, sc_time time) + tlm_phase phase, const sc_time &time) { if (currentTransactionsInSystem.count(&trans) == 0) introduceTransactionSystem(trans); @@ -147,7 +146,7 @@ void TlmRecorder::updateDataStrobe(const sc_time &begin, const sc_time &end, } -void TlmRecorder::recordDebugMessage(std::string message, sc_time time) +void TlmRecorder::recordDebugMessage(const std::string &message, const sc_time &time) { insertDebugMessageInDB(message, time); } @@ -194,7 +193,7 @@ void TlmRecorder::commitRecordedDataToDB() sqlite3_exec(db, "BEGIN;", nullptr, nullptr, nullptr); for (Transaction &recordingData : recordedData) { - assert(recordingData.recordedPhases.size() > 0); + assert(!recordingData.recordedPhases.empty()); insertTransactionInDB(recordingData); for (Transaction::Phase &phaseData : recordingData.recordedPhases) { @@ -216,20 +215,20 @@ void TlmRecorder::commitRecordedDataToDB() } -void TlmRecorder::Transaction::insertPhase(std::string name, sc_time begin) +void TlmRecorder::Transaction::insertPhase(const std::string &phaseName, const sc_time &begin) { - recordedPhases.push_back(Phase(name, begin)); + recordedPhases.emplace_back(phaseName, begin); } -void TlmRecorder::Transaction::setPhaseEnd(std::string name, sc_time end) +void TlmRecorder::Transaction::setPhaseEnd(const std::string &phaseName, const sc_time &end) { - // Find the latest recorder phase for that transaction with a matching name and update it + // Find the latest recorder phase for that transaction with a matching phaseName and update it // Note: Transactions might have the same phase multiple times (e.g. PRE->ACT->REF->ACT->RD) // only update the latest one that has been recorded for (size_t i = recordedPhases.size(); i > 0; i--) { Phase &data = recordedPhases[i - 1]; - if (data.name == name) + if (data.name == phaseName) { data.interval.end = end; return; @@ -239,18 +238,18 @@ void TlmRecorder::Transaction::setPhaseEnd(std::string name, sc_time end) "While trying to set phase end: phaseBegin has not been recorded"); } -void TlmRecorder::openDB(std::string name) +void TlmRecorder::openDB(const std::string &dbName) { - std::ifstream f(name.c_str()); + std::ifstream f(dbName.c_str()); if (f.good()) { - if (remove(name.c_str()) != 0) + if (remove(dbName.c_str()) != 0) { SC_REPORT_FATAL("TlmRecorder", "Error deleting file" ); } } - if (sqlite3_open(name.c_str(), &db) != SQLITE_OK) + if (sqlite3_open(dbName.c_str(), &db) != SQLITE_OK) { SC_REPORT_FATAL("Error in TraceRecorder", "Error cannot open database"); sqlite3_close(db); @@ -262,24 +261,18 @@ void TlmRecorder::setUpTransactionTerminatingPhases() transactionTerminatingPhases.push_back(END_RESP); // Refresh All - transactionTerminatingPhases.push_back(static_cast - (END_REFA)); + transactionTerminatingPhases.push_back(END_REFA); // Refresh Bank - transactionTerminatingPhases.push_back(static_cast - (END_REFB)); + transactionTerminatingPhases.push_back(END_REFB); // Refresh Same Bank - transactionTerminatingPhases.push_back(static_cast - (END_REFSB)); + transactionTerminatingPhases.push_back(END_REFSB); // Phases for Power Down - transactionTerminatingPhases.push_back(static_cast - (END_PDNA)); - transactionTerminatingPhases.push_back(static_cast - (END_PDNP)); - transactionTerminatingPhases.push_back(static_cast - (END_SREF)); + transactionTerminatingPhases.push_back(END_PDNA); + transactionTerminatingPhases.push_back(END_PDNP); + transactionTerminatingPhases.push_back(END_SREF); } void TlmRecorder::prepareSqlStatements() @@ -331,7 +324,7 @@ void TlmRecorder::prepareSqlStatements() sqlite3_prepare_v2(db, insertBandwidthString.c_str(), -1, &insertBandwidthStatement, nullptr); } -void TlmRecorder::insertDebugMessageInDB(std::string message, const sc_time &time) +void TlmRecorder::insertDebugMessageInDB(const std::string &message, const sc_time &time) { sqlite3_bind_int64(insertDebugMessageStatement, 1, static_cast(time.value())); sqlite3_bind_text(insertDebugMessageStatement, 2, message.c_str(), static_cast(message.length()), nullptr); @@ -379,24 +372,24 @@ void TlmRecorder::insertCommandLengths() { const MemSpec *memSpec = Configuration::getInstance().memSpec; - sqlite3_bind_int(insertCommandLengthsStatement, 1, static_cast(memSpec->getCommandLength(Command::NOP) / memSpec->tCK + 0.5)); - sqlite3_bind_int(insertCommandLengthsStatement, 2, static_cast(memSpec->getCommandLength(Command::RD) / memSpec->tCK + 0.5)); - sqlite3_bind_int(insertCommandLengthsStatement, 3, static_cast(memSpec->getCommandLength(Command::WR) / memSpec->tCK + 0.5)); - sqlite3_bind_int(insertCommandLengthsStatement, 4, static_cast(memSpec->getCommandLength(Command::RDA) / memSpec->tCK + 0.5)); - sqlite3_bind_int(insertCommandLengthsStatement, 5, static_cast(memSpec->getCommandLength(Command::WRA) / memSpec->tCK + 0.5)); - sqlite3_bind_int(insertCommandLengthsStatement, 6, static_cast(memSpec->getCommandLength(Command::ACT) / memSpec->tCK + 0.5)); - sqlite3_bind_int(insertCommandLengthsStatement, 7, static_cast(memSpec->getCommandLength(Command::PRE) / memSpec->tCK + 0.5)); - sqlite3_bind_int(insertCommandLengthsStatement, 8, static_cast(memSpec->getCommandLength(Command::REFB) / memSpec->tCK + 0.5)); - sqlite3_bind_int(insertCommandLengthsStatement, 9, static_cast(memSpec->getCommandLength(Command::PRESB) / memSpec->tCK + 0.5)); - sqlite3_bind_int(insertCommandLengthsStatement, 10, static_cast(memSpec->getCommandLength(Command::REFSB) / memSpec->tCK + 0.5)); - sqlite3_bind_int(insertCommandLengthsStatement, 11, static_cast(memSpec->getCommandLength(Command::PREA) / memSpec->tCK + 0.5)); - sqlite3_bind_int(insertCommandLengthsStatement, 12, static_cast(memSpec->getCommandLength(Command::REFA) / memSpec->tCK + 0.5)); - sqlite3_bind_int(insertCommandLengthsStatement, 13, static_cast(memSpec->getCommandLength(Command::PDEA) / memSpec->tCK + 0.5)); - sqlite3_bind_int(insertCommandLengthsStatement, 14, static_cast(memSpec->getCommandLength(Command::PDXA) / memSpec->tCK + 0.5)); - sqlite3_bind_int(insertCommandLengthsStatement, 15, static_cast(memSpec->getCommandLength(Command::PDEP) / memSpec->tCK + 0.5)); - sqlite3_bind_int(insertCommandLengthsStatement, 16, static_cast(memSpec->getCommandLength(Command::PDXP) / memSpec->tCK + 0.5)); - sqlite3_bind_int(insertCommandLengthsStatement, 17, static_cast(memSpec->getCommandLength(Command::SREFEN) / memSpec->tCK + 0.5)); - sqlite3_bind_int(insertCommandLengthsStatement, 18, static_cast(memSpec->getCommandLength(Command::SREFEX) / memSpec->tCK + 0.5)); + sqlite3_bind_int(insertCommandLengthsStatement, 1, static_cast(lround(memSpec->getCommandLength(Command::NOP) / memSpec->tCK))); + sqlite3_bind_int(insertCommandLengthsStatement, 2, static_cast(lround(memSpec->getCommandLength(Command::RD) / memSpec->tCK))); + sqlite3_bind_int(insertCommandLengthsStatement, 3, static_cast(lround(memSpec->getCommandLength(Command::WR) / memSpec->tCK))); + sqlite3_bind_int(insertCommandLengthsStatement, 4, static_cast(lround(memSpec->getCommandLength(Command::RDA) / memSpec->tCK))); + sqlite3_bind_int(insertCommandLengthsStatement, 5, static_cast(lround(memSpec->getCommandLength(Command::WRA) / memSpec->tCK))); + sqlite3_bind_int(insertCommandLengthsStatement, 6, static_cast(lround(memSpec->getCommandLength(Command::ACT) / memSpec->tCK))); + sqlite3_bind_int(insertCommandLengthsStatement, 7, static_cast(lround(memSpec->getCommandLength(Command::PRE) / memSpec->tCK))); + sqlite3_bind_int(insertCommandLengthsStatement, 8, static_cast(lround(memSpec->getCommandLength(Command::REFB) / memSpec->tCK))); + sqlite3_bind_int(insertCommandLengthsStatement, 9, static_cast(lround(memSpec->getCommandLength(Command::PRESB) / memSpec->tCK))); + sqlite3_bind_int(insertCommandLengthsStatement, 10, static_cast(lround(memSpec->getCommandLength(Command::REFSB) / memSpec->tCK))); + sqlite3_bind_int(insertCommandLengthsStatement, 11, static_cast(lround(memSpec->getCommandLength(Command::PREA) / memSpec->tCK))); + sqlite3_bind_int(insertCommandLengthsStatement, 12, static_cast(lround(memSpec->getCommandLength(Command::REFA) / memSpec->tCK))); + sqlite3_bind_int(insertCommandLengthsStatement, 13, static_cast(lround(memSpec->getCommandLength(Command::PDEA) / memSpec->tCK))); + sqlite3_bind_int(insertCommandLengthsStatement, 14, static_cast(lround(memSpec->getCommandLength(Command::PDXA) / memSpec->tCK))); + sqlite3_bind_int(insertCommandLengthsStatement, 15, static_cast(lround(memSpec->getCommandLength(Command::PDEP) / memSpec->tCK))); + sqlite3_bind_int(insertCommandLengthsStatement, 16, static_cast(lround(memSpec->getCommandLength(Command::PDXP) / memSpec->tCK))); + sqlite3_bind_int(insertCommandLengthsStatement, 17, static_cast(lround(memSpec->getCommandLength(Command::SREFEN) / memSpec->tCK))); + sqlite3_bind_int(insertCommandLengthsStatement, 18, static_cast(lround(memSpec->getCommandLength(Command::SREFEX) / memSpec->tCK))); executeSqlStatement(insertCommandLengthsStatement); } @@ -442,7 +435,7 @@ void TlmRecorder::insertRangeInDB(uint64_t id, const sc_time &begin, executeSqlStatement(insertRangeStatement); } -void TlmRecorder::insertPhaseInDB(std::string phaseName, const sc_time &begin, +void TlmRecorder::insertPhaseInDB(const std::string &phaseName, const sc_time &begin, const sc_time &end, uint64_t transactionID) { diff --git a/DRAMSys/library/src/common/TlmRecorder.h b/DRAMSys/library/src/common/TlmRecorder.h index fd422987..37bf787b 100644 --- a/DRAMSys/library/src/common/TlmRecorder.h +++ b/DRAMSys/library/src/common/TlmRecorder.h @@ -56,30 +56,29 @@ class TlmRecorder { public: std::string sqlScriptURI; - std::string dbName; - TlmRecorder(std::string name, std::string dbname); + TlmRecorder(const std::string &name, const std::string &dbName); ~TlmRecorder(); - void recordMCconfig(std::string mcconfig) + void recordMcConfig(std::string _mcconfig) { - this->mcconfig = mcconfig; + mcconfig = _mcconfig; } - void recordMemspec(std::string memspec) + void recordMemspec(std::string _memspec) { - this->memspec = memspec; + memspec = _memspec; } - void recordTracenames(std::string traces) + void recordTraceNames(std::string _traces) { - this->traces = traces; + traces = _traces; } void recordPhase(tlm::tlm_generic_payload &trans, tlm::tlm_phase phase, - sc_time time); + const sc_time &time); void recordPower(double timeInSeconds, double averagePower); void recordBufferDepth(double timeInSeconds, const std::vector &averageBufferDepth); void recordBandwidth(double timeInSeconds, double averageBandwidth); - void recordDebugMessage(std::string message, sc_time time); + void recordDebugMessage(const std::string &message, const sc_time &time); void updateDataStrobe(const sc_time &begin, const sc_time &end, tlm::tlm_generic_payload &trans); void closeConnection(); @@ -106,8 +105,8 @@ private: }; std::vector recordedPhases; - void insertPhase(std::string name, sc_time begin); - void setPhaseEnd(std::string name, sc_time end); + void insertPhase(const std::string &phaseName, const sc_time &begin); + void setPhaseEnd(const std::string &phaseName, const sc_time &end); }; std::string name; @@ -116,9 +115,9 @@ private: void prepareSqlStatements(); void executeInitialSqlCommand(); - void executeSqlStatement(sqlite3_stmt *statement); + static void executeSqlStatement(sqlite3_stmt *statement); - void openDB(std::string name); + void openDB(const std::string &dbName); void setUpTransactionTerminatingPhases(); void introduceTransactionSystem(tlm::tlm_generic_payload &trans); @@ -129,9 +128,9 @@ private: void insertCommandLengths(); void insertTransactionInDB(Transaction &recordingData); void insertRangeInDB(uint64_t id, const sc_time &begin, const sc_time &end); - void insertPhaseInDB(std::string phaseName, const sc_time &begin, const sc_time &end, + void insertPhaseInDB(const std::string &phaseName, const sc_time &begin, const sc_time &end, uint64_t transactionID); - void insertDebugMessageInDB(std::string message, const sc_time &time); + void insertDebugMessageInDB(const std::string &message, const sc_time &time); static const int transactionCommitRate = 1000; std::vector recordedData; diff --git a/DRAMSys/library/src/common/utils.cpp b/DRAMSys/library/src/common/utils.cpp index a8c2d649..f9b6b520 100644 --- a/DRAMSys/library/src/common/utils.cpp +++ b/DRAMSys/library/src/common/utils.cpp @@ -46,18 +46,18 @@ using namespace tlm; using json = nlohmann::json; -bool TimeInterval::timeIsInInterval(sc_time time) +bool TimeInterval::timeIsInInterval(const sc_time &time) const { return (start < time && time < end); } -bool TimeInterval::intersects(TimeInterval other) +bool TimeInterval::intersects(const TimeInterval &other) const { return other.timeIsInInterval(this->start) || this->timeIsInInterval(other.start); } -sc_time TimeInterval::getLength() +sc_time TimeInterval::getLength() const { if (end > start) return end - start; @@ -72,7 +72,7 @@ std::string getPhaseName(tlm_phase phase) return oss.str(); } -json parseJSON(std::string path) +json parseJSON(const std::string &path) { std::ifstream file(path); if (file.is_open()) @@ -87,7 +87,7 @@ json parseJSON(std::string path) throw std::invalid_argument("Failed to open file '" + path + "'."); } -bool parseBool(json &obj, std::string name) +bool parseBool(json &obj, const std::string &name) { if (!obj.empty()) { @@ -100,7 +100,7 @@ bool parseBool(json &obj, std::string name) throw std::invalid_argument("Parameter '" + name + "' does not exist."); } -unsigned int parseUint(json &obj, std::string name) +unsigned int parseUint(json &obj, const std::string &name) { if (!obj.empty()) { @@ -113,7 +113,7 @@ unsigned int parseUint(json &obj, std::string name) throw std::invalid_argument("Parameter '" + name + "' does not exist."); } -double parseUdouble(json &obj, std::string name) +double parseUdouble(json &obj, const std::string &name) { if (!obj.empty()) { @@ -126,7 +126,7 @@ double parseUdouble(json &obj, std::string name) throw std::invalid_argument("Parameter '" + name + "' does not exist."); } -std::string parseString(json &obj, std::string name) +std::string parseString(json &obj, const std::string &name) { if (!obj.empty()) { diff --git a/DRAMSys/library/src/common/utils.h b/DRAMSys/library/src/common/utils.h index e98fde2d..e9bee6d5 100644 --- a/DRAMSys/library/src/common/utils.h +++ b/DRAMSys/library/src/common/utils.h @@ -57,9 +57,9 @@ public: TimeInterval() : start(SC_ZERO_TIME), end(SC_ZERO_TIME) {} TimeInterval(sc_time start, sc_time end) : start(start), end(end) {} - sc_time getLength(); - bool timeIsInInterval(sc_time time); - bool intersects(TimeInterval other); + sc_time getLength() const; + bool timeIsInInterval(const sc_time &time) const; + bool intersects(const TimeInterval &other) const; }; constexpr const char headline[] = @@ -67,11 +67,11 @@ constexpr const char headline[] = std::string getPhaseName(tlm::tlm_phase phase); -nlohmann::json parseJSON(std::string path); -bool parseBool(nlohmann::json &obj, std::string name); -unsigned int parseUint(nlohmann::json &obj, std::string name); -double parseUdouble(nlohmann::json &obj, std::string name); -std::string parseString(nlohmann::json &obj, std::string name); +nlohmann::json parseJSON(const std::string &path); +bool parseBool(nlohmann::json &obj, const std::string &name); +unsigned int parseUint(nlohmann::json &obj, const std::string &name); +double parseUdouble(nlohmann::json &obj, const std::string &name); +std::string parseString(nlohmann::json &obj, const std::string &name); void setUpDummy(tlm::tlm_generic_payload &payload, uint64_t channelPayloadID, Rank rank = Rank(0), BankGroup bankGroup = BankGroup(0), Bank bank = Bank(0)); diff --git a/DRAMSys/library/src/configuration/Configuration.cpp b/DRAMSys/library/src/configuration/Configuration.cpp index 065aee78..f1496bd5 100644 --- a/DRAMSys/library/src/configuration/Configuration.cpp +++ b/DRAMSys/library/src/configuration/Configuration.cpp @@ -55,10 +55,10 @@ using json = nlohmann::json; -std::string Configuration::memspecUri = ""; -std::string Configuration::mcconfigUri = ""; +std::string Configuration::memspecUri; +std::string Configuration::mcconfigUri; -enum sc_time_unit string2TimeUnit(std::string s) +enum sc_time_unit string2TimeUnit(const std::string &s) { if (s == "s") return SC_SEC; @@ -79,7 +79,7 @@ enum sc_time_unit string2TimeUnit(std::string s) } } -void Configuration::setParameter(std::string name, nlohmann::json value) +void Configuration::setParameter(const std::string &name, const nlohmann::json &value) { // MCConfig if (name == "PagePolicy") @@ -283,14 +283,14 @@ void Configuration::setParameter(std::string name, nlohmann::json value) ("Parameter " + name + " not defined in Configuration").c_str()); } -void Configuration::setPathToResources(std::string path) +void Configuration::setPathToResources(const std::string &path) { pathToResources = path; temperatureSim.setPathToResources(path); } // Changes the number of bytes depeding on the ECC Controller. This function is needed for modules which get data directly or indirectly from the ECC Controller -unsigned int Configuration::adjustNumBytesAfterECC(unsigned nBytes) +unsigned int Configuration::adjustNumBytesAfterECC(unsigned nBytes) const { // Manipulate the number of bytes only if there is an ECC Controller selected if (eccMode == ECCMode::Disabled) diff --git a/DRAMSys/library/src/configuration/Configuration.h b/DRAMSys/library/src/configuration/Configuration.h index 7bcf88b7..c83bd039 100644 --- a/DRAMSys/library/src/configuration/Configuration.h +++ b/DRAMSys/library/src/configuration/Configuration.h @@ -61,7 +61,7 @@ public: private: Configuration() {} Configuration(const Configuration &); - Configuration & operator = (const Configuration &); + Configuration &operator = (const Configuration &); public: static std::string memspecUri; @@ -107,7 +107,7 @@ public: // MemSpec (from DRAM-Power) const MemSpec *memSpec; - void setParameter(std::string name, nlohmann::json value); + void setParameter(const std::string &name, const nlohmann::json &value); //Configs for Seed, csv file and StorageMode unsigned int errorChipSeed; @@ -117,8 +117,8 @@ public: // Temperature Simulation related TemperatureSimConfig temperatureSim; - unsigned int adjustNumBytesAfterECC(unsigned bytes); - void setPathToResources(std::string path); + unsigned int adjustNumBytesAfterECC(unsigned bytes) const; + void setPathToResources(const std::string &path); void loadMCConfig(Configuration &config, std::string amconfigUri); void loadSimConfig(Configuration &config, std::string simconfigUri); diff --git a/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp b/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp index 25a89d5c..3693e3eb 100644 --- a/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp +++ b/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp @@ -100,11 +100,11 @@ void DRAMSysRecordable::setupTlmRecorders(const std::string &traceName) TlmRecorder *tlmRecorder = new TlmRecorder(recorderName, dbName.c_str()); - tlmRecorder->recordMCconfig(Configuration::getInstance().mcconfigUri); + tlmRecorder->recordMcConfig(Configuration::getInstance().mcconfigUri); tlmRecorder->recordMemspec(Configuration::getInstance().memspecUri); std::string traceNames = Configuration::getInstance().simulationName; - tlmRecorder->recordTracenames(traceNames); + tlmRecorder->recordTraceNames(traceNames); tlmRecorders.push_back(tlmRecorder); } From 38fbf9f63a77cd20d992557757a758cd6b4da0c5 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Thu, 20 May 2021 18:24:04 +0200 Subject: [PATCH 6/6] Let power down manager check state of bank machines. --- DRAMSys/library/src/controller/Controller.cpp | 3 ++- .../powerdown/PowerDownManagerStaggered.cpp | 27 +++++++++---------- .../powerdown/PowerDownManagerStaggered.h | 5 ++-- 3 files changed, 16 insertions(+), 19 deletions(-) diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index ce9e5426..2d727780 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -175,7 +175,8 @@ Controller::Controller(const sc_module_name &name) : { for (unsigned rankID = 0; rankID < memSpec->numberOfRanks; rankID++) { - PowerDownManagerIF *manager = new PowerDownManagerStaggered(Rank(rankID), checker); + PowerDownManagerIF *manager = new PowerDownManagerStaggered(bankMachinesOnRank[rankID], + Rank(rankID), checker); powerDownManagers.push_back(manager); } } diff --git a/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.cpp b/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.cpp index 17f8ea4e..7fb1fac9 100644 --- a/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.cpp +++ b/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.cpp @@ -37,8 +37,9 @@ using namespace tlm; -PowerDownManagerStaggered::PowerDownManagerStaggered(Rank rank, CheckerIF *checker) - : rank(rank), checker(checker) +PowerDownManagerStaggered::PowerDownManagerStaggered(std::vector &bankMachinesOnRank, + Rank rank, CheckerIF *checker) + : bankMachinesOnRank(bankMachinesOnRank), checker(checker) { setUpDummy(powerDownPayload, UINT64_MAX - 1, rank); } @@ -94,10 +95,15 @@ sc_time PowerDownManagerStaggered::start() } else if (entryTriggered) { - if (activatedBanks != 0) - nextCommand = Command::PDEA; - else - nextCommand = Command::PDEP; + nextCommand = Command::PDEP; + for (auto it : bankMachinesOnRank) + { + if (it->getState() == BankMachine::State::Activated) + { + nextCommand = Command::PDEA; + break; + } + } timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, &powerDownPayload); } @@ -114,15 +120,6 @@ void PowerDownManagerStaggered::updateState(Command command) { switch (command) { - case Command::ACT: - activatedBanks++; - break; - case Command::PRE: - activatedBanks--; - break; - case Command::PREA: - activatedBanks = 0; - break; case Command::PDEA: state = State::ActivePdn; entryTriggered = false; diff --git a/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.h b/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.h index f9d88bc7..f79004a9 100644 --- a/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.h +++ b/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.h @@ -42,7 +42,7 @@ class PowerDownManagerStaggered final : public PowerDownManagerIF { public: - PowerDownManagerStaggered(Rank, CheckerIF *); + PowerDownManagerStaggered(std::vector &, Rank, CheckerIF *); void triggerEntry() override; void triggerExit() override; @@ -55,7 +55,7 @@ public: private: enum class State {Idle, ActivePdn, PrechargePdn, SelfRefresh, ExtraRefresh} state = State::Idle; tlm::tlm_generic_payload powerDownPayload; - Rank rank; + std::vector &bankMachinesOnRank; CheckerIF *checker; sc_time timeToSchedule = sc_max_time(); @@ -65,7 +65,6 @@ private: bool entryTriggered = true; bool exitTriggered = false; bool enterSelfRefresh = false; - unsigned activatedBanks = 0; }; #endif // POWERDOWNMANAGERSTAGGERED_H