diff --git a/dram/src/controller/core/configuration/ConfigurationLoader.cpp b/dram/src/controller/core/configuration/ConfigurationLoader.cpp
index 5e1499b9..2969426e 100644
--- a/dram/src/controller/core/configuration/ConfigurationLoader.cpp
+++ b/dram/src/controller/core/configuration/ConfigurationLoader.cpp
@@ -115,6 +115,7 @@ void ConfigurationLoader::loadDDR4(Configuration& config, XMLElement* memspec)
     config.memSpec.DataRate = queryUIntParameter(architecture, "dataRate");
     config.memSpec.NumberOfRows = queryUIntParameter(architecture, "nbrOfRows");
     config.memSpec.NumberOfColumns = queryUIntParameter(architecture, "nbrOfColumns");
+    config.memSpec.BusWidth = queryUIntParameter(architecture, "width");
 
     //MemTimings
     XMLElement* timings = memspec->FirstChildElement("memtimingspec");
@@ -166,6 +167,7 @@ void ConfigurationLoader::loadWideIO(Configuration& config, XMLElement* memspec)
     config.memSpec.DataRate = queryUIntParameter(architecture, "dataRate");
     config.memSpec.NumberOfRows = queryUIntParameter(architecture, "nbrOfRows");
     config.memSpec.NumberOfColumns = queryUIntParameter(architecture, "nbrOfColumns");
+    config.memSpec.BusWidth = queryUIntParameter(architecture, "width");
 
     //MemTimings
     XMLElement* timings = memspec->FirstChildElement("memtimingspec");
diff --git a/dram/src/controller/core/configuration/MemSpec.h b/dram/src/controller/core/configuration/MemSpec.h
index 80890d9c..0f8b02af 100644
--- a/dram/src/controller/core/configuration/MemSpec.h
+++ b/dram/src/controller/core/configuration/MemSpec.h
@@ -54,6 +54,7 @@ struct MemSpec
     unsigned int DataRate;
     unsigned int NumberOfRows;
     unsigned int NumberOfColumns;
+    unsigned int BusWidth;
 
 	sc_time clk;
 	sc_time tRP;		//precharge-time (pre -> act same bank)
diff --git a/dram/src/error/flip_memory.cpp b/dram/src/error/flip_memory.cpp
index 31c8ef2b..c6cb7e17 100644
--- a/dram/src/error/flip_memory.cpp
+++ b/dram/src/error/flip_memory.cpp
@@ -69,7 +69,8 @@ DecodedAddress flip_memory::getUnifiedNode(unsigned int addr)
     n.bank = 0;
     return n;
 }
-
+//TODO: here get map createt on which address errors will occur, so insert here errormap from board.
+//	dont forget to delete this line
 // Decide which Cells will be weak cells
 void flip_memory::initWeakCells()
 {
@@ -87,7 +88,7 @@ void flip_memory::initWeakCells()
 		col = (unsigned int) (rand() % COLS_PER_ROW);
 		bit = (unsigned int) (rand() % (BYTES_PER_COL*8));
 
-		cout << "row" << row << "\t col" << col << "\t bit" << bit << endl;
+        cout << "row" << row << "\t col" << col << "\t bit" << bit << endl;
 
 		// Avoid duplicates in weakCells[]
 		bool found = false;
@@ -128,14 +129,14 @@ void flip_memory::initWeakCells()
 	}
 
 	// Debug
-	for (unsigned int i=0; i<maxWeakCells; i++)
+    for (unsigned int i=0; i<maxWeakCells; i++)
 	{
 		cout << "row=" << weakCells[i][0];
 		cout << "\tcol=" << weakCells[i][1];
 		cout << "\tbit=" << weakCells[i][2];
 		cout << "\tflip=" << weakCells[i][3];
 		cout << "\tdep=" << weakCells[i][4] << endl;
-	}
+    }
 
 }
 
@@ -239,20 +240,20 @@ void flip_memory::load(tlm::tlm_generic_payload &trans)
 void flip_memory::refresh(unsigned int row)
 {
 	// How many Bits have flipped?
-    cout << "TEST=" << refr[row] << endl;
+	//cout << "TEST=" << refr[row] << endl;
 	sc_time deltaT = sc_time_stamp() - refr[row];
 
-
 	unsigned int n = errormap->getFlipRate(TEMPERATURE, deltaT);
 
-	//cout << sc_time_stamp() << ": deltaT=" << deltaT << " n=" << n << endl;
-
+    	//cout << sc_time_stamp() << ": deltaT=" << deltaT << " n=" << n << endl;
+    	//cout << "Flip_Memory::refresh" << endl;
 	// Flip the first n Bits in array
 	for (unsigned int i=0; i<n; i++) {
 		// Check if Bit has not flipped yet
-		if (weakCells[i][3] == 0 && weakCells[i][0] == row)
+        	if (weakCells[i][3] == 0 && weakCells[i][0] == row)
 		{
-			DecodedAddress no;
+            		//cout << "weak3=0, weak0=row" << endl;
+            		DecodedAddress no;
 			no = getUnifiedNode(0);
 			no.row = weakCells[i][0];
 			no.column = weakCells[i][1];
@@ -268,7 +269,7 @@ void flip_memory::refresh(unsigned int row)
 			if (mem.count(addr) > 0)
 			{
 				char memBefore = mem[addr][byte];
-				//cout << "Flip1?" << endl;
+                		//cout << "Flip1?" << endl;
 
 				if(getBit(no.row,no.column,byte,bit) == 1) // flip only if it is really a one
 				{
diff --git a/dram/src/error/flip_memory.h b/dram/src/error/flip_memory.h
index 77eb1ad4..2ef22e7b 100644
--- a/dram/src/error/flip_memory.h
+++ b/dram/src/error/flip_memory.h
@@ -16,13 +16,14 @@
 
 using namespace tlm;
 using namespace std;
+using namespace core;
 
 class flip_memory
 {
 	private:
 		// Remember to adjust this value by hand when editing in simulation
-		static const unsigned int BUSWIDTH = 128;           //TODO
-		static const unsigned int BURSTLENGTH = 2;          //get from config file
+		unsigned int BUSWIDTH = Configuration::getInstance().memSpec.BusWidth;           //static const unsigned int BUSWIDTH=128;
+		unsigned int BURSTLENGTH = Configuration::getInstance().memSpec.BurstLength;          //static const unsigned int BURSTLENGTH = 2; but in wideIO.xml its 4
 
 		nest_map *errormap;
 		map <unsigned int, vector<unsigned char> > mem;
diff --git a/dram/src/error/nest_map.cpp b/dram/src/error/nest_map.cpp
index a602dcdf..75fb96a6 100644
--- a/dram/src/error/nest_map.cpp
+++ b/dram/src/error/nest_map.cpp
@@ -73,7 +73,7 @@ void nest_map::initMap(string fn)
 			tr[i].d = ceil(distribution2(generator2)); // calculate normal distribution of # of dependent errors
 
 			//print normal distribution of csv file
-			cout << "T=\t" << tr[i].T << "\t t=" << tr[i].t << "\t n=" << tr[i].n << "\t s=" << sigma << "\t d=" << tr[i].d << "\t s=" << sigma2 << endl;
+			//cout << "T=\t" << tr[i].T << "\t t=" << tr[i].t << "\t n=" << tr[i].n << "\t s=" << sigma << "\t d=" << tr[i].d << "\t s=" << sigma2 << endl;
 
 			// Search the largest entry of n in list
 			if ((tr[i].n + tr[i].d)> maxWeakCells)
diff --git a/dram/src/simulation/Dram.h b/dram/src/simulation/Dram.h
index 0f414022..8188c02c 100644
--- a/dram/src/simulation/Dram.h
+++ b/dram/src/simulation/Dram.h
@@ -50,7 +50,7 @@ struct Dram: sc_module
     tlm_utils::simple_target_socket<Dram, BUSWIDTH, tlm::tlm_base_protocol_types> tSocket;
     IFPOW(libDRAMPower *DRAMPower);
 
-    const unsigned int StorageMode = Configuration::getInstance().StorMode;    // 0 no storage,    1 store,    2 error model  read form file TODO
+    const unsigned int StorageMode = Configuration::getInstance().StorMode;    // 0 no storage,    1 store,    2 error model
 
     flip_memory * fmemory; 
     //Configuration::getInstance().memSpec.NumberOfBanks];
@@ -83,7 +83,7 @@ struct Dram: sc_module
                 cout << "BIT_ERRORS Bank: " <<b <<"="<< fmemory[b].BIT_ERR << endl;
             }
         }
-        //cout << "Simulation finished!!!" << endl; // TODO Aufrauemen!
+        // TODO Aufrauemen!
         //delete fmemory; // TODO Testen!
         //std::cout << "Simulated Memory Size: " << memory.size() << endl; // TODO Aufrauemen
     }
@@ -126,7 +126,7 @@ struct Dram: sc_module
             {
                 // Don't store data
             }
-            else if (StorageMode == 1)    //don't use StorageMode
+            else if (StorageMode == 1) //don't use StorageMode
             {
                 memcpy(&memory[payload.get_address()], payload.get_data_ptr(), BUSWIDTH/8);
             }
@@ -142,7 +142,7 @@ struct Dram: sc_module
             sendToController(payload, END_RD, delay +  getExecutionTime(Command::Read, payload));
 
             // Load data:
-            if (StorageMode == 1)    //don't use StorageMode
+            if (StorageMode == 1)    //use StorageMode
             {
                 if(memory.count(payload.get_address()) == 1)
                 {
@@ -153,7 +153,7 @@ struct Dram: sc_module
                     //SC_REPORT_WARNING ("DRAM", "Reading from an empty memory location.");
                 }
             }
-            else if(StorageMode == 2)// use StorageMode
+            else if(StorageMode == 2)// use StorageMode with errormodel
             {
                 fmemory[bank].load(payload);
             }
@@ -256,6 +256,4 @@ struct Dram: sc_module
 
 };
 
-
-
 #endif /* DRAM_H_ */
diff --git a/dram/src/simulation/StlPlayer.h b/dram/src/simulation/StlPlayer.h
index 884756c2..21f8afe2 100644
--- a/dram/src/simulation/StlPlayer.h
+++ b/dram/src/simulation/StlPlayer.h
@@ -35,7 +35,7 @@ public:
         long parsedAdress = std::stoi(address.c_str(), 0, 16);
 
         gp* payload = this->allocatePayload();
-        unsigned char * dataElement = new unsigned char[16]; // TODO: column / burst breite
+        unsigned char * dataElement = new unsigned char[16*2]; // TODO: column / burst breite
 
         payload->set_address(parsedAdress);
         payload->set_response_status(TLM_INCOMPLETE_RESPONSE);
@@ -60,7 +60,7 @@ public:
             {
                 //cout << "parsing write data: " << data << std::endl;
 
-                for(int i = 0; i < 16; i++) // TODO column / burst breite
+                for(int i = 0; i < 16*2; i++) // TODO column / burst breite
                 {
                     std::string byteString = "0x";
                     byteString.append(data.substr(2*(i+1), 2));
@@ -75,7 +75,7 @@ public:
                             (string("Corrupted tracefile, command ") + command + string(" unknown")).c_str());
         }
 
-        sc_time sendingTime = std::stoi(time.c_str())*clk;
+        sc_time sendingTime = std::stoull(time.c_str())*clk;
 
         if (sendingTime <= sc_time_stamp())
         {
diff --git a/dram/src/simulation/TracePlayer.h b/dram/src/simulation/TracePlayer.h
index 55f8ae48..d5c35961 100644
--- a/dram/src/simulation/TracePlayer.h
+++ b/dram/src/simulation/TracePlayer.h
@@ -86,9 +86,9 @@ template<unsigned int BUSWIDTH>
 void TracePlayer<BUSWIDTH>::setDataPointer(gp* payload, unsigned char * dataElement)
 {
     //check if payload takes ownership
-    payload->set_data_length(16); // TODO: column / burst breite ..... buswidth * burst /8
+    payload->set_data_length(16*2); // TODO: column / burst breite ..... buswidth * burst /8
     payload->set_data_ptr(dataElement);
-    for(int i = 0; i < 16; i++) // TODO: column / burst breite
+    for(int i = 0; i < 16*2; i++) // TODO: column / burst breite
         dataElement[i] = 0;
 }
 
@@ -120,6 +120,19 @@ void TracePlayer<BUSWIDTH>::peqCallback(tlm_generic_payload &payload, const tlm_
     }
     else if (phase == BEGIN_RESP)
     {
+//TODO: cleanup:
+//        unsigned char * dataElement = payload.get_data_ptr();
+//
+//        if(payload.get_command() == TLM_READ_COMMAND)
+//        {
+//            cout << "0x";
+//            for(int i=0; i < 16*2; i++)
+//            {
+//                cout << hex << int(dataElement[i]);
+//            }
+//            cout << endl;
+//         }
+
         sendToTarget(payload, END_RESP, SC_ZERO_TIME);
         payload.release();
     }