merged everythin into one project
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Janik Schlemminger
270
dram/src/simulation/controllerwrapper.h
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270
dram/src/simulation/controllerwrapper.h
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/*
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* ControllerWrapper.h
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*
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* Created on: Mar 15, 2014
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* Author: gernhard
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*/
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#ifndef CONTROLLERWRAPPER_H_
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#define CONTROLLERWRAPPER_H_
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#include <tlm.h>
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#include <systemc.h>
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#include <tlm_utils/simple_target_socket.h>
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#include <tlm_utils/simple_initiator_socket.h>
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#include <tlm_utils/peq_with_cb_and_phase.h>
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#include <iostream>
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#include <map>
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#include "../common/protocol.h"
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#include "../common/tlmDBPhaseRecorder.h"
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#include "../core/IWrapperConnector.h"
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#include "../core/Controller.h"
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#include "../scheduler/Scheduler.h"
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#include "../scheduler/Fifo.h"
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using namespace std;
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using namespace tlm;
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using namespace core;
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using namespace scheduler;
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template<unsigned int BUSWIDTH = 128>
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struct ControllerWrapper: public sc_module, public IWrapperConnector
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{
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public:
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tlm_utils::simple_initiator_socket<ControllerWrapper, BUSWIDTH, tlm::tlm_base_protocol_types> iSocket;
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tlm_utils::simple_target_socket<ControllerWrapper, BUSWIDTH, tlm::tlm_base_protocol_types> tSocket;
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ControllerWrapper(sc_module_name name, tlmDBPhaseRecorder& tpr):
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frontendPEQ(this, &ControllerWrapper::frontendPEQCallback), dramPEQ(
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this, &ControllerWrapper::dramPEQCallback), controllerPEQ(this,
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&ControllerWrapper::controllerPEQCallback), tpr(tpr)
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{
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controller = new DramController(*this);
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scheduler = new Fifo(controller->getBankStates());
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inputBufferDelay = controller->config.Timings.clk;
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iSocket.register_nb_transport_bw(this, &ControllerWrapper::nb_transport_bw);
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tSocket.register_nb_transport_fw(this, &ControllerWrapper::nb_transport_fw);
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for(Bank bank:controller->getBankStates().getBanks())
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bankIsFreeForRequest[bank] = true;
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}
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~ControllerWrapper()
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{
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delete controller;
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delete scheduler;
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}
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virtual void send(const ScheduledCommand& command) override
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{
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assert(command.getStart() >= sc_time_stamp());
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sc_time delay = command.getStart() - sc_time_stamp();
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tlm::tlm_phase phase;
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switch (command.getCommand())
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{
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case Read:
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phase = BEGIN_RD;
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break;
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case Write:
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phase = BEGIN_WR;
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break;
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case Refresh:
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phase = BEGIN_REFA;
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break;
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case Activate:
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phase = BEGIN_ACT;
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break;
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case Precharge:
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phase = BEGIN_PRE;
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break;
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default:
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SC_REPORT_FATAL(0, "unsupported command in controller wrapper");
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break;
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}
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dramPEQ.notify(command.getTransaction(), phase, delay);
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}
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virtual void send(Trigger trigger, sc_time time) override
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{
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assert(time >= sc_time_stamp());
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sc_time delay = time - sc_time_stamp();
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controllerPEQ.notify(triggerDummy, REFRESH_TRIGGER, delay);
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}
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private:
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DramController* controller;
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Scheduler* scheduler;
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map<Bank, bool> bankIsFreeForRequest;
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tlm_utils::peq_with_cb_and_phase<ControllerWrapper> frontendPEQ;
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tlm_utils::peq_with_cb_and_phase<ControllerWrapper> dramPEQ;
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tlm_utils::peq_with_cb_and_phase<ControllerWrapper> controllerPEQ;
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sc_time inputBufferDelay;
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tlm::tlm_generic_payload triggerDummy;
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tlmDBPhaseRecorder& tpr;
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void payloadEntersSystem(tlm_generic_payload& payload)
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{
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//std::cout << "----------------------------------------------------------------------- " << std::endl;
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//std::cout << "Transaction enters system at " << sc_time_stamp() << std::endl;
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Bank bank = DramExtension::getExtension(payload).getBank();
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scheduler->schedule(&payload);
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scheduleNextPayload(bank);
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}
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void scheduleNextPayload(Bank bank)
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{
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//std::cout << "----------------------------------------------------------------------- " << std::endl;
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//std::cout << "In trigger for bank " << bank.ID() << std::endl;
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if(controller->isBusy(sc_time_stamp(), bank))
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return;
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else if(scheduler->hasTransactionForBank(bank))
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{
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tlm_generic_payload* nextTransaction = scheduler->getTransactionForBank(bank);
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if(controller->schedule(sc_time_stamp(), *nextTransaction))
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{
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//std::cout << "Next payload was scheduled by core " << std::endl;
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scheduler->popTransactionForBank(bank);
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}
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else
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{
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//std::cout << "Next payload was not scheduled because of refresh " << std::endl;
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}
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}
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}
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void payloadLeavesSystem(tlm_generic_payload& payload)
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{
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}
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// Initiated by dram
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tlm_sync_enum nb_transport_bw(tlm_generic_payload& payload, tlm_phase& phase, sc_time& bwDelay)
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{
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dramPEQ.notify(payload, phase, bwDelay);
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return TLM_ACCEPTED;
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}
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// Initiated by dram frontend
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tlm_sync_enum nb_transport_fw(tlm_generic_payload& payload, tlm_phase& phase, sc_time& fwDelay)
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{
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DramExtension::getExtension(payload);
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tpr.recordPhase(payload,phase,sc_time_stamp());
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if (phase == BEGIN_REQ)
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{
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payload.acquire();
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frontendPEQ.notify(payload, phase, inputBufferDelay);
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}
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else if (phase == END_RESP)
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{
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payloadLeavesSystem(payload);
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payload.release();
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}
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return TLM_ACCEPTED;
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}
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void frontendPEQCallback(tlm_generic_payload& payload, const tlm_phase& phase)
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{
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if (phase == BEGIN_REQ)
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{
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payloadEntersSystem(payload);
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payload.set_response_status(tlm::TLM_OK_RESPONSE);
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tpr.recordPhase(payload, END_REQ, sc_time_stamp());
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sendToFrontend(payload, END_REQ, SC_ZERO_TIME);
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}
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else
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{
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SC_REPORT_FATAL(0,
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"Frontend PEQ event queue in controller wrapper was triggered with unknown phase");
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}
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}
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void dramPEQCallback(tlm_generic_payload& payload, const tlm_phase& phase)
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{
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tpr.recordPhase(payload,phase,sc_time_stamp());
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DramExtension *result = NULL;
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payload.get_extension(result);
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if(result==NULL)
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{
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cout << "ERROR AT TIME " << sc_time_stamp() << std::endl;
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cout << "Payload " << payload.get_address() << " " << phase;
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assert(result != NULL);
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}
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if (phase == BEGIN_RD || phase == BEGIN_WR)
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{
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//std::cout << "BEGIN_RD at " <<sc_time_stamp() << " on Bank " << DramExtension::getExtension(payload).getBank().ID() << std::endl;
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scheduleNextPayload(DramExtension::getExtension(payload).getBank());
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sendToDram(payload, phase, SC_ZERO_TIME);
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}
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else if(phase == BEGIN_REFA || phase == BEGIN_ACT
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|| phase == BEGIN_PRE)
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{
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sendToDram(payload, phase, SC_ZERO_TIME);
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}
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else if(phase == END_REFA)
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{
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//std::cout << " --- END_REFA --- @:" <<sc_time_stamp() << std::endl;
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for(Bank bank:controller->getBankStates().getBanks())
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scheduleNextPayload(bank);
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}
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else if (phase == END_RD || phase == END_WR)
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{
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tpr.recordPhase(payload, BEGIN_RESP, sc_time_stamp());
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sendToFrontend(payload, BEGIN_RESP, SC_ZERO_TIME);
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}
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else if (phase == END_PRE || phase == END_ACT)
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{
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}
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else
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{
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SC_REPORT_FATAL(0,
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"dramPEQCallback queue in controller wrapper was triggered with unknown phase");
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}
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}
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void controllerPEQCallback(tlm_generic_payload& payload, const tlm_phase& phase)
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{
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if (phase == REFRESH_TRIGGER)
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{
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controller->scheduleRefresh(sc_time_stamp());
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}
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else
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{
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SC_REPORT_FATAL(0,
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"controllerPEQCallback queue in controller wrapper was triggered with unknown phase");
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}
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}
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void sendToDram(tlm_generic_payload& payload, const tlm_phase& phase, const sc_time& delay)
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{
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DramExtension::getExtension(payload);
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tlm_phase TPhase = phase;
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sc_time TDelay = delay;
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iSocket->nb_transport_fw(payload, TPhase, TDelay);
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}
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void sendToFrontend(tlm_generic_payload& payload, const tlm_phase& phase, const sc_time& delay)
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{
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tlm_phase TPhase = phase;
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sc_time TDelay = delay;
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tSocket->nb_transport_bw(payload, TPhase, TDelay);
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}
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};
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#endif /* CONTROLLERWRAPPER_H_ */
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