merged everythin into one project

This commit is contained in:
Janik Schlemminger
2014-03-21 13:46:38 +01:00
parent 27e209f549
commit cd556eb572
53 changed files with 9026 additions and 219 deletions

View File

@@ -1,80 +1,8 @@
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<scannerConfigBuildInfo instanceId="cdt.managedbuild.config.gnu.exe.debug.513647443;cdt.managedbuild.config.gnu.exe.debug.513647443.;cdt.managedbuild.tool.gnu.c.compiler.exe.debug.151665950;cdt.managedbuild.tool.gnu.c.compiler.input.1721222219">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
</scannerConfigBuildInfo>
<scannerConfigBuildInfo instanceId="cdt.managedbuild.config.gnu.exe.debug.1370040858.2044251296;cdt.managedbuild.config.gnu.exe.debug.1370040858.2044251296.;cdt.managedbuild.tool.gnu.cpp.compiler.exe.debug.743207946;cdt.managedbuild.tool.gnu.cpp.compiler.input.1014131258">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
</scannerConfigBuildInfo>

2
dram/.gitignore vendored
View File

@@ -1,3 +1,5 @@
/simulation
/unit_test
/unit_test
/build-simulation
/simulation-build

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@@ -1,20 +1,10 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project>
<configuration id="cdt.managedbuild.config.gnu.exe.debug.1370040858" name="simulation">
<configuration id="cdt.managedbuild.config.gnu.exe.debug.513647443" name="build-simulation">
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-64906255729110141" id="org.eclipse.cdt.managedbuilder.core.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT GCC Built-in Compiler Settings" parameter="${COMMAND} -E -P -v -dD &quot;${INPUTS}&quot; -std=c++11">
<language-scope id="org.eclipse.cdt.core.gcc"/>
<language-scope id="org.eclipse.cdt.core.g++"/>
</provider>
</extension>
</configuration>
<configuration id="cdt.managedbuild.config.gnu.exe.debug.1370040858.2044251296" name="unit_test">
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-64906255729110141" id="org.eclipse.cdt.managedbuilder.core.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT GCC Built-in Compiler Settings" parameter="${COMMAND} -E -P -v -dD &quot;${INPUTS}&quot; -std=c++11">
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-2055719358" id="org.eclipse.cdt.managedbuilder.core.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT GCC Built-in Compiler Settings" parameter="${COMMAND} -E -P -v -dD &quot;${INPUTS}&quot; -std=c++11">
<language-scope id="org.eclipse.cdt.core.gcc"/>
<language-scope id="org.eclipse.cdt.core.g++"/>
</provider>

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@@ -0,0 +1,50 @@
/*
* DebugManager.cpp
*
* Created on: Mar 20, 2014
* Author: jonny
*/
#include "DebugManager.h"
#include <string>
using namespace std;
DebugManager& DebugManager::getInstance()
{
static DebugManager manager;
return manager;
}
void DebugManager::printDebug(Importance importancy, Sender sender, sc_time time, std::string message)
{
cout << "[" << importancyToString(importancy) << "]";
if(printTime) std::cout << " at " << time;
if(printLocation) std::cout << " in " << senderToString(sender);
cout << ": " << message << endl;
}
string DebugManager::importancyToString(Importance importancy)
{
//if((unsigned int)importancy == Importancy::Warning)
// return "Warning";
switch(importancy)
{
case Importance::Info: return "[Info]";
case Importance::Warning: return "[Warning]";
case Importance::Error: return "[Error]";
}
return "unknown importance";
}
string DebugManager::senderToString(Sender sender)
{
/*switch(sender)
{
case Sender::Core: return "Core";
case Sender::Scheduler: return "Scheduler";
}*/
return "Core";
}

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@@ -0,0 +1,35 @@
/*
* DebugManager.h
*
* Created on: Mar 20, 2014
* Author: jonny
*/
#ifndef DEBUGMANAGER_H_
#define DEBUGMANAGER_H_
#include <systemc.h>
enum class Importance {Warning, Error, Info};
class DebugManager
{
public:
static DebugManager& getInstance();
enum Sender {Core, Scheduler};
bool printTime;
bool printLocation;
void printDebug(Importance i, Sender s, sc_time time, std::string message);
private:
DebugManager() : printTime(true), printLocation(true) {};
DebugManager(const DebugManager&);
std::string senderToString(Sender sender);
std::string importancyToString(Importance importancy);
};
#endif /* DEBUGMANAGER_H_ */

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@@ -0,0 +1,94 @@
#include "dramExtension.h"
#include <assert.h>
using namespace tlm;
tlm_extension_base* DramExtension::clone() const
{
return new DramExtension(thread, bank, row, column);
}
void DramExtension::copy_from(const tlm_extension_base &ext)
{
const DramExtension &cpyFrom = static_cast<const DramExtension&>(ext);
thread = cpyFrom.thread;
bank = cpyFrom.bank;
row = cpyFrom.row;
column = cpyFrom.column;
}
/* Static methods
*
*/
const DramExtension& DramExtension::getExtension(const tlm_generic_payload *payload)
{
DramExtension *result = NULL;
payload->get_extension(result);
assert(result != NULL);
return *result;
}
const DramExtension& DramExtension::getExtension(const tlm_generic_payload &payload)
{
return DramExtension::getExtension(&payload);
}
bool operator ==(const Thread& lhs, const Thread& rhs)
{
return lhs.ID() == rhs.ID();
}
bool operator !=(const Thread& lhs, const Thread& rhs)
{
return !(lhs == rhs);
}
bool operator ==(const Channel& lhs, const Channel& rhs)
{
return lhs.ID() == rhs.ID();
}
bool operator !=(const Channel& lhs, const Channel& rhs)
{
return !(lhs == rhs);
}
bool operator ==(const Bank& lhs, const Bank& rhs)
{
return lhs.ID() == rhs.ID();
}
bool operator !=(const Bank& lhs, const Bank& rhs)
{
return !(lhs == rhs);
}
bool operator <(const Bank& lhs, const Bank& rhs)
{
return lhs.ID() < rhs.ID();
}
const Row Row::NO_ROW;
bool operator ==(const Row& lhs, const Row& rhs)
{
if(lhs.isNoRow != rhs.isNoRow)
return false;
return lhs.ID() == rhs.ID();
}
bool operator !=(const Row& lhs, const Row& rhs)
{
return !(lhs == rhs);
}
bool operator ==(const Column& lhs, const Column& rhs)
{
return lhs.ID() == rhs.ID();
}
bool operator !=(const Column& lhs, const Column& rhs)
{
return !(lhs == rhs);
}

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/*
* DramExtension.h
*
* Created on: Mar 9, 2014
* Author: gernhard
*/
#ifndef DRAMEXTENSION_H_
#define DRAMEXTENSION_H_
#include <tlm.h>
#include <iostream>
class Thread
{
public :
explicit Thread(unsigned int id) : id(id) {}
unsigned int ID() const { return id;}
private:
unsigned int id;
};
class Channel
{
public :
explicit Channel(unsigned int id) : id(id) {}
unsigned int ID() const { return id;}
private:
unsigned int id;
};
class Bank
{
public :
explicit Bank(unsigned int id) : id(id) {}
unsigned int ID() const { return id;}
private:
unsigned int id;
};
class Row
{
public :
static const Row NO_ROW;
Row() : id(0), isNoRow(true) {}
explicit Row(unsigned int id) : id(id), isNoRow(false) {}
unsigned int ID() const { return id;}
private:
unsigned int id;
bool isNoRow;
friend bool operator==(const Row &lhs, const Row &rhs);
};
class Column
{
public :
explicit Column(unsigned int id) : id(id) {}
unsigned int ID() const { return id;}
private:
unsigned int id;
};
bool operator==(const Thread &lhs, const Thread &rhs);
bool operator!=(const Thread &lhs, const Thread &rhs);
bool operator==(const Channel &lhs, const Channel &rhs);
bool operator!=(const Channel &lhs, const Channel &rhs);
bool operator==(const Bank &lhs, const Bank &rhs);
bool operator!=(const Bank &lhs, const Bank &rhs);
bool operator<(const Bank &lhs, const Bank &rhs);
bool operator==(const Row &lhs, const Row &rhs);
bool operator!=(const Row &lhs, const Row &rhs);
bool operator==(const Column &lhs, const Column &rhs);
bool operator!=(const Column &lhs, const Column &rhs);
class DramExtension : public tlm::tlm_extension<DramExtension>
{
private:
Thread thread;
Channel channel;
Bank bank;
Row row;
Column column;
public:
DramExtension():thread(0),channel(0),bank(0),row(0),column(0){}
DramExtension(const Thread& thread, const Bank& bank, const Row& row, const Column& column) :
thread(thread),channel(0),bank(bank),row(row),column(column){}
DramExtension(const Thread& thread,const Channel& channel, const Bank& bank, const Row& row, const Column& column) :
thread(thread),channel(channel),bank(bank),row(row),column(column){}
~DramExtension(){}
virtual tlm::tlm_extension_base* clone() const;
virtual void copy_from(const tlm_extension_base &ext);
const Thread& getThread() const{return thread;}
const Channel& getChannel() const{return channel;}
const Bank& getBank() const{return bank;}
const Row& getRow() const{return row;}
const Column& getColumn() const{return column;}
static const DramExtension& getExtension(const tlm::tlm_generic_payload *payload);
static const DramExtension& getExtension(const tlm::tlm_generic_payload &payload);
};
#endif /* DRAMEXTENSION_H_ */

50
dram/src/common/protocol.h Executable file
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#ifndef EXTENDED_PHASE_DRAM
#define EXTENDED_PHASE_DRAM
// DRAM Control Phases
DECLARE_EXTENDED_PHASE(BEGIN_PRE);
DECLARE_EXTENDED_PHASE(END_PRE);
DECLARE_EXTENDED_PHASE(BEGIN_ACT);
DECLARE_EXTENDED_PHASE(END_ACT);
DECLARE_EXTENDED_PHASE(BEGIN_REFA);
DECLARE_EXTENDED_PHASE(END_REFA);
DECLARE_EXTENDED_PHASE(BEGIN_REFB);
DECLARE_EXTENDED_PHASE(END_REFB);
// Phases for Read and Write
DECLARE_EXTENDED_PHASE(BEGIN_WR);
DECLARE_EXTENDED_PHASE(END_WR);
DECLARE_EXTENDED_PHASE(BEGIN_RD);
DECLARE_EXTENDED_PHASE(END_RD);
DECLARE_EXTENDED_PHASE(BEGIN_WRA);
DECLARE_EXTENDED_PHASE(END_WRA);
DECLARE_EXTENDED_PHASE(BEGIN_RDA);
DECLARE_EXTENDED_PHASE(END_RDA);
// Phases for Power Down
DECLARE_EXTENDED_PHASE(BEGIN_PDNP);
DECLARE_EXTENDED_PHASE(END_PDNP);
DECLARE_EXTENDED_PHASE(BEGIN_PDNA);
DECLARE_EXTENDED_PHASE(END_PDNA);
DECLARE_EXTENDED_PHASE(BEGIN_SREF);
DECLARE_EXTENDED_PHASE(END_SREF);
// Internal Phases
DECLARE_EXTENDED_PHASE(START_PROCESSING);
DECLARE_EXTENDED_PHASE(AUTO_PRECHARGE);
//Triggers
DECLARE_EXTENDED_PHASE(REFRESH_TRIGGER);
#endif

111
dram/src/common/third_party/tinystr.cpp vendored Executable file
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/*
www.sourceforge.net/projects/tinyxml
This software is provided 'as-is', without any express or implied
warranty. In no event will the authors be held liable for any
damages arising from the use of this software.
Permission is granted to anyone to use this software for any
purpose, including commercial applications, and to alter it and
redistribute it freely, subject to the following restrictions:
1. The origin of this software must not be misrepresented; you must
not claim that you wrote the original software. If you use this
software in a product, an acknowledgment in the product documentation
would be appreciated but is not required.
2. Altered source versions must be plainly marked as such, and
must not be misrepresented as being the original software.
3. This notice may not be removed or altered from any source
distribution.
*/
#ifndef TIXML_USE_STL
#include "tinystr.h"
// Error value for find primitive
const TiXmlString::size_type TiXmlString::npos = static_cast< TiXmlString::size_type >(-1);
// Null rep.
TiXmlString::Rep TiXmlString::nullrep_ = { 0, 0, { '\0' } };
void TiXmlString::reserve (size_type cap)
{
if (cap > capacity())
{
TiXmlString tmp;
tmp.init(length(), cap);
memcpy(tmp.start(), data(), length());
swap(tmp);
}
}
TiXmlString& TiXmlString::assign(const char* str, size_type len)
{
size_type cap = capacity();
if (len > cap || cap > 3*(len + 8))
{
TiXmlString tmp;
tmp.init(len);
memcpy(tmp.start(), str, len);
swap(tmp);
}
else
{
memmove(start(), str, len);
set_size(len);
}
return *this;
}
TiXmlString& TiXmlString::append(const char* str, size_type len)
{
size_type newsize = length() + len;
if (newsize > capacity())
{
reserve (newsize + capacity());
}
memmove(finish(), str, len);
set_size(newsize);
return *this;
}
TiXmlString operator + (const TiXmlString & a, const TiXmlString & b)
{
TiXmlString tmp;
tmp.reserve(a.length() + b.length());
tmp += a;
tmp += b;
return tmp;
}
TiXmlString operator + (const TiXmlString & a, const char* b)
{
TiXmlString tmp;
TiXmlString::size_type b_len = static_cast<TiXmlString::size_type>( strlen(b) );
tmp.reserve(a.length() + b_len);
tmp += a;
tmp.append(b, b_len);
return tmp;
}
TiXmlString operator + (const char* a, const TiXmlString & b)
{
TiXmlString tmp;
TiXmlString::size_type a_len = static_cast<TiXmlString::size_type>( strlen(a) );
tmp.reserve(a_len + b.length());
tmp.append(a, a_len);
tmp += b;
return tmp;
}
#endif // TIXML_USE_STL

305
dram/src/common/third_party/tinystr.h vendored Executable file
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/*
www.sourceforge.net/projects/tinyxml
This software is provided 'as-is', without any express or implied
warranty. In no event will the authors be held liable for any
damages arising from the use of this software.
Permission is granted to anyone to use this software for any
purpose, including commercial applications, and to alter it and
redistribute it freely, subject to the following restrictions:
1. The origin of this software must not be misrepresented; you must
not claim that you wrote the original software. If you use this
software in a product, an acknowledgment in the product documentation
would be appreciated but is not required.
2. Altered source versions must be plainly marked as such, and
must not be misrepresented as being the original software.
3. This notice may not be removed or altered from any source
distribution.
*/
#ifndef TIXML_USE_STL
#ifndef TIXML_STRING_INCLUDED
#define TIXML_STRING_INCLUDED
#include <assert.h>
#include <string.h>
/* The support for explicit isn't that universal, and it isn't really
required - it is used to check that the TiXmlString class isn't incorrectly
used. Be nice to old compilers and macro it here:
*/
#if defined(_MSC_VER) && (_MSC_VER >= 1200 )
// Microsoft visual studio, version 6 and higher.
#define TIXML_EXPLICIT explicit
#elif defined(__GNUC__) && (__GNUC__ >= 3 )
// GCC version 3 and higher.s
#define TIXML_EXPLICIT explicit
#else
#define TIXML_EXPLICIT
#endif
/*
TiXmlString is an emulation of a subset of the std::string template.
Its purpose is to allow compiling TinyXML on compilers with no or poor STL support.
Only the member functions relevant to the TinyXML project have been implemented.
The buffer allocation is made by a simplistic power of 2 like mechanism : if we increase
a string and there's no more room, we allocate a buffer twice as big as we need.
*/
class TiXmlString
{
public :
// The size type used
typedef size_t size_type;
// Error value for find primitive
static const size_type npos; // = -1;
// TiXmlString empty constructor
TiXmlString () : rep_(&nullrep_)
{
}
// TiXmlString copy constructor
TiXmlString ( const TiXmlString & copy) : rep_(0)
{
init(copy.length());
memcpy(start(), copy.data(), length());
}
// TiXmlString constructor, based on a string
TIXML_EXPLICIT TiXmlString ( const char * copy) : rep_(0)
{
init( static_cast<size_type>( strlen(copy) ));
memcpy(start(), copy, length());
}
// TiXmlString constructor, based on a string
TIXML_EXPLICIT TiXmlString ( const char * str, size_type len) : rep_(0)
{
init(len);
memcpy(start(), str, len);
}
// TiXmlString destructor
~TiXmlString ()
{
quit();
}
TiXmlString& operator = (const char * copy)
{
return assign( copy, (size_type)strlen(copy));
}
TiXmlString& operator = (const TiXmlString & copy)
{
return assign(copy.start(), copy.length());
}
// += operator. Maps to append
TiXmlString& operator += (const char * suffix)
{
return append(suffix, static_cast<size_type>( strlen(suffix) ));
}
// += operator. Maps to append
TiXmlString& operator += (char single)
{
return append(&single, 1);
}
// += operator. Maps to append
TiXmlString& operator += (const TiXmlString & suffix)
{
return append(suffix.data(), suffix.length());
}
// Convert a TiXmlString into a null-terminated char *
const char * c_str () const { return rep_->str; }
// Convert a TiXmlString into a char * (need not be null terminated).
const char * data () const { return rep_->str; }
// Return the length of a TiXmlString
size_type length () const { return rep_->size; }
// Alias for length()
size_type size () const { return rep_->size; }
// Checks if a TiXmlString is empty
bool empty () const { return rep_->size == 0; }
// Return capacity of string
size_type capacity () const { return rep_->capacity; }
// single char extraction
const char& at (size_type index) const
{
assert( index < length() );
return rep_->str[ index ];
}
// [] operator
char& operator [] (size_type index) const
{
assert( index < length() );
return rep_->str[ index ];
}
// find a char in a string. Return TiXmlString::npos if not found
size_type find (char lookup) const
{
return find(lookup, 0);
}
// find a char in a string from an offset. Return TiXmlString::npos if not found
size_type find (char tofind, size_type offset) const
{
if (offset >= length()) return npos;
for (const char* p = c_str() + offset; *p != '\0'; ++p)
{
if (*p == tofind) return static_cast< size_type >( p - c_str() );
}
return npos;
}
void clear ()
{
//Lee:
//The original was just too strange, though correct:
// TiXmlString().swap(*this);
//Instead use the quit & re-init:
quit();
init(0,0);
}
/* Function to reserve a big amount of data when we know we'll need it. Be aware that this
function DOES NOT clear the content of the TiXmlString if any exists.
*/
void reserve (size_type cap);
TiXmlString& assign (const char* str, size_type len);
TiXmlString& append (const char* str, size_type len);
void swap (TiXmlString& other)
{
Rep* r = rep_;
rep_ = other.rep_;
other.rep_ = r;
}
private:
void init(size_type sz) { init(sz, sz); }
void set_size(size_type sz) { rep_->str[ rep_->size = sz ] = '\0'; }
char* start() const { return rep_->str; }
char* finish() const { return rep_->str + rep_->size; }
struct Rep
{
size_type size, capacity;
char str[1];
};
void init(size_type sz, size_type cap)
{
if (cap)
{
// Lee: the original form:
// rep_ = static_cast<Rep*>(operator new(sizeof(Rep) + cap));
// doesn't work in some cases of new being overloaded. Switching
// to the normal allocation, although use an 'int' for systems
// that are overly picky about structure alignment.
const size_type bytesNeeded = sizeof(Rep) + cap;
const size_type intsNeeded = ( bytesNeeded + sizeof(int) - 1 ) / sizeof( int );
rep_ = reinterpret_cast<Rep*>( new int[ intsNeeded ] );
rep_->str[ rep_->size = sz ] = '\0';
rep_->capacity = cap;
}
else
{
rep_ = &nullrep_;
}
}
void quit()
{
if (rep_ != &nullrep_)
{
// The rep_ is really an array of ints. (see the allocator, above).
// Cast it back before delete, so the compiler won't incorrectly call destructors.
delete [] ( reinterpret_cast<int*>( rep_ ) );
}
}
Rep * rep_;
static Rep nullrep_;
} ;
inline bool operator == (const TiXmlString & a, const TiXmlString & b)
{
return ( a.length() == b.length() ) // optimization on some platforms
&& ( strcmp(a.c_str(), b.c_str()) == 0 ); // actual compare
}
inline bool operator < (const TiXmlString & a, const TiXmlString & b)
{
return strcmp(a.c_str(), b.c_str()) < 0;
}
inline bool operator != (const TiXmlString & a, const TiXmlString & b) { return !(a == b); }
inline bool operator > (const TiXmlString & a, const TiXmlString & b) { return b < a; }
inline bool operator <= (const TiXmlString & a, const TiXmlString & b) { return !(b < a); }
inline bool operator >= (const TiXmlString & a, const TiXmlString & b) { return !(a < b); }
inline bool operator == (const TiXmlString & a, const char* b) { return strcmp(a.c_str(), b) == 0; }
inline bool operator == (const char* a, const TiXmlString & b) { return b == a; }
inline bool operator != (const TiXmlString & a, const char* b) { return !(a == b); }
inline bool operator != (const char* a, const TiXmlString & b) { return !(b == a); }
TiXmlString operator + (const TiXmlString & a, const TiXmlString & b);
TiXmlString operator + (const TiXmlString & a, const char* b);
TiXmlString operator + (const char* a, const TiXmlString & b);
/*
TiXmlOutStream is an emulation of std::ostream. It is based on TiXmlString.
Only the operators that we need for TinyXML have been developped.
*/
class TiXmlOutStream : public TiXmlString
{
public :
// TiXmlOutStream << operator.
TiXmlOutStream & operator << (const TiXmlString & in)
{
*this += in;
return *this;
}
// TiXmlOutStream << operator.
TiXmlOutStream & operator << (const char * in)
{
*this += in;
return *this;
}
} ;
#endif // TIXML_STRING_INCLUDED
#endif // TIXML_USE_STL

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dram/src/common/third_party/tinyxml.cpp vendored Executable file

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dram/src/common/third_party/tinyxml.h vendored Executable file

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52
dram/src/common/third_party/tinyxmlerror.cpp vendored Executable file
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/*
www.sourceforge.net/projects/tinyxml
Original code (2.0 and earlier )copyright (c) 2000-2006 Lee Thomason (www.grinninglizard.com)
This software is provided 'as-is', without any express or implied
warranty. In no event will the authors be held liable for any
damages arising from the use of this software.
Permission is granted to anyone to use this software for any
purpose, including commercial applications, and to alter it and
redistribute it freely, subject to the following restrictions:
1. The origin of this software must not be misrepresented; you must
not claim that you wrote the original software. If you use this
software in a product, an acknowledgment in the product documentation
would be appreciated but is not required.
2. Altered source versions must be plainly marked as such, and
must not be misrepresented as being the original software.
3. This notice may not be removed or altered from any source
distribution.
*/
#include "tinyxml.h"
// The goal of the seperate error file is to make the first
// step towards localization. tinyxml (currently) only supports
// english error messages, but the could now be translated.
//
// It also cleans up the code a bit.
//
const char* TiXmlBase::errorString[ TiXmlBase::TIXML_ERROR_STRING_COUNT ] =
{
"No error",
"Error",
"Failed to open file",
"Error parsing Element.",
"Failed to read Element name",
"Error reading Element value.",
"Error reading Attributes.",
"Error: empty tag.",
"Error reading end tag.",
"Error parsing Unknown.",
"Error parsing Comment.",
"Error parsing Declaration.",
"Error document empty.",
"Error null (0) or unexpected EOF found in input stream.",
"Error parsing CDATA.",
"Error when TiXmlDocument added to document, because TiXmlDocument can only be at the root.",
};

1638
dram/src/common/third_party/tinyxmlparser.cpp vendored Executable file

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// Filename: tlm2_base_protocol_checker.h
//----------------------------------------------------------------------
// Copyright (c) 2008 by Doulos Ltd.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//----------------------------------------------------------------------
// Author: John Aynsley, Doulos
// Version 1, 11 July 2008
// Version 2, 16 July 2008 Only generate ref_count > 1 warning from 1st checker of path
// Version 3, 17 July 2008 Support compilation under SystemC 2.1.v1
// Version 4, 12 Aug 2008 Add header #include <map>
// Version 5, 08 Sep 2008 Fix bugs in message text
// TLM-2.0 Base Protocol Compliance Checker
/*
Instantiate this checker module in-line between initiator and target, initiator and interconnect,
or interconnect and target by binding the target_socket and initiator_socket
Binding two checkers either side of an interconnect component, or interleaving a series of
checkers with interconnect components, will enable some deeper checks as against having just
a single checker
For example
Initiator *initiator;
Bus *bus;
Memory *memory;
...
initiator->socket.bind(bus->target_socket);
bus->initiator_socket.bind(memory->socket);
might become
tlm_utils::tlm2_base_protocol_checker<32> *checker1;
tlm_utils::tlm2_base_protocol_checker<32> *checker2;
...
initiator->socket.bind(checker1->target_socket);
checker1->initiator_socket.bind(bus->target_socket);
bus->initiator_socket.bind(checker2->target_socket);
checker2->initiator_socket.bind(memory->socket);
GENERAL FEATURES OF THE BASE PROTOCOL CHECKER
The checks are relatively expensive, hence by default the number of checks is limited.
A maximum number can be set explicitly by calling set_num_checks(max)
Checking can be deactivated at any time by calling set_num_checks(0)
All checkers decrement a single global count, because having some checkers running and
others not can cause bogus violation reports
It is not permitted to turn checks on by calling set_num_checks() once checking has been
deactivated, because this could cause bogus violation reports
The DMI and debug checks are unaffected by the num_checks count (because they are cheap)
The error messages contain User Manual references
The checker is designed to be used with a transaction pool: otherwise it could consume
a lot of memory. The checker keeps a local copy of each transaction object
Failures are reported with a severity of SC_ERROR. The actions may be overridden by calling:
sc_report_handler::set_actions("tlm2_protocol_checker", ...);
SPECIFIC CHECKS
nb_transport: phase sequence BEGIN_REQ -> END_REQ -> BEGIN_RESP -> END_RESP
Must not have two outstanding requests or responses (exclusion rules)
Must not have decreasing timing annotations on calls to or returns from nb_transport_fw/bw
Phase extensions permitted and ignored
Must not call b_transport during nb_transport phase sequence and vice-versa
nb_transport: memory manager must be set
nb_transport: reference count must be non-zero
First checker in BEGIN_REQ path should see ref_count == 1 (warning only)
An interconnect component that sets a memory manager should also clear it
An interconnect component that sets extensions with no memory manager should also clear them
(Does not bother with these memory manager checks for DMI and debug)
Transaction object must be properly initialized
Many generic payload attributes must not be modified during the transaction lifetime
Transaction object must not be re-allocated for a new transaction while still in use
DMI descriptor must be properly initialized
Debug transaction must be properly initialized
Debug byte count must be less than data_length
Checks that require multiple checkers to be instantiated along a transaction path:
The BEGIN_RESP path must be the reverse of the BEGIN_REQ path
Transaction object must not be sent with BEGIN_REQ while participating in a previous response
Interconnect component must not set response status attribute to TLM_OK_RESPONSE
Interconnect component must not modify data array on the response path
*/
// ******************** PREAMBLE ********************
#ifndef __tlm2_base_protocol_checker__
#define __tlm2_base_protocol_checker__
#include "systemc"
using std::cout;
using std::endl;
using std::dec;
using std::hex;
#include <tlm.h>
#include <sstream>
#include <map>
namespace tlm_utils {
// Number of checks remaining
const sc_dt::uint64 default_num_checks = 100000;
static sc_dt::uint64 num_checks = default_num_checks;
// Types used when building a trace of the transaction path
typedef unsigned char uchar_t;
typedef std::deque<sc_core::sc_module*> deque_t;
struct path_t {
path_t () { response_in_progress = false; ok_response = false; resp_data_ptr = 0; }
bool response_in_progress;
bool ok_response;
deque_t path;
uchar_t* resp_data_ptr; // Copy of data on response path
};
// Global variable used for checks involving multiple checkers along a transaction path
static std::map<tlm::tlm_generic_payload*, path_t> shared_map;
// ******************** CLASS DEFINITION ********************
template <unsigned int BUSWIDTH = 32>
class tlm2_base_protocol_checker
: public sc_core::sc_module
, public tlm::tlm_fw_transport_if<tlm::tlm_base_protocol_types>
, public tlm::tlm_bw_transport_if<tlm::tlm_base_protocol_types>
{
public:
// Instantiate and bind checker inline between an existing pair of initiator and target sockets
tlm::tlm_target_socket <BUSWIDTH, tlm::tlm_base_protocol_types, 1> target_socket;
tlm::tlm_initiator_socket<BUSWIDTH, tlm::tlm_base_protocol_types, 1> initiator_socket;
SC_CTOR(tlm2_base_protocol_checker)
: m_request_in_progress(0), m_response_in_progress(0)
{
target_socket .bind( *this );
initiator_socket.bind( *this );
}
// Access methods for num_checks count
static void set_num_checks(sc_dt::uint64 n) {
if (num_checks == 0)
SC_REPORT_FATAL("tlm2_protocol_checker", "Method set_num_checks called after checking has stopped due to maximum number of checks being reached");
num_checks = n;
}
static sc_dt::uint64 get_num_checks() { return num_checks; }
// TLM-2.0 interface methods for initiator and target sockets, instrumented with checks
virtual tlm::tlm_sync_enum nb_transport_fw(
tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_core::sc_time& delay)
{
tlm::tlm_phase& start_phase = phase;
if (num_checks)
nb_transport_fw_pre_checks( trans, phase, delay );
tlm::tlm_sync_enum status;
status = initiator_socket->nb_transport_fw( trans, phase, delay );
if (num_checks)
nb_transport_fw_post_checks( trans, start_phase, phase, delay, status );
return status;
}
virtual tlm::tlm_sync_enum nb_transport_bw(
tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_core::sc_time& delay)
{
if (num_checks)
nb_transport_bw_pre_checks( trans, phase, delay );
tlm::tlm_sync_enum status;
status = target_socket->nb_transport_bw( trans, phase, delay );
if (num_checks)
nb_transport_bw_post_checks( trans, phase, delay, status );
return status;
}
virtual void b_transport( tlm::tlm_generic_payload& trans, sc_core::sc_time& delay )
{
if (num_checks)
b_transport_pre_checks( trans, delay );
initiator_socket->b_transport( trans, delay );
if (num_checks)
b_transport_post_checks( trans, delay );
}
virtual bool get_direct_mem_ptr(tlm::tlm_generic_payload& trans,
tlm::tlm_dmi& dmi_data)
{
get_direct_mem_ptr_pre_checks( trans, dmi_data );
bool status;
status = initiator_socket->get_direct_mem_ptr( trans, dmi_data );
return status;
}
virtual void invalidate_direct_mem_ptr(sc_dt::uint64 start_range,
sc_dt::uint64 end_range)
{
target_socket->invalidate_direct_mem_ptr(start_range, end_range);
}
virtual unsigned int transport_dbg(tlm::tlm_generic_payload& trans)
{
transport_dbg_pre_checks( trans );
unsigned int count;
count = initiator_socket->transport_dbg( trans );
transport_dbg_post_checks( trans, count );
return count;
}
private:
void b_transport_pre_checks( tlm::tlm_generic_payload& trans, sc_core::sc_time& delay);
void b_transport_post_checks( tlm::tlm_generic_payload& trans, sc_core::sc_time& delay);
void nb_transport_fw_pre_checks(
tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_core::sc_time& delay);
void nb_transport_fw_post_checks(
tlm::tlm_generic_payload& trans, tlm::tlm_phase& start_phase, tlm::tlm_phase& phase,
sc_core::sc_time& delay, tlm::tlm_sync_enum status);
void nb_transport_bw_pre_checks(
tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_core::sc_time& delay);
void nb_transport_bw_post_checks(
tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_core::sc_time& delay,
tlm::tlm_sync_enum status);
void nb_transport_response_checks(
tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_core::sc_time& delay,
const char* txt2, const char* txt3, const char* txt4);
void check_initial_state( tlm::tlm_generic_payload& trans, const char* txt2 );
void check_trans_not_modified( tlm::tlm_generic_payload& trans, const char* txt2 );
void check_response_path( tlm::tlm_generic_payload& trans, const char* txt2 );
void get_direct_mem_ptr_pre_checks( tlm::tlm_generic_payload& trans, tlm::tlm_dmi& dmi_data );
void transport_dbg_pre_checks( tlm::tlm_generic_payload& trans );
void transport_dbg_post_checks( tlm::tlm_generic_payload& trans, unsigned int count );
void tlm2error( tlm::tlm_generic_payload& trans, const char* ref, bool warning = false );
private:
struct state_t {
state_t() { b_call = 0; ph = tlm::UNINITIALIZED_PHASE; gp = 0; }
bool has_mm;
unsigned int b_call; // Number of b_transport calls in progress
tlm::tlm_phase ph;
sc_core::sc_time time; // Current time + annotated delay
tlm::tlm_generic_payload* gp; // Points to new data and byte enable buffers
uchar_t* data_ptr; // Stores original pointers
uchar_t* byte_enable_ptr;
};
// Transaction state for the specific hop where this checker is inlined
std::map<tlm::tlm_generic_payload*, state_t> m_map;
// Flags for exclusion rules
tlm::tlm_generic_payload* m_request_in_progress;
tlm::tlm_generic_payload* m_response_in_progress;
std::ostringstream txt;
};
// ******************** MEMBER FUNCTION DEFINITIONS ********************
#define BOILERPLATE \
template <unsigned int BUSWIDTH> \
void tlm2_base_protocol_checker<BUSWIDTH>::
BOILERPLATE
b_transport_pre_checks(
tlm::tlm_generic_payload& trans, sc_core::sc_time& delay)
{
++ m_map[&trans].b_call;
if ( trans.has_mm() && trans.get_ref_count() == 0)
{
txt << "Transaction passed to b_transport with memory manager and reference count of 0";
tlm2error(trans, "6.5 s)");
}
check_initial_state(trans, "b_transport");
#if !(defined SYSTEMC_VERSION & SYSTEMC_VERSION <= 20050714)
if (sc_core::sc_get_current_process_handle().proc_kind() == sc_core::SC_METHOD_PROC_)
{
txt << "b_transport called from method process";
tlm2error(trans, "4.1.1.4 b)");
}
#endif
if (m_map[&trans].ph > 0 && m_map[&trans].ph < 4)
{
txt << "b_transport called during a sequence of nb_transport calls";
tlm2error(trans, "7.2.5 k)");
}
}
BOILERPLATE
b_transport_post_checks(
tlm::tlm_generic_payload& trans, sc_core::sc_time& delay)
{
check_response_path(trans, "b_transport");
check_trans_not_modified(trans, "b_transport");
-- m_map[&trans].b_call;
}
BOILERPLATE
nb_transport_fw_pre_checks(
tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_core::sc_time& delay)
{
if ( !trans.has_mm() )
{
txt << "Transaction passed to nb_transport_fw with no memory manager set";
tlm2error(trans, "6.5 h)");
}
if ( trans.get_ref_count() == 0)
{
txt << "Transaction passed to nb_transport_fw with reference count of 0";
tlm2error(trans, "6.5 s)");
}
switch (phase)
{
case tlm::BEGIN_REQ:
check_initial_state(trans, "nb_transport_fw");
if (m_map[&trans].ph > 0 && m_map[&trans].ph < 4) // END_RESP -> BEGIN_REQ is legal
{
txt << "Phase " << phase << " sent out-of-sequence on forward path, detected in nb_transport_fw";
tlm2error(trans, "7.2.3 i)");
}
if (m_request_in_progress)
{
txt << "Transaction violates BEGIN_REQ exclusion rule, detected in nb_transport_fw";
tlm2error(trans, "7.2.4 b)");
}
m_request_in_progress = &trans;
if (m_map[&trans].b_call)
{
txt << "nb_transport_fw called during a b_transport call";
tlm2error(trans, "7.2.5 k)");
}
break;
case tlm::END_REQ:
case tlm::BEGIN_RESP:
case tlm::UNINITIALIZED_PHASE:
txt << "Phase " << phase << " sent on forward path, detected in nb_transport_fw";
tlm2error(trans, "7.2.3 d)");
break;
case tlm::END_RESP:
if (m_map[&trans].ph != tlm::BEGIN_RESP)
{
txt << "Phase " << phase << " sent out-of-sequence on forward path, detected in nb_transport_fw";
tlm2error(trans, "7.2.3 i)");
}
m_response_in_progress = 0;
break;
}
if (phase < 5) // Ignore extended phases
m_map[&trans].ph = phase;
if (sc_core::sc_time_stamp() + delay < m_map[&trans].time)
{
txt << "nb_transport_fw called with decreasing timing annotation:"
<< " delay = " << delay
<< ", sc_time_stamp() + delay from previous call = " << m_map[&trans].time;
tlm2error(trans, "7.2.5 e)");
}
m_map[&trans].time = sc_core::sc_time_stamp() + delay;
}
BOILERPLATE
nb_transport_fw_post_checks(
tlm::tlm_generic_payload& trans, tlm::tlm_phase& start_phase, tlm::tlm_phase& phase,
sc_core::sc_time& delay, tlm::tlm_sync_enum status)
{
if (status == tlm::TLM_UPDATED)
{
nb_transport_response_checks(
trans, phase, delay, "(forward) return", "Return from nb_transport_fw", "nb_transport_fw");
}
else if (status == tlm::TLM_COMPLETED)
{
if (start_phase == tlm::BEGIN_REQ)
check_response_path(trans, "nb_transport_fw");
m_request_in_progress = 0;
m_map[&trans].ph = tlm::UNINITIALIZED_PHASE;
}
// Transaction object should not be re-allocated, even during the END_RESP phase
//if (phase != tlm::END_RESP)
{
std::ostringstream txt;
txt << "nb_transport_fw, phase = " << phase;
check_trans_not_modified(trans, txt.str().c_str());
}
}
BOILERPLATE
nb_transport_bw_pre_checks(
tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_core::sc_time& delay)
{
if ( !trans.has_mm() )
{
txt << "Transaction passed to nb_transport_bw with no memory manager set";
tlm2error(trans, "6.5 h)");
}
if ( trans.get_ref_count() == 0)
{
txt << "Transaction passed to nb_transport_bw with reference count of 0";
tlm2error(trans, "6.5 s)");
}
nb_transport_response_checks(
trans, phase, delay, "backward", "nb_transport_bw called", "nb_transport_bw");
}
BOILERPLATE
nb_transport_bw_post_checks(
tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_core::sc_time& delay,
tlm::tlm_sync_enum status)
{
if (status == tlm::TLM_UPDATED)
{
switch (phase)
{
case tlm::BEGIN_REQ:
txt << "Phase " << phase << " sent out-of-sequence on (backward) return path, detected in nb_transport_bw";
tlm2error(trans, "7.2.3 i)");
break;
case tlm::END_REQ:
case tlm::BEGIN_RESP:
case tlm::UNINITIALIZED_PHASE:
txt << "Phase " << phase << " sent on (backward) return path, detected in nb_transport_bw";
tlm2error(trans, "7.2.3 d)");
break;
case tlm::END_RESP:
if (m_map[&trans].ph != tlm::BEGIN_RESP)
{
txt << "Phase " << phase << " sent out-of-sequence on (backward) return path, detected in nb_transport_bw";
tlm2error(trans, "7.2.3 i)");
}
m_response_in_progress = 0;
break;
}
if (phase < 5) // Ignore extended phases
m_map[&trans].ph = phase;
if (sc_core::sc_time_stamp() + delay < m_map[&trans].time)
{
txt << "Return from nb_transport_bw with decreasing timing annotation:"
<< " delay = " << delay
<< ", sc_time_stamp() + delay from previous call = " << m_map[&trans].time;
tlm2error(trans, "7.2.5 e)");
}
m_map[&trans].time = sc_core::sc_time_stamp() + delay;
}
else if (status == tlm::TLM_COMPLETED)
{
m_response_in_progress = 0;
m_map[&trans].ph = tlm::UNINITIALIZED_PHASE;
}
// Transaction object should not be re-allocated, even during the END_RESP phase
//if (phase != tlm::END_RESP)
{
std::ostringstream txt;
txt << "nb_transport_bw, phase = " << phase;
check_trans_not_modified(trans, txt.str().c_str());
}
}
BOILERPLATE
nb_transport_response_checks(
tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_core::sc_time& delay,
const char* txt2, const char* txt3, const char* txt4)
{
if (trans.is_response_ok())
if (shared_map[&trans].response_in_progress && !shared_map[&trans].ok_response)
{
txt << "Interconnect component sets response status attribute to TLM_OK_RESPONSE"
<< ", detected in " << txt4;
tlm2error(trans, "6.7)");
}
switch (phase)
{
case tlm::BEGIN_REQ:
case tlm::END_RESP:
case tlm::UNINITIALIZED_PHASE:
txt << "Phase " << phase << " sent on " << txt2 << " path"
<< ", detected in " << txt4;
tlm2error(trans, "7.2.3 d)");
break;
case tlm::END_REQ:
if (m_map[&trans].ph != tlm::BEGIN_REQ)
{
txt << "Phase " << phase << " sent out-of-sequence on " << txt2 << " path"
<< ", detected in " << txt4;
tlm2error(trans, "7.2.3 i)");
}
m_request_in_progress = 0;
break;
case tlm::BEGIN_RESP:
if (m_map[&trans].ph != tlm::BEGIN_REQ && m_map[&trans].ph != tlm::END_REQ)
{
txt << "Phase " << phase << " sent out-of-sequence on " << txt2 << " path"
<< ", detected in " << txt4;
tlm2error(trans, "7.2.3 i)");
}
if (&trans == m_request_in_progress)
m_request_in_progress = 0;
if (m_response_in_progress)
{
txt << "Transaction violates BEGIN_RESP exclusion rule"
<< ", detected in " << txt4;
tlm2error(trans, "7.2.4 c)");
}
m_response_in_progress = &trans;
check_response_path(trans, txt4);
break;
}
if (phase < 5) // Ignore extended phases
m_map[&trans].ph = phase;
if (sc_core::sc_time_stamp() + delay < m_map[&trans].time)
{
txt << txt3 << " with decreasing timing annotation:"
<< " delay = " << delay
<< ", sc_time_stamp() + delay from previous call = " << m_map[&trans].time;
tlm2error(trans, "7.2.5 e)");
}
m_map[&trans].time = sc_core::sc_time_stamp() + delay;
}
BOILERPLATE
check_initial_state(
tlm::tlm_generic_payload& trans, const char* txt2 )
{
if (num_checks > 0)
{
--num_checks;
if (num_checks == 0)
SC_REPORT_INFO("tlm2_protocol_checker", "Checkers deactivated after executing the set number of checks");
}
if ( trans.has_mm() && trans.get_ref_count() > 1 && shared_map[&trans].path.empty() )
{
txt << "New transaction passed to " << txt2 << " with reference count = "
<< trans.get_ref_count();
tlm2error(trans, "6.5 s)", true);
}
if (trans.get_data_ptr() == 0)
{
txt << "Transaction not properly initialized: data_ptr == 0, detected in " << txt2;
tlm2error(trans, "6.10 e)");
}
if (trans.get_data_length() == 0)
{
txt << "Transaction not properly initialized: data_langth == 0, detected in " << txt2;
tlm2error(trans, "6.11 d)");
}
if (trans.get_byte_enable_ptr() != 0 && trans.get_byte_enable_length() == 0)
{
txt << "Transaction not properly initialized: "
<< "byte_enable_ptr != 0 and byte_enable_length == 0, detected in " << txt2;
tlm2error(trans, "6.13 f)");
}
if (trans.get_streaming_width() == 0)
{
txt << "Transaction not properly initialized: streaming_width == 0, detected in " << txt2;
tlm2error(trans, "6.14 f)");
}
if (trans.is_dmi_allowed())
{
txt << "Transaction not properly initialized: dmi_allowed == true, detected in " << txt2;
tlm2error(trans, "6.15)");
}
if (trans.get_response_status() != tlm::TLM_INCOMPLETE_RESPONSE)
{
txt << "Transaction not properly initialized: response_status != TLM_INCOMPLETE_RESPONSE, detected in " << txt2;
tlm2error(trans, "6.16 e)");
}
// Setup clones of transaction and buffers in map
tlm::tlm_generic_payload* gp = m_map[&trans].gp;
if (gp == 0)
gp = new tlm::tlm_generic_payload; // Memory leak: transactions are never cleared from map
else
{
delete [] gp->get_data_ptr();
gp->free_all_extensions();
}
gp->set_data_ptr( new uchar_t[trans.get_data_length()] );
m_map[&trans].data_ptr = trans.get_data_ptr();
if (gp->get_byte_enable_ptr())
delete [] gp->get_byte_enable_ptr();
if (trans.get_byte_enable_ptr())
gp->set_byte_enable_ptr( new uchar_t[trans.get_byte_enable_length()] );
else
gp->set_byte_enable_ptr(0);
m_map[&trans].byte_enable_ptr = trans.get_byte_enable_ptr();
gp->deep_copy_from(trans);
m_map[&trans].gp = gp;
m_map[&trans].time = sc_core::SC_ZERO_TIME;
m_map[&trans].has_mm = trans.has_mm();
// Store request path checker sequence
if (shared_map[&trans].resp_data_ptr)
{
delete [] shared_map[&trans].resp_data_ptr;
shared_map[&trans].resp_data_ptr = 0;
}
if (shared_map[&trans].response_in_progress)
{
txt << "Transaction object sent with BEGIN_REQ while still being used on a previous response path, detected in " << txt2;
tlm2error(trans, "6.5");
}
shared_map[&trans].ok_response = false;
shared_map[&trans].path.push_back(this);
}
BOILERPLATE
check_trans_not_modified(
tlm::tlm_generic_payload& trans, const char* txt2 )
{
tlm::tlm_generic_payload* init = m_map[&trans].gp;
if (trans.get_command() != init->get_command())
{
txt << "Command attribute modified during transaction lifetime, detected in " << txt2;
tlm2error(trans, "6.7)");
}
if (trans.get_data_ptr() != m_map[&trans].data_ptr)
{
txt << "Data pointer attribute modified during transaction lifetime, detected in " << txt2;
tlm2error(trans, "6.7)");
}
if (trans.get_data_length() != init->get_data_length())
{
txt << "Data length attribute modified during transaction lifetime, detected in " << txt2;
tlm2error(trans, "6.7)");
}
if (trans.get_command() == tlm::TLM_WRITE_COMMAND)
for (unsigned int i = 0; i < init->get_data_length(); i++)
if (trans.get_data_ptr()[i] != init->get_data_ptr()[i])
{
txt << "Data array modified during transaction lifetime, detected in " << txt2;
tlm2error(trans, "6.7)");
}
if (trans.get_byte_enable_ptr() != m_map[&trans].byte_enable_ptr)
{
txt << "Byte enable pointer attribute modified during transaction lifetime, detected in " << txt2;
tlm2error(trans, "6.7)");
}
if (trans.get_byte_enable_length() != init->get_byte_enable_length())
{
txt << "Byte enable length attribute modified during transaction lifetime, detected in " << txt2;
tlm2error(trans, "6.7)");
}
if (trans.get_byte_enable_ptr())
for (unsigned int i = 0; i < init->get_byte_enable_length(); i++)
if (trans.get_byte_enable_ptr()[i] != init->get_byte_enable_ptr()[i])
{
txt << "Byte enable array modified during transaction lifetime, detected in " << txt2;
tlm2error(trans, "6.7)");
}
if (trans.get_streaming_width() != init->get_streaming_width())
{
txt << "Streaming width attribute modified during transaction lifetime, detected in " << txt2;
tlm2error(trans, "6.7)");
}
if ( !m_map[&trans].has_mm )
{
if (trans.has_mm())
{
txt << "Interconnect component sets a memory manager, but does not clear it on return, detected in " << txt2;
tlm2error(trans, "6.5y)");
}
for (unsigned int i = 0; i < tlm::max_num_extensions(); i++)
if (trans.get_extension(i))
if ( !m_map[&trans].gp->get_extension(i) )
{
txt << "Extension set (index = " << i << ") without also being deleted in the absence of a memory manager, detected in " << txt2;
tlm2error(trans, "6.5 y)");
}
}
uchar_t* resp_data_ptr = shared_map[&trans].resp_data_ptr;
if (resp_data_ptr)
for (unsigned int i = 0; i < trans.get_data_length(); i++)
if (trans.get_data_ptr()[i] != resp_data_ptr[i])
{
txt << "Transaction data array modified in interconnect component on response path, detected in " << txt2;
tlm2error(trans, "6.7)");
}
}
BOILERPLATE
check_response_path(
tlm::tlm_generic_payload& trans, const char* txt2 )
{
if ( !shared_map[&trans].path.empty() )
{
if ( this != shared_map[&trans].path.back() )
{
txt << "BEGIN_RESP path is not the reverse of the BEGIN_REQ path.";
txt << "\nBEGIN_REQ path includes these checkers: -> ";
deque_t path = shared_map[&trans].path;
for (deque_t::iterator i = path.begin(); i < path.end(); i++)
txt << (*i)->name() << " -> ";
txt << "\nDetected in " << txt2;
tlm2error(trans, "7.2.5 m-n)");
}
shared_map[&trans].path.pop_back();
shared_map[&trans].response_in_progress = !shared_map[&trans].path.empty();
shared_map[&trans].ok_response = trans.is_response_ok();
// Create a copy of the data array for comparison on the response path
if ( !shared_map[&trans].resp_data_ptr )
{
shared_map[&trans].resp_data_ptr = new u_char[trans.get_data_length()];
memcpy(shared_map[&trans].resp_data_ptr, trans.get_data_ptr(), trans.get_data_length());
}
}
}
BOILERPLATE
get_direct_mem_ptr_pre_checks(
tlm::tlm_generic_payload& trans, tlm::tlm_dmi& dmi_data )
{
if (dmi_data.get_dmi_ptr() != 0)
{
txt << "DMI descriptor not properly initialized: dmi_ptr != 0";
tlm2error(trans, "4.2.5 f)");
}
if (!dmi_data.is_none_allowed())
{
txt << "DMI descriptor not properly initialized: granted_access != DMI_ACCESS_NONE";
tlm2error(trans, "4.2.5 a)");
}
if (dmi_data.get_start_address() != 0)
{
txt << "DMI descriptor not properly initialized: start_address != 0";
tlm2error(trans, "4.2.5 s)");
}
if (dmi_data.get_end_address() != (sc_dt::uint64)(-1))
{
txt << "DMI descriptor not properly initialized: end_address != 0";
tlm2error(trans, "4.2.5 s)");
}
if (dmi_data.get_read_latency() != sc_core::SC_ZERO_TIME)
{
txt << "DMI descriptor not properly initialized: read_latency != SC_ZERO_TIME";
tlm2error(trans, "4.2.5 aa)");
}
if (dmi_data.get_write_latency() != sc_core::SC_ZERO_TIME)
{
txt << "DMI descriptor not properly initialized: write_latency != SC_ZERO_TIME";
tlm2error(trans, "4.2.5 aa)");
}
}
BOILERPLATE
transport_dbg_pre_checks( tlm::tlm_generic_payload& trans )
{
if (trans.get_data_length() > 0 && trans.get_data_ptr() == 0)
{
txt << "Debug transaction has data_ptr == 0";
tlm2error(trans, "4.3.4 j)");
}
}
BOILERPLATE
transport_dbg_post_checks( tlm::tlm_generic_payload& trans, unsigned int count )
{
if (trans.get_data_length() > 0 && trans.get_data_ptr() == 0)
{
txt << "Debug transaction has data_ptr == 0";
tlm2error(trans, "4.3.4 j)");
}
if (count > trans.get_data_length())
{
txt << "Count returned from transport_dbg is greater than data_length";
tlm2error(trans, "4.3.4 o)");
}
}
BOILERPLATE
tlm2error( tlm::tlm_generic_payload& trans, const char* ref, bool warning )
{
txt << "\n\nRefer to TLM-2.0 User Manual, version JA22, clause " << ref;
txt << "\n\nChecker instance: " << this->name();
txt << "\n\nTransaction details:";
txt << "\n has_mm = " << dec << trans.has_mm() << " (bool)";
txt << "\n ref_count = " << dec << trans.get_ref_count() << " (int)";
txt << "\n\n command = " <<
(trans.get_command() == tlm::TLM_READ_COMMAND ? "TLM_READ_COMMAND"
:trans.get_command() == tlm::TLM_WRITE_COMMAND ? "TLM_WRITE_COMMAND"
: "TLM_IGNORE_COMMAND");
txt << "\n address = " << hex << trans.get_address() << " (hex)";
txt << "\n data_ptr = " << hex
<< reinterpret_cast<int*>(trans.get_data_ptr()) << " (hex)";
txt << "\n data_length = " << hex << trans.get_data_length() << " (hex)";
txt << "\n streaming_width = " << hex << trans.get_streaming_width() << " (hex)";
txt << "\n byte_enable_ptr = " << hex
<< reinterpret_cast<int*>(trans.get_byte_enable_ptr()) << " (hex)";
txt << "\n byte_enable_length = " << hex << trans.get_byte_enable_length() << " (hex)";
txt << "\n dmi_allowed = " << dec << trans.is_dmi_allowed() << " (bool)";
txt << "\n response_status = " << trans.get_response_string();
bool extensions_present = false;
for (unsigned int i = 0; i < tlm::max_num_extensions(); i++)
{
tlm::tlm_extension_base* ext = trans.get_extension(i);
if (ext)
{
if (!extensions_present)
txt << "\n\n extensions:";
txt << "\n index = " << i << " type = " << typeid(*ext).name();
extensions_present = true;
}
}
txt << "\n\n";
if (warning)
SC_REPORT_WARNING("tlm2_protocol_checker", txt.str().c_str());
else
SC_REPORT_ERROR("tlm2_protocol_checker", txt.str().c_str());
}
} // namespace tlm_utils
#endif // __tlm2_base_protocol_checker__

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#include "tlmDBPhaseRecorder.h"
#include "protocol.h"
#include "dramExtension.h"
#include "xmlAddressdecoder.h"
#include <iostream>
using namespace std;
tlmDBPhaseRecorder::tlmDBPhaseRecorder(string name, string pathToConfigs) :
transactionIDCounter(1), PicosecondsPerNanosecond(1e3), pathToConfigs(pathToConfigs)
{
openDB(name.c_str());
createTables();
cout << "Created tables in file " << name << std::endl;
setUpTransactionTerminatingPhases();
cout << "Set up terminating phases " << name << std::endl;
prepareSqlStatements();
cout << "Prepared statements " << name << std::endl;
sqlite3_exec(db, "BEGIN", 0, 0, 0);
cout << "Started new transaction " << name << std::endl;
}
tlmDBPhaseRecorder::~tlmDBPhaseRecorder()
{
insertGeneralInfo();
sqlite3_exec(db, "COMMIT", 0, 0, 0);
cout << "Number of transactions written to DB: " << transactionIDCounter - 1 << endl;
cout << "tlmPhaseRecorder:\tEnd Recording" << endl;
sqlite3_close(db);
}
void tlmDBPhaseRecorder::recordPhase(tlm::tlm_generic_payload& trans, tlm::tlm_phase phase,
sc_time time)
{
time /= PicosecondsPerNanosecond;
if (currentTransactionsInSystem.count(&trans) == 0)
introduceNewTransactionToSystem(time, trans);
unsigned int id = currentTransactionsInSystem[&trans];
string phaseName = phaseToString(phase);
string phaseBeginPrefix = "BEGIN_";
string phaseEndPrefix = "END_";
if (phaseName.find(phaseBeginPrefix) != string::npos)
insertPhaseInDB(phaseName, time, id);
else
updatePhaseEndInDB(phaseName, time, id);
bool phaseTerminatesTransaction = count(transactionTerminatingPhases.begin(),
transactionTerminatingPhases.end(), phase) == 1;
if (phaseTerminatesTransaction)
removeTransactionFromSystem(time, id, trans);
recordingEndTime = time;
}
void tlmDBPhaseRecorder::recordDebugMessage(std::string message, sc_time time)
{
time /= PicosecondsPerNanosecond;
insertDebugMessageInDB(message, time);
}
void tlmDBPhaseRecorder::createTables()
{
string initial = getFileContents(pathToConfigs + string("/createTraceDB.sql"));
executeSqlCommand(initial);
}
void tlmDBPhaseRecorder::prepareSqlStatements()
{
insertTransactionString =
"INSERT INTO Transactions VALUES (:id,:rangeID,:address,:thread,:channel,:bank,:row,:column,:command)";
insertRangeString = "INSERT INTO Ranges VALUES (:id,:begin,:end)";
updateRangeString = "UPDATE Ranges SET End = :end WHERE ID = :id";
insertPhaseString =
"INSERT INTO Phases (PhaseName,PhaseBegin,PhaseEnd,Transact) VALUES (:name,:begin,:end,:transaction)";
updatePhaseString =
"UPDATE Phases SET PhaseEnd = :end WHERE Transact = :trans AND PhaseName = :name";
insertGeneralInfoString =
"INSERT INTO GeneralInfo (NumberOfTransactions,TraceEnd,NumberOfBanks,description,clk,UnitOfTime) Values (:numberOfTransactions,:end,:numberOfBanks,:description,:clk,:unitOfTime)";
insertDebugMessageString = "INSERT INTO DebugMessages (Time,Message) Values (:time,:message)";
sqlite3_prepare(db, insertTransactionString.c_str(), -1, &insertTransactionStatement, 0);
sqlite3_prepare(db, insertRangeString.c_str(), -1, &insertRangeStatement, 0);
sqlite3_prepare(db, updateRangeString.c_str(), -1, &updateRangeStatement, 0);
sqlite3_prepare(db, insertPhaseString.c_str(), -1, &insertPhaseStatement, 0);
sqlite3_prepare(db, updatePhaseString.c_str(), -1, &updatePhaseStatement, 0);
sqlite3_prepare(db, insertGeneralInfoString.c_str(), -1, &insertGeneralInfoStatement, 0);
sqlite3_prepare(db, insertDebugMessageString.c_str(), -1, &insertDebugMessageStatement, 0);
}
void tlmDBPhaseRecorder::setUpTransactionTerminatingPhases()
{
transactionTerminatingPhases.push_back(tlm::END_RESP);
transactionTerminatingPhases.push_back(static_cast<const tlm::tlm_phase>(END_REFA));
transactionTerminatingPhases.push_back(static_cast<const tlm::tlm_phase>(END_REFB));
transactionTerminatingPhases.push_back(static_cast<const tlm::tlm_phase>(END_PDNP));
transactionTerminatingPhases.push_back(static_cast<const tlm::tlm_phase>(END_PDNA));
transactionTerminatingPhases.push_back(static_cast<const tlm::tlm_phase>(END_SREF));
}
void tlmDBPhaseRecorder::openDB(std::string name)
{
if (sqlite3_open(name.c_str(), &db))
{
cout << "ERROR Cannot open DB" << endl;
sqlite3_close(db);
}
}
void tlmDBPhaseRecorder::insertDebugMessageInDB(string message, const sc_time& time)
{
sqlite3_bind_int64(insertDebugMessageStatement, 1, time.value());
sqlite3_bind_text(insertDebugMessageStatement, 2, message.c_str(), message.length(), 0);
executeSqlStatement(insertDebugMessageStatement);
}
void tlmDBPhaseRecorder::insertGeneralInfo()
{
sqlite3_bind_int64(insertGeneralInfoStatement, 1, transactionIDCounter - 1);
sqlite3_bind_int64(insertGeneralInfoStatement, 2, recordingEndTime.value());
sqlite3_bind_int(insertGeneralInfoStatement, 3, xmlAddressDecoder::getInstance().getNumberOfBanks());
sqlite3_bind_text(insertGeneralInfoStatement, 4, "", 0, NULL);
sqlite3_bind_int(insertGeneralInfoStatement, 5, 6);
sqlite3_bind_text(insertGeneralInfoStatement, 6, "NS", 2, NULL);
executeSqlStatement(insertGeneralInfoStatement);
}
void tlmDBPhaseRecorder::insertTransactionInDB(unsigned int id, tlm::tlm_generic_payload& trans)
{
sqlite3_bind_int(insertTransactionStatement, 1, id);
sqlite3_bind_int(insertTransactionStatement, 2, id);
sqlite3_bind_int(insertTransactionStatement, 3, trans.get_address());
sqlite3_bind_text(insertTransactionStatement, 9,
trans.get_command() == tlm::TLM_READ_COMMAND ? "R" : "W", 1, 0);
const DramExtension& extension = DramExtension::getExtension(trans);
sqlite3_bind_int(insertTransactionStatement, 4, extension.getThread().ID());
sqlite3_bind_int(insertTransactionStatement, 5, extension.getChannel().ID());
sqlite3_bind_int(insertTransactionStatement, 6, extension.getBank().ID());
sqlite3_bind_int(insertTransactionStatement, 7, extension.getRow().ID());
sqlite3_bind_int(insertTransactionStatement, 8, extension.getColumn().ID());
executeSqlStatement(insertTransactionStatement);
}
void tlmDBPhaseRecorder::insertRangeInDB(unsigned int id, const sc_time& time)
{
sqlite3_bind_int(insertRangeStatement, 1, id);
sqlite3_bind_int64(insertRangeStatement, 2, time.value());
sqlite3_bind_int64(insertRangeStatement, 3, time.value());
executeSqlStatement(insertRangeStatement);
}
void tlmDBPhaseRecorder::insertPhaseInDB(string phaseName, const sc_time& time, unsigned int id)
{
string phaseBeginPrefix = "BEGIN_";
phaseName.erase(0, phaseBeginPrefix.length());
sqlite3_bind_text(insertPhaseStatement, 1, phaseName.c_str(), phaseName.length(), 0);
sqlite3_bind_int64(insertPhaseStatement, 2, time.value());
sqlite3_bind_int64(insertPhaseStatement, 3, time.value());
sqlite3_bind_int(insertPhaseStatement, 4, id);
executeSqlStatement(insertPhaseStatement);
}
void tlmDBPhaseRecorder::updatePhaseEndInDB(string phaseName, const sc_time& time, unsigned int id)
{
string phaseEndPrefix = "END_";
phaseName.erase(0, phaseEndPrefix.length());
sqlite3_bind_int64(updatePhaseStatement, 1, time.value());
sqlite3_bind_int(updatePhaseStatement, 2, id);
sqlite3_bind_text(updatePhaseStatement, 3, phaseName.c_str(), phaseName.length(), 0);
executeSqlStatement(updatePhaseStatement);
}
void tlmDBPhaseRecorder::introduceNewTransactionToSystem(const sc_time& time,
tlm::tlm_generic_payload& trans)
{
unsigned int id = transactionIDCounter++;
currentTransactionsInSystem[&trans] = id;
insertTransactionInDB(id, trans);
insertRangeInDB(id, time);
if (id % transactionCommitRate == 0)
{
sqlite3_exec(db, "COMMIT", 0, 0, 0);
cout << "Committing trasaction nr. " << id << " (and previous) to database" << endl;
sqlite3_exec(db, "BEGIN", 0, 0, 0);
}
}
void tlmDBPhaseRecorder::removeTransactionFromSystem(const sc_time& time, unsigned int id,
tlm::tlm_generic_payload& trans)
{
currentTransactionsInSystem.erase(&trans);
sqlite3_bind_int64(updateRangeStatement, 1, time.value());
sqlite3_bind_int(updateRangeStatement, 2, id);
executeSqlStatement(updateRangeStatement);
}
void tlmDBPhaseRecorder::executeSqlStatement(sqlite3_stmt* statement)
{
if (sqlite3_step(statement) != SQLITE_DONE)
{
cout << "Could not execute statement" << endl;
}
sqlite3_reset(statement);
}
void tlmDBPhaseRecorder::executeSqlCommand(string command)
{
cout << "executing sql-script" << endl;
char * errMsg = 0;
int rc = sqlite3_exec(db, command.c_str(), NULL, 0, &errMsg);
if (rc != SQLITE_OK)
{
cout << errMsg << endl;
SC_REPORT_FATAL("SQLITE Error", errMsg);
sqlite3_free(errMsg);
}
cout << "done executing script" << endl;
}
string tlmDBPhaseRecorder::getFileContents(string filename)
{
ifstream in(filename.c_str(), ios::in | ios::binary);
if (in)
{
string contents;
in.seekg(0, ios::end);
contents.resize(in.tellg());
in.seekg(0, ios::beg);
in.read(&contents[0], contents.size());
in.close();
return (contents);
}
throw(errno);
}
string tlmDBPhaseRecorder::phaseToString(tlm::tlm_phase phase)
{
ostringstream oss;
oss << phase;
string str = oss.str();
return str;
}

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#ifndef TLMPHASERECORDER_H
#define TLMPHASERECORDER_H
#include <iostream>
#include <ostream>
#include <string>
#include <map>
#include <algorithm>
#include <sqlite3.h>
#include <fstream>
#include <cerrno>
#include <tlm.h>
#include <systemc.h>
#include "xmlAddressdecoder.h"
using namespace std;
class tlmDBPhaseRecorder
{
public:
tlmDBPhaseRecorder(std::string name, std::string pathToConfigs);
~tlmDBPhaseRecorder();
void recordPhase(tlm::tlm_generic_payload &trans, tlm::tlm_phase phase, sc_time time);
void recordDebugMessage(std::string message, sc_time time);
private:
std::string phaseToString(tlm::tlm_phase phase);
std::string getFileContents(std::string filename);
void executeSqlCommand(std::string command);
void executeSqlStatement(sqlite3_stmt* statement);
void prepareSqlStatements();
void openDB(std::string name);
void setUpTransactionTerminatingPhases();
void introduceNewTransactionToSystem(const sc_time& time, tlm::tlm_generic_payload& trans);
void removeTransactionFromSystem(const sc_time& time, unsigned int transactionID, tlm::tlm_generic_payload& trans);
void createTables();
void insertGeneralInfo();
void insertTransactionInDB(unsigned int transactionID, tlm::tlm_generic_payload& trans);
void insertRangeInDB(unsigned int transactionID, const sc_time& time);
void insertPhaseInDB(string phaseName, const sc_time& time, unsigned int transactionID);
void updatePhaseEndInDB(string phaseName, const sc_time& time, unsigned int transactionID);
void insertDebugMessageInDB(string message, const sc_time& time);
static const int transactionCommitRate = 10000;
map<tlm::tlm_generic_payload*, unsigned int> currentTransactionsInSystem;
unsigned int transactionIDCounter;
sc_time recordingEndTime;
std::vector<tlm::tlm_phase> transactionTerminatingPhases;
sqlite3 *db;
sqlite3_stmt *insertTransactionStatement, *insertRangeStatement, *updateRangeStatement,
*insertPhaseStatement, *updatePhaseStatement, *insertGeneralInfoStatement, *insertDebugMessageStatement;
std::string insertTransactionString, insertRangeString, updateRangeString, insertPhaseString, updatePhaseString, insertGeneralInfoString,
insertDebugMessageString;
double PicosecondsPerNanosecond;
std::string pathToConfigs;
};
#endif

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#include "xmlAddressdecoder.h"
#include <systemc.h>
using namespace std;
string xmlAddressDecoder::URI = "";
xmlAddressDecoder::xmlAddressDecoder(string URI)
{
doc = new TiXmlDocument(URI.c_str());
if (doc->LoadFile())
{
dramconfig = doc->FirstChildElement("dramconfig");
addressmap = dramconfig->FirstChildElement("addressmap");
unsigned int from;
unsigned int to;
// get channel:
TiXmlElement* channel = addressmap->FirstChildElement("channel");
from = getAttribute<unsigned int>(channel, "from");
to = getAttribute<unsigned int>(channel, "to");
channelShift = from;
channelMask = pow(2.0, to + 1.0) - pow(2.0, from + 0.0);
channelSize = pow(2.0, to - from + 1.0);
// get row:
TiXmlElement* row = addressmap->FirstChildElement("row");
from = getAttribute<unsigned int>(row, "from");
to = getAttribute<unsigned int>(row, "to");
rowShift = from;
rowMask = pow(2.0, to + 1.0) - pow(2.0, from + 0.0);
rowSize = pow(2.0, to - from + 1.0);
// get bank:
TiXmlElement* bank = addressmap->FirstChildElement("bank");
from = getAttribute<unsigned int>(bank, "from");
to = getAttribute<unsigned int>(bank, "to");
bankShift = from;
bankMask = pow(2.0, to + 1.0) - pow(2.0, from + 0.0);
bankSize = pow(2.0, to - from + 1.0);
// get colum:
TiXmlElement* colum = addressmap->FirstChildElement("colum");
from = getAttribute<unsigned int>(colum, "from");
to = getAttribute<unsigned int>(colum, "to");
columShift = from;
columMask = pow(2.0, to + 1.0) - pow(2.0, from + 0.0);
columSize = pow(2.0, to - from + 1.0);
// get bytes:
TiXmlElement* bytes = addressmap->FirstChildElement("bytes");
from = getAttribute<unsigned int>(bytes, "from");
to = getAttribute<unsigned int>(bytes, "to");
bytesShift = from;
bytesMask = pow(2.0, to + 1.0) - pow(2.0, from + 0.0);
bytesSize = pow(2.0, to - from + 1.0);
}
else
{
SC_REPORT_ERROR("xmlAddressDecoder can not find ", URI.c_str());
}
}
xmlAddressDecoder& xmlAddressDecoder::getInstance()
{
static xmlAddressDecoder decoder(xmlAddressDecoder::URI);
return decoder;
}
xmlAddressDecoder::~xmlAddressDecoder()
{
delete doc;
}
void xmlAddressDecoder::getNode(unsigned int addr, node * n)
{
n->channel = (addr & channelMask) >> channelShift;
n->row = (addr & rowMask) >> rowShift;
n->bank = (addr & bankMask) >> bankShift;
n->colum = (addr & columMask) >> columShift;
}
void xmlAddressDecoder::getBRC(unsigned int addr, unsigned int &bank, unsigned int &row,
unsigned int &colum)
{
row = (addr & rowMask) >> rowShift;
bank = (addr & bankMask) >> bankShift;
colum = (addr & columMask) >> columShift;
}
void xmlAddressDecoder::getCBRC(unsigned int addr, unsigned int &channel, unsigned int &bank,
unsigned int &row, unsigned int &colum)
{
channel = (addr & channelMask) >> channelShift;
getBRC(addr, bank, row, colum);
}
void xmlAddressDecoder::getC(unsigned int addr, unsigned int &channel)
{
channel = (addr & channelMask) >> channelShift;
}
unsigned int xmlAddressDecoder::getNumberOfBanks()
{
return bankSize;
}
unsigned int xmlAddressDecoder::getNumberOfRowsPerBank()
{
return rowSize;
}
unsigned int xmlAddressDecoder::getNumberOfColumsPerRow()
{
return columSize;
}
unsigned int xmlAddressDecoder::getNumberOfBytesPerColumn()
{
return bytesSize;
}

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#ifndef _XMLADDRESSDECODER_H
#define _XMLADDRESSDECODER_H
// Copyright (C) 2011 University of Kaiserslautern
// Microelectronic System Design Research Group
//
// de.uni-kl.eit.ems.vp
//
// Matthias Jung <jungma@eit.uni-kl.de> 2012
//
/// \file
/// \brief XML address decoder
/// \author Matthias Jung <jungma@eit.uni-kl.de>
/// \date 02.07.2012
//
#include <tlm.h>
#include <iostream>
#include <sstream>
#include <string>
#include <math.h>
#include "third_party/tinyxml.h"
struct node
{
unsigned int channel;
unsigned int row;
unsigned int bank;
unsigned int colum;
tlm::tlm_command command;
tlm::tlm_phase phase;
};
class xmlAddressDecoder
{
public:
static std::string URI;
static xmlAddressDecoder& getInstance();
void getNode(unsigned int addr, node * n);
void getBRC(unsigned int addr, unsigned int &bank, unsigned int &row, unsigned int &colum);
void getCBRC(unsigned int addr, unsigned int &channel, unsigned int &bank, unsigned int &row, unsigned int &colum);
void getC(unsigned int addr, unsigned int &channel);
unsigned int getNumberOfBanks();
unsigned int getNumberOfRowsPerBank();
unsigned int getNumberOfColumsPerRow();
unsigned int getNumberOfBytesPerColumn();
private:
xmlAddressDecoder(std::string URI);
~xmlAddressDecoder();
unsigned int channelMask;
unsigned int rowMask;
unsigned int bankMask;
unsigned int columMask;
unsigned int bytesMask;
unsigned int channelShift;
unsigned int rowShift;
unsigned int bankShift;
unsigned int columShift;
unsigned int bytesShift;
unsigned int channelSize;
unsigned int bankSize;
unsigned int rowSize;
unsigned int columSize;
unsigned int bytesSize;
TiXmlDocument * doc;
TiXmlElement * dramconfig;
TiXmlElement * addressmap;
template <class T>
T getAttribute(TiXmlElement * element, const std::string s)
{
T d;
element->QueryValueAttribute<T>(s, &d);
return d;
}
};
#endif

99
dram/src/common/xmlConfig.h Executable file
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#ifndef CONFIH_H
#define CONFIH_H
#include <systemc.h>
#include <tlm.h>
#include "third_party/tinyxml.h"
using namespace std;
class xmlConfig
{
public:
sc_time clk;
sc_time tRRD;
sc_time tRC;
sc_time tRCD;
sc_time tBL;
sc_time tRL;
sc_time tWL;
sc_time tWTR;
sc_time tRP;
sc_time tRAS;
sc_time tWR;
sc_time tREF;
sc_time tRFC;
sc_time tXP;
sc_time tCKE;
sc_time tXSR;
sc_time tCKESR;
sc_time tREFA;
sc_time tREFB;
sc_time tPDNTO;
double IDD0;
double IDD2N;
double IDD3N;
double IDD4R;
double IDD4W;
double IDD5;
double IDD6;
double IDD5B1;
double IDD2P;
double IDD3P;
double VDD;
sc_time ccPreprocessingTime;
public:
xmlConfig()
{
//clk = sc_time(6.0, SC_NS); // 166MHz
clk = sc_time(6.0, SC_NS); // 166MHz
// Timings:
// WC timings for 200MHz
// before thermal:
tRRD = 2 * clk; // 2 * clk; // 4 * clk;//1 * clk; //2 * clk;
tRCD = 3 * clk; // 2 * clk; // 10 * clk;//3 * clk; //4 * clk;
tRL = 3 * clk; // 3 * clk; // 10 * clk;//3 * clk; //3 * clk;
tBL = 1 * clk; // 1 * clk; // 1 * clk;//1 * clk; //1 * clk;
tWL = 1 * clk; // 1 * clk; // 9 * clk;//1 * clk; //1 * clk;
tWTR = 3 * clk; // 3 * clk; // 4 * clk;//3 * clk; //3 * clk;
tRP = 3 * clk; // 3 * clk; // 10 * clk;//3 * clk; //4 * clk; // sadri changed from 2 to 3 = 18ns/6ns
tRAS = 6 * clk; // 5 * clk; // 18 * clk;//8 * clk; //9 * clk;
tWR = 2 * clk; // 2 * clk; // 10 * clk;//2 * clk; //3 * clk;
tRFC = 18 * clk; // 22 * clk; // 15 * clk; // 110* clk;//18 * clk; // sadri changed from 15 to 22 = 130ns/6ns
tXP = 2 * clk;
tCKE = 3 * clk;
tXSR = tRFC + 2 * clk;
tCKESR = 3 * clk;
tPDNTO = 0 * clk;
tRC = tRP + tRAS;
tREF = sc_time(64, SC_MS);
tREFA = tRP + tRFC;
tREFB = tRP + tRC; // refresh for one bank
// Power realted currents and voltages:
// 166MHz thermal non minimal timings (200MHz)
// 166MHz with minimal timing
IDD0 = 37.85 / 1000.0; // 47.3 / 1000.0; //64 / 1000.0;
IDD2N = 4.36 / 1000.0; // 4.36 / 1000.0; //4.4 / 1000.0;
IDD3N = 5.60 / 1000.0; // 6.07 / 1000.0; //5.9 / 1000.0;
IDD4R = 94.64 / 1000.0; // 94.65 / 1000.0; //94 / 1000.0;
IDD4W = 88.65 / 1000.0; // 88.66 / 1000.0; //88 / 1000.0;
IDD5 = 136.20 / 1000.0; // 162.56 / 1000.0; //163 / 1000.0;
IDD5B1 = 37.32 / 1000.0; //
IDD2P = 2.4 / 1000.0; //
IDD3P = 3.6 / 1000.0; //
IDD6 = 3.4 / 1000.0; //
VDD = 1.2;
ccPreprocessingTime = 1 * clk;
}
};
#endif

View File

@@ -8,7 +8,7 @@
#ifndef BANKSTATES_H_
#define BANKSTATES_H_
#include <vector>
#include "common/dramExtension.h"
#include "../common/dramExtension.h"
namespace core
{

View File

@@ -12,32 +12,12 @@ namespace core {
void CommandBus::schedule(ScheduledCommand& command)
{
std::cout<<command.getCommand()<<" Before cmd bus"<<command.getStart()<<std::endl;
scheduleOnBus(command);
//TODO state change in state!!
changeControllerState(command);
state.pendingBusCommands.insert(command.getStart());
//TODO do in refresh manager
if(command.getCommand() == Refresh)
{
for(unsigned int i = 0; i < config.numberOfBanks; ++i)
{
state.lastCommandsOnBus[command.getCommand()][Bank(i)] = command;
}
}
else
{
state.lastCommandsOnBus[command.getCommand()][command.getBank()] = command;
//state.lastCommandsOnBus[command.getCommand()][command.getBank()].invalidateTransaction();
}
state.change(command);
std::cout<<command.getCommand()<<" After cmd bus"<<command.getStart()<<std::endl;
if(command.getCommand() == Activate)
{
state.nActivateWindow.put(command.getStart());
}
}
@@ -45,6 +25,8 @@ void CommandBus::scheduleOnBus(ScheduledCommand& command)
{
//TODO write nicer -- make own bus checker
sc_time newStart = command.getStart();
//if(!isClkAligned(newStart, config.Timings.clk))
//std::cout<<command.getCommand()<<std::endl;
sc_assert(isClkAligned(newStart, config.Timings.clk));
std::set<sc_time>::iterator it = state.pendingBusCommands.begin();
@@ -81,55 +63,8 @@ void CommandBus::cleanUpBus(sc_time currentTime)
state.pendingBusCommands.lower_bound(currentTime));
}
void CommandBus::changeControllerState(const ScheduledCommand& command)
{
switch (command.getCommand())
{
case Refresh:
refresh(command);
break;
case Activate:
activate(command);
break;
case Precharge:
precharge(command);
default:
break;
}
}
void CommandBus::refresh(const ScheduledCommand& command)
{
if (config.RefreshBankwise)
{
state.bankStates.closeRowBuffer(command.getBank());
}
else
{
state.bankStates.closeAllRowBuffers();
}
}
void CommandBus::precharge(const ScheduledCommand& command)
{
if (command.getCommand() == Precharge)
{
state.bankStates.closeRowBuffer(command.getBank());
}
else if (command.getCommand() == PrechargeAll)
{
state.bankStates.closeAllRowBuffers();
}
}
void CommandBus::activate(const ScheduledCommand& command)
{
if (command.getCommand() == Activate)
{
state.bankStates.openRowInRowBuffer(command.getBank(), command.getRow());
}
}
} /* namespace controller */

View File

@@ -16,7 +16,7 @@ namespace core {
DramController::DramController(IWrapperConnector& wrapperConnector):
config(),state(config.numberOfBanks, config.nActivate), savedState(config.numberOfBanks, config.nActivate), commandSequenceGenerator(state), commandChecker(), commandSequenceScheduler(
bus, commandChecker), bus(wrapperConnector, config, state), refreshManager(bus, config.Timings.refreshTimings[0])
bus, commandChecker), bus(wrapperConnector, config, state), refreshManager(bus, config.Timings.refreshTimings)
{
commandChecker[Activate] = new ActivateChecker(config, state);

View File

@@ -14,7 +14,7 @@
#include "CommandBus.h"
#include "Configuration.h"
#include "powerdown/PowerDownManager.h"
#include "refresh/RefreshManager.h"
#include "refresh/BankwiseRefreshManager.h"
#include "scheduling/CommandSequenceGenerator.h"
#include "scheduling/checker/ICommandChecker.h"
#include "scheduling/CommandSequenceScheduler.h"
@@ -47,7 +47,7 @@ private:
std::map<Command, ICommandChecker*> commandChecker;
CommandSequenceScheduler commandSequenceScheduler;
CommandBus bus;
RefreshManager refreshManager;
BankwiseRefreshManager refreshManager;
//std::vector<ICommandChecker*> allCommandChecker;
//PowerDownManager powerDownManager;

View File

@@ -40,4 +40,40 @@ const ScheduledCommand ControllerState::getLastCommand(Bank bank)
return lastCommand;
}
void ControllerState::change(const ScheduledCommand& scheduledCommand)
{
pendingBusCommands.insert(scheduledCommand.getStart());
lastCommandsOnBus[scheduledCommand.getCommand()][scheduledCommand.getBank()] = scheduledCommand;
lastCommandsOnBus[scheduledCommand.getCommand()][scheduledCommand.getBank()].invalidateTransaction();
//TODO do in refresh manager
/*if(scheduledCommand.getCommand() == Refresh)
{
for(unsigned int i = 0; i < bankStates.getNumberOfBanks(); ++i)
{
lastCommandsOnBus[scheduledCommand.getCommand()][Bank(i)] = scheduledCommand;
}
}*/
switch (scheduledCommand.getCommand())
{
case Refresh:
bankStates.closeRowBuffer(scheduledCommand.getBank());
break;
case Activate:
bankStates.openRowInRowBuffer(scheduledCommand.getBank(), scheduledCommand.getRow());
nActivateWindow.put(scheduledCommand.getStart());
break;
case Precharge:
bankStates.closeRowBuffer(scheduledCommand.getBank());
break;
default:
break;
}
}
} /* namespace controller */

View File

@@ -27,6 +27,8 @@ public:
const ScheduledCommand getLastCommand(Command command);
const ScheduledCommand getLastCommand(Bank bank);
void change(const ScheduledCommand& scheduledCommand);
BankStates bankStates;
//used by the various checkers

View File

@@ -9,7 +9,7 @@
#define BANKWISEREFRESHMANAGER_H_
#include "IRefreshManager.h"
#include "common/dramExtension.h"
#include "../../common/dramExtension.h"
#include "RefreshManager.h"
namespace core {

View File

@@ -21,7 +21,14 @@ class IRefreshManager
public:
virtual ~IRefreshManager() {}
/*
*Checks whether a schedule collides with the next planned refresh
*/
virtual bool hasCollision(const CommandSchedule& schedule) = 0;
/*
*Schedules the next planned refresh if it's start time is not in the past
*/
virtual void scheduleRefresh(sc_time time) = 0;
};

View File

@@ -12,18 +12,14 @@
namespace core {
RefreshManager::RefreshManager(CommandBus& bus, const RefreshTiming& refreshTiming) : bus(bus),
refreshTiming(refreshTiming)
RefreshManager::RefreshManager(CommandBus& bus, const RefreshTiming& refreshTiming
) : bus(bus), refreshTiming(refreshTiming)
{
setupTransaction(refreshTransaction, Bank(0));
nextPlannedRefresh = new ScheduledCommand(refreshTransaction, Refresh, SC_ZERO_TIME,
refreshTiming.tRFC);
sc_assert(refreshTiming.tRFC > SC_ZERO_TIME);
sc_assert(nextPlannedRefresh->getExecutionTime()>SC_ZERO_TIME);
planNextRefresh(*nextPlannedRefresh);
}
RefreshManager::RefreshManager(CommandBus& bus, const RefreshTiming& refreshTiming,
Bank bank) : bus(bus), refreshTiming(refreshTiming)
{
@@ -58,7 +54,7 @@ bool RefreshManager::hasCollision(const CommandSchedule& schedule)
void RefreshManager::scheduleRefresh(sc_time time)
{
if (time <= nextPlannedRefresh->getStart())
if (time == nextPlannedRefresh->getStart())
scheduleRefresh(*nextPlannedRefresh);
}

View File

@@ -9,7 +9,7 @@
#define REFRESHMANAGER_H_
#include "IRefreshManager.h"
#include "common/dramExtension.h"
#include "../../common/dramExtension.h"
namespace core {

View File

@@ -9,7 +9,7 @@
#define COMMANDSCHEDULE_H_
#include <vector>
#include "common/dramExtension.h"
#include "../../common/dramExtension.h"
#include "ScheduledCommand.h"
namespace core {

View File

@@ -6,7 +6,7 @@
*/
#include "CommandSequenceGenerator.h"
#include "common/dramExtension.h"
#include "../../common/dramExtension.h"
using namespace std;

View File

@@ -11,7 +11,7 @@
#include <systemc.h>
#include <tlm.h>
#include "../Command.h"
#include "common/dramExtension.h"
#include "../../common/dramExtension.h"
namespace core {

View File

@@ -21,7 +21,7 @@ void ActivateChecker::delayToSatisfyConstraints(ScheduledCommand& command) const
if(lastCommandOnBank.isValidCommand())
//implies precharge to activate (tRP) and refresh to activate (tFRC)
sc_assert(command.getStart() >= state.getLastCommand(command.getBank()));
sc_assert(command.getStart() >= state.getLastCommand(command.getBank()).getStart());
satisfy_activateToActivate_sameBank(command);
satisfy_activateToActivate_differentBank(command);

View File

@@ -11,10 +11,10 @@ namespace core {
void PrechargeChecker::delayToSatisfyConstraints(ScheduledCommand& command) const
{
sc_assert(command.getCommand() == Precharge || command == PrechargeAll);
sc_assert(command.getCommand() == Precharge || command.getCommand() == PrechargeAll);
ScheduledCommand lastCommandOnBank = state.getLastCommand(command.getBank());
if(lastCommandOnBank.isValidCommand())
sc_assert(command.getStart() >= state.getLastCommand(command.getBank()));
sc_assert(command.getStart() >= state.getLastCommand(command.getBank()).getStart());
}
sc_time PrechargeChecker::getExecutionTime(const tlm::tlm_generic_payload& payload,

View File

@@ -10,7 +10,7 @@
#include <systemc.h>
#include <tlm.h>
#include "common/dramExtension.h"
#include "../../common/dramExtension.h"
unsigned int getStartAddress(Bank bank);
unsigned int getBurstLengthInBytes(const tlm::tlm_generic_payload& payload, unsigned int buswidth);

View File

@@ -1,6 +1,6 @@
//#include "Fr_Fcfs.h"
//#include "assert.h"
//#include "common/dramExtension.h"
//#include "../common/dramExtension.h"
//
//using namespace tlm;
//using namespace std;

View File

@@ -1,7 +1,7 @@
#ifndef SCHEDULER_H
#define SCHEDULER_H
#include <tlm.h>
#include "common/dramExtension.h"
#include "../common/dramExtension.h"
namespace scheduler {

View File

@@ -0,0 +1,50 @@
/*
* MemoryManager.cpp
*
* Created on: Mar 16, 2014
* Author: robert
*/
#include "MemoryManager.h"
#include <iostream>
using namespace std;
MemoryManager::MemoryManager(): numberOfAllocations(0), numberOfFrees(0)
{
}
MemoryManager::~MemoryManager()
{
for(gp* payload: freePayloads)
{
delete payload;
numberOfFrees++;
}
cout << "Memory Manager: Number of allocated payloads: " << numberOfAllocations << std::endl;
cout << "Memory Manager: Number of freed payloads: " << numberOfFrees << std::endl;
}
gp* MemoryManager::allocate()
{
//if(freePayloads.empty())
//{
//numberOfAllocations++;
return new gp(this);
//}
//else
//{
// gp* result = freePayloads.back();
// freePayloads.pop_back();
// return result;
// }
}
void MemoryManager::free(gp* payload)
{
payload->reset(); //clears all extensions
freePayloads.push_back(payload);
}

View File

@@ -0,0 +1,29 @@
/*
* MemoryManager.h
*
* Created on: Mar 16, 2014
* Author: robert
*/
#ifndef MEMORYMANAGER_H_
#define MEMORYMANAGER_H_
#include <tlm.h>
#include <vector>
typedef tlm::tlm_generic_payload gp;
class MemoryManager : public tlm::tlm_mm_interface
{
public:
MemoryManager();
virtual ~MemoryManager();
virtual gp* allocate();
virtual void free(gp* payload);
private:
unsigned int numberOfAllocations;
unsigned int numberOfFrees;
std::vector<gp*> freePayloads;
};
#endif /* MEMORYMANAGER_H_ */

View File

@@ -0,0 +1,145 @@
/*
* arbiter.h
*
* Created on: Mar 16, 2014
* Author: robert
*/
#ifndef ARBITER_H_
#define ARBITER_H_
#include <deque>
#include <tlm.h>
#include <systemc.h>
#include <tlm_utils/simple_target_socket.h>
#include <tlm_utils/simple_initiator_socket.h>
#include <tlm_utils/peq_with_cb_and_phase.h>
#include "../common/xmlAddressdecoder.h"
#include "../common/dramExtension.h"
#include <iostream>
using namespace std;
using namespace tlm;
template<unsigned int NUMBER_OF_THREADS = 1, unsigned int BUSWIDTH = 128>
struct Arbiter: public sc_module
{
public:
tlm_utils::simple_initiator_socket<Arbiter,BUSWIDTH, tlm::tlm_base_protocol_types> iSocket;
tlm_utils::simple_target_socket_tagged<Arbiter, BUSWIDTH, tlm::tlm_base_protocol_types> tSockets[NUMBER_OF_THREADS];
SC_CTOR(Arbiter) :
payloadEventQueue(this, &Arbiter::peqCallback), channelIsFree(true)
{
iSocket.register_nb_transport_bw(this, &Arbiter::nb_transport_bw);
for (unsigned int i = 0; i < NUMBER_OF_THREADS; ++i)
{
tSockets[i].register_nb_transport_fw(this, &Arbiter::nb_transport_fw, i);
}
}
private:
tlm_utils::peq_with_cb_and_phase<Arbiter> payloadEventQueue;
bool channelIsFree;
deque<tlm_generic_payload* > backpressure;
// Initiated by schedulerWrapper
tlm_sync_enum nb_transport_bw(tlm_generic_payload& payload, tlm_phase& phase, sc_time& bwDelay)
{
payloadEventQueue.notify(payload, phase, bwDelay);
return TLM_ACCEPTED;
}
// Initiated by .stl players
tlm_sync_enum nb_transport_fw(int socketId, tlm_generic_payload& payload, tlm_phase& phase,
sc_time& fwDelay)
{
if(phase == BEGIN_REQ)
{
appendDramExtension(socketId, payload);
payload.acquire();
}
else if(phase == END_RESP)
payload.release();
payloadEventQueue.notify(payload, phase, fwDelay);
return TLM_ACCEPTED;
}
void peqCallback(tlm_generic_payload& payload, const tlm_phase& phase)
{
//Phases initiated by .stl players
if (phase == BEGIN_REQ)
{
if(channelIsFree)
{
channelIsFree = false;
sendToChannel(payload, phase, SC_ZERO_TIME );
}
else
{
backpressure.push_back(&payload);
}
}
else if (phase == END_RESP)
{
sendToChannel(payload, phase, SC_ZERO_TIME );
}
//Phases initiated by dram backend
else if (phase == END_REQ)
{
channelIsFree = true;
sendToTraceplayer(DramExtension::getExtension(payload).getThread().ID(), payload, phase, SC_ZERO_TIME);
if(!backpressure.empty())
{
tlm_generic_payload* payloadToSend = backpressure.front();
backpressure.pop_front();
sendToChannel(*payloadToSend, BEGIN_REQ, SC_ZERO_TIME );
channelIsFree = false;
}
}
else if (phase == BEGIN_RESP)
{
sendToTraceplayer(DramExtension::getExtension(payload).getThread().ID(), payload, phase, SC_ZERO_TIME);
}
else
{
SC_REPORT_FATAL(0, "Payload event queue in arbiter was triggered with unknown phase");
}
}
void sendToChannel(tlm_generic_payload& payload, const tlm_phase& phase, const sc_time& delay)
{
tlm_phase TPhase = phase;
sc_time TDelay = delay;
iSocket->nb_transport_fw(payload, TPhase, TDelay);
}
void sendToTraceplayer(unsigned int id, tlm_generic_payload& payload, const tlm_phase& phase, const sc_time& delay)
{
tlm_phase TPhase = phase;
sc_time TDelay = delay;
tSockets[id]->nb_transport_bw(payload, TPhase, TDelay);
}
void appendDramExtension(int socketId, tlm_generic_payload& payload)
{
node n;
xmlAddressDecoder::getInstance().getNode(static_cast<unsigned int>(payload.get_address()), &n);
DramExtension* extension = new DramExtension(Thread(socketId), Channel(n.channel), Bank(n.bank), Row(n.row), Column(n.colum));
payload.set_auto_extension(extension);
}
};
#endif /* ARBITER_H_ */

View File

@@ -16,8 +16,8 @@
#include <iostream>
#include <map>
#include "common/protocol.h"
#include "common/tlmDBPhaseRecorder.h"
#include "../common/protocol.h"
#include "../common/tlmDBPhaseRecorder.h"
#include "../core/IWrapperConnector.h"
#include "../core/Controller.h"
#include "../scheduler/Scheduler.h"

219
dram/src/simulation/dram.h Normal file
View File

@@ -0,0 +1,219 @@
/*
* dram.h
*
* Created on: Mar 16, 2014
* Author: robert
*/
#ifndef DRAM_H_
#define DRAM_H_
#include <iomanip>
#include <fstream>
#include <tlm.h>
#include <systemc.h>
#include <tlm_utils/peq_with_cb_and_phase.h>
#include <tlm_utils/simple_initiator_socket.h>
#include <tlm_utils/simple_target_socket.h>
#include "../common/protocol.h"
#include "../common/xmlConfig.h"
using namespace sc_core;
using namespace sc_dt;
using namespace std;
using namespace tlm;
xmlConfig xc;
template <unsigned int BUSWIDTH = 128, unsigned int WORDS = 4096, bool STORE = true, bool FIXED_BL = false, unsigned int FIXED_BL_VALUE = 0>
struct Dram: sc_module
{
tlm_utils::simple_target_socket<Dram, BUSWIDTH, tlm::tlm_base_protocol_types> tSocket;
sc_event target_done_event;
tlm_utils::peq_with_cb_and_phase<Dram> m_peq;
SC_CTOR(Dram) : tSocket("socket") ,m_peq(this, &Dram::peq_cb)
{
tSocket.register_nb_transport_fw(this, &Dram::nb_transport_fw);
}
~Dram()
{
}
// TLM-2 non-blocking transport method
virtual tlm::tlm_sync_enum nb_transport_fw( tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_time& delay )
{
// Queue the transaction until the annotated time has elapsed
m_peq.notify( trans, phase, delay);
return tlm::TLM_ACCEPTED;
}
void peq_cb(tlm::tlm_generic_payload& trans, const tlm::tlm_phase& phase)
{
if(phase == BEGIN_PRE || phase == AUTO_PRECHARGE)
{
if(phase == BEGIN_PRE)
{
send_end_pre(trans);
}
}
else if(phase == BEGIN_ACT)
{
send_end_act(trans);
}
else if(phase == BEGIN_WR)
{
send_end_wr(trans,true);
}
else if(phase == BEGIN_RD)
{
send_end_rd(trans,true);
}
else if(phase == BEGIN_WRA)
{
send_end_wr(trans,false);
}
else if(phase == BEGIN_RDA)
{
send_end_rd(trans,false);
}
else if(phase == BEGIN_REFA)
{
send_end_refa(trans);
}
else if(phase == BEGIN_REFB)
{
send_end_refb(trans);
}
else if(phase == BEGIN_PDNP)
{
}
else if(phase == END_PDNP)
{
}
else if(phase == BEGIN_PDNA)
{
}
else if(phase == END_PDNA)
{
}
else if(phase == BEGIN_SREF)
{
}
else if(phase == END_SREF)
{
}
else // case tlm::BEGIN_REQ,END_REQ...
{
SC_REPORT_FATAL("TLM-2", "Illegal transaction phase received by target (2)");
}
}
void send_end_refa(tlm::tlm_generic_payload& trans)
{
tlm::tlm_phase bw_phase;
sc_time delay;
bw_phase = END_REFA;
delay = xc.tREFA;
tSocket->nb_transport_bw( trans, bw_phase, delay );
}
void send_end_refb(tlm::tlm_generic_payload& trans)
{
tlm::tlm_phase bw_phase;
sc_time delay;
bw_phase = END_REFB;
delay = xc.tREFB;
tSocket->nb_transport_bw( trans, bw_phase, delay );
}
void send_end_rd(tlm::tlm_generic_payload& trans, bool open_page_policy_f)
{
tlm::tlm_phase bw_phase;
sc_time delay = SC_ZERO_TIME;
unsigned int BL = 2;
if(open_page_policy_f == true)
{
bw_phase = END_RD;
delay = xc.tRL + xc.clk * BL;
}
else
{
bw_phase = END_RDA;
delay = xc.tRL + xc.clk * BL;
}
tSocket->nb_transport_bw( trans, bw_phase, delay );
}
void send_end_wr(tlm::tlm_generic_payload& trans, bool open_page_policy_f)
{
tlm::tlm_phase bw_phase;
sc_time delay = SC_ZERO_TIME;
unsigned int BL = 2;
if(open_page_policy_f == true)
{
bw_phase = END_WR;
delay = xc.tWL + xc.clk * (BL -1);
}
else
{
bw_phase = END_WRA;
delay = xc.tWL + xc.clk * (BL -1) + xc.tWR;
}
// Send end of WR
tSocket->nb_transport_bw( trans, bw_phase, delay );
}
void send_end_pre(tlm::tlm_generic_payload& trans)
{
tlm::tlm_phase bw_phase;
sc_time delay;
bw_phase = END_PRE;
delay = xc.tRP;
tSocket->nb_transport_bw( trans, bw_phase, delay );
}
void send_end_act(tlm::tlm_generic_payload& trans)
{
tlm::tlm_phase bw_phase;
sc_time delay;
bw_phase = END_ACT;
delay = xc.tRCD;
tSocket->nb_transport_bw( trans, bw_phase, delay );
}
};
#endif /* DRAM_H_ */

View File

@@ -0,0 +1,77 @@
/*
* main.cpp
*
* Created on: Mar 16, 2014
* Author: robert
*/
#include <iostream>
#include <systemc.h>
#include <fstream>
#include <algorithm>
#include <string>
#include "../common/tlmDBPhaseRecorder.h"
#include "../common/DebugManager.h"
#include "../common/xmlAddressdecoder.h"
#include "controllerwrapper.h"
#include "dram.h"
#include "arbiter.h"
#include "traceplayer.h"
#include <string>
#include <ctime>
using namespace std;
int sc_main(int argc, char **argv) {
DebugManager::getInstance().printDebug(Importance::Warning, DebugManager::Sender::Core, SC_ZERO_TIME, "hhh");
string executableName(argv[0]);
string pathOfExecutable = executableName.substr(0,executableName.find_last_of('/'));
//string pathToStaticFolder = pathOfExecutable + string("../static");
string pathToStaticFolder = string("/home/jonny/git/dram/dram/static");
xmlAddressDecoder::URI = pathToStaticFolder + string("/addressConfig.xml");
tlmDBPhaseRecorder *recorder = new tlmDBPhaseRecorder("tpr.tdb", pathToStaticFolder);
//TracePlayer<> player("player","/home/robert/traces/trace.stl");
//TracePlayer<> player("player",string("/home/robert/common/common/static/test2.stl"));
//TracePlayer<> player("player",string("/home/jonny/traces/mediabench-h263encode_32.stl"));
TracePlayer<> player("player",string("/home/jonny/traces/mediabench-h263decode_32.stl"));
cout << "Toplevel: build player" << std::endl;
Dram<> dram("dram");
cout << "Toplevel: build dram" << std::endl;
Arbiter<> arbiter("arbiter");
cout << "Toplevel: build arbiter" << std::endl;
ControllerWrapper<> controller("controller",*recorder);
cout << "Toplevel: build controller" << std::endl;
cout << "Toplevel: binding sockets" << std::endl;
player.iSocket.bind(arbiter.tSockets[0]);
arbiter.iSocket.bind(controller.tSocket);
controller.iSocket.bind(dram.tSocket);
cout << "Toplevel: simulation start" << std::endl;
clock_t begin = clock();
sc_start();
clock_t end = clock();
double elapsed_secs = double(end - begin) / CLOCKS_PER_SEC;
cout << "Simulation took " << elapsed_secs << " seconds. You better optimize your model ! " << endl;
delete recorder;
string testingScript = pathToStaticFolder + string("/tests.py");
string runTestCommand = string("python ") + testingScript + string(" tpr.tdb");
//system(runTestCommand.c_str());
string run_tpr = "/home/jonny/git/analyzer/build-traceAnalyzer-Desktop-Debug/traceAnalyzer tpr.tdb";
system(run_tpr.c_str());
return 0;
}

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/*
* traceplayer.h
*
* Created on: Mar 16, 2014
* Author: robert
*/
#ifndef TRACEPLAYER_H_
#define TRACEPLAYER_H_
#include <deque>
#include <tlm.h>
#include <systemc.h>
#include <tlm_utils/simple_initiator_socket.h>
#include <tlm_utils/peq_with_cb_and_phase.h>
#include <iostream>
#include <string>
#include "MemoryManager.h"
using namespace std;
using namespace tlm;
template<unsigned int BUSWIDTH = 128>
struct TracePlayer: public sc_module
{
public:
tlm_utils::simple_initiator_socket<TracePlayer,BUSWIDTH, tlm::tlm_base_protocol_types> iSocket;
unsigned int transactionsSend;
TracePlayer(sc_module_name name, string pathToTrace) :
payloadEventQueue(this, &TracePlayer::peqCallback), file(pathToTrace), numberOfPendingTransactions(0), transactionsSend(0)
{
if (!file.is_open())
SC_REPORT_FATAL(0, (string("Could not open trace ") + pathToTrace).c_str());
if(!file)
{
SC_REPORT_FATAL(0, "trace is empty! Simulation stops");
sc_stop();
}
iSocket.register_nb_transport_bw(this, &TracePlayer::nb_transport_bw);
scheduleNextPayload();
}
private:
tlm_utils::peq_with_cb_and_phase<TracePlayer> payloadEventQueue;
MemoryManager memoryManager;
ifstream file;
unsigned int numberOfPendingTransactions;
void scheduleNextPayload()
{
if(file)
{
string time,command,address;
file >> time >> command >>address;
//if there is a newline at the end of the .stl
if(time.empty() || command.empty() || address.empty())
return;
gp* payload = memoryManager.allocate();
long parsedAdress = std::stoi(address.c_str(),0,16);
payload->set_address(parsedAdress);
if(command == "read")
{
payload->set_command(TLM_READ_COMMAND);
}
else if(command == "write")
{
payload->set_command(TLM_WRITE_COMMAND);
}
else
{
SC_REPORT_FATAL(0, (string("Corrupted tracefile, command ") + command + string(" unknown")).c_str());
}
payload->set_data_length(BUSWIDTH/8);
payload->set_response_status(TLM_INCOMPLETE_RESPONSE);
payload->set_dmi_allowed(false);
payload->set_byte_enable_length(0);
payload->set_streaming_width(0);
sc_time sendingTime = sc_time(std::stoi(time.c_str()), SC_NS);
if(sendingTime <= sc_time_stamp())
{
payloadEventQueue.notify(*payload,BEGIN_REQ,SC_ZERO_TIME);
}
else
{
payloadEventQueue.notify(*payload,BEGIN_REQ,sendingTime - sc_time_stamp());
}
numberOfPendingTransactions++;
}
}
tlm_sync_enum nb_transport_bw(tlm_generic_payload& payload, tlm_phase& phase, sc_time& bwDelay)
{
payloadEventQueue.notify(payload, phase, bwDelay);
return TLM_ACCEPTED;
}
void peqCallback(tlm_generic_payload& payload, const tlm_phase& phase)
{
if (phase == BEGIN_REQ)
{
payload.acquire();
sendToTarget(payload,phase,SC_ZERO_TIME);
//cout << "Sending transaction number: " << transactionsSend << std::endl;
transactionsSend++;
//cout << "Traceplayer: sending transaction at " << sc_time_stamp() << std::endl;
}
else if (phase == END_REQ)
{
scheduleNextPayload();
}
else if (phase == BEGIN_RESP)
{
payload.release();
sendToTarget(payload,END_RESP,SC_ZERO_TIME);
numberOfPendingTransactions--;
//cout << numberOfPendingTransactions << std::endl;
if(numberOfPendingTransactions == 0)
payloadEventQueue.notify(payload, END_RESP, SC_ZERO_TIME);
}
//kleiner hack
else if (phase == END_RESP)
{
cout << "simulation stop at " << sc_time_stamp() << std::endl;
sc_stop();
}
else
{
SC_REPORT_FATAL(0, "TracePlayer PEQ was triggered with unknown phase");
}
}
void sendToTarget(tlm_generic_payload& payload, const tlm_phase& phase, const sc_time& delay)
{
tlm_phase TPhase = phase;
sc_time TDelay = delay;
iSocket->nb_transport_fw(payload, TPhase, TDelay);
}
};
#endif /* TRACEPLAYER_H_ */

3
dram/static/.gitignore vendored Normal file
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*.stl
*.pyc
sampleStlGeneration.py

21
dram/static/addressConfig.xml Executable file
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<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<!--
<dramconfig>
<addressmap length="29">
<channel from="27" to="28" />
<bank from="24" to="26" />
<row from="11" to="23" />
<colum from="4" to="10" />
<bytes from="0" to="3" />
</addressmap>
</dramconfig>
-->
<dramconfig>
<addressmap length="29">
<channel from="27" to="28" />
<row from="14" to="26" />
<bank from="11" to="13" />
<colum from="4" to="10" />
<bytes from="0" to="3" />
</addressmap>
</dramconfig>

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DROP TABLE IF EXISTS Phases;
DROP TABLE IF EXISTS GeneralInfo;
DROP TABLE IF EXISTS Comments;
DROP TABLE IF EXISTS ranges;
DROP TABLE IF EXISTS Transactions;
DROP TABLE IF EXISTS DebugMessages;
CREATE TABLE Phases(
ID INTEGER PRIMARY KEY,
PhaseName TEXT,
PhaseBegin INTEGER,
PhaseEnd INTEGER,
Transact INTEGER
);
CREATE TABLE GeneralInfo(
NumberOfTransactions INTEGER,
TraceEnd INTEGER,
NumberOfBanks INTEGER,
Description TEXT,
clk INTEGER,
UnitOfTime TEXT
);
CREATE TABLE Comments(
Time INTEGER,
Text TEXT
);
CREATE TABLE DebugMessages(
Time INTEGER,
Message TEXT
);
-- use SQLITE R* TREE Module to make queries on timespans effecient (see http://www.sqlite.org/rtree.html)
CREATE VIRTUAL TABLE ranges USING rtree(
id,
begin, end
);
CREATE TABLE Transactions(
ID INTEGER PRIMARY KEY,
Range INTEGER,
Address INTEGER,
TThread INTEGER,
TChannel INTEGER,
TBank INTEGER,
TRow INTEGER,
TColumn INTEGER,
Command TEXT);
CREATE INDEX ranges_index ON Transactions(Range);
CREATE INDEX "phasesTransactions" ON "Phases" ("Transact" ASC);
CREATE INDEX "messageTimes" ON "DebugMessages" ("Time" ASC)

25
dram/static/metrics.py Normal file
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import sys
import sqlite3
def the_answer_to_life_the_universe_and_everything(connection):
return 42
def number_of_precharges(connection):
return 21
def calculateMetrics(pathToTrace):
connection = sqlite3.connect(pathToTrace)
metrics = [the_answer_to_life_the_universe_and_everything, number_of_precharges]
result = []
for metric in metrics:
result.append((metric.__name__.replace("_"," "), metric(connection)))
connection.close()
print(result)
return result
if __name__ == "__main__":
path = sys.argv[1]
calculateMetrics(path)

120
dram/static/stlGenerator.py Normal file
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import xml.etree.ElementTree as ET
import re
import sys
import os
class DramConfigReader:
maxValues = {}
startBits = {}
endBits = {}
def __extractAdressEncoding(self, root, elementName):
rowElement = root[0].find(elementName)
rowBitFrom, rowBitsTo = int(
rowElement.attrib['from']), int(rowElement.attrib['to'])
rowBitRange = rowBitsTo - rowBitFrom + 1
maxRow = 2 ** rowBitRange - 1
#print('{0}: range {1}..{2}'.format(elementName, 0, maxRow))
self.startBits[elementName] = rowBitFrom
self.endBits[elementName] = rowBitsTo
self.maxValues[elementName] = maxRow
def __init__(self):
root = ET.parse(
os.path.dirname(os.path.realpath(sys.argv[0])) + '/addressConfig.xml').getroot()
self.__extractAdressEncoding(root, 'channel')
self.__extractAdressEncoding(root, 'bank')
self.__extractAdressEncoding(root, 'row')
self.__extractAdressEncoding(root, 'colum')
class StlReader:
__dramConfigReader = DramConfigReader()
def onesMask(self, numberOfOnes):
result = 0
for i in range(numberOfOnes):
result = result | 1 << i
return result
def parseAttributeFromAddress(self, address, element):
return address >> self.__dramConfigReader.startBits[element] & self.onesMask(self.__dramConfigReader.endBits[element] - self.__dramConfigReader.startBits[element] + 1)
def formatStlLine(self, line):
try:
found = re.search('0x[0-9,a-f]+', line).group(0)
address = int(found, 16)
decodedAddress = '[Channel: {0} Bank: {1} Row:{2} Column: {3}]'.format(self.parseAttributeFromAddress(address, 'channel'),
self.parseAttributeFromAddress(address, 'bank'), self.parseAttributeFromAddress(address, 'row'), self.parseAttributeFromAddress(address, 'colum'))
return line.replace("\n", " ") + decodedAddress
except AttributeError:
return ''
def printStlPretty(self, filename):
f = open(filename)
for line in f.readlines():
print(self.formatStlLine(line))
class StlGenerator:
__actions = []
__time = 0
__dramConfigReader = DramConfigReader()
def clear(self):
self.__actions = []
self.__time = 0
def setTime(self, time):
self.__time = time
def addAction(self, bank, row, channel=0, RD_WR='read'):
tupel = (self.__time, RD_WR, self.__generateAdress(channel, bank, row))
self.__actions.append(tupel)
def setTimeAndAddAction(self, time, bank, row, channel=0, RD_WR='read'):
self.setTime(self, time)
self.addAction(self, bank, row, channel, RD_WR)
def addLoad(self, banks, rows, channel=0, RD_WR='read'):
for bank in banks:
for row in rows:
self.addAction(bank, row, channel, RD_WR)
def setTimeAndAddLoad(self, time, banks, rows, channel=0, RD_WR='read'):
self.setTime(self, time)
self.addLoad(banks, rows, channel, RD_WR)
def generateStl(self, filename):
f = open(filename, 'w')
tmp = []
for tupel in self.__actions:
tmp.append('{0}: {1} {2:#x}'.format(tupel[0], tupel[1], tupel[2]))
result = '\n'.join(tmp)
f.write(result)
f.close()
print(
'<---------------------- Generated stl {0} ---------------------->'.format(filename))
print(result)
print(
'<---------------------- End generated stl ---------------------->'.format(filename))
def __generateAdress(self, channel, bank, row):
if(channel > self.__dramConfigReader.maxValues['channel']):
raise(BaseException('Channel argument out of range'))
if(bank > self.__dramConfigReader.maxValues['bank']):
raise(BaseException('Bank argument out of range'))
if(row > self.__dramConfigReader.maxValues['row']):
raise(BaseException('Row argument out of range'))
return (channel << self.__dramConfigReader.startBits['channel']) | (bank << self.__dramConfigReader.startBits['bank']) | (row << self.__dramConfigReader.startBits['row'])
def __init__(self):
pass
if __name__ == '__main__':
if(len(sys.argv) > 1):
stlReader = StlReader()
for line in sys.argv[1:]:
stlReader.printStlPretty(line)

281
dram/static/tests.py Normal file
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@@ -0,0 +1,281 @@
import sys
import sqlite3
import math
class DramConfig(object):
"""Holds the timing constraints in the standard and the configuration of the DRAM"""
unitOfTime = "ns"
nActivateWindow = 0
burstLengtht = 2
clk = numberOfBanks = 0
tRP = tRAS = tRC = tRRD = tRCD = tTAW = tRL = tWL = tWTR = 0
def clkAlign(self, value):
return math.ceil(value/self.clk)*self.clk
def parseFromXml(self):
self.clk = 6
self.numberOfBanks = 8
self.nActivateWindow = 2
self.burstLength = 2
self.tRP = 3*self.clk
self.tRAS = 6*self.clk
self.tRRD = 2*self.clk
self.tRC = self.tRP + self.tRAS
self.tRCD = 3*self.clk
self.tRL = 3*self.clk
self.tWL = 1*self.clk
self.tWTR = 3*self.clk
self.tTAW = self.clkAlign(50)
def __init__(self):
self.parseFromXml()
dramconfig = DramConfig()
# ----------- test utils ---------------------------------------
tests = []
def test(function):
tests.append(function)
return function
class TestResult(object):
passed = True
message = ''
def __init__(self, passed = True, message = ''):
self.passed = passed
self.message = message
def TestSuceeded():
return TestResult()
def TestFailed(message):
return TestResult(False,message);
def formatTime(time):
return ('{0} {1}'.format(time, dramconfig.unitOfTime))
# ----------- command bus checks ---------------------------------------
@test
def commands_are_clockaligned(connection):
"""Checks that all commands on the command bus are aligned to the system clock"""
passedTest = True
cursor = connection.cursor()
cursor.execute("SELECT ID, PhaseBegin, PhaseEnd from Phases WHERE PhaseName NOT IN ('REQ','RESP') ORDER BY PhaseBegin")
lastRow = cursor.fetchone()
for currentRow in cursor:
phaseBegin = currentRow[1]
phaseEnd = currentRow[2]
if(phaseBegin % dramconfig.clk != 0):
return TestFailed("Command with PhaseID {0} starts at {1} and is not aligned to system clock ({2})".format(
currentRow[0], formatTime(phaseBegin), formatTime(dramconfig.clk)))
if(phaseEnd % dramconfig.clk != 0):
return TestFailed("Command with PhaseID {0} end at {1} and is not aligned to system clock ({2})".format(
currentRow[0], formatTime(phaseEnd), formatTime(dramconfig.clk)))
return TestSuceeded()
@test
def commandbus_slots_are_used_once(connection):
"""Checks that no two phases on the command bus start at the same time"""
cursor = connection.cursor()
cursor.execute("SELECT ID,PhaseBegin from Phases WHERE PhaseName NOT IN ('REQ', 'RESP') ORDER BY PhaseBegin")
lastRow = cursor.fetchone()
for currentRow in cursor:
if(lastRow[1] != currentRow[1]):
lastRow = currentRow
else:
return TestFailed("Commandbus slot is used twice by commands with PhaseID {0} and {1}".format(lastRow[0], currentRow[0]))
return TestSuceeded()
# ----------- precharge checks ---------------------------------------
# ----------- activate checks ---------------------------------------
@test
def precharge_before_activate(connection):
"""Checks that all activate commands are preceeded by a precharge or a refresh or a powerdown"""
cursor = connection.cursor()
query = """SELECT Phases.ID, PhaseName, PhaseBegin FROM Transactions INNER JOIN Phases ON Phases.Transact = Transactions.ID
WHERE (TBank = :bank AND PhaseName IN ('ACT','PRE','REFB')) OR PhaseName IN ('REFA','SREF','PDNP','PDNA') ORDER BY PhaseBegin"""
for bankNumber in range(dramconfig.numberOfBanks):
cursor.execute(query,{"bank": bankNumber})
lastRow = cursor.fetchone()
for currentRow in cursor:
if(lastRow[1] != currentRow[1] or currentRow[1] != 'ACT'):
lastRow = currentRow
else:
return TestFailed("No precharge between activates with PhaseID {0} and {1}".format(lastRow[0], currentRow[0]))
return TestSuceeded()
@test
def activate_to_activate(connection):
"""Checks minimal time between two activates (JEDEC 229, P. 27)"""
cursor = connection.cursor()
cursor.execute("SELECT ID,PhaseBegin from Phases WHERE PhaseName = 'ACT' ORDER BY PhaseBegin")
lastRow = cursor.fetchone()
for currentRow in cursor:
timeBetweenActivates = currentRow[1] - lastRow[1];
if(timeBetweenActivates < dramconfig.tRRD):
return TestFailed("Activates with PhaseIDs {0} and {1} are {2} apart. Minimum time between two activates is {3}".format(currentRow[0], lastRow[0],formatTime(timeBetweenActivates), dramconfig.tRRD))
else:
lastRow = currentRow
return TestSuceeded()
@test
def activate_to_activate_on_same_bank(connection):
"""Checks minimal time between two activates on the same bank (JEDEC 229, P. 27)"""
cursor = connection.cursor()
query = "SELECT Phases.ID,PhaseBegin from Phases INNER JOIN Transactions ON Phases.Transact = Transactions.ID WHERE PhaseName = 'ACT' AND TBANK = :bank ORDER BY PhaseBegin"
for bankNumber in range(dramconfig.numberOfBanks):
cursor.execute(query,{"bank": bankNumber})
lastRow = cursor.fetchone()
for currentRow in cursor:
timeBetweenActivates = currentRow[1] - lastRow[1];
if(timeBetweenActivates < dramconfig.tRC):
return TestFailed("Activates with PhaseIDs {0} and {1} are {2} apart. Minimum time between two activates is {3}, since they are on the same bank({4})".
format(currentRow[0], lastRow[0],formatTime(timeBetweenActivates), dramconfig.tRC))
else:
lastRow = currentRow
return TestSuceeded()
@test
def n_activate_window(connection):
"""Checks n-Activate constraint (JEDEC 229, P. 27)"""
cursor = connection.cursor()
cursor.execute("SELECT ID,PhaseBegin from Phases WHERE PhaseName = 'ACT' ORDER BY PhaseBegin")
activateWindow = []
for currentRow in cursor:
activateWindow.append(currentRow[1])
if(len(activateWindow) > dramconfig.nActivateWindow + 1):
activateWindow.pop(0)
if(activateWindow[dramconfig.nActivateWindow] - activateWindow[0] < dramconfig.tTAW):
return TestFailed("Activate with PhaseID {0} and the {1} preceeding activates violate the '{1} activate window' constraint."
" No more than {1} activates should be in rolling time window of {2}".format(currentRow[0], dramconfig.nActivateWindow,formatTime(dramconfig.tTAW)))
return TestSuceeded()
# ----------- read checks ---------------------------------------
@test
def activate_to_read(connection):
"""Checks minimal time bewteen activate and following read (JEDEC 229, P. 29)"""
cursor = connection.cursor()
query = "SELECT Phases.ID,PhaseBegin,PhaseName from Phases INNER JOIN Transactions ON Phases.Transact = Transactions.ID WHERE PhaseName IN ('ACT','RD') AND TBANK = :bank ORDER BY PhaseBegin"
for bankNumber in range(dramconfig.numberOfBanks):
cursor.execute(query,{"bank": bankNumber})
lastRow = cursor.fetchone()
for currentRow in cursor:
if(currentRow[2] == "RD" and lastRow[2] == "ACT"):
actToReadTime = currentRow[1] - lastRow[1];
if(actToReadTime < dramconfig.tRCD):
return TestFailed("Read with PhaseID {0} starts {1} after activate {2}. Minimum activate to read time is {3}".
format(currentRow[0],formatTime(actToReadTime),lastRow[0], formatTime(dramconfig.tRCD)))
lastRow = currentRow
return TestSuceeded()
@test
def read_to_read(connection):
"""Checks minimal time between two reads(JEDEC 229, P. 29)"""
cursor = connection.cursor()
cursor.execute("SELECT Phases.ID, PhaseBegin, PhaseEnd from Phases WHERE PhaseName = 'RD' ORDER BY PhaseBegin")
lastRow = cursor.fetchone()
for currentRow in cursor:
if(currentRow[1] < lastRow[2]):
timeBetweenReads = currentRow[1] - lastRow[1];
clocksBetweenReads = round(timeBetweenReads/dramconfig.clk)
if(clocksBetweenReads % 2 == 1):
return TestFailed("Read with PhaseID {0} interrupts read {1}. They are {2} clocks ({3}) apart. Numbers of clock between interrupting reads must be even.".
format(currentRow[0], lastRow[0], clocksBetweenReads, formatTime(timeBetweenReads)))
lastRow = currentRow
return TestSuceeded()
@test
def write_to_read(connection):
"""Checks minimal time between write and following read (JEDEC 229, P. 34)"""
cursor = connection.cursor()
query = "SELECT Phases.ID,PhaseBegin,PhaseEnd,PhaseName from Phases INNER JOIN Transactions ON Phases.Transact = Transactions.ID WHERE PhaseName IN ('RD','WR') AND TBANK = :bank ORDER BY PhaseBegin"
for bankNumber in range(dramconfig.numberOfBanks):
cursor.execute(query,{"bank": bankNumber})
lastRow = cursor.fetchone()
for currentRow in cursor:
if(currentRow[3] == "RD" and lastRow[3] == "WR"):
writeEndToReadBegin = currentRow[1] - lastRow[2];
if(writeEndToReadBegin < dramconfig.tWTR ):
return TestFailed("Read with PhaseID {0} starts {1} after end of write {2}. Minimum time between end of write and start of read is {3}".
format(currentRow[0],formatTime(writeEndToReadBegin),lastRow[0], formatTime(dramconfig.tWTR )))
lastRow = currentRow
return TestSuceeded()
# -------------------------- interface methods --------------------
def runTests(pathToTrace):
connection = sqlite3.connect(pathToTrace)
testResults = []
numberOfFailedTest = 0
print("================================")
print("RUNNING TEST ON {0}".format(pathToTrace))
print("-----------------------------\n")
for test in tests:
testResult = test(connection)
testName = test.__name__.replace("_"," ")
testResults.append((testName, testResult.passed,testResult.message))
if(testResult.passed):
print("{0} passed".format(testName))
else:
print(">>>>>>{0} failed. Message: {1}".format(testName, testResult.message))
numberOfFailedTest = numberOfFailedTest + 1
print("\n-----------------------------")
if(numberOfFailedTest == 0):
print("All tests passed")
else:
print("{0} of {1} tests passed".format(len(tests) - numberOfFailedTest,len(tests)))
print("================================")
connection.close()
return testResults
if __name__ == "__main__":
path = sys.argv[1]
runTests(path)

View File

@@ -9,7 +9,7 @@
#include <gmock/gmock.h>
#include <core/refresh/BankwiseRefreshManager.h>
#include "testUtils.h"
#include "common/dramExtension.h"
#include "../common/dramExtension.h"
using namespace testing;

View File

@@ -14,7 +14,7 @@
#include <core/refresh/BankwiseRefreshManager.h>
#include "tlm/IControllerWrapper.h"
#include "testUtils.h"
#include "common/dramExtension.h"
#include "../common/dramExtension.h"
#include "core/Controller.h"
#include <tlm.h>