From cb4455710dda9112869411f29699792489699ac1 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Mon, 17 May 2021 15:51:55 +0200 Subject: [PATCH] Add config files for STT-MRAM. --- .../am_stt-mram_8x2Gbx8_dimm_p1KB_rbc.json | 43 ++++++++++++++ .../configs/mcconfigs/fr_fcfs_noref.json | 16 ++++++ .../configs/memspecs/STT-MRAM-1.2x.json | 44 +++++++++++++++ .../configs/memspecs/STT-MRAM-1.5x.json | 44 +++++++++++++++ .../configs/memspecs/STT-MRAM-2.0x.json | 44 +++++++++++++++ .../resources/configs/simulator/stt-mram.json | 19 +++++++ .../simulations/stt-mram-example.json | 16 ++++++ .../configuration/memspec/MemSpecSTTMRAM.cpp | 5 -- .../configuration/memspec/MemSpecSTTMRAM.h | 19 +++---- .../src/controller/checker/CheckerDDR3.cpp | 4 +- .../src/controller/checker/CheckerDDR4.cpp | 6 +- .../src/controller/checker/CheckerSTTMRAM.cpp | 56 ++----------------- 12 files changed, 245 insertions(+), 71 deletions(-) create mode 100644 DRAMSys/library/resources/configs/amconfigs/am_stt-mram_8x2Gbx8_dimm_p1KB_rbc.json create mode 100644 DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_noref.json create mode 100644 DRAMSys/library/resources/configs/memspecs/STT-MRAM-1.2x.json create mode 100644 DRAMSys/library/resources/configs/memspecs/STT-MRAM-1.5x.json create mode 100644 DRAMSys/library/resources/configs/memspecs/STT-MRAM-2.0x.json create mode 100644 DRAMSys/library/resources/configs/simulator/stt-mram.json create mode 100644 DRAMSys/library/resources/simulations/stt-mram-example.json diff --git a/DRAMSys/library/resources/configs/amconfigs/am_stt-mram_8x2Gbx8_dimm_p1KB_rbc.json b/DRAMSys/library/resources/configs/amconfigs/am_stt-mram_8x2Gbx8_dimm_p1KB_rbc.json new file mode 100644 index 00000000..d1bcfe70 --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_stt-mram_8x2Gbx8_dimm_p1KB_rbc.json @@ -0,0 +1,43 @@ +{ + "CONGEN": { + "BANK_BIT": [ + 13, + 14, + 15 + ], + "BYTE_BIT": [ + 0, + 1, + 2 + ], + "COLUMN_BIT": [ + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12 + ], + "ROW_BIT": [ + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30 + ] + } +} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_noref.json b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_noref.json new file mode 100644 index 00000000..b0d0a554 --- /dev/null +++ b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_noref.json @@ -0,0 +1,16 @@ +{ + "mcconfig": { + "PagePolicy": "Open", + "Scheduler": "FrFcfs", + "SchedulerBuffer": "Bankwise", + "RequestBufferSize": 8, + "CmdMux": "Oldest", + "RespQueue": "Fifo", + "RefreshPolicy": "NoRefresh", + "RefreshMaxPostponed": 0, + "RefreshMaxPulledin": 0, + "PowerDownPolicy": "NoPowerDown", + "Arbiter": "Simple", + "MaxActiveTransactions": 128 + } +} diff --git a/DRAMSys/library/resources/configs/memspecs/STT-MRAM-1.2x.json b/DRAMSys/library/resources/configs/memspecs/STT-MRAM-1.2x.json new file mode 100644 index 00000000..88511099 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/STT-MRAM-1.2x.json @@ -0,0 +1,44 @@ +{ + "memspec": { + "memarchitecturespec": { + "burstLength": 8, + "dataRate": 2, + "nbrOfBanks": 8, + "nbrOfColumns": 1024, + "nbrOfRanks": 1, + "nbrOfRows": 32768, + "width": 8, + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 + }, + "memoryId": "STT-MRAM-1.2x", + "memoryType": "STT-MRAM", + "memtimingspec": { + "AL": 0, + "CCD": 4, + "CKE": 4, + "CKESR": 7, + "CL": 11, + "DQSCK": 0, + "FAW": 29, + "RAS": 20, + "RC": 34, + "RCD": 14, + "RL": 11, + "RP": 14, + "RRD": 6, + "RTP": 6, + "WL": 11, + "WR": 12, + "WTR": 2, + "XP": 5, + "XPDLL": 325, + "XS": 324, + "XSDLL": 512, + "ACTPDEN": 2, + "PRPDEN": 2, + "RTRS": 1, + "clkMhz": 800 + } + } +} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/STT-MRAM-1.5x.json b/DRAMSys/library/resources/configs/memspecs/STT-MRAM-1.5x.json new file mode 100644 index 00000000..57440f78 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/STT-MRAM-1.5x.json @@ -0,0 +1,44 @@ +{ + "memspec": { + "memarchitecturespec": { + "burstLength": 8, + "dataRate": 2, + "nbrOfBanks": 8, + "nbrOfColumns": 1024, + "nbrOfRanks": 1, + "nbrOfRows": 32768, + "width": 8, + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 + }, + "memoryId": "STT-MRAM-1.5x", + "memoryType": "STT-MRAM", + "memtimingspec": { + "AL": 0, + "CCD": 4, + "CKE": 4, + "CKESR": 7, + "CL": 11, + "DQSCK": 0, + "FAW": 36, + "RAS": 23, + "RC": 40, + "RCD": 14, + "RL": 11, + "RP": 17, + "RRD": 8, + "RTP": 6, + "WL": 11, + "WR": 12, + "WTR": 6, + "XP": 5, + "XPDLL": 325, + "XS": 324, + "XSDLL": 512, + "ACTPDEN": 2, + "PRPDEN": 2, + "RTRS": 1, + "clkMhz": 800 + } + } +} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/STT-MRAM-2.0x.json b/DRAMSys/library/resources/configs/memspecs/STT-MRAM-2.0x.json new file mode 100644 index 00000000..08d0ba9b --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/STT-MRAM-2.0x.json @@ -0,0 +1,44 @@ +{ + "memspec": { + "memarchitecturespec": { + "burstLength": 8, + "dataRate": 2, + "nbrOfBanks": 8, + "nbrOfColumns": 1024, + "nbrOfRanks": 1, + "nbrOfRows": 32768, + "width": 8, + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 + }, + "memoryId": "STT-MRAM-2.0x", + "memoryType": "STT-MRAM", + "memtimingspec": { + "AL": 0, + "CCD": 4, + "CKE": 4, + "CKESR": 7, + "CL": 11, + "DQSCK": 0, + "FAW": 36, + "RAS": 28, + "RC": 50, + "RCD": 14, + "RL": 11, + "RP": 22, + "RRD": 10, + "RTP": 6, + "WL": 11, + "WR": 48, + "WTR": 6, + "XP": 5, + "XPDLL": 325, + "XS": 324, + "XSDLL": 512, + "ACTPDEN": 2, + "PRPDEN": 2, + "RTRS": 1, + "clkMhz": 800 + } + } +} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/simulator/stt-mram.json b/DRAMSys/library/resources/configs/simulator/stt-mram.json new file mode 100644 index 00000000..3248e9f0 --- /dev/null +++ b/DRAMSys/library/resources/configs/simulator/stt-mram.json @@ -0,0 +1,19 @@ +{ + "simconfig": { + "AddressOffset": 0, + "CheckTLM2Protocol": false, + "DatabaseRecording": true, + "Debug": false, + "ECCControllerMode": "Disabled", + "EnableWindowing": false, + "ErrorCSVFile": "", + "ErrorChipSeed": 42, + "PowerAnalysis": false, + "SimulationName": "stt-mram", + "SimulationProgressBar": true, + "StoreMode": "NoStorage", + "ThermalSimulation": false, + "UseMalloc": false, + "WindowSize": 1000 + } +} diff --git a/DRAMSys/library/resources/simulations/stt-mram-example.json b/DRAMSys/library/resources/simulations/stt-mram-example.json new file mode 100644 index 00000000..fd9e3fce --- /dev/null +++ b/DRAMSys/library/resources/simulations/stt-mram-example.json @@ -0,0 +1,16 @@ +{ + "simulation": { + "addressmapping": "am_stt-mram_8x2Gbx8_dimm_p1KB_rbc.json", + "mcconfig": "fr_fcfs_noref.json", + "memspec": "STT-MRAM-1.2x.json", + "simconfig": "stt-mram.json", + "simulationid": "stt-mram-example", + "thermalconfig": "config.json", + "tracesetup": [ + { + "clkMhz": 800, + "name": "ddr3_example.stl" + } + ] + } +} diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.cpp index bab51776..1d4d52c6 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.cpp @@ -64,8 +64,6 @@ MemSpecSTTMRAM::MemSpecSTTMRAM(json &memspec) tXS (tCK * parseUint(memspec["memtimingspec"]["XS"], "XS")), tCCD (tCK * parseUint(memspec["memtimingspec"]["CCD"], "CCD")), tFAW (tCK * parseUint(memspec["memtimingspec"]["FAW"], "FAW")), - tREFI (tCK * parseUint(memspec["memtimingspec"]["REFI"], "REFI")), - tRFC (tCK * parseUint(memspec["memtimingspec"]["RFC"], "RFC")), tRP (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")), tRRD (tCK * parseUint(memspec["memtimingspec"]["RRD"], "RRD")), tWTR (tCK * parseUint(memspec["memtimingspec"]["WTR"], "WTR")), @@ -74,7 +72,6 @@ MemSpecSTTMRAM::MemSpecSTTMRAM(json &memspec) tXSDLL (tCK * parseUint(memspec["memtimingspec"]["XSDLL"], "XSDLL")), tACTPDEN (tCK * parseUint(memspec["memtimingspec"]["ACTPDEN"], "ACTPDEN")), tPRPDEN (tCK * parseUint(memspec["memtimingspec"]["PRPDEN"], "PRPDEN")), - tREFPDEN (tCK * parseUint(memspec["memtimingspec"]["REFPDEN"], "REFPDEN")), tRTRS (tCK * parseUint(memspec["memtimingspec"]["RTRS"], "RTRS")) {} @@ -93,8 +90,6 @@ sc_time MemSpecSTTMRAM::getExecutionTime(Command command, const tlm_generic_payl return tWL + burstDuration; else if (command == Command::WRA) return tWL + burstDuration + tWR + tRP; - else if (command == Command::REFA) - return tRFC; else { SC_REPORT_FATAL("getExecutionTime", diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.h b/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.h index a8a5753f..cdd72a0f 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.h @@ -46,8 +46,8 @@ public: // Memspec Variables: const sc_time tCKE; - const sc_time tPD; - const sc_time tCKESR; + const sc_time tPD;//-- + const sc_time tCKESR;//-- const sc_time tRAS; const sc_time tRC; const sc_time tRCD; @@ -56,21 +56,18 @@ public: const sc_time tWL; const sc_time tWR; const sc_time tXP; - const sc_time tXS; - const sc_time tREFI; - const sc_time tRFC; + const sc_time tXS;//-- const sc_time tRP; - const sc_time tDQSCK; + const sc_time tDQSCK;//-- const sc_time tCCD; const sc_time tFAW; const sc_time tRRD; const sc_time tWTR; - const sc_time tXPDLL; - const sc_time tXSDLL; + const sc_time tXPDLL;//-- + const sc_time tXSDLL;//-- const sc_time tAL; - const sc_time tACTPDEN; - const sc_time tPRPDEN; - const sc_time tREFPDEN; + const sc_time tACTPDEN;//-- + const sc_time tPRPDEN;//-- const sc_time tRTRS; // Currents and Voltages: diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp index 0d52b904..089a753b 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp @@ -52,7 +52,7 @@ CheckerDDR3::CheckerDDR3() tBURST = memSpec->burstLength / memSpec->dataRate * memSpec->tCK; tRDWR = memSpec->tRL + tBURST + 2 * memSpec->tCK - memSpec->tWL; tRDWR_R = memSpec->tRL + tBURST + memSpec->tRTRS - memSpec->tWL; - tWRRD = memSpec->tWL + tBURST + memSpec->tWTR; + tWRRD = memSpec->tWL + tBURST + memSpec->tWTR - memSpec->tAL; tWRRD_R = memSpec->tWL + tBURST + memSpec->tRTRS - memSpec->tRL; tWRPRE = memSpec->tWL + tBURST + memSpec->tWR; tRDPDEN = memSpec->tRL + tBURST + memSpec->tCK; @@ -91,7 +91,7 @@ sc_time CheckerDDR3::timeToSatisfyConstraints(Command command, Rank rank, BankGr { lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE - memSpec->tRTP); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE - memSpec->tRTP - memSpec->tAL); } lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp index 25544d7b..3dda147b 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp @@ -54,8 +54,8 @@ CheckerDDR4::CheckerDDR4() tBURST = memSpec->burstLength / memSpec->dataRate * memSpec->tCK; tRDWR = memSpec->tRL + tBURST + memSpec->tCK - memSpec->tWL + memSpec->tWPRE; tRDWR_R = memSpec->tRL + tBURST + memSpec->tRTRS - memSpec->tWL + memSpec->tWPRE; - tWRRD_S = memSpec->tWL + tBURST + memSpec->tWTR_S; - tWRRD_L = memSpec->tWL + tBURST + memSpec->tWTR_L; + tWRRD_S = memSpec->tWL + tBURST + memSpec->tWTR_S - memSpec->tAL; + tWRRD_L = memSpec->tWL + tBURST + memSpec->tWTR_L - memSpec->tAL; tWRRD_R = memSpec->tWL + tBURST + memSpec->tRTRS - memSpec->tRL + memSpec->tRPRE; tWRPRE = memSpec->tWL + tBURST + memSpec->tWR; tRDPDEN = memSpec->tRL + tBURST + memSpec->tCK; @@ -102,7 +102,7 @@ sc_time CheckerDDR4::timeToSatisfyConstraints(Command command, Rank rank, BankGr { lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE - memSpec->tRTP); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE - memSpec->tRTP - memSpec->tAL); } lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; diff --git a/DRAMSys/library/src/controller/checker/CheckerSTTMRAM.cpp b/DRAMSys/library/src/controller/checker/CheckerSTTMRAM.cpp index 99c00fe5..bb157ee7 100644 --- a/DRAMSys/library/src/controller/checker/CheckerSTTMRAM.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerSTTMRAM.cpp @@ -52,7 +52,7 @@ CheckerSTTMRAM::CheckerSTTMRAM() tBURST = memSpec->burstLength / memSpec->dataRate * memSpec->tCK; tRDWR = memSpec->tRL + tBURST + 2 * memSpec->tCK - memSpec->tWL; tRDWR_R = memSpec->tRL + tBURST + memSpec->tRTRS - memSpec->tWL; - tWRRD = memSpec->tWL + tBURST + memSpec->tWTR; + tWRRD = memSpec->tWL + tBURST + memSpec->tWTR - memSpec->tAL; tWRRD_R = memSpec->tWL + tBURST + memSpec->tRTRS - memSpec->tRL; tWRPRE = memSpec->tWL + tBURST + memSpec->tWR; tRDPDEN = memSpec->tRL + tBURST + memSpec->tCK; @@ -75,7 +75,8 @@ sc_time CheckerSTTMRAM::timeToSatisfyConstraints(Command command, Rank rank, Ban if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD); - lastCommandStart = lastScheduledByCommand[Command::RD] != lastScheduledByCommandAndRank[Command::RD][rank.ID()] ? lastScheduledByCommand[Command::RD] : sc_max_time(); + lastCommandStart = lastScheduledByCommand[Command::RD] != lastScheduledByCommandAndRank[Command::RD][rank.ID()] ? + lastScheduledByCommand[Command::RD] : sc_max_time(); if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST + memSpec->tRTRS); @@ -83,7 +84,8 @@ sc_time CheckerSTTMRAM::timeToSatisfyConstraints(Command command, Rank rank, Ban if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD); - lastCommandStart = lastScheduledByCommand[Command::RDA] != lastScheduledByCommandAndRank[Command::RDA][rank.ID()] ? lastScheduledByCommand[Command::RDA] : sc_max_time(); + lastCommandStart = lastScheduledByCommand[Command::RDA] != lastScheduledByCommandAndRank[Command::RDA][rank.ID()] ? + lastScheduledByCommand[Command::RDA] : sc_max_time(); if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST + memSpec->tRTRS); @@ -91,7 +93,7 @@ sc_time CheckerSTTMRAM::timeToSatisfyConstraints(Command command, Rank rank, Ban { lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE - memSpec->tRTP); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE - memSpec->tRTP - memSpec->tAL); } lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; @@ -198,10 +200,6 @@ sc_time CheckerSTTMRAM::timeToSatisfyConstraints(Command command, Rank rank, Ban if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS); @@ -253,40 +251,6 @@ sc_time CheckerSTTMRAM::timeToSatisfyConstraints(Command command, Rank rank, Ban if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); } - else if (command == Command::REFA) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tAL + memSpec->tRTP + memSpec->tRP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tRP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); - - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS); - } else if (command == Command::PDEA) { lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; @@ -349,10 +313,6 @@ sc_time CheckerSTTMRAM::timeToSatisfyConstraints(Command command, Rank rank, Ban if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCKE); - lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tREFPDEN); - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS); @@ -389,10 +349,6 @@ sc_time CheckerSTTMRAM::timeToSatisfyConstraints(Command command, Rank rank, Ban if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS);