From ca026981e15463d7bc9e1f1aaa4e38d6be784e18 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Wed, 20 Jan 2021 08:50:15 +0100 Subject: [PATCH] Remove think delay from scheduler. --- DRAMSys/library/src/controller/Controller.cpp | 9 ++++---- DRAMSys/library/src/controller/Controller.h | 2 +- .../controller/scheduler/SchedulerFifo.cpp | 22 ++++++------------- .../src/controller/scheduler/SchedulerFifo.h | 9 ++------ .../controller/scheduler/SchedulerFrFcfs.cpp | 18 +++------------ .../controller/scheduler/SchedulerFrFcfs.h | 9 ++------ .../scheduler/SchedulerFrFcfsGrp.cpp | 18 +++------------ .../controller/scheduler/SchedulerFrFcfsGrp.h | 9 ++------ .../src/controller/scheduler/SchedulerIF.h | 2 +- 9 files changed, 25 insertions(+), 73 deletions(-) diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index b9788d16..f47008b4 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -67,8 +67,7 @@ Controller::Controller(sc_module_name name) : ControllerIF(name) { SC_METHOD(controllerMethod); - sensitive << beginReqEvent << endRespEvent - << controllerEvent << dataResponseEvent << thinkDelayEvent; + sensitive << beginReqEvent << endRespEvent << controllerEvent << dataResponseEvent; Configuration &config = Configuration::getInstance(); memSpec = config.memSpec; @@ -102,11 +101,11 @@ Controller::Controller(sc_module_name name) : // instantiate scheduler and command mux if (config.scheduler == Configuration::Scheduler::Fifo) - scheduler = new SchedulerFifo(thinkDelayEvent); + scheduler = new SchedulerFifo(); else if (config.scheduler == Configuration::Scheduler::FrFcfs) - scheduler = new SchedulerFrFcfs(thinkDelayEvent); + scheduler = new SchedulerFrFcfs(); else if (config.scheduler == Configuration::Scheduler::FrFcfsGrp) - scheduler = new SchedulerFrFcfsGrp(thinkDelayEvent); + scheduler = new SchedulerFrFcfsGrp(); if (config.cmdMux == Configuration::CmdMux::Oldest) cmdMux = new CmdMuxOldest(); diff --git a/DRAMSys/library/src/controller/Controller.h b/DRAMSys/library/src/controller/Controller.h index 354e3814..4a6e9c54 100644 --- a/DRAMSys/library/src/controller/Controller.h +++ b/DRAMSys/library/src/controller/Controller.h @@ -101,7 +101,7 @@ private: void manageResponses(); void manageRequests(); - sc_event beginReqEvent, endRespEvent, controllerEvent, dataResponseEvent, thinkDelayEvent; + sc_event beginReqEvent, endRespEvent, controllerEvent, dataResponseEvent; }; #endif // CONTROLLER_H diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp b/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp index ba3c05f2..90d38301 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp @@ -40,8 +40,7 @@ using namespace tlm; -SchedulerFifo::SchedulerFifo(sc_event &thinkDelayEvent) - : thinkDelayEvent(thinkDelayEvent) +SchedulerFifo::SchedulerFifo() { Configuration &config = Configuration::getInstance(); buffer = std::vector>(config.memSpec->numberOfBanks); @@ -66,7 +65,7 @@ bool SchedulerFifo::hasBufferSpace() const void SchedulerFifo::storeRequest(tlm_generic_payload *payload) { - thinkDelayBuffer.push({payload, sc_time_stamp() + thinkDelay}); + buffer[DramExtension::getBank(payload).ID()].push_back(payload); bufferCounter->storeRequest(payload); } @@ -76,18 +75,8 @@ void SchedulerFifo::removeRequest(tlm_generic_payload *payload) bufferCounter->removeRequest(payload); } -tlm_generic_payload *SchedulerFifo::getNextRequest(BankMachine *bankMachine) +tlm_generic_payload *SchedulerFifo::getNextRequest(BankMachine *bankMachine) const { - while ((!thinkDelayBuffer.empty()) && (thinkDelayBuffer.front().second <= sc_time_stamp())) - { - tlm_generic_payload *payload = thinkDelayBuffer.front().first; - buffer[DramExtension::getBank(payload).ID()].push_back(payload); - thinkDelayBuffer.pop(); - } - - if (!thinkDelayBuffer.empty()) - thinkDelayEvent.notify(thinkDelayBuffer.front().second - sc_time_stamp()); - unsigned bankID = bankMachine->getBank().ID(); if (!buffer[bankID].empty()) return buffer[bankID].front(); @@ -108,7 +97,10 @@ bool SchedulerFifo::hasFurtherRowHit(Bank bank, Row row) const bool SchedulerFifo::hasFurtherRequest(Bank bank) const { - return (buffer[bank.ID()].size() >= 2); + if (buffer[bank.ID()].size() >= 2) + return true; + else + return false; } const std::vector &SchedulerFifo::getBufferDepth() const diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFifo.h b/DRAMSys/library/src/controller/scheduler/SchedulerFifo.h index 167fd074..ae06ac48 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFifo.h +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFifo.h @@ -38,8 +38,6 @@ #include #include #include -#include -#include #include "SchedulerIF.h" #include "../../common/dramExtensions.h" @@ -49,21 +47,18 @@ class SchedulerFifo final : public SchedulerIF { public: - SchedulerFifo(sc_event &); + SchedulerFifo(); virtual ~SchedulerFifo() override; virtual bool hasBufferSpace() const override; virtual void storeRequest(tlm::tlm_generic_payload *) override; virtual void removeRequest(tlm::tlm_generic_payload *) override; - virtual tlm::tlm_generic_payload *getNextRequest(BankMachine *) override; + virtual tlm::tlm_generic_payload *getNextRequest(BankMachine *) const override; virtual bool hasFurtherRowHit(Bank, Row) const override; virtual bool hasFurtherRequest(Bank) const override; virtual const std::vector &getBufferDepth() const override; private: std::vector> buffer; - std::queue> thinkDelayBuffer; - sc_time thinkDelay; - sc_event &thinkDelayEvent; BufferCounterIF *bufferCounter; }; diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp index 0fa4f433..a15dc6f2 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp @@ -40,12 +40,10 @@ using namespace tlm; -SchedulerFrFcfs::SchedulerFrFcfs(sc_event &thinkDelayEvent) - : thinkDelayEvent(thinkDelayEvent) +SchedulerFrFcfs::SchedulerFrFcfs() { Configuration &config = Configuration::getInstance(); buffer = std::vector>(config.memSpec->numberOfBanks); - thinkDelay = config.thinkDelay; if (config.schedulerBuffer == Configuration::SchedulerBuffer::Bankwise) bufferCounter = new BufferCounterBankwise(config.requestBufferSize, config.memSpec->numberOfBanks); @@ -67,7 +65,7 @@ bool SchedulerFrFcfs::hasBufferSpace() const void SchedulerFrFcfs::storeRequest(tlm_generic_payload *payload) { - thinkDelayBuffer.push({payload, sc_time_stamp() + thinkDelay}); + buffer[DramExtension::getBank(payload).ID()].push_back(payload); bufferCounter->storeRequest(payload); } @@ -85,18 +83,8 @@ void SchedulerFrFcfs::removeRequest(tlm_generic_payload *payload) } } -tlm_generic_payload *SchedulerFrFcfs::getNextRequest(BankMachine *bankMachine) +tlm_generic_payload *SchedulerFrFcfs::getNextRequest(BankMachine *bankMachine) const { - while ((!thinkDelayBuffer.empty()) && (thinkDelayBuffer.front().second <= sc_time_stamp())) - { - tlm_generic_payload *payload = thinkDelayBuffer.front().first; - buffer[DramExtension::getBank(payload).ID()].push_back(payload); - thinkDelayBuffer.pop(); - } - - if (!thinkDelayBuffer.empty()) - thinkDelayEvent.notify(thinkDelayBuffer.front().second - sc_time_stamp()); - unsigned bankID = bankMachine->getBank().ID(); if (!buffer[bankID].empty()) { diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.h b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.h index 5b15b503..15633b51 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.h +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.h @@ -38,8 +38,6 @@ #include #include #include -#include -#include #include "SchedulerIF.h" #include "../../common/dramExtensions.h" @@ -49,21 +47,18 @@ class SchedulerFrFcfs final : public SchedulerIF { public: - SchedulerFrFcfs(sc_event &); + SchedulerFrFcfs(); virtual ~SchedulerFrFcfs() override; virtual bool hasBufferSpace() const override; virtual void storeRequest(tlm::tlm_generic_payload *) override; virtual void removeRequest(tlm::tlm_generic_payload *) override; - virtual tlm::tlm_generic_payload *getNextRequest(BankMachine *) override; + virtual tlm::tlm_generic_payload *getNextRequest(BankMachine *) const override; virtual bool hasFurtherRowHit(Bank, Row) const override; virtual bool hasFurtherRequest(Bank) const override; virtual const std::vector &getBufferDepth() const override; private: std::vector> buffer; - std::queue> thinkDelayBuffer; - sc_time thinkDelay; - sc_event &thinkDelayEvent; BufferCounterIF *bufferCounter; }; diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.cpp b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.cpp index 98d758c0..a1510123 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.cpp +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.cpp @@ -40,12 +40,10 @@ using namespace tlm; -SchedulerFrFcfsGrp::SchedulerFrFcfsGrp(sc_event &thinkDelayEvent) - : thinkDelayEvent(thinkDelayEvent) +SchedulerFrFcfsGrp::SchedulerFrFcfsGrp() { Configuration &config = Configuration::getInstance(); buffer = std::vector>(config.memSpec->numberOfBanks); - thinkDelay = config.thinkDelay; if (config.schedulerBuffer == Configuration::SchedulerBuffer::Bankwise) bufferCounter = new BufferCounterBankwise(config.requestBufferSize, config.memSpec->numberOfBanks); @@ -67,7 +65,7 @@ bool SchedulerFrFcfsGrp::hasBufferSpace() const void SchedulerFrFcfsGrp::storeRequest(tlm_generic_payload *payload) { - thinkDelayBuffer.push({payload, sc_time_stamp() + thinkDelay}); + buffer[DramExtension::getBank(payload).ID()].push_back(payload); bufferCounter->storeRequest(payload); } @@ -86,18 +84,8 @@ void SchedulerFrFcfsGrp::removeRequest(tlm_generic_payload *payload) } } -tlm_generic_payload *SchedulerFrFcfsGrp::getNextRequest(BankMachine *bankMachine) +tlm_generic_payload *SchedulerFrFcfsGrp::getNextRequest(BankMachine *bankMachine) const { - while ((!thinkDelayBuffer.empty()) && (thinkDelayBuffer.front().second <= sc_time_stamp())) - { - tlm_generic_payload *payload = thinkDelayBuffer.front().first; - buffer[DramExtension::getBank(payload).ID()].push_back(payload); - thinkDelayBuffer.pop(); - } - - if (!thinkDelayBuffer.empty()) - thinkDelayEvent.notify(thinkDelayBuffer.front().second - sc_time_stamp()); - unsigned bankID = bankMachine->getBank().ID(); if (!buffer[bankID].empty()) { diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.h b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.h index 8096366e..b6f67e1c 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.h +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.h @@ -38,8 +38,6 @@ #include #include #include -#include -#include #include "SchedulerIF.h" #include "../../common/dramExtensions.h" @@ -49,21 +47,18 @@ class SchedulerFrFcfsGrp final : public SchedulerIF { public: - SchedulerFrFcfsGrp(sc_event &); + SchedulerFrFcfsGrp(); virtual ~SchedulerFrFcfsGrp() override; virtual bool hasBufferSpace() const override; virtual void storeRequest(tlm::tlm_generic_payload *) override; virtual void removeRequest(tlm::tlm_generic_payload *) override; - virtual tlm::tlm_generic_payload *getNextRequest(BankMachine *) override; + virtual tlm::tlm_generic_payload *getNextRequest(BankMachine *) const override; virtual bool hasFurtherRowHit(Bank, Row) const override; virtual bool hasFurtherRequest(Bank) const override; virtual const std::vector &getBufferDepth() const override; private: std::vector> buffer; - std::queue> thinkDelayBuffer; - sc_time thinkDelay; - sc_event &thinkDelayEvent; tlm::tlm_command lastCommand = tlm::TLM_READ_COMMAND; BufferCounterIF *bufferCounter; }; diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerIF.h b/DRAMSys/library/src/controller/scheduler/SchedulerIF.h index 7066c791..fbde3fdb 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerIF.h +++ b/DRAMSys/library/src/controller/scheduler/SchedulerIF.h @@ -49,7 +49,7 @@ public: virtual bool hasBufferSpace() const = 0; virtual void storeRequest(tlm::tlm_generic_payload *) = 0; virtual void removeRequest(tlm::tlm_generic_payload *) = 0; - virtual tlm::tlm_generic_payload *getNextRequest(BankMachine *) = 0; + virtual tlm::tlm_generic_payload *getNextRequest(BankMachine *) const = 0; virtual bool hasFurtherRowHit(Bank, Row) const = 0; virtual bool hasFurtherRequest(Bank) const = 0; virtual const std::vector &getBufferDepth() const = 0;