diff --git a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp
index 81fd0dba..a20c9e3e 100644
--- a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp
+++ b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp
@@ -167,315 +167,334 @@ void ConfigurationLoader::loadCommons(Configuration &config, XMLElement *memspec
     config.memSpec->MemoryType = queryStringParameter(memspec, "memoryType");
 }
 
-void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *memspec)
+void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *xmlSpec)
 {
-    //MemArchitecture
-    XMLElement *architecture = memspec->FirstChildElement("memarchitecturespec");
+    MemSpecDDR3 *memSpec = dynamic_cast<MemSpecDDR3 *>(config.memSpec);
+    if (memSpec == nullptr)
+        SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen");
 
-    config.memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks");
-  config.memSpec->NumberOfBankGroups = 1;
-    config.memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks");
-    config.memSpec->BurstLength = queryUIntParameter(architecture, "burstLength");
-  config.memSpec->nActivate = 4;
-    config.memSpec->DataRate = queryUIntParameter(architecture, "dataRate");
-    config.memSpec->NumberOfRows = queryUIntParameter(architecture, "nbrOfRows");
-    config.memSpec->NumberOfColumns = queryUIntParameter(architecture,
+    //MemArchitecture
+    XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec");
+
+    memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks");
+  memSpec->NumberOfBankGroups = 1;
+    memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks");
+    memSpec->BurstLength = queryUIntParameter(architecture, "burstLength");
+  memSpec->nActivate = 4;
+    memSpec->DataRate = queryUIntParameter(architecture, "dataRate");
+    memSpec->NumberOfRows = queryUIntParameter(architecture, "nbrOfRows");
+    memSpec->NumberOfColumns = queryUIntParameter(architecture,
                                                         "nbrOfColumns");
-    config.memSpec->bitWidth = queryUIntParameter(architecture, "width");
-  config.memSpec->DLL = true;
-  config.memSpec->termination = true;
+    memSpec->bitWidth = queryUIntParameter(architecture, "width");
+  memSpec->DLL = true;
+  memSpec->termination = true;
 
     //MemTimings
-    XMLElement *timings = memspec->FirstChildElement("memtimingspec");
-    config.memSpec->clkMHz = queryDoubleParameter(timings, "clkMhz");
-    config.memSpec->clk = FrequencyToClk(config.memSpec->clkMHz);
-    sc_time clk = config.memSpec->clk;
-    config.memSpec->tRP = clk * queryUIntParameter(timings, "RP");
-    config.memSpec->tRAS = clk * queryUIntParameter(timings, "RAS");
-    config.memSpec->tRC = clk * queryUIntParameter(timings, "RC");
-    config.memSpec->tRTP = clk * queryUIntParameter(timings, "RTP");
-  config.memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD");
-  config.memSpec->tRRD_L = clk * queryUIntParameter(timings, "RRD");
-  config.memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD");
-  config.memSpec->tCCD_L = clk * queryUIntParameter(timings, "CCD");
-    config.memSpec->tRCD = clk * queryUIntParameter(timings, "RCD");
-  config.memSpec->tNAW = clk * queryUIntParameter(timings, "FAW");
-    config.memSpec->tRL = clk * queryUIntParameter(timings, "RL");
-    config.memSpec->tWL = clk * queryUIntParameter(timings, "WL");
-    config.memSpec->tWR = clk * queryUIntParameter(timings, "WR");
-  config.memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR");
-  config.memSpec->tWTR_L = clk * queryUIntParameter(timings, "WTR");
-    config.memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR");
-    config.memSpec->tCKE = clk * queryUIntParameter(timings, "CKE");
-    config.memSpec->tXP = clk * queryUIntParameter(timings, "XP");
-    config.memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL");
-  config.memSpec->tXSR = clk * queryUIntParameter(timings, "XS");
-  config.memSpec->tXSRDLL = clk * queryUIntParameter(timings, "XSDLL");
-    config.memSpec->tAL = clk * queryUIntParameter(timings, "AL");
-    config.memSpec->tRFC = clk * queryUIntParameter(timings, "RFC");
-    config.memSpec->tREFI = clk * queryUIntParameter(timings, "REFI");
-    config.memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK");
+    XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec");
+    memSpec->clkMHz = queryDoubleParameter(timings, "clkMhz");
+    memSpec->clk = FrequencyToClk(memSpec->clkMHz);
+    sc_time clk = memSpec->clk;
+    memSpec->tRP = clk * queryUIntParameter(timings, "RP");
+    memSpec->tRAS = clk * queryUIntParameter(timings, "RAS");
+    memSpec->tRC = clk * queryUIntParameter(timings, "RC");
+    memSpec->tRTP = clk * queryUIntParameter(timings, "RTP");
+  memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD");
+  memSpec->tRRD_L = clk * queryUIntParameter(timings, "RRD");
+      memSpec->tRRD = clk * queryUIntParameter(timings, "RRD");
+  memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD");
+  memSpec->tCCD_L = clk * queryUIntParameter(timings, "CCD");
+      memSpec->tCCD = clk * queryUIntParameter(timings, "CCD");
+    memSpec->tRCD = clk * queryUIntParameter(timings, "RCD");
+  memSpec->tNAW = clk * queryUIntParameter(timings, "FAW");
+    memSpec->tRL = clk * queryUIntParameter(timings, "RL");
+    memSpec->tWL = clk * queryUIntParameter(timings, "WL");
+    memSpec->tWR = clk * queryUIntParameter(timings, "WR");
+  memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR");
+  memSpec->tWTR_L = clk * queryUIntParameter(timings, "WTR");
+      memSpec->tWTR = clk * queryUIntParameter(timings, "WTR");
+    memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR");
+    memSpec->tCKE = clk * queryUIntParameter(timings, "CKE");
+    memSpec->tXP = clk * queryUIntParameter(timings, "XP");
+    memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL");
+  memSpec->tXSR = clk * queryUIntParameter(timings, "XS");
+  memSpec->tXSRDLL = clk * queryUIntParameter(timings, "XSDLL");
+    memSpec->tAL = clk * queryUIntParameter(timings, "AL");
+    memSpec->tRFC = clk * queryUIntParameter(timings, "RFC");
+    memSpec->tREFI = clk * queryUIntParameter(timings, "REFI");
+    memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK");
 
-  config.memSpec->refreshTimings.clear();
-    for (unsigned int i = 0; i < config.memSpec->NumberOfBanks; ++i) {
-        config.memSpec->refreshTimings[Bank(i)] = RefreshTiming(config.memSpec->tRFC,
-                                                               config.memSpec->tREFI);
+  memSpec->refreshTimings.clear();
+    for (unsigned int i = 0; i < memSpec->NumberOfBanks; ++i) {
+        memSpec->refreshTimings[Bank(i)] = RefreshTiming(memSpec->tRFC,
+                                                               memSpec->tREFI);
     }
 
     // Currents and Volatages: TODO Check if this is correct.
-    XMLElement *powers = memspec->FirstChildElement("mempowerspec");
-    config.memSpec->iDD0    = queryDoubleParameter(powers, "idd0");
-  config.memSpec->iDD02   = 0;
-    config.memSpec->iDD2P0  = queryDoubleParameter(powers, "idd2p0");
-    config.memSpec->iDD2P1  = queryDoubleParameter(powers, "idd2p1");
-    config.memSpec->iDD2N   = queryDoubleParameter(powers, "idd2n");
-    config.memSpec->iDD3P0  = queryDoubleParameter(powers, "idd3p0");
-    config.memSpec->iDD3P1  = queryDoubleParameter(powers, "idd3p1");
-    config.memSpec->iDD3N   = queryDoubleParameter(powers, "idd3n");
-    config.memSpec->iDD4R   = queryDoubleParameter(powers, "idd4r");
-    config.memSpec->iDD4W   = queryDoubleParameter(powers, "idd4w");
-    config.memSpec->iDD5    = queryDoubleParameter(powers, "idd5");
-    config.memSpec->iDD6    = queryDoubleParameter(powers, "idd6");
-  config.memSpec->iDD62   = 0;
-    config.memSpec->vDD     = queryDoubleParameter(powers, "vdd");
-  config.memSpec->vDD2    = 0;
+    XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec");
+    memSpec->iDD0    = queryDoubleParameter(powers, "idd0");
+  memSpec->iDD02   = 0;
+    memSpec->iDD2P0  = queryDoubleParameter(powers, "idd2p0");
+    memSpec->iDD2P1  = queryDoubleParameter(powers, "idd2p1");
+    memSpec->iDD2N   = queryDoubleParameter(powers, "idd2n");
+    memSpec->iDD3P0  = queryDoubleParameter(powers, "idd3p0");
+    memSpec->iDD3P1  = queryDoubleParameter(powers, "idd3p1");
+    memSpec->iDD3N   = queryDoubleParameter(powers, "idd3n");
+    memSpec->iDD4R   = queryDoubleParameter(powers, "idd4r");
+    memSpec->iDD4W   = queryDoubleParameter(powers, "idd4w");
+    memSpec->iDD5    = queryDoubleParameter(powers, "idd5");
+    memSpec->iDD6    = queryDoubleParameter(powers, "idd6");
+  memSpec->iDD62   = 0;
+    memSpec->vDD     = queryDoubleParameter(powers, "vdd");
+  memSpec->vDD2    = 0;
 }
 
-void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *memspec)
+void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec)
 {
-    //MemArchitecture
-    XMLElement *architecture = memspec->FirstChildElement("memarchitecturespec");
+    MemSpecDDR4 *memSpec = dynamic_cast<MemSpecDDR4 *>(config.memSpec);
+    if (memSpec == nullptr)
+        SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen");
 
-    config.memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks");
-    config.memSpec->NumberOfBankGroups = queryUIntParameter(architecture,
+    //MemArchitecture
+    XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec");
+
+    memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks");
+    memSpec->NumberOfBankGroups = queryUIntParameter(architecture,
                                                            "nbrOfBankGroups");
-    config.memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks");
-    config.memSpec->BurstLength = queryUIntParameter(architecture, "burstLength");
-  config.memSpec->nActivate = 4;
-    config.memSpec->DataRate = queryUIntParameter(architecture, "dataRate");
-    config.memSpec->NumberOfRows = queryUIntParameter(architecture, "nbrOfRows");
-    config.memSpec->NumberOfColumns = queryUIntParameter(architecture,
+    memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks");
+    memSpec->BurstLength = queryUIntParameter(architecture, "burstLength");
+  memSpec->nActivate = 4;
+    memSpec->DataRate = queryUIntParameter(architecture, "dataRate");
+    memSpec->NumberOfRows = queryUIntParameter(architecture, "nbrOfRows");
+    memSpec->NumberOfColumns = queryUIntParameter(architecture,
                                                         "nbrOfColumns");
-    config.memSpec->bitWidth = queryUIntParameter(architecture, "width");
-  config.memSpec->DLL = true;
-  config.memSpec->termination = true;
+    memSpec->bitWidth = queryUIntParameter(architecture, "width");
+  memSpec->DLL = true;
+  memSpec->termination = true;
 
     //MemTimings
-    XMLElement *timings = memspec->FirstChildElement("memtimingspec");
-    config.memSpec->clkMHz = queryDoubleParameter(timings, "clkMhz");
-    config.memSpec->clk = FrequencyToClk(config.memSpec->clkMHz);
-    sc_time clk = config.memSpec->clk;
-    config.memSpec->tRP = clk * queryUIntParameter(timings, "RP");
-    config.memSpec->tRAS = clk * queryUIntParameter(timings, "RAS");
-    config.memSpec->tRC = clk * queryUIntParameter(timings, "RC");
-    config.memSpec->tRTP = clk * queryUIntParameter(timings, "RTP");
-    config.memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD_S");
-    config.memSpec->tRRD_L = clk * queryUIntParameter(timings, "RRD_L");
-    config.memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD_S");
-    config.memSpec->tCCD_L = clk * queryUIntParameter(timings, "CCD_L");
-    config.memSpec->tRCD = clk * queryUIntParameter(timings, "RCD");
-  config.memSpec->tNAW = clk * queryUIntParameter(timings, "FAW");
-    config.memSpec->tRL = clk * queryUIntParameter(timings, "RL");
-    config.memSpec->tWL = clk * queryUIntParameter(timings, "WL");
-    config.memSpec->tWR = clk * queryUIntParameter(timings, "WR");
-    config.memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR_S");
-    config.memSpec->tWTR_L = clk * queryUIntParameter(timings, "WTR_L");
-    config.memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR");
-    config.memSpec->tCKE = clk * queryUIntParameter(timings, "CKE");
-    config.memSpec->tXP = clk * queryUIntParameter(timings, "XP");
-    config.memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL");
-  config.memSpec->tXSR = clk * queryUIntParameter(timings, "XS");
-  config.memSpec->tXSRDLL = clk * queryUIntParameter(timings, "XSDLL");
-    config.memSpec->tAL = clk * queryUIntParameter(timings, "AL");
-    config.memSpec->tRFC = clk * queryUIntParameter(timings, "RFC");
-    config.memSpec->tRFC2 = clk * queryUIntParameter(timings, "RFC2");
-    config.memSpec->tRFC4 = clk * queryUIntParameter(timings, "RFC4");
-    config.memSpec->tREFI = clk * queryUIntParameter(timings, "REFI");
-    config.memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK");
+    XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec");
+    memSpec->clkMHz = queryDoubleParameter(timings, "clkMhz");
+    memSpec->clk = FrequencyToClk(memSpec->clkMHz);
+    sc_time clk = memSpec->clk;
+    memSpec->tRP = clk * queryUIntParameter(timings, "RP");
+    memSpec->tRAS = clk * queryUIntParameter(timings, "RAS");
+    memSpec->tRC = clk * queryUIntParameter(timings, "RC");
+    memSpec->tRTP = clk * queryUIntParameter(timings, "RTP");
+    memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD_S");
+    memSpec->tRRD_L = clk * queryUIntParameter(timings, "RRD_L");
+    memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD_S");
+    memSpec->tCCD_L = clk * queryUIntParameter(timings, "CCD_L");
+    memSpec->tRCD = clk * queryUIntParameter(timings, "RCD");
+  memSpec->tNAW = clk * queryUIntParameter(timings, "FAW");
+    memSpec->tRL = clk * queryUIntParameter(timings, "RL");
+    memSpec->tWL = clk * queryUIntParameter(timings, "WL");
+    memSpec->tWR = clk * queryUIntParameter(timings, "WR");
+    memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR_S");
+    memSpec->tWTR_L = clk * queryUIntParameter(timings, "WTR_L");
+    memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR");
+    memSpec->tCKE = clk * queryUIntParameter(timings, "CKE");
+    memSpec->tXP = clk * queryUIntParameter(timings, "XP");
+    memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL");
+  memSpec->tXSR = clk * queryUIntParameter(timings, "XS");
+  memSpec->tXSRDLL = clk * queryUIntParameter(timings, "XSDLL");
+    memSpec->tAL = clk * queryUIntParameter(timings, "AL");
+    memSpec->tRFC = clk * queryUIntParameter(timings, "RFC");
+    memSpec->tRFC2 = clk * queryUIntParameter(timings, "RFC2");
+    memSpec->tRFC4 = clk * queryUIntParameter(timings, "RFC4");
+    memSpec->tREFI = clk * queryUIntParameter(timings, "REFI");
+    memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK");
 
-    config.memSpec->refreshTimings.clear();
-    for (unsigned int i = 0; i < config.memSpec->NumberOfBanks; ++i) {
-        config.memSpec->refreshTimings[Bank(i)] = RefreshTiming(config.memSpec->tRFC,
-                                                               config.memSpec->tRFC2,
-                                                               config.memSpec->tRFC4,
-                                                               config.memSpec->tREFI);
+    memSpec->refreshTimings.clear();
+    for (unsigned int i = 0; i < memSpec->NumberOfBanks; ++i) {
+        memSpec->refreshTimings[Bank(i)] = RefreshTiming(memSpec->tRFC,
+                                                               memSpec->tRFC2,
+                                                               memSpec->tRFC4,
+                                                               memSpec->tREFI);
     }
 
     // Currents and Volatages:
-    XMLElement *powers = memspec->FirstChildElement("mempowerspec");
-    config.memSpec->iDD0    = queryDoubleParameter(powers, "idd0");
-    config.memSpec->iDD02   = queryDoubleParameter(powers, "idd02");
-    config.memSpec->iDD2P0  = queryDoubleParameter(powers, "idd2p0");
-    config.memSpec->iDD2P1  = queryDoubleParameter(powers, "idd2p1");
-    config.memSpec->iDD2N   = queryDoubleParameter(powers, "idd2n");
-    config.memSpec->iDD3P0  = queryDoubleParameter(powers, "idd3p0");
-    config.memSpec->iDD3P1  = queryDoubleParameter(powers, "idd3p1");
-    config.memSpec->iDD3N   = queryDoubleParameter(powers, "idd3n");
-    config.memSpec->iDD4R   = queryDoubleParameter(powers, "idd4r");
-    config.memSpec->iDD4W   = queryDoubleParameter(powers, "idd4w");
-    config.memSpec->iDD5    = queryDoubleParameter(powers, "idd5");
-    config.memSpec->iDD6    = queryDoubleParameter(powers, "idd6");
-    config.memSpec->iDD62   = queryDoubleParameter(powers, "idd62");
-    config.memSpec->vDD     = queryDoubleParameter(powers, "vdd");
-    config.memSpec->vDD2    = queryDoubleParameter(powers, "vdd2");
+    XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec");
+    memSpec->iDD0    = queryDoubleParameter(powers, "idd0");
+    memSpec->iDD02   = queryDoubleParameter(powers, "idd02");
+    memSpec->iDD2P0  = queryDoubleParameter(powers, "idd2p0");
+    memSpec->iDD2P1  = queryDoubleParameter(powers, "idd2p1");
+    memSpec->iDD2N   = queryDoubleParameter(powers, "idd2n");
+    memSpec->iDD3P0  = queryDoubleParameter(powers, "idd3p0");
+    memSpec->iDD3P1  = queryDoubleParameter(powers, "idd3p1");
+    memSpec->iDD3N   = queryDoubleParameter(powers, "idd3n");
+    memSpec->iDD4R   = queryDoubleParameter(powers, "idd4r");
+    memSpec->iDD4W   = queryDoubleParameter(powers, "idd4w");
+    memSpec->iDD5    = queryDoubleParameter(powers, "idd5");
+    memSpec->iDD6    = queryDoubleParameter(powers, "idd6");
+    memSpec->iDD62   = queryDoubleParameter(powers, "idd62");
+    memSpec->vDD     = queryDoubleParameter(powers, "vdd");
+    memSpec->vDD2    = queryDoubleParameter(powers, "vdd2");
 }
 
 // TODO: change timings for LPDDR4
-void ConfigurationLoader::loadLPDDR4(Configuration &config, XMLElement *memspec)
+void ConfigurationLoader::loadLPDDR4(Configuration &config, XMLElement *xmlSpec)
 {
-    //MemArchitecture:
-    XMLElement *architecture = memspec->FirstChildElement("memarchitecturespec");
+    MemSpecLPDDR4 *memSpec = dynamic_cast<MemSpecLPDDR4 *>(config.memSpec);
+    if (memSpec == nullptr)
+        SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen");
 
-    config.memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks");
-  config.memSpec->NumberOfBankGroups = 1;
-    config.memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks");
-    config.memSpec->BurstLength = queryUIntParameter(architecture, "burstLength");
-  config.memSpec->nActivate = 4;
-    config.memSpec->DataRate = queryUIntParameter(architecture, "dataRate");
-    config.memSpec->NumberOfRows = queryUIntParameter(architecture, "nbrOfRows");
-    config.memSpec->NumberOfColumns = queryUIntParameter(architecture,
+    //MemArchitecture:
+    XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec");
+
+    memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks");
+  memSpec->NumberOfBankGroups = 1;
+    memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks");
+    memSpec->BurstLength = queryUIntParameter(architecture, "burstLength");
+  memSpec->nActivate = 4;
+    memSpec->DataRate = queryUIntParameter(architecture, "dataRate");
+    memSpec->NumberOfRows = queryUIntParameter(architecture, "nbrOfRows");
+    memSpec->NumberOfColumns = queryUIntParameter(architecture,
                                                         "nbrOfColumns");
-    config.memSpec->bitWidth = queryUIntParameter(architecture, "width");
-  config.memSpec->DLL = false; // TODO: Correct?
-  config.memSpec->termination = true; // TODO: Correct?
+    memSpec->bitWidth = queryUIntParameter(architecture, "width");
+  memSpec->DLL = false; // TODO: Correct?
+  memSpec->termination = true; // TODO: Correct?
 
     //MemTimings
-    XMLElement *timings = memspec->FirstChildElement("memtimingspec");
-    config.memSpec->clkMHz = queryDoubleParameter(timings, "clkMhz");
-    config.memSpec->clk = FrequencyToClk(config.memSpec->clkMHz);
-    sc_time clk = config.memSpec->clk;
-  config.memSpec->tRP = clk * queryUIntParameter(timings, "RPPB");
-    config.memSpec->tRPAB = clk * queryUIntParameter(timings, "RPAB");
-    config.memSpec->tRAS = clk * queryUIntParameter(timings, "RAS");
-    config.memSpec->tRC = clk * queryUIntParameter(timings, "RC");
-    config.memSpec->tRTP = clk * queryUIntParameter(timings, "RTP");
-  config.memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD");
-  config.memSpec->tRRD_L = clk * queryUIntParameter(timings, "RRD");
-  config.memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD");
-  config.memSpec->tCCD_L = clk * queryUIntParameter(timings, "CCD");
-    config.memSpec->tRCD = clk * queryUIntParameter(timings, "RCD");
-  config.memSpec->tNAW = clk * queryUIntParameter(timings, "FAW");
-    config.memSpec->tRL = clk * queryUIntParameter(timings, "RL");
-    config.memSpec->tWL = clk * queryUIntParameter(timings, "WL");
-    config.memSpec->tWR = clk * queryUIntParameter(timings, "WR");
-  config.memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR");
-  config.memSpec->tWTR_L = clk * queryUIntParameter(timings, "WTR");
-    config.memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR");
-    config.memSpec->tCKE = clk * queryUIntParameter(timings, "CKE");
-    config.memSpec->tXP = clk * queryUIntParameter(timings, "XP");
-  config.memSpec->tXPDLL = clk * queryUIntParameter(timings, "XP");
-  config.memSpec->tXSR = clk * queryUIntParameter(timings, "XS");
-  config.memSpec->tXSRDLL = clk * queryUIntParameter(timings, "XS");
-    config.memSpec->tAL = clk * queryUIntParameter(timings, "AL");
-  config.memSpec->tRFC = clk * queryUIntParameter(timings, "RFCAB");
-  // TODO: config.memSpec->tRFCPB = clk * queryUIntParameter(timings, "RFCPB");
-  config.memSpec->tREFI = clk * queryUIntParameter(timings, "REFIAB");
-  // TODO: config.memSpec->tREFIPB = clk * queryUIntParameter(timings, "RFCPB");
-    config.memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK");
+    XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec");
+    memSpec->clkMHz = queryDoubleParameter(timings, "clkMhz");
+    memSpec->clk = FrequencyToClk(memSpec->clkMHz);
+    sc_time clk = memSpec->clk;
+  memSpec->tRP = clk * queryUIntParameter(timings, "RPPB");
+    memSpec->tRPAB = clk * queryUIntParameter(timings, "RPAB");
+    memSpec->tRAS = clk * queryUIntParameter(timings, "RAS");
+    memSpec->tRC = clk * queryUIntParameter(timings, "RC");
+    memSpec->tRTP = clk * queryUIntParameter(timings, "RTP");
+  memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD");
+  memSpec->tRRD_L = clk * queryUIntParameter(timings, "RRD");
+  memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD");
+  memSpec->tCCD_L = clk * queryUIntParameter(timings, "CCD");
+    memSpec->tRCD = clk * queryUIntParameter(timings, "RCD");
+  memSpec->tNAW = clk * queryUIntParameter(timings, "FAW");
+    memSpec->tRL = clk * queryUIntParameter(timings, "RL");
+    memSpec->tWL = clk * queryUIntParameter(timings, "WL");
+    memSpec->tWR = clk * queryUIntParameter(timings, "WR");
+  memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR");
+  memSpec->tWTR_L = clk * queryUIntParameter(timings, "WTR");
+    memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR");
+    memSpec->tCKE = clk * queryUIntParameter(timings, "CKE");
+    memSpec->tXP = clk * queryUIntParameter(timings, "XP");
+  memSpec->tXPDLL = clk * queryUIntParameter(timings, "XP");
+  memSpec->tXSR = clk * queryUIntParameter(timings, "XS");
+  memSpec->tXSRDLL = clk * queryUIntParameter(timings, "XS");
+    memSpec->tAL = clk * queryUIntParameter(timings, "AL");
+  memSpec->tRFC = clk * queryUIntParameter(timings, "RFCAB");
+  // TODO: memSpec->tRFCPB = clk * queryUIntParameter(timings, "RFCPB");
+  memSpec->tREFI = clk * queryUIntParameter(timings, "REFIAB");
+  // TODO: memSpec->tREFIPB = clk * queryUIntParameter(timings, "RFCPB");
+    memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK");
 
-  config.memSpec->refreshTimings.clear();
-    for (unsigned int i = 0; i < config.memSpec->NumberOfBanks; ++i) {
-        config.memSpec->refreshTimings[Bank(i)] = RefreshTiming(config.memSpec->tRFC,
-                                                               config.memSpec->tREFI);
+  memSpec->refreshTimings.clear();
+    for (unsigned int i = 0; i < memSpec->NumberOfBanks; ++i) {
+        memSpec->refreshTimings[Bank(i)] = RefreshTiming(memSpec->tRFC,
+                                                               memSpec->tREFI);
     }
 
     // Currents and Volatages:
-    XMLElement *powers = memspec->FirstChildElement("mempowerspec");
-    config.memSpec->iDD0    = queryDoubleParameter(powers, "idd0");
-    config.memSpec->iDD02   = queryDoubleParameter(powers, "idd02");
-  config.memSpec->iDD2P0  = queryDoubleParameter(powers, "idd2p");
-  config.memSpec->iDD2P1  = queryDoubleParameter(powers, "idd2p2");
-    config.memSpec->iDD2N   = queryDoubleParameter(powers, "idd2n");
-  config.memSpec->iDD3P0  = queryDoubleParameter(powers, "idd3p");
-  config.memSpec->iDD3P1  = queryDoubleParameter(powers, "idd3p2");
-    config.memSpec->iDD3N   = queryDoubleParameter(powers, "idd3n");
-    config.memSpec->iDD4R   = queryDoubleParameter(powers, "idd4r");
-    config.memSpec->iDD4W   = queryDoubleParameter(powers, "idd4w");
-    config.memSpec->iDD5    = queryDoubleParameter(powers, "idd5");
-    config.memSpec->iDD6    = queryDoubleParameter(powers, "idd6");
-    config.memSpec->iDD62   = queryDoubleParameter(powers, "idd62");
-    config.memSpec->vDD     = queryDoubleParameter(powers, "vdd");
-    config.memSpec->vDD2    = queryDoubleParameter(powers, "vdd2");
+    XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec");
+    memSpec->iDD0    = queryDoubleParameter(powers, "idd0");
+    memSpec->iDD02   = queryDoubleParameter(powers, "idd02");
+  memSpec->iDD2P0  = queryDoubleParameter(powers, "idd2p");
+  memSpec->iDD2P1  = queryDoubleParameter(powers, "idd2p2");
+    memSpec->iDD2N   = queryDoubleParameter(powers, "idd2n");
+  memSpec->iDD3P0  = queryDoubleParameter(powers, "idd3p");
+  memSpec->iDD3P1  = queryDoubleParameter(powers, "idd3p2");
+    memSpec->iDD3N   = queryDoubleParameter(powers, "idd3n");
+    memSpec->iDD4R   = queryDoubleParameter(powers, "idd4r");
+    memSpec->iDD4W   = queryDoubleParameter(powers, "idd4w");
+    memSpec->iDD5    = queryDoubleParameter(powers, "idd5");
+    memSpec->iDD6    = queryDoubleParameter(powers, "idd6");
+    memSpec->iDD62   = queryDoubleParameter(powers, "idd62");
+    memSpec->vDD     = queryDoubleParameter(powers, "vdd");
+    memSpec->vDD2    = queryDoubleParameter(powers, "vdd2");
 }
 
 void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *memspec)
 {
+    MemSpecWideIO *memSpec = dynamic_cast<MemSpecWideIO *>(config.memSpec);
+    if (memSpec == nullptr)
+        SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen");
+
     //MemSpecification
     XMLElement *architecture = memspec->FirstChildElement("memarchitecturespec");
 
-    config.memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks");
-  config.memSpec->NumberOfBankGroups = 1;
-  config.memSpec->NumberOfRanks = 1;
-    config.memSpec->BurstLength = queryUIntParameter(architecture, "burstLength");
-  config.memSpec->nActivate = 2;
-    config.memSpec->DataRate = queryUIntParameter(architecture, "dataRate");
-    config.memSpec->NumberOfRows = queryUIntParameter(architecture, "nbrOfRows");
-    config.memSpec->NumberOfColumns = queryUIntParameter(architecture,
+    memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks");
+  memSpec->NumberOfBankGroups = 1;
+  memSpec->NumberOfRanks = 1;
+    memSpec->BurstLength = queryUIntParameter(architecture, "burstLength");
+  memSpec->nActivate = 2;
+    memSpec->DataRate = queryUIntParameter(architecture, "dataRate");
+    memSpec->NumberOfRows = queryUIntParameter(architecture, "nbrOfRows");
+    memSpec->NumberOfColumns = queryUIntParameter(architecture,
                                                         "nbrOfColumns");
-    config.memSpec->bitWidth = queryUIntParameter(architecture, "width");
-  config.memSpec->DLL = false;
-  config.memSpec->termination = false;
+    memSpec->bitWidth = queryUIntParameter(architecture, "width");
+  memSpec->DLL = false;
+  memSpec->termination = false;
 
     //MemTimings
     XMLElement *timings = memspec->FirstChildElement("memtimingspec");
-    config.memSpec->clkMHz = queryDoubleParameter(timings, "clkMhz");
-    config.memSpec->clk = FrequencyToClk(config.memSpec->clkMHz);
-    sc_time clk = config.memSpec->clk;
-    config.memSpec->tRP = clk * queryUIntParameter(timings, "RP");
-    config.memSpec->tRAS = clk * queryUIntParameter(timings, "RAS");
-    config.memSpec->tRC = clk * queryUIntParameter(timings, "RC");
-  config.memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD");
-  config.memSpec->tRRD_L = config.memSpec->tRRD_S;
-  config.memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD");
-  config.memSpec->tCCD_L = config.memSpec->tCCD_S;
-    config.memSpec->tRCD = clk * queryUIntParameter(timings, "RCD");
-  config.memSpec->tNAW = clk * queryUIntParameter(timings, "TAW");
-    config.memSpec->tRL = clk * queryUIntParameter(timings, "RL");
-    config.memSpec->tWL = clk * queryUIntParameter(timings, "WL");
-    config.memSpec->tWR = clk * queryUIntParameter(timings, "WR");
-  config.memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR");
-  config.memSpec->tWTR_L = config.memSpec->tWTR_S;
-    config.memSpec->tRTP = clk * queryUIntParameter(timings, "RTP");
-    config.memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR");
-    config.memSpec->tCKE = clk * queryUIntParameter(timings, "CKE");
-    config.memSpec->tXP = clk * queryUIntParameter(timings, "XP");
-  config.memSpec->tXPDLL = config.memSpec->tXP;
-  config.memSpec->tXSR = clk * queryUIntParameter(timings, "XS");
-  config.memSpec->tXSRDLL = config.memSpec->tXSR;
-  config.memSpec->tAL = clk * queryUIntParameter(timings, "AL");
-  config.memSpec->tRFC = clk * queryUIntParameter(timings, "RFC");
-  config.memSpec->tREFI = clk * queryUIntParameter(timings, "REFI");
+    memSpec->clkMHz = queryDoubleParameter(timings, "clkMhz");
+    memSpec->clk = FrequencyToClk(memSpec->clkMHz);
+    sc_time clk = memSpec->clk;
+    memSpec->tRP = clk * queryUIntParameter(timings, "RP");
+    memSpec->tRAS = clk * queryUIntParameter(timings, "RAS");
+    memSpec->tRC = clk * queryUIntParameter(timings, "RC");
+  memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD");
+  memSpec->tRRD_L = memSpec->tRRD_S;
+  memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD");
+  memSpec->tCCD_L = memSpec->tCCD_S;
+    memSpec->tRCD = clk * queryUIntParameter(timings, "RCD");
+  memSpec->tNAW = clk * queryUIntParameter(timings, "TAW");
+    memSpec->tRL = clk * queryUIntParameter(timings, "RL");
+    memSpec->tWL = clk * queryUIntParameter(timings, "WL");
+    memSpec->tWR = clk * queryUIntParameter(timings, "WR");
+  memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR");
+  memSpec->tWTR_L = memSpec->tWTR_S;
+    memSpec->tRTP = clk * queryUIntParameter(timings, "RTP");
+    memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR");
+    memSpec->tCKE = clk * queryUIntParameter(timings, "CKE");
+    memSpec->tXP = clk * queryUIntParameter(timings, "XP");
+  memSpec->tXPDLL = memSpec->tXP;
+  memSpec->tXSR = clk * queryUIntParameter(timings, "XS");
+  memSpec->tXSRDLL = memSpec->tXSR;
+  memSpec->tAL = clk * queryUIntParameter(timings, "AL");
+  memSpec->tRFC = clk * queryUIntParameter(timings, "RFC");
+  memSpec->tREFI = clk * queryUIntParameter(timings, "REFI");
 
-  config.memSpec->refreshTimings.clear();
-    for (unsigned int i = 0; i < config.memSpec->NumberOfBanks; ++i) {
-        config.memSpec->refreshTimings[Bank(i)] = RefreshTiming(config.memSpec->tRFC,
-                                                               config.memSpec->tREFI);
+  memSpec->refreshTimings.clear();
+    for (unsigned int i = 0; i < memSpec->NumberOfBanks; ++i) {
+        memSpec->refreshTimings[Bank(i)] = RefreshTiming(memSpec->tRFC,
+                                                               memSpec->tREFI);
     }
 
     // Currents and Volatages:
     XMLElement *powers = memspec->FirstChildElement("mempowerspec");
-    config.memSpec->iDD0    = queryDoubleParameter(powers, "idd0");
-    config.memSpec->iDD02   = queryDoubleParameter(powers, "idd02");
-    config.memSpec->iDD2P0  = queryDoubleParameter(powers, "idd2p0");
-    config.memSpec->iDD2P02 = queryDoubleParameter(powers, "idd2p02");
-    config.memSpec->iDD2P1  = queryDoubleParameter(powers, "idd2p1");
-    config.memSpec->iDD2P12 = queryDoubleParameter(powers, "idd2p12");
-    config.memSpec->iDD2N   = queryDoubleParameter(powers, "idd2n");
-    config.memSpec->iDD2N2  = queryDoubleParameter(powers, "idd2n2");
-    config.memSpec->iDD3P0  = queryDoubleParameter(powers, "idd3p0");
-    config.memSpec->iDD3P02 = queryDoubleParameter(powers, "idd3p02");
-    config.memSpec->iDD3P1  = queryDoubleParameter(powers, "idd3p1");
-    config.memSpec->iDD3P12 = queryDoubleParameter(powers, "idd3p12");
-    config.memSpec->iDD3N   = queryDoubleParameter(powers, "idd3n");
-    config.memSpec->iDD3N2  = queryDoubleParameter(powers, "idd3n2");
-    config.memSpec->iDD4R   = queryDoubleParameter(powers, "idd4r");
-    config.memSpec->iDD4R2  = queryDoubleParameter(powers, "idd4r2");
-    config.memSpec->iDD4W   = queryDoubleParameter(powers, "idd4w");
-    config.memSpec->iDD4W2  = queryDoubleParameter(powers, "idd4w2");
-    config.memSpec->iDD5    = queryDoubleParameter(powers, "idd5");
-    config.memSpec->iDD52   = queryDoubleParameter(powers, "idd52");
-    config.memSpec->iDD6    = queryDoubleParameter(powers, "idd6");
-    config.memSpec->iDD62   = queryDoubleParameter(powers, "idd62");
-    config.memSpec->vDD     = queryDoubleParameter(powers, "vdd");
-    config.memSpec->vDD2    = queryDoubleParameter(powers, "vdd2");
+    memSpec->iDD0    = queryDoubleParameter(powers, "idd0");
+    memSpec->iDD02   = queryDoubleParameter(powers, "idd02");
+    memSpec->iDD2P0  = queryDoubleParameter(powers, "idd2p0");
+    memSpec->iDD2P02 = queryDoubleParameter(powers, "idd2p02");
+    memSpec->iDD2P1  = queryDoubleParameter(powers, "idd2p1");
+    memSpec->iDD2P12 = queryDoubleParameter(powers, "idd2p12");
+    memSpec->iDD2N   = queryDoubleParameter(powers, "idd2n");
+    memSpec->iDD2N2  = queryDoubleParameter(powers, "idd2n2");
+    memSpec->iDD3P0  = queryDoubleParameter(powers, "idd3p0");
+    memSpec->iDD3P02 = queryDoubleParameter(powers, "idd3p02");
+    memSpec->iDD3P1  = queryDoubleParameter(powers, "idd3p1");
+    memSpec->iDD3P12 = queryDoubleParameter(powers, "idd3p12");
+    memSpec->iDD3N   = queryDoubleParameter(powers, "idd3n");
+    memSpec->iDD3N2  = queryDoubleParameter(powers, "idd3n2");
+    memSpec->iDD4R   = queryDoubleParameter(powers, "idd4r");
+    memSpec->iDD4R2  = queryDoubleParameter(powers, "idd4r2");
+    memSpec->iDD4W   = queryDoubleParameter(powers, "idd4w");
+    memSpec->iDD4W2  = queryDoubleParameter(powers, "idd4w2");
+    memSpec->iDD5    = queryDoubleParameter(powers, "idd5");
+    memSpec->iDD52   = queryDoubleParameter(powers, "idd52");
+    memSpec->iDD6    = queryDoubleParameter(powers, "idd6");
+    memSpec->iDD62   = queryDoubleParameter(powers, "idd62");
+    memSpec->vDD     = queryDoubleParameter(powers, "vdd");
+    memSpec->vDD2    = queryDoubleParameter(powers, "vdd2");
 }
diff --git a/DRAMSys/library/src/controller/core/configuration/MemSpec.h b/DRAMSys/library/src/controller/core/configuration/MemSpec.h
index 28503d19..a4ab8da5 100644
--- a/DRAMSys/library/src/controller/core/configuration/MemSpec.h
+++ b/DRAMSys/library/src/controller/core/configuration/MemSpec.h
@@ -168,7 +168,9 @@ struct MemSpec
 
 struct MemSpecDDR3 : public MemSpec
 {
-
+    sc_time tCCD;
+    sc_time tRRD;
+    sc_time tWTR;
 };
 
 struct MemSpecDDR4 : public MemSpec
diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp
index e5d06288..cc851250 100644
--- a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp
+++ b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp
@@ -45,7 +45,7 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const
                 break;
             case Command::SREFX:
                 command.establishMinDistanceFromStart(lastCommandOnBank.getStart(),
-                                                      memSpec->tXS);
+                                                      memSpec->tXSR);
                 break;
             case Command::AutoRefresh:
                 command.establishMinDistanceFromStart(lastCommandOnBank.getStart(),
@@ -207,7 +207,7 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const
                     break;
                 case Command::SREFX:
                     command.establishMinDistanceFromStart(lastCommand.getStart(),
-                                                          memSpec->tXS);
+                                                          memSpec->tXSR);
                     break;
                 case Command::AutoRefresh:
                     command.establishMinDistanceFromStart(lastCommand.getStart(),
@@ -263,7 +263,7 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const
                 break;
             case Command::SREFX:
                 command.establishMinDistanceFromStart(lastCommandOnBank.getStart(),
-                                                      memSpec->tXS);
+                                                      memSpec->tXSR);
                 break;
             default:
                 reportFatal("Checker DDR3", commandToString(NextCmd) + " can not follow "
@@ -325,7 +325,7 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const
                     break;
                 case Command::SREFX:
                     command.establishMinDistanceFromStart(lastCommandOnBank.getStart(),
-                                                          memSpec->tXS);
+                                                          memSpec->tXSR);
                     break;
                 default:
                     reportFatal("Checker DDR3",
@@ -372,7 +372,7 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const
                         break;
                     case Command::SREFX:
                         command.establishMinDistanceFromStart(lastCommand.getStart(),
-                                                              memSpec->tXS);
+                                                              memSpec->tXSR);
                         break;
                     default:
                         reportFatal("Checker DDR3",
@@ -480,7 +480,7 @@ void CheckerDDR3::delayToSatisfyDLL(ScheduledCommand &read) const
 {
     ScheduledCommand lastSREFX = state.getLastCommand(Command::SREFX, read.getBank());
     if (lastSREFX.isValidCommand())
-        read.establishMinDistanceFromStart(lastSREFX.getStart(), memSpec->tXSDLL);
+        read.establishMinDistanceFromStart(lastSREFX.getStart(), memSpec->tXSRDLL);
 }
 
 
@@ -489,10 +489,7 @@ sc_time CheckerDDR3::writeToRead(ScheduledCommand &write, ScheduledCommand &read
     sc_assert(read.getCommand() == Command::Read || read.getCommand() == Command::ReadA);
     sc_assert(write.getCommand() == Command::Write || write.getCommand() == Command::WriteA);
 
-    if (write.getBankGroup() == read.getBankGroup())
-    {
-        return memSpec->tWL + getWriteAccessTime() + memSpec->tWTR;
-    }
+    return memSpec->tWL + getWriteAccessTime() + memSpec->tWTR;
 }
 
 /* CAS-CAS */
@@ -502,19 +499,15 @@ sc_time CheckerDDR3::CasToCas(ScheduledCommand &firstCAS, ScheduledCommand &seco
     if (firstCAS.getCommand() == Command::Read || firstCAS.getCommand() == Command::ReadA)
     {
         if (secondCAS.getCommand() == Command::Read || secondCAS.getCommand() == Command::ReadA)
-        {
-            if (firstCAS.getBankGroup() == secondCAS.getBankGroup())
-                return std::max(memSpec->tCCD, getReadAccessTime());
-        }
+            return std::max(memSpec->tCCD, getReadAccessTime());
     }
     else if (firstCAS.getCommand() == Command::Write || firstCAS.getCommand() == Command::WriteA)
     {
         if (secondCAS.getCommand() == Command::Write || secondCAS.getCommand() == Command::WriteA)
-        {
-            if (firstCAS.getBankGroup() == secondCAS.getBankGroup())
-                return std::max(memSpec->tCCD, getWriteAccessTime());
-        }
+            return std::max(memSpec->tCCD, getWriteAccessTime());
     }
+    SC_REPORT_FATAL("CasToCas", "Exception reached");
+    return SC_ZERO_TIME;
 }
 
 /*
diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.h b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.h
index dde7204d..55e8c299 100644
--- a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.h
+++ b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.h
@@ -14,7 +14,7 @@ public:
     {
         memSpec = dynamic_cast<MemSpecDDR3 *>(Configuration::getInstance().memSpec);
         if (memSpec == nullptr)
-            SC_REPORT_FATAL("CheckerDDR3", "Wrong MemSpec chosen.");
+            SC_REPORT_FATAL("CheckerDDR3", "Wrong MemSpec chosen");
     }
     virtual ~CheckerDDR3() {}