From c07d09f392bb5818f2e4d8b2f2c25cfcde68479c Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Tue, 29 Aug 2023 09:26:25 +0200 Subject: [PATCH] Format all files --- .../businessObjects/commentmodel.cpp | 147 +- .../businessObjects/commentmodel.h | 51 +- .../businessObjects/configmodels.cpp | 78 +- .../businessObjects/configmodels.h | 38 +- .../businessObjects/dependencymodels.cpp | 56 +- .../businessObjects/dependencymodels.h | 36 +- .../common/QStringComparator.cpp | 6 +- .../common/QStringComparator.h | 3 +- .../common/StringMapper.cpp | 65 +- .../common/StringMapper.h | 120 +- .../dramTimeDependencies/common/common.h | 14 +- .../common/timedependency.h | 36 +- .../configurations/configurationBase.cpp | 33 +- .../configurations/configurationBase.h | 34 +- .../configurations/configurationfactory.cpp | 133 +- .../configurations/configurationfactory.h | 5 +- .../specialized/DDR3Configuration.cpp | 27 +- .../specialized/DDR3Configuration.h | 11 +- .../specialized/DDR4Configuration.cpp | 20 +- .../specialized/DDR4Configuration.h | 8 +- .../specialized/DDR5Configuration.cpp | 30 +- .../specialized/DDR5Configuration.h | 8 +- .../specialized/HBM2Configuration.cpp | 24 +- .../specialized/HBM2Configuration.h | 8 +- .../specialized/LPDDR4Configuration.cpp | 27 +- .../specialized/LPDDR4Configuration.h | 8 +- .../specialized/LPDDR5Configuration.cpp | 27 +- .../specialized/LPDDR5Configuration.h | 8 +- .../dbEntries/dbphaseentryBase.h | 15 +- .../specialized/DDR3dbphaseentry.cpp | 34 +- .../dbEntries/specialized/DDR3dbphaseentry.h | 8 +- .../specialized/DDR4dbphaseentry.cpp | 43 +- .../dbEntries/specialized/DDR4dbphaseentry.h | 8 +- .../specialized/DDR5dbphaseentry.cpp | 62 +- .../dbEntries/specialized/DDR5dbphaseentry.h | 8 +- .../specialized/HBM2dbphaseentry.cpp | 43 +- .../dbEntries/specialized/HBM2dbphaseentry.h | 8 +- .../specialized/LPDDR4dbphaseentry.cpp | 34 +- .../specialized/LPDDR4dbphaseentry.h | 8 +- .../specialized/LPDDR5dbphaseentry.cpp | 67 +- .../specialized/LPDDR5dbphaseentry.h | 8 +- .../dramtimedependenciesbase.cpp | 134 +- .../dramtimedependenciesbase.h | 27 +- .../deviceDependencies/poolcontroller.cpp | 60 +- .../deviceDependencies/poolcontroller.h | 5 +- .../deviceDependencies/poolcontrollermap.cpp | 62 +- .../deviceDependencies/poolcontrollermap.h | 5 +- .../specialized/DDR3TimeDependencies.cpp | 461 ++--- .../specialized/DDR3TimeDependencies.h | 6 +- .../specialized/TimeDependenciesInfoDDR3.cpp | 595 +++--- .../specialized/TimeDependenciesInfoDDR3.h | 10 +- .../specialized/TimeDependenciesInfoDDR4.cpp | 657 +++---- .../specialized/TimeDependenciesInfoDDR4.h | 10 +- .../specialized/TimeDependenciesInfoDDR5.cpp | 1656 +++++++++++------ .../specialized/TimeDependenciesInfoDDR5.h | 10 +- .../specialized/TimeDependenciesInfoHBM2.cpp | 670 +++---- .../specialized/TimeDependenciesInfoHBM2.h | 10 +- .../TimeDependenciesInfoLPDDR4.cpp | 693 ++++--- .../specialized/TimeDependenciesInfoLPDDR4.h | 10 +- .../TimeDependenciesInfoLPDDR5.cpp | 956 ++++++---- .../specialized/TimeDependenciesInfoLPDDR5.h | 12 +- .../phasedependenciestracker.cpp | 282 +-- .../phasedependenciestracker.h | 27 +- .../businessObjects/generalinfo.h | 50 +- .../businessObjects/phases/dependencyinfos.h | 15 +- .../businessObjects/phases/phase.cpp | 129 +- .../businessObjects/phases/phase.h | 497 ++--- .../phases/phasedependency.cpp | 86 +- .../businessObjects/phases/phasedependency.h | 20 +- .../businessObjects/phases/phasefactory.cpp | 415 ++++- .../businessObjects/phases/phasefactory.h | 18 +- .../businessObjects/pythoncaller.cpp | 18 +- .../businessObjects/pythoncaller.h | 7 +- .../businessObjects/testresult.h | 24 +- .../businessObjects/timespan.cpp | 4 +- .../traceAnalyzer/businessObjects/timespan.h | 36 +- .../businessObjects/tracecalculatedmetrics.h | 23 +- .../businessObjects/traceplotlinemodel.cpp | 226 ++- .../businessObjects/traceplotlinemodel.h | 122 +- .../traceAnalyzer/businessObjects/tracetime.h | 4 +- .../businessObjects/transaction.cpp | 35 +- .../businessObjects/transaction.h | 34 +- .../apps/traceAnalyzer/data/QueryTexts.h | 28 +- .../apps/traceAnalyzer/data/tracedb.cpp | 265 +-- extensions/apps/traceAnalyzer/data/tracedb.h | 69 +- .../apps/traceAnalyzer/evaluationtool.cpp | 75 +- .../apps/traceAnalyzer/evaluationtool.h | 34 +- .../apps/traceAnalyzer/gototimedialog.cpp | 8 +- .../apps/traceAnalyzer/gototimedialog.h | 12 +- extensions/apps/traceAnalyzer/main.cpp | 24 +- .../apps/traceAnalyzer/markerplotitem.h | 15 +- .../presentation/debugmessagetreewidget.cpp | 54 +- .../presentation/debugmessagetreewidget.h | 32 +- .../selectedtransactiontreewidget.cpp | 11 +- .../selectedtransactiontreewidget.h | 11 +- .../presentation/tracePlotMouseLabel.cpp | 25 +- .../presentation/tracePlotMouseLabel.h | 35 +- .../presentation/tracedrawing.cpp | 63 +- .../traceAnalyzer/presentation/tracedrawing.h | 36 +- .../presentation/tracedrawingproperties.cpp | 17 +- .../presentation/tracedrawingproperties.h | 14 +- .../presentation/tracemetrictreewidget.cpp | 28 +- .../presentation/tracemetrictreewidget.h | 8 +- .../presentation/tracenavigator.cpp | 61 +- .../presentation/tracenavigator.h | 49 +- .../traceAnalyzer/presentation/traceplot.cpp | 418 +++-- .../traceAnalyzer/presentation/traceplot.h | 129 +- .../presentation/traceplotitem.cpp | 21 +- .../presentation/traceplotitem.h | 39 +- .../presentation/tracescroller.cpp | 190 +- .../presentation/tracescroller.h | 21 +- .../presentation/transactiontreewidget.cpp | 55 +- .../presentation/transactiontreewidget.h | 29 +- .../presentation/util/clkgrid.cpp | 26 +- .../traceAnalyzer/presentation/util/clkgrid.h | 11 +- .../presentation/util/colorgenerator.cpp | 22 +- .../presentation/util/colorgenerator.h | 3 +- .../presentation/util/colorobject.cpp | 3 +- .../presentation/util/colorobject.h | 5 +- .../util/customlabelscaledraw.cpp | 8 +- .../presentation/util/customlabelscaledraw.h | 8 +- .../presentation/util/engineeringScaleDraw.h | 4 +- .../presentation/util/testlight.cpp | 5 +- .../presentation/util/testlight.h | 7 +- .../util/togglecollapsedaction.cpp | 26 +- .../presentation/util/togglecollapsedaction.h | 8 +- extensions/apps/traceAnalyzer/queryeditor.cpp | 9 +- extensions/apps/traceAnalyzer/queryeditor.h | 13 +- .../apps/traceAnalyzer/selectmetrics.cpp | 48 +- extensions/apps/traceAnalyzer/selectmetrics.h | 16 +- .../apps/traceAnalyzer/simulationdialog.cpp | 46 +- .../apps/traceAnalyzer/simulationdialog.h | 12 +- .../apps/traceAnalyzer/traceanalyzer.cpp | 71 +- extensions/apps/traceAnalyzer/traceanalyzer.h | 43 +- .../apps/traceAnalyzer/tracefiletab.cpp | 286 +-- extensions/apps/traceAnalyzer/tracefiletab.h | 42 +- .../configuration/memspec/MemSpecDDR5.cpp | 199 +- .../configuration/memspec/MemSpecDDR5.h | 11 +- .../DDR5/DRAMSys/simulation/dram/DramDDR5.cpp | 3 +- .../configuration/memspec/MemSpecHBM3.cpp | 125 +- .../configuration/memspec/MemSpecHBM3.h | 15 +- .../HBM3/DRAMSys/simulation/dram/DramHBM3.cpp | 3 +- .../HBM3/DRAMSys/simulation/dram/DramHBM3.h | 2 +- .../configuration/memspec/MemSpecLPDDR5.cpp | 152 +- .../configuration/memspec/MemSpecLPDDR5.h | 36 +- .../DRAMSys/simulation/dram/DramLPDDR5.cpp | 3 +- .../DRAMSys/config/AddressMapping.h | 2 +- .../DRAMSys/config/DRAMSysConfiguration.cpp | 20 +- .../DRAMSys/config/DRAMSysConfiguration.h | 15 +- src/configuration/DRAMSys/config/McConfig.h | 91 +- src/configuration/DRAMSys/config/SimConfig.h | 11 +- src/configuration/DRAMSys/config/TraceSetup.h | 30 +- .../config/memspec/MemArchitectureSpec.cpp | 10 +- .../config/memspec/MemArchitectureSpec.h | 6 +- .../DRAMSys/config/memspec/MemPowerSpec.cpp | 10 +- .../DRAMSys/config/memspec/MemPowerSpec.h | 6 +- .../DRAMSys/config/memspec/MemSpec.h | 7 +- .../DRAMSys/config/memspec/MemTimingSpec.cpp | 10 +- .../DRAMSys/config/memspec/MemTimingSpec.h | 6 +- .../DRAMSys/common/DebugManager.cpp | 15 +- src/libdramsys/DRAMSys/common/DebugManager.h | 17 +- src/libdramsys/DRAMSys/common/TlmRecorder.cpp | 247 ++- src/libdramsys/DRAMSys/common/TlmRecorder.h | 117 +- .../DRAMSys/common/dramExtensions.cpp | 87 +- .../DRAMSys/common/dramExtensions.h | 67 +- src/libdramsys/DRAMSys/common/utils.cpp | 20 +- src/libdramsys/DRAMSys/common/utils.h | 21 +- .../DRAMSys/configuration/Configuration.cpp | 62 +- .../DRAMSys/configuration/Configuration.h | 68 +- .../DRAMSys/configuration/memspec/MemSpec.cpp | 102 +- .../DRAMSys/configuration/memspec/MemSpec.h | 121 +- .../configuration/memspec/MemSpecDDR3.cpp | 133 +- .../configuration/memspec/MemSpecDDR3.h | 11 +- .../configuration/memspec/MemSpecDDR4.cpp | 171 +- .../configuration/memspec/MemSpecDDR4.h | 9 +- .../configuration/memspec/MemSpecGDDR5.cpp | 129 +- .../configuration/memspec/MemSpecGDDR5.h | 13 +- .../configuration/memspec/MemSpecGDDR5X.cpp | 129 +- .../configuration/memspec/MemSpecGDDR5X.h | 13 +- .../configuration/memspec/MemSpecGDDR6.cpp | 135 +- .../configuration/memspec/MemSpecGDDR6.h | 13 +- .../configuration/memspec/MemSpecHBM2.cpp | 120 +- .../configuration/memspec/MemSpecHBM2.h | 15 +- .../configuration/memspec/MemSpecLPDDR4.cpp | 117 +- .../configuration/memspec/MemSpecLPDDR4.h | 10 +- .../configuration/memspec/MemSpecSTTMRAM.cpp | 100 +- .../configuration/memspec/MemSpecSTTMRAM.h | 9 +- .../configuration/memspec/MemSpecWideIO.cpp | 155 +- .../configuration/memspec/MemSpecWideIO.h | 9 +- .../configuration/memspec/MemSpecWideIO2.cpp | 107 +- .../configuration/memspec/MemSpecWideIO2.h | 9 +- .../DRAMSys/controller/BankMachine.cpp | 88 +- .../DRAMSys/controller/BankMachine.h | 16 +- src/libdramsys/DRAMSys/controller/Command.cpp | 229 ++- src/libdramsys/DRAMSys/controller/Command.h | 21 +- .../DRAMSys/controller/Controller.cpp | 190 +- .../DRAMSys/controller/Controller.h | 35 +- .../DRAMSys/controller/ControllerIF.h | 82 +- .../controller/ControllerRecordable.cpp | 31 +- .../DRAMSys/controller/ControllerRecordable.h | 19 +- src/libdramsys/DRAMSys/controller/ManagerIF.h | 8 +- .../DRAMSys/controller/cmdmux/CmdMuxIF.h | 12 +- .../controller/cmdmux/CmdMuxOldest.cpp | 33 +- .../DRAMSys/controller/cmdmux/CmdMuxOldest.h | 7 +- .../controller/cmdmux/CmdMuxStrict.cpp | 49 +- .../DRAMSys/controller/cmdmux/CmdMuxStrict.h | 6 +- .../controller/powerdown/PowerDownManagerIF.h | 2 +- .../powerdown/PowerDownManagerStaggered.cpp | 82 +- .../powerdown/PowerDownManagerStaggered.h | 11 +- .../refresh/RefreshManagerAllBank.cpp | 110 +- .../refresh/RefreshManagerAllBank.h | 18 +- .../controller/refresh/RefreshManagerDummy.h | 1 + .../controller/refresh/RefreshManagerIF.h | 13 +- .../refresh/RefreshManagerPer2Bank.cpp | 143 +- .../refresh/RefreshManagerPer2Bank.h | 22 +- .../refresh/RefreshManagerPerBank.cpp | 98 +- .../refresh/RefreshManagerPerBank.h | 22 +- .../refresh/RefreshManagerSameBank.cpp | 116 +- .../refresh/RefreshManagerSameBank.h | 26 +- .../controller/respqueue/RespQueueFifo.h | 2 +- .../controller/respqueue/RespQueueIF.h | 8 +- .../scheduler/BufferCounterBankwise.cpp | 4 +- .../scheduler/BufferCounterBankwise.h | 2 +- .../controller/scheduler/BufferCounterIF.h | 10 +- .../scheduler/BufferCounterReadWrite.cpp | 7 +- .../scheduler/BufferCounterReadWrite.h | 2 +- .../scheduler/BufferCounterShared.cpp | 4 +- .../scheduler/BufferCounterShared.h | 2 +- .../controller/scheduler/SchedulerFifo.cpp | 6 +- .../controller/scheduler/SchedulerFifo.h | 10 +- .../controller/scheduler/SchedulerFrFcfs.cpp | 10 +- .../controller/scheduler/SchedulerFrFcfs.h | 10 +- .../scheduler/SchedulerFrFcfsGrp.cpp | 16 +- .../controller/scheduler/SchedulerFrFcfsGrp.h | 12 +- .../scheduler/SchedulerGrpFrFcfs.cpp | 20 +- .../controller/scheduler/SchedulerGrpFrFcfs.h | 10 +- .../scheduler/SchedulerGrpFrFcfsWm.cpp | 29 +- .../scheduler/SchedulerGrpFrFcfsWm.h | 12 +- .../controller/scheduler/SchedulerIF.h | 16 +- .../DRAMSys/simulation/AddressDecoder.cpp | 131 +- .../DRAMSys/simulation/AddressDecoder.h | 29 +- src/libdramsys/DRAMSys/simulation/Arbiter.cpp | 147 +- src/libdramsys/DRAMSys/simulation/Arbiter.h | 39 +- src/libdramsys/DRAMSys/simulation/DRAMSys.cpp | 90 +- src/libdramsys/DRAMSys/simulation/DRAMSys.h | 15 +- .../DRAMSys/simulation/DRAMSysRecordable.cpp | 85 +- .../DRAMSys/simulation/DRAMSysRecordable.h | 11 +- .../DRAMSys/simulation/ReorderBuffer.h | 76 +- .../DRAMSys/simulation/dram/Dram.cpp | 61 +- src/libdramsys/DRAMSys/simulation/dram/Dram.h | 12 +- .../DRAMSys/simulation/dram/DramDDR3.cpp | 141 +- .../DRAMSys/simulation/dram/DramDDR4.cpp | 141 +- .../DRAMSys/simulation/dram/DramGDDR5.cpp | 3 +- .../DRAMSys/simulation/dram/DramGDDR5X.cpp | 3 +- .../DRAMSys/simulation/dram/DramGDDR6.cpp | 3 +- .../DRAMSys/simulation/dram/DramHBM2.cpp | 3 +- .../DRAMSys/simulation/dram/DramHBM2.h | 2 +- .../DRAMSys/simulation/dram/DramLPDDR4.cpp | 3 +- .../simulation/dram/DramRecordable.cpp | 61 +- .../DRAMSys/simulation/dram/DramRecordable.h | 13 +- .../DRAMSys/simulation/dram/DramSTTMRAM.cpp | 4 +- .../DRAMSys/simulation/dram/DramWideIO.cpp | 141 +- .../DRAMSys/simulation/dram/DramWideIO2.cpp | 4 +- src/simulator/simulator/Cache.cpp | 164 +- src/simulator/simulator/Cache.h | 68 +- src/simulator/simulator/EccModule.cpp | 46 +- src/simulator/simulator/EccModule.h | 32 +- src/simulator/simulator/Initiator.h | 10 +- src/simulator/simulator/MemoryManager.cpp | 13 +- src/simulator/simulator/MemoryManager.h | 10 +- src/simulator/simulator/SimpleInitiator.h | 31 +- .../simulator/generator/RandomProducer.cpp | 18 +- .../generator/SequentialProducer.cpp | 18 +- .../simulator/generator/TrafficGenerator.h | 10 +- src/simulator/simulator/hammer/RowHammer.cpp | 12 +- src/simulator/simulator/hammer/RowHammer.h | 4 +- src/simulator/simulator/player/StlPlayer.cpp | 58 +- .../simulator/request/RequestIssuer.cpp | 28 +- .../simulator/request/RequestIssuer.h | 14 +- .../simulator/request/RequestProducer.h | 8 +- src/util/DRAMSys/util/json.h | 85 +- src/util/DRAMSys/util/util.cpp | 3 +- src/util/DRAMSys/util/util.h | 5 +- 283 files changed, 10375 insertions(+), 8412 deletions(-) diff --git a/extensions/apps/traceAnalyzer/businessObjects/commentmodel.cpp b/extensions/apps/traceAnalyzer/businessObjects/commentmodel.cpp index 10c9cd51..71dc469d 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/commentmodel.cpp +++ b/extensions/apps/traceAnalyzer/businessObjects/commentmodel.cpp @@ -35,11 +35,12 @@ #include "commentmodel.h" -#include #include #include +#include -CommentModel::CommentModel(QObject *parent) : QAbstractTableModel(parent), +CommentModel::CommentModel(QObject* parent) : + QAbstractTableModel(parent), gotoAction(new QAction("Goto comment", this)), editAction(new QAction("Edit comment", this)), deleteAction(new QAction("Delete comment", this)), @@ -52,52 +53,72 @@ CommentModel::CommentModel(QObject *parent) : QAbstractTableModel(parent), void CommentModel::setUpActions() { - QObject::connect(gotoAction, &QAction::triggered, this, [=](){ - const QModelIndexList indexes = internalSelectionModel->selectedRows(); - for (const QModelIndex ¤tIndex : indexes) - { - emit gotoCommentTriggered(currentIndex); - } - }); + QObject::connect(gotoAction, + &QAction::triggered, + this, + [=]() + { + const QModelIndexList indexes = internalSelectionModel->selectedRows(); + for (const QModelIndex& currentIndex : indexes) + { + emit gotoCommentTriggered(currentIndex); + } + }); - QObject::connect(editAction, &QAction::triggered, this, [=](){ - const QModelIndexList indexes = internalSelectionModel->selectedRows(); - for (const QModelIndex ¤tIndex : indexes) - emit editTriggered(index(currentIndex.row(), static_cast(Column::Comment))); - }); + QObject::connect(editAction, + &QAction::triggered, + this, + [=]() + { + const QModelIndexList indexes = internalSelectionModel->selectedRows(); + for (const QModelIndex& currentIndex : indexes) + emit editTriggered( + index(currentIndex.row(), static_cast(Column::Comment))); + }); - QObject::connect(deleteAction, &QAction::triggered, this, [=](){ - const QModelIndexList indexes = internalSelectionModel->selectedRows(); - for (const QModelIndex ¤tIndex : indexes) - removeComment(currentIndex); - }); + QObject::connect(deleteAction, + &QAction::triggered, + this, + [=]() + { + const QModelIndexList indexes = internalSelectionModel->selectedRows(); + for (const QModelIndex& currentIndex : indexes) + removeComment(currentIndex); + }); - QObject::connect(selectAllAction, &QAction::triggered, this, [=](){ - QModelIndex topLeft = index(0, 0); - QModelIndex bottomRight = index(rowCount() - 1, columnCount() - 1); - internalSelectionModel->select(QItemSelection(topLeft, bottomRight), - QItemSelectionModel::Select | QItemSelectionModel::Rows); - }); + QObject::connect(selectAllAction, + &QAction::triggered, + this, + [=]() + { + QModelIndex topLeft = index(0, 0); + QModelIndex bottomRight = index(rowCount() - 1, columnCount() - 1); + internalSelectionModel->select(QItemSelection(topLeft, bottomRight), + QItemSelectionModel::Select | + QItemSelectionModel::Rows); + }); - QObject::connect(deselectAllAction, &QAction::triggered, - internalSelectionModel, &QItemSelectionModel::clearSelection); + QObject::connect(deselectAllAction, + &QAction::triggered, + internalSelectionModel, + &QItemSelectionModel::clearSelection); } -int CommentModel::rowCount(const QModelIndex &parent) const +int CommentModel::rowCount(const QModelIndex& parent) const { Q_UNUSED(parent) return comments.size(); } -int CommentModel::columnCount(const QModelIndex &parent) const +int CommentModel::columnCount(const QModelIndex& parent) const { Q_UNUSED(parent) return static_cast(Column::COLUMNCOUNT); } -QVariant CommentModel::data(const QModelIndex &index, int role) const +QVariant CommentModel::data(const QModelIndex& index, int role) const { if (!index.isValid()) return QVariant(); @@ -106,12 +127,13 @@ QVariant CommentModel::data(const QModelIndex &index, int role) const if (role != Qt::DisplayRole && role != Qt::EditRole && role != Qt::UserRole) return QVariant(); - const Comment &comment = comments.at(index.row()); + const Comment& comment = comments.at(index.row()); if (role == Qt::UserRole && static_cast(index.column()) == Column::Time) return QVariant(comment.time); - switch (static_cast(index.column())) { + switch (static_cast(index.column())) + { case Column::Time: return QVariant(prettyFormatTime(comment.time)); case Column::Comment: @@ -123,7 +145,7 @@ QVariant CommentModel::data(const QModelIndex &index, int role) const return QVariant(); } -bool CommentModel::setData(const QModelIndex &index, const QVariant &value, int role) +bool CommentModel::setData(const QModelIndex& index, const QVariant& value, int role) { if (!index.isValid()) return false; @@ -136,7 +158,7 @@ bool CommentModel::setData(const QModelIndex &index, const QVariant &value, int QString newText = value.toString(); - Comment &comment = comments.at(index.row()); + Comment& comment = comments.at(index.row()); comment.text = newText; emit dataChanged(index, index); @@ -150,7 +172,8 @@ QVariant CommentModel::headerData(int section, Qt::Orientation orientation, int if (orientation == Qt::Horizontal) { - switch (static_cast(section)) { + switch (static_cast(section)) + { case Column::Time: return "Time"; case Column::Comment: @@ -163,7 +186,7 @@ QVariant CommentModel::headerData(int section, Qt::Orientation orientation, int return QVariant(); } -Qt::ItemFlags CommentModel::flags(const QModelIndex &index) const +Qt::ItemFlags CommentModel::flags(const QModelIndex& index) const { Qt::ItemFlags flags = QAbstractItemModel::flags(index); @@ -178,28 +201,26 @@ void CommentModel::openContextMenu() if (!internalSelectionModel->hasSelection()) return; - QMenu *menu = new QMenu(); + QMenu* menu = new QMenu(); menu->addActions({gotoAction, editAction, deleteAction}); menu->addSeparator(); menu->addActions({selectAllAction, deselectAllAction}); - QObject::connect(menu, &QMenu::aboutToHide, [=]() { - menu->deleteLater(); - }); + QObject::connect(menu, &QMenu::aboutToHide, [=]() { menu->deleteLater(); }); menu->popup(QCursor::pos()); } -QItemSelectionModel *CommentModel::selectionModel() const +QItemSelectionModel* CommentModel::selectionModel() const { return internalSelectionModel; } void CommentModel::addComment(traceTime time) { - auto commentIt = std::find_if(comments.rbegin(), comments.rend(), [time](const Comment &comment){ - return comment.time <= time; - }); + auto commentIt = std::find_if(comments.rbegin(), + comments.rend(), + [time](const Comment& comment) { return comment.time <= time; }); int insertIndex = std::distance(comments.begin(), commentIt.base()); @@ -207,17 +228,17 @@ void CommentModel::addComment(traceTime time) comments.insert(comments.begin() + insertIndex, {time, "Enter comment text..."}); endInsertRows(); - internalSelectionModel->setCurrentIndex(index(insertIndex, 0), - QItemSelectionModel::ClearAndSelect | QItemSelectionModel::Rows); + internalSelectionModel->setCurrentIndex( + index(insertIndex, 0), QItemSelectionModel::ClearAndSelect | QItemSelectionModel::Rows); emit editTriggered(index(insertIndex, 1)); } void CommentModel::addComment(traceTime time, QString text) { - auto commentIt = std::find_if(comments.rbegin(), comments.rend(), [time](const Comment &comment){ - return comment.time <= time; - }); + auto commentIt = std::find_if(comments.rbegin(), + comments.rend(), + [time](const Comment& comment) { return comment.time <= time; }); int insertIndex = std::distance(comments.begin(), commentIt.base()); @@ -228,9 +249,9 @@ void CommentModel::addComment(traceTime time, QString text) void CommentModel::removeComment(traceTime time) { - auto commentIt = std::find_if(comments.begin(), comments.end(), [time](const Comment &comment){ - return comment.time == time; - }); + auto commentIt = std::find_if(comments.begin(), + comments.end(), + [time](const Comment& comment) { return comment.time == time; }); if (commentIt == comments.end()) return; @@ -242,19 +263,19 @@ void CommentModel::removeComment(traceTime time) endRemoveRows(); } -void CommentModel::removeComment(const QModelIndex &index) +void CommentModel::removeComment(const QModelIndex& index) { beginRemoveRows(QModelIndex(), index.row(), index.row()); comments.erase(comments.begin() + index.row()); endRemoveRows(); } -const std::vector &CommentModel::getComments() const +const std::vector& CommentModel::getComments() const { return comments; } -traceTime CommentModel::getTimeFromIndex(const QModelIndex &index) const +traceTime CommentModel::getTimeFromIndex(const QModelIndex& index) const { Q_ASSERT(comments.size() > index.row()); @@ -263,9 +284,11 @@ traceTime CommentModel::getTimeFromIndex(const QModelIndex &index) const QModelIndex CommentModel::hoveredComment(Timespan timespan) const { - auto commentIt = std::find_if(comments.begin(), comments.end(), [timespan](const Comment &comment){ - return timespan.Begin() < comment.time && comment.time < timespan.End(); - }); + auto commentIt = + std::find_if(comments.begin(), + comments.end(), + [timespan](const Comment& comment) + { return timespan.Begin() < comment.time && comment.time < timespan.End(); }); if (commentIt == comments.end()) return QModelIndex(); @@ -275,17 +298,17 @@ QModelIndex CommentModel::hoveredComment(Timespan timespan) const return index(commentIndex, 0); } -bool CommentModel::eventFilter(QObject *object, QEvent *event) +bool CommentModel::eventFilter(QObject* object, QEvent* event) { Q_UNUSED(object) if (event->type() == QEvent::KeyPress) { - QKeyEvent *keyEvent = static_cast(event); + QKeyEvent* keyEvent = static_cast(event); if (keyEvent->key() == Qt::Key_Delete) { const QModelIndexList indexes = internalSelectionModel->selectedRows(); - for (const QModelIndex ¤tIndex : indexes) + for (const QModelIndex& currentIndex : indexes) { removeComment(currentIndex); } @@ -295,7 +318,7 @@ bool CommentModel::eventFilter(QObject *object, QEvent *event) return false; } -void CommentModel::rowDoubleClicked(const QModelIndex &index) +void CommentModel::rowDoubleClicked(const QModelIndex& index) { if (!index.isValid()) return; diff --git a/extensions/apps/traceAnalyzer/businessObjects/commentmodel.h b/extensions/apps/traceAnalyzer/businessObjects/commentmodel.h index d5cdb0a2..55643e40 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/commentmodel.h +++ b/extensions/apps/traceAnalyzer/businessObjects/commentmodel.h @@ -36,8 +36,8 @@ #ifndef COMMENTMODEL_H #define COMMENTMODEL_H -#include "tracetime.h" #include "timespan.h" +#include "tracetime.h" #include #include @@ -50,22 +50,25 @@ class CommentModel : public QAbstractTableModel Q_OBJECT public: - explicit CommentModel(QObject *parent = nullptr); + explicit CommentModel(QObject* parent = nullptr); - struct Comment { + struct Comment + { traceTime time; QString text; }; - int rowCount(const QModelIndex &parent = QModelIndex()) const override; - int columnCount(const QModelIndex &parent = QModelIndex()) const override; + int rowCount(const QModelIndex& parent = QModelIndex()) const override; + int columnCount(const QModelIndex& parent = QModelIndex()) const override; - QVariant data(const QModelIndex &index, int role = Qt::DisplayRole) const override; - QVariant headerData(int section, Qt::Orientation orientation, int role = Qt::DisplayRole) const override; + QVariant data(const QModelIndex& index, int role = Qt::DisplayRole) const override; + QVariant + headerData(int section, Qt::Orientation orientation, int role = Qt::DisplayRole) const override; - Qt::ItemFlags flags(const QModelIndex &index) const override; + Qt::ItemFlags flags(const QModelIndex& index) const override; - enum class Column { + enum class Column + { Time = 0, Comment, COLUMNCOUNT @@ -73,47 +76,47 @@ public: void openContextMenu(); - QItemSelectionModel *selectionModel() const; + QItemSelectionModel* selectionModel() const; void addComment(traceTime time); void addComment(traceTime time, QString text); void removeComment(traceTime time); - void removeComment(const QModelIndex &index); + void removeComment(const QModelIndex& index); - const std::vector &getComments() const; + const std::vector& getComments() const; - traceTime getTimeFromIndex(const QModelIndex &index) const; + traceTime getTimeFromIndex(const QModelIndex& index) const; QModelIndex hoveredComment(Timespan timespan) const; public Q_SLOTS: - void rowDoubleClicked(const QModelIndex &index); + void rowDoubleClicked(const QModelIndex& index); protected: - bool setData(const QModelIndex &index, const QVariant &value, int role = Qt::EditRole) override; + bool setData(const QModelIndex& index, const QVariant& value, int role = Qt::EditRole) override; /** * The eventFilter is used to delete comments using the delete key. */ - bool eventFilter(QObject *object, QEvent *event) override; + bool eventFilter(QObject* object, QEvent* event) override; Q_SIGNALS: - void editTriggered(const QModelIndex &index); - void gotoCommentTriggered(const QModelIndex &index); + void editTriggered(const QModelIndex& index); + void gotoCommentTriggered(const QModelIndex& index); private: void setUpActions(); std::vector comments; - QAction *gotoAction; - QAction *editAction; - QAction *deleteAction; - QAction *selectAllAction; - QAction *deselectAllAction; + QAction* gotoAction; + QAction* editAction; + QAction* deleteAction; + QAction* selectAllAction; + QAction* deselectAllAction; - QItemSelectionModel *internalSelectionModel; + QItemSelectionModel* internalSelectionModel; }; #endif // COMMENTMODEL_H diff --git a/extensions/apps/traceAnalyzer/businessObjects/configmodels.cpp b/extensions/apps/traceAnalyzer/businessObjects/configmodels.cpp index ff3f6011..bc63ef86 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/configmodels.cpp +++ b/extensions/apps/traceAnalyzer/businessObjects/configmodels.cpp @@ -35,10 +35,11 @@ #include "configmodels.h" -#include #include +#include -McConfigModel::McConfigModel(const TraceDB &traceFile, QObject *parent) : QAbstractTableModel(parent) +McConfigModel::McConfigModel(const TraceDB& traceFile, QObject* parent) : + QAbstractTableModel(parent) { QSqlDatabase db = traceFile.getDatabase(); QString query = "SELECT MCconfig FROM GeneralInfo"; @@ -52,7 +53,7 @@ McConfigModel::McConfigModel(const TraceDB &traceFile, QObject *parent) : QAbstr parseJson(mcConfigJson); } -void McConfigModel::parseJson(const QString &jsonString) +void McConfigModel::parseJson(const QString& jsonString) { QJsonDocument jsonDocument = QJsonDocument::fromJson(jsonString.toUtf8()); QJsonObject mcConfigJson = jsonDocument.object()["mcconfig"].toObject(); @@ -76,31 +77,34 @@ void McConfigModel::parseJson(const QString &jsonString) } } -void McConfigModel::addAdditionalInfos(const GeneralInfo &generalInfo) +void McConfigModel::addAdditionalInfos(const GeneralInfo& generalInfo) { - auto addEntry = [this](const QString &key, const QString &value) { entries.push_back({key, value}); }; + auto addEntry = [this](const QString& key, const QString& value) { + entries.push_back({key, value}); + }; addEntry("Number of Transactions", QString::number(generalInfo.numberOfTransactions)); - addEntry("Clock period", QString::number(generalInfo.clkPeriod) + " " + generalInfo.unitOfTime.toLower()); + addEntry("Clock period", + QString::number(generalInfo.clkPeriod) + " " + generalInfo.unitOfTime.toLower()); addEntry("Length of trace", prettyFormatTime(generalInfo.span.End())); addEntry("Window size", QString::number(generalInfo.windowSize)); } -int McConfigModel::rowCount(const QModelIndex &parent) const +int McConfigModel::rowCount(const QModelIndex& parent) const { Q_UNUSED(parent) return entries.size(); } -int McConfigModel::columnCount(const QModelIndex &parent) const +int McConfigModel::columnCount(const QModelIndex& parent) const { Q_UNUSED(parent) return 2; } -QVariant McConfigModel::data(const QModelIndex &index, int role) const +QVariant McConfigModel::data(const QModelIndex& index, int role) const { if (!index.isValid()) return QVariant(); @@ -125,7 +129,8 @@ QVariant McConfigModel::headerData(int section, Qt::Orientation orientation, int if (orientation == Qt::Horizontal) { - switch (section) { + switch (section) + { case 0: return "Field"; case 1: @@ -138,7 +143,7 @@ QVariant McConfigModel::headerData(int section, Qt::Orientation orientation, int return QVariant(); } -MemSpecModel::MemSpecModel(const TraceDB &traceFile, QObject *parent) : QAbstractItemModel(parent) +MemSpecModel::MemSpecModel(const TraceDB& traceFile, QObject* parent) : QAbstractItemModel(parent) { QSqlDatabase db = traceFile.getDatabase(); QString query = "SELECT Memspec FROM GeneralInfo"; @@ -156,23 +161,24 @@ int MemSpecModel::Node::getRow() const if (!parent) return 0; - const auto &siblings = parent->children; - const auto siblingsIt = std::find_if(siblings.begin(), siblings.end(), [this](const std::unique_ptr &node){ - return node.get() == this; - }); + const auto& siblings = parent->children; + const auto siblingsIt = + std::find_if(siblings.begin(), + siblings.end(), + [this](const std::unique_ptr& node) { return node.get() == this; }); Q_ASSERT(siblingsIt != siblings.end()); return std::distance(siblings.begin(), siblingsIt); } -void MemSpecModel::parseJson(const QString &jsonString) +void MemSpecModel::parseJson(const QString& jsonString) { QJsonDocument jsonDocument = QJsonDocument::fromJson(jsonString.toUtf8()); QJsonObject memSpecJson = jsonDocument.object()["memspec"].toObject(); - std::function &)> addNodes; - addNodes = [&addNodes](const QJsonObject &obj, std::unique_ptr &parentNode) + std::function&)> addNodes; + addNodes = [&addNodes](const QJsonObject& obj, std::unique_ptr& parentNode) { for (auto key : obj.keys()) { @@ -192,7 +198,8 @@ void MemSpecModel::parseJson(const QString &jsonString) value = currentValue.toBool() ? "True" : "False"; } - std::unique_ptr node = std::unique_ptr(new Node({key, value}, parentNode.get())); + std::unique_ptr node = + std::unique_ptr(new Node({key, value}, parentNode.get())); addNodes(obj[key].toObject(), node); parentNode->children.push_back(std::move(node)); @@ -202,29 +209,29 @@ void MemSpecModel::parseJson(const QString &jsonString) addNodes(memSpecJson, rootNode); } -int MemSpecModel::rowCount(const QModelIndex &parent) const +int MemSpecModel::rowCount(const QModelIndex& parent) const { if (parent.column() > 0) return 0; - const Node *parentNode; + const Node* parentNode; if (!parent.isValid()) parentNode = rootNode.get(); else - parentNode = static_cast(parent.internalPointer()); + parentNode = static_cast(parent.internalPointer()); return parentNode->childCount(); } -int MemSpecModel::columnCount(const QModelIndex &parent) const +int MemSpecModel::columnCount(const QModelIndex& parent) const { Q_UNUSED(parent) return 2; } -QVariant MemSpecModel::data(const QModelIndex &index, int role) const +QVariant MemSpecModel::data(const QModelIndex& index, int role) const { if (!index.isValid()) return QVariant(); @@ -232,7 +239,7 @@ QVariant MemSpecModel::data(const QModelIndex &index, int role) const if (role != Qt::DisplayRole && role != Qt::ToolTipRole) return QVariant(); - auto *node = static_cast(index.internalPointer()); + auto* node = static_cast(index.internalPointer()); if (index.column() == 0) return QVariant(node->data.first); @@ -247,7 +254,8 @@ QVariant MemSpecModel::headerData(int section, Qt::Orientation orientation, int if (orientation == Qt::Horizontal) { - switch (section) { + switch (section) + { case 0: return "Field"; case 1: @@ -260,33 +268,33 @@ QVariant MemSpecModel::headerData(int section, Qt::Orientation orientation, int return QVariant(); } -QModelIndex MemSpecModel::index(int row, int column, const QModelIndex &parent) const +QModelIndex MemSpecModel::index(int row, int column, const QModelIndex& parent) const { if (!hasIndex(row, column, parent)) return QModelIndex(); - const Node *parentNode; + const Node* parentNode; if (!parent.isValid()) parentNode = rootNode.get(); else - parentNode = static_cast(parent.internalPointer()); + parentNode = static_cast(parent.internalPointer()); - const Node *node = parentNode->children[row].get(); + const Node* node = parentNode->children[row].get(); - return createIndex(row, column, const_cast(node)); + return createIndex(row, column, const_cast(node)); } -QModelIndex MemSpecModel::parent(const QModelIndex &index) const +QModelIndex MemSpecModel::parent(const QModelIndex& index) const { if (!index.isValid()) return QModelIndex(); - const Node *childNode = static_cast(index.internalPointer()); - const Node *parentNode = childNode->parent; + const Node* childNode = static_cast(index.internalPointer()); + const Node* parentNode = childNode->parent; if (!parentNode || parentNode == rootNode.get()) return QModelIndex(); - return createIndex(parentNode->getRow(), 0, const_cast(parentNode)); + return createIndex(parentNode->getRow(), 0, const_cast(parentNode)); } diff --git a/extensions/apps/traceAnalyzer/businessObjects/configmodels.h b/extensions/apps/traceAnalyzer/businessObjects/configmodels.h index 5373473c..004e0441 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/configmodels.h +++ b/extensions/apps/traceAnalyzer/businessObjects/configmodels.h @@ -40,22 +40,23 @@ #include "phases/dependencyinfos.h" #include -#include #include +#include class McConfigModel : public QAbstractTableModel { Q_OBJECT public: - explicit McConfigModel(const TraceDB &traceFile, QObject *parent = nullptr); + explicit McConfigModel(const TraceDB& traceFile, QObject* parent = nullptr); protected: - int rowCount(const QModelIndex &parent = QModelIndex()) const override; - int columnCount(const QModelIndex &parent = QModelIndex()) const override; + int rowCount(const QModelIndex& parent = QModelIndex()) const override; + int columnCount(const QModelIndex& parent = QModelIndex()) const override; - QVariant data(const QModelIndex &index, int role = Qt::DisplayRole) const override; - QVariant headerData(int section, Qt::Orientation orientation, int role = Qt::DisplayRole) const override; + QVariant data(const QModelIndex& index, int role = Qt::DisplayRole) const override; + QVariant + headerData(int section, Qt::Orientation orientation, int role = Qt::DisplayRole) const override; private: /** @@ -63,13 +64,13 @@ private: * In case of failure, nothing is added and therefore the model * will stay empty. */ - void parseJson(const QString &jsonString); + void parseJson(const QString& jsonString); /** * Add additional infos about the tracefile which were * previously displayed in the fileDescription widget. */ - void addAdditionalInfos(const GeneralInfo &generalInfo); + void addAdditionalInfos(const GeneralInfo& generalInfo); std::vector> entries; }; @@ -79,17 +80,18 @@ class MemSpecModel : public QAbstractItemModel Q_OBJECT public: - explicit MemSpecModel(const TraceDB &traceFile, QObject *parent = nullptr); + explicit MemSpecModel(const TraceDB& traceFile, QObject* parent = nullptr); protected: - int rowCount(const QModelIndex &parent = QModelIndex()) const override; - int columnCount(const QModelIndex &parent) const override; + int rowCount(const QModelIndex& parent = QModelIndex()) const override; + int columnCount(const QModelIndex& parent) const override; - QVariant data(const QModelIndex &index, int role = Qt::DisplayRole) const override; - QVariant headerData(int section, Qt::Orientation orientation, int role = Qt::DisplayRole) const override; + QVariant data(const QModelIndex& index, int role = Qt::DisplayRole) const override; + QVariant + headerData(int section, Qt::Orientation orientation, int role = Qt::DisplayRole) const override; - QModelIndex index(int row, int column, const QModelIndex &parent) const override; - QModelIndex parent(const QModelIndex &index) const override; + QModelIndex index(int row, int column, const QModelIndex& parent) const override; + QModelIndex parent(const QModelIndex& index) const override; private: /** @@ -97,7 +99,7 @@ private: * In case of failure, nothing is added and therefore the model * will stay empty. */ - void parseJson(const QString &jsonString); + void parseJson(const QString& jsonString); struct Node { @@ -108,7 +110,7 @@ private: */ Node() = default; - Node(NodeData data, const Node *parent) : data(data), parent(parent) {} + Node(NodeData data, const Node* parent) : data(data), parent(parent) {} /** * Gets the row relative to its parent. @@ -118,7 +120,7 @@ private: NodeData data; - const Node *parent = nullptr; + const Node* parent = nullptr; std::vector> children; }; diff --git a/extensions/apps/traceAnalyzer/businessObjects/dependencymodels.cpp b/extensions/apps/traceAnalyzer/businessObjects/dependencymodels.cpp index 200c602f..384d72f7 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dependencymodels.cpp +++ b/extensions/apps/traceAnalyzer/businessObjects/dependencymodels.cpp @@ -35,7 +35,8 @@ #include "dependencymodels.h" -DependencyInfosModel::DependencyInfosModel(TraceDB &traceFile, QObject *parent) : QAbstractItemModel(parent) +DependencyInfosModel::DependencyInfosModel(TraceDB& traceFile, QObject* parent) : + QAbstractItemModel(parent) { mDepInfosDepType = traceFile.getDependencyInfos(DependencyInfos::Type::DependencyType); mDepInfosTimeDep = traceFile.getDependencyInfos(DependencyInfos::Type::TimeDependency); @@ -53,9 +54,11 @@ int DependencyInfosModel::Node::getRow() const if (!parent) return 0; - const auto &siblings = parent->children; - const auto siblingsIt = std::find_if(siblings.begin(), siblings.end(), - [this](const std::unique_ptr &node) { return node.get() == this; }); + const auto& siblings = parent->children; + const auto siblingsIt = + std::find_if(siblings.begin(), + siblings.end(), + [this](const std::unique_ptr& node) { return node.get() == this; }); Q_ASSERT(siblingsIt != siblings.end()); @@ -65,48 +68,51 @@ int DependencyInfosModel::Node::getRow() const void DependencyInfosModel::parseInfos() { - std::vector> infos = {{"Dependency Granularity", mDepInfosDepType}, - {"Time Dependencies", mDepInfosTimeDep}, - {"Delayed Phases", mDepInfosDelPhase}, - {"Dependency Phases", mDepInfosDepPhase}}; + std::vector> infos = { + {"Dependency Granularity", mDepInfosDepType}, + {"Time Dependencies", mDepInfosTimeDep}, + {"Delayed Phases", mDepInfosDelPhase}, + {"Dependency Phases", mDepInfosDepPhase}}; for (auto pair : infos) { - std::unique_ptr node = std::unique_ptr(new Node({pair.first, ""}, rootNode.get())); + std::unique_ptr node = + std::unique_ptr(new Node({pair.first, ""}, rootNode.get())); for (auto v : pair.second.getInfos()) { QString value = QString::number(v.value) + " %"; - node->children.push_back(std::move(std::unique_ptr(new Node({v.id, value}, node.get())))); + node->children.push_back( + std::move(std::unique_ptr(new Node({v.id, value}, node.get())))); } rootNode->children.push_back(std::move(node)); } } -int DependencyInfosModel::rowCount(const QModelIndex &parent) const +int DependencyInfosModel::rowCount(const QModelIndex& parent) const { if (parent.column() > 0) return 0; - const Node *parentNode; + const Node* parentNode; if (!parent.isValid()) parentNode = rootNode.get(); else - parentNode = static_cast(parent.internalPointer()); + parentNode = static_cast(parent.internalPointer()); return parentNode->childCount(); } -int DependencyInfosModel::columnCount(const QModelIndex &parent) const +int DependencyInfosModel::columnCount(const QModelIndex& parent) const { Q_UNUSED(parent) return 2; } -QVariant DependencyInfosModel::data(const QModelIndex &index, int role) const +QVariant DependencyInfosModel::data(const QModelIndex& index, int role) const { if (!index.isValid()) return QVariant(); @@ -114,7 +120,7 @@ QVariant DependencyInfosModel::data(const QModelIndex &index, int role) const if (role != Qt::DisplayRole && role != Qt::ToolTipRole) return QVariant(); - auto *node = static_cast(index.internalPointer()); + auto* node = static_cast(index.internalPointer()); if (index.column() == 0) return QVariant(node->data.first); @@ -143,33 +149,33 @@ QVariant DependencyInfosModel::headerData(int section, Qt::Orientation orientati return QVariant(); } -QModelIndex DependencyInfosModel::index(int row, int column, const QModelIndex &parent) const +QModelIndex DependencyInfosModel::index(int row, int column, const QModelIndex& parent) const { if (!hasIndex(row, column, parent)) return QModelIndex(); - const Node *parentNode; + const Node* parentNode; if (!parent.isValid()) parentNode = rootNode.get(); else - parentNode = static_cast(parent.internalPointer()); + parentNode = static_cast(parent.internalPointer()); - const Node *node = parentNode->children[row].get(); + const Node* node = parentNode->children[row].get(); - return createIndex(row, column, const_cast(node)); + return createIndex(row, column, const_cast(node)); } -QModelIndex DependencyInfosModel::parent(const QModelIndex &index) const +QModelIndex DependencyInfosModel::parent(const QModelIndex& index) const { if (!index.isValid()) return QModelIndex(); - const Node *childNode = static_cast(index.internalPointer()); - const Node *parentNode = childNode->parent; + const Node* childNode = static_cast(index.internalPointer()); + const Node* parentNode = childNode->parent; if (!parentNode) return QModelIndex(); - return createIndex(parentNode->getRow(), 0, const_cast(parentNode)); + return createIndex(parentNode->getRow(), 0, const_cast(parentNode)); } diff --git a/extensions/apps/traceAnalyzer/businessObjects/dependencymodels.h b/extensions/apps/traceAnalyzer/businessObjects/dependencymodels.h index b73f5883..7fabaa0c 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dependencymodels.h +++ b/extensions/apps/traceAnalyzer/businessObjects/dependencymodels.h @@ -40,27 +40,26 @@ #include #include -#include #include +#include class DependencyInfosModel : public QAbstractItemModel { Q_OBJECT public: - explicit DependencyInfosModel(TraceDB &traceFile, QObject *parent = nullptr); - ~DependencyInfosModel() - { - } + explicit DependencyInfosModel(TraceDB& traceFile, QObject* parent = nullptr); + ~DependencyInfosModel() {} protected: - int rowCount(const QModelIndex &parent = QModelIndex()) const override; - int columnCount(const QModelIndex &parent) const override; + int rowCount(const QModelIndex& parent = QModelIndex()) const override; + int columnCount(const QModelIndex& parent) const override; - QVariant data(const QModelIndex &index, int role = Qt::DisplayRole) const override; - QVariant headerData(int section, Qt::Orientation orientation, int role = Qt::DisplayRole) const override; + QVariant data(const QModelIndex& index, int role = Qt::DisplayRole) const override; + QVariant + headerData(int section, Qt::Orientation orientation, int role = Qt::DisplayRole) const override; - QModelIndex index(int row, int column, const QModelIndex &parent) const override; - QModelIndex parent(const QModelIndex &index) const override; + QModelIndex index(int row, int column, const QModelIndex& parent) const override; + QModelIndex parent(const QModelIndex& index) const override; private: DependencyInfos mDepInfosDepType; @@ -73,25 +72,18 @@ private: { using NodeData = std::pair; - Node() - { - } - Node(NodeData data, const Node *parent) : data(data), parent(parent) - { - } + Node() {} + Node(NodeData data, const Node* parent) : data(data), parent(parent) {} /** * Gets the row relative to its parent. */ int getRow() const; - int childCount() const - { - return children.size(); - } + int childCount() const { return children.size(); } NodeData data; - const Node *parent = nullptr; + const Node* parent = nullptr; std::vector> children; }; diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/common/QStringComparator.cpp b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/common/QStringComparator.cpp index 286d1427..2aef3e0d 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/common/QStringComparator.cpp +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/common/QStringComparator.cpp @@ -35,10 +35,12 @@ #include "QStringComparator.h" -bool QStringsComparator::operator()(const QString& s1, const QString& s2) const { +bool QStringsComparator::operator()(const QString& s1, const QString& s2) const +{ return s1.compare(s2) < 0; } -bool QStringsComparator::compareQStrings(const QString& s1, const QString& s2) { +bool QStringsComparator::compareQStrings(const QString& s1, const QString& s2) +{ return s1.compare(s2) < 0; } \ No newline at end of file diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/common/QStringComparator.h b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/common/QStringComparator.h index 0a354275..1ef2a8d0 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/common/QStringComparator.h +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/common/QStringComparator.h @@ -37,7 +37,8 @@ #include -struct QStringsComparator { +struct QStringsComparator +{ bool operator()(const QString& s1, const QString& s2) const; static bool compareQStrings(const QString& s1, const QString& s2); }; \ No newline at end of file diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/common/StringMapper.cpp b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/common/StringMapper.cpp index 6e908620..d14860e7 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/common/StringMapper.cpp +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/common/StringMapper.cpp @@ -35,15 +35,16 @@ #include "StringMapper.h" -StringMapper::StringMapper(const QString& name) { +StringMapper::StringMapper(const QString& name) +{ mIDEnum = getIDEnum(name); mIDStr = name; mIsPool = mAuxIsPool(mIDEnum); - } -QString StringMapper::getIDStr(StringMapper::Identifier id) { - static const std::map enumToStr { +QString StringMapper::getIDStr(StringMapper::Identifier id) +{ + static const std::map enumToStr{ {StringMapper::Identifier::CMD_BUS, "CMD_BUS"}, {StringMapper::Identifier::RAS_BUS, "RAS_BUS"}, {StringMapper::Identifier::CAS_BUS, "CAS_BUS"}, @@ -77,13 +78,16 @@ QString StringMapper::getIDStr(StringMapper::Identifier id) { }; auto it = enumToStr.find(id); - if (it != enumToStr.end()) return it->second; - else throw std::invalid_argument("The provided StringMapper::StringMapper::Identifier is not valid."); - + if (it != enumToStr.end()) + return it->second; + else + throw std::invalid_argument( + "The provided StringMapper::StringMapper::Identifier is not valid."); } -StringMapper::Identifier StringMapper::getIDEnum(const QString& id) { - static const std::map strToEnum { +StringMapper::Identifier StringMapper::getIDEnum(const QString& id) +{ + static const std::map strToEnum{ {"CMD_BUS", StringMapper::Identifier::CMD_BUS}, {"RAS_BUS", StringMapper::Identifier::RAS_BUS}, {"CAS_BUS", StringMapper::Identifier::CAS_BUS}, @@ -117,43 +121,48 @@ StringMapper::Identifier StringMapper::getIDEnum(const QString& id) { }; auto it = strToEnum.find(id); - if (it != strToEnum.end()) return it->second; - else throw std::invalid_argument("The provided StringMapper::Identifier '" + id.toStdString() + "' is not valid."); - + if (it != strToEnum.end()) + return it->second; + else + throw std::invalid_argument("The provided StringMapper::Identifier '" + id.toStdString() + + "' is not valid."); } -bool StringMapper::mAuxIsPool(StringMapper::Identifier id) { - return id == StringMapper::Identifier::CMD_BUS - || id == StringMapper::Identifier::RAS_BUS - || id == StringMapper::Identifier::CAS_BUS - || id == StringMapper::Identifier::NAW - || id == StringMapper::Identifier::FAW - || id == StringMapper::Identifier::_32AW - || id == StringMapper::Identifier::FAW_LOGICAL - || id == StringMapper::Identifier::FAW_PHYSICAL; - +bool StringMapper::mAuxIsPool(StringMapper::Identifier id) +{ + return id == StringMapper::Identifier::CMD_BUS || id == StringMapper::Identifier::RAS_BUS || + id == StringMapper::Identifier::CAS_BUS || id == StringMapper::Identifier::NAW || + id == StringMapper::Identifier::FAW || id == StringMapper::Identifier::_32AW || + id == StringMapper::Identifier::FAW_LOGICAL || + id == StringMapper::Identifier::FAW_PHYSICAL; } -bool StringMapper::operator==(const StringMapper& str2) const { +bool StringMapper::operator==(const StringMapper& str2) const +{ return mIDEnum == str2.mIDEnum; } -bool StringMapper::operator!=(const StringMapper& str2) const { +bool StringMapper::operator!=(const StringMapper& str2) const +{ return mIDEnum != str2.mIDEnum; } -bool StringMapper::operator<(const StringMapper& str2) const { +bool StringMapper::operator<(const StringMapper& str2) const +{ return mIDEnum < str2.mIDEnum; } -bool StringMapper::compare(const StringMapper& str1, const StringMapper& str2) { +bool StringMapper::compare(const StringMapper& str1, const StringMapper& str2) +{ return str1.getIDEnum() < str2.getIDEnum(); } -bool StringMapper::operator==(const StringMapper::Identifier& id) const { +bool StringMapper::operator==(const StringMapper::Identifier& id) const +{ return mIDEnum == id; } -bool StringMapper::operator!=(const StringMapper::Identifier& id) const { +bool StringMapper::operator!=(const StringMapper::Identifier& id) const +{ return mIDEnum != id; } diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/common/StringMapper.h b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/common/StringMapper.h index 510e24e0..c9f7e326 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/common/StringMapper.h +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/common/StringMapper.h @@ -35,73 +35,75 @@ #pragma once -#include #include "QStringComparator.h" +#include -class StringMapper { - public: - enum Identifier { - None, - CMD_BUS, - RAS_BUS, - CAS_BUS, - NAW, - FAW, - _32AW, - FAW_LOGICAL, - FAW_PHYSICAL, - REFAB, - PREAB, - PDEP, - PDXP, - SREFEN, - SREFEX, - PDEA, - PDXA, - SRPDEN, - SRPDEX, - ACT, - RD, - WR, - PREPB, - RDA, - WRA, - REFPB, - REFP2B, - PRESB, - RFMAB, - REFSB, - RFMSB - }; +class StringMapper +{ +public: + enum Identifier + { + None, + CMD_BUS, + RAS_BUS, + CAS_BUS, + NAW, + FAW, + _32AW, + FAW_LOGICAL, + FAW_PHYSICAL, + REFAB, + PREAB, + PDEP, + PDXP, + SREFEN, + SREFEX, + PDEA, + PDXA, + SRPDEN, + SRPDEX, + ACT, + RD, + WR, + PREPB, + RDA, + WRA, + REFPB, + REFP2B, + PRESB, + RFMAB, + REFSB, + RFMSB + }; - public: - StringMapper() = default; - StringMapper(const QString& id); - StringMapper(const char* str) : StringMapper(std::forward(str)) {} - ~StringMapper() = default; +public: + StringMapper() = default; + StringMapper(const QString& id); + StringMapper(const char* str) : StringMapper(std::forward(str)) {} + ~StringMapper() = default; - Identifier getIDEnum() const { return mIDEnum; } - const QString getIDStr() const { return mIDStr; } + Identifier getIDEnum() const { return mIDEnum; } + const QString getIDStr() const { return mIDStr; } - bool isPool() const { return mIsPool; } + bool isPool() const { return mIsPool; } - static QString getIDStr(Identifier); - static Identifier getIDEnum(const QString&); + static QString getIDStr(Identifier); + static Identifier getIDEnum(const QString&); - bool operator==(const StringMapper&) const; - bool operator!=(const StringMapper&) const; - bool operator<(const StringMapper&) const; - - bool operator==(const Identifier&) const; - bool operator!=(const Identifier&) const; + bool operator==(const StringMapper&) const; + bool operator!=(const StringMapper&) const; + bool operator<(const StringMapper&) const; - static bool compare(const StringMapper&, const StringMapper&); + bool operator==(const Identifier&) const; + bool operator!=(const Identifier&) const; - protected: - Identifier mIDEnum = None; - QString mIDStr = ""; - bool mIsPool = false; + static bool compare(const StringMapper&, const StringMapper&); - protected: - static bool mAuxIsPool(Identifier); +protected: + Identifier mIDEnum = None; + QString mIDStr = ""; + bool mIsPool = false; + +protected: + static bool mAuxIsPool(Identifier); }; diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/common/common.h b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/common/common.h index 574f514c..61133bd4 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/common/common.h +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/common/common.h @@ -36,19 +36,20 @@ #pragma once #include -#include #include +#include -#include -#include -#include #include +#include #include +#include +#include #include "businessObjects/phases/phasedependency.h" #include "timedependency.h" -struct PhaseTimeDependencies { +struct PhaseTimeDependencies +{ explicit PhaseTimeDependencies(std::initializer_list d) : dependencies(d) {} std::vector dependencies; @@ -57,7 +58,8 @@ struct PhaseTimeDependencies { typedef std::map DependencyMap; -struct DBDependencyEntry { +struct DBDependencyEntry +{ size_t delayedPhaseID; QString delayedPhaseName; QString dependencyType; diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/common/timedependency.h b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/common/timedependency.h index 4cd1e7fe..bfd22b47 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/common/timedependency.h +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/common/timedependency.h @@ -35,29 +35,41 @@ #pragma once +#include "StringMapper.h" #include #include -#include "StringMapper.h" class DBPhaseEntryBase; -#define PASSFUNCTIONDECL (const std::shared_ptr thisPhase, const std::shared_ptr otherPhase) -struct PassFunction { - using Fn = std::function; - PassFunction(Fn passFunction) : mPassFn{std::move(passFunction)} {} +#define PASSFUNCTIONDECL \ + (const std::shared_ptr thisPhase, \ + const std::shared_ptr otherPhase) +struct PassFunction +{ + using Fn = std::function; + PassFunction(Fn passFunction) : mPassFn{std::move(passFunction)} {} - bool execute PASSFUNCTIONDECL { return mPassFn(thisPhase, otherPhase); } + bool execute PASSFUNCTIONDECL { return mPassFn(thisPhase, otherPhase); } - Fn mPassFn; + Fn mPassFn; }; -class TimeDependency { +class TimeDependency +{ public: TimeDependency() = default; - TimeDependency(size_t timeValue, QString phaseDep, DependencyType depType, - QString timeDepName, std::shared_ptr pass=nullptr) - : timeValue{timeValue}, phaseDep{phaseDep}, depType{depType}, - timeDepName{timeDepName}, passFunction{pass} {} + TimeDependency(size_t timeValue, + QString phaseDep, + DependencyType depType, + QString timeDepName, + std::shared_ptr pass = nullptr) : + timeValue{timeValue}, + phaseDep{phaseDep}, + depType{depType}, + timeDepName{timeDepName}, + passFunction{pass} + { + } size_t timeValue; StringMapper phaseDep; diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationBase.cpp b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationBase.cpp index 2fc94625..4a9f3f4b 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationBase.cpp +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationBase.cpp @@ -35,32 +35,40 @@ #include "configurationBase.h" -const uint ConfigurationBase::getClk() const { - if (!mDeviceDeps) - throw std::invalid_argument("Invalid DRAMTimeDependenciesBase object in 'ConfigurationBase::getClk'."); +const uint ConfigurationBase::getClk() const +{ + if (!mDeviceDeps) + throw std::invalid_argument( + "Invalid DRAMTimeDependenciesBase object in 'ConfigurationBase::getClk'."); return mDeviceDeps->getClk(); } -DependencyMap ConfigurationBase::getDependencies(std::vector& commands) const { - if (!mDeviceDeps) - throw std::invalid_argument("Invalid DRAMTimeDependenciesBase object in 'ConfigurationBase::getDependencies'."); +DependencyMap ConfigurationBase::getDependencies(std::vector& commands) const +{ + if (!mDeviceDeps) + throw std::invalid_argument( + "Invalid DRAMTimeDependenciesBase object in 'ConfigurationBase::getDependencies'."); return mDeviceDeps->getDependencies(commands); } -PoolControllerMap ConfigurationBase::getPools() const { - if (!mDeviceDeps) - throw std::invalid_argument("Invalid DRAMTimeDependenciesBase object in 'ConfigurationBase::getAWPools'."); +PoolControllerMap ConfigurationBase::getPools() const +{ + if (!mDeviceDeps) + throw std::invalid_argument( + "Invalid DRAMTimeDependenciesBase object in 'ConfigurationBase::getAWPools'."); return mDeviceDeps->getPools(); } -const QString ConfigurationBase::getDeviceName(const TraceDB& tdb) { +const QString ConfigurationBase::getDeviceName(const TraceDB& tdb) +{ return mGetMemspec(tdb)["memoryType"].toString(); } -const uint ConfigurationBase::mGetClk(const TraceDB& tdb) { +const uint ConfigurationBase::mGetClk(const TraceDB& tdb) +{ QSqlDatabase db = tdb.getDatabase(); QString query = "SELECT clk FROM GeneralInfo"; QSqlQuery sqlQuery = db.exec(query); @@ -72,7 +80,8 @@ const uint ConfigurationBase::mGetClk(const TraceDB& tdb) { return clock; } -const QJsonObject ConfigurationBase::mGetMemspec(const TraceDB& tdb) { +const QJsonObject ConfigurationBase::mGetMemspec(const TraceDB& tdb) +{ QSqlDatabase db = tdb.getDatabase(); QString query = "SELECT Memspec FROM GeneralInfo"; QSqlQuery sqlQuery = db.exec(query); diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationBase.h b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationBase.h index 690fd596..73703001 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationBase.h +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationBase.h @@ -37,30 +37,30 @@ #include -#include "businessObjects/dramTimeDependencies/deviceDependencies/dramtimedependenciesbase.h" #include "businessObjects/dramTimeDependencies/dbEntries/dbphaseentryBase.h" +#include "businessObjects/dramTimeDependencies/deviceDependencies/dramtimedependenciesbase.h" -class ConfigurationBase { +class ConfigurationBase +{ public: - ConfigurationBase() {}; - virtual ~ConfigurationBase() = default; + ConfigurationBase(){}; + virtual ~ConfigurationBase() = default; - virtual QString getQueryStr(const std::vector& commands) const = 0; - virtual std::shared_ptr makePhaseEntry(const QSqlQuery&) const = 0; - - // Delegated methods - const uint getClk() const; - DependencyMap getDependencies(std::vector& commands) const; - PoolControllerMap getPools() const; + virtual QString getQueryStr(const std::vector& commands) const = 0; + virtual std::shared_ptr makePhaseEntry(const QSqlQuery&) const = 0; - static const QString getDeviceName(const TraceDB& tdb); + // Delegated methods + const uint getClk() const; + DependencyMap getDependencies(std::vector& commands) const; + PoolControllerMap getPools() const; + + static const QString getDeviceName(const TraceDB& tdb); protected: - std::shared_ptr mDeviceDeps = nullptr; + std::shared_ptr mDeviceDeps = nullptr; - static const uint mGetClk(const TraceDB& tdb); - static const QJsonObject mGetMemspec(const TraceDB& tdb); - - QSqlQuery mExecuteQuery(const QString& queryStr); + static const uint mGetClk(const TraceDB& tdb); + static const QJsonObject mGetMemspec(const TraceDB& tdb); + QSqlQuery mExecuteQuery(const QString& queryStr); }; diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationfactory.cpp b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationfactory.cpp index b8134677..1cb0d6e2 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationfactory.cpp +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationfactory.cpp @@ -35,88 +35,111 @@ #include "configurationfactory.h" -std::shared_ptr ConfigurationFactory::make(const TraceDB& tdb) { +std::shared_ptr ConfigurationFactory::make(const TraceDB& tdb) +{ const QString deviceName = ConfigurationBase::getDeviceName(tdb); - - if (deviceName == "DDR3") { + + if (deviceName == "DDR3") + { return std::make_shared(tdb); - - } else if (deviceName == "DDR4") { - return std::make_shared(tdb); - - } else if (deviceName == "HBM2") { - return std::make_shared(tdb); - - } else if (deviceName == "LPDDR4") { - return std::make_shared(tdb); - - } else if (deviceName == "DDR5") { - return std::make_shared(tdb); - - } else if (deviceName == "LPDDR5") { - return std::make_shared(tdb); - - } else { - // TODO maybe throw? - throw std::invalid_argument("Could not find the device type '" + deviceName.toStdString() + '\''); - } - + else if (deviceName == "DDR4") + { + return std::make_shared(tdb); + } + else if (deviceName == "HBM2") + { + return std::make_shared(tdb); + } + else if (deviceName == "LPDDR4") + { + return std::make_shared(tdb); + } + else if (deviceName == "DDR5") + { + return std::make_shared(tdb); + } + else if (deviceName == "LPDDR5") + { + return std::make_shared(tdb); + } + else + { + // TODO maybe throw? + throw std::invalid_argument("Could not find the device type '" + deviceName.toStdString() + + '\''); + } } -const std::vector ConfigurationFactory::possiblePhases(const TraceDB& tdb) { +const std::vector ConfigurationFactory::possiblePhases(const TraceDB& tdb) +{ const QString deviceName = ConfigurationBase::getDeviceName(tdb); - - if (deviceName == "DDR3") { + + if (deviceName == "DDR3") + { // return DDR3TimeDependencies::getPossiblePhases(); return TimeDependenciesInfoDDR3::getPossiblePhases(); - - } else if (deviceName == "DDR4") { + } + else if (deviceName == "DDR4") + { return TimeDependenciesInfoDDR4::getPossiblePhases(); - - } else if (deviceName == "HBM2") { + } + else if (deviceName == "HBM2") + { return TimeDependenciesInfoHBM2::getPossiblePhases(); - - } else if (deviceName == "LPDDR4") { + } + else if (deviceName == "LPDDR4") + { return TimeDependenciesInfoLPDDR4::getPossiblePhases(); - - } else if (deviceName == "DDR5") { + } + else if (deviceName == "DDR5") + { return TimeDependenciesInfoDDR5::getPossiblePhases(); - - } else if (deviceName == "LPDDR5") { + } + else if (deviceName == "LPDDR5") + { return TimeDependenciesInfoLPDDR5::getPossiblePhases(); - - } else { + } + else + { // TODO maybe throw? - // throw std::invalid_argument("Could not find the device type '" + deviceName.toStdString() + '\''); + // throw std::invalid_argument("Could not find the device type '" + deviceName.toStdString() + // + '\''); return {""}; } - } -bool ConfigurationFactory::deviceSupported(const TraceDB& tdb) { +bool ConfigurationFactory::deviceSupported(const TraceDB& tdb) +{ uint clk; // Not used const QString deviceName = ConfigurationBase::getDeviceName(tdb); - if (deviceName == "DDR3") { + if (deviceName == "DDR3") + { return true; - - } else if (deviceName == "DDR4") { + } + else if (deviceName == "DDR4") + { return true; - - } else if (deviceName == "HBM2") { + } + else if (deviceName == "HBM2") + { return true; - - } else if (deviceName == "LPDDR4") { + } + else if (deviceName == "LPDDR4") + { return true; - - } else if (deviceName == "DDR5") { + } + else if (deviceName == "DDR5") + { return true; - - } else if (deviceName == "LPDDR5") { + } + else if (deviceName == "LPDDR5") + { return true; - - } else { + } + else + { return false; } } diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationfactory.h b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationfactory.h index db81ae20..fc5883e5 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationfactory.h +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationfactory.h @@ -41,14 +41,15 @@ #include "specialized/DDR3Configuration.h" #include "specialized/DDR4Configuration.h" +#include "specialized/DDR5Configuration.h" #include "specialized/HBM2Configuration.h" #include "specialized/LPDDR4Configuration.h" -#include "specialized/DDR5Configuration.h" #include "specialized/LPDDR5Configuration.h" #include "data/tracedb.h" -class ConfigurationFactory { +class ConfigurationFactory +{ public: static std::shared_ptr make(const TraceDB& tdb); diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR3Configuration.cpp b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR3Configuration.cpp index 536a4685..eb85ca52 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR3Configuration.cpp +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR3Configuration.cpp @@ -35,27 +35,32 @@ #include "DDR3Configuration.h" -DDR3Configuration::DDR3Configuration(const TraceDB& tdb) { - // mDeviceDeps = std::make_shared(std::forward(mGetMemspec(tdb)), mGetClk(tdb)); - mDeviceDeps = std::make_shared(std::forward(mGetMemspec(tdb)), mGetClk(tdb)); - +DDR3Configuration::DDR3Configuration(const TraceDB& tdb) +{ + // mDeviceDeps = std::make_shared(std::forward(mGetMemspec(tdb)), mGetClk(tdb)); + mDeviceDeps = std::make_shared( + std::forward(mGetMemspec(tdb)), mGetClk(tdb)); } QString DDR3Configuration::getQueryStr(const std::vector& commands) const { - QString queryStr = "SELECT Phases.ID, Phases.PhaseName, Phases.PhaseBegin, Phases.PhaseEnd, Phases.Transact, Phases.Bank, Phases.Rank " - " FROM Phases " - " WHERE PhaseName IN ("; - - for (const auto& cmd : commands) { + QString queryStr = "SELECT Phases.ID, Phases.PhaseName, Phases.PhaseBegin, Phases.PhaseEnd, " + "Phases.Transact, Phases.Bank, Phases.Rank " + " FROM Phases " + " WHERE PhaseName IN ("; + + for (const auto& cmd : commands) + { queryStr = queryStr + '\"' + cmd + "\","; } - queryStr.back() = ')'; + queryStr.back() = ')'; queryStr += " ORDER BY PhaseBegin; "; return queryStr; } -std::shared_ptr DDR3Configuration::makePhaseEntry(const QSqlQuery& query) const { +std::shared_ptr DDR3Configuration::makePhaseEntry(const QSqlQuery& query) const +{ return std::make_shared(query); } diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR3Configuration.h b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR3Configuration.h index 24168f67..8d4459d5 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR3Configuration.h +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR3Configuration.h @@ -36,15 +36,16 @@ #pragma once #include "businessObjects/dramTimeDependencies/configurations/configurationBase.h" -// #include "businessObjects/dramTimeDependencies/deviceDependencies/specialized/DDR3TimeDependencies.h" -#include "businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR3.h" +// #include +// "businessObjects/dramTimeDependencies/deviceDependencies/specialized/DDR3TimeDependencies.h" #include "businessObjects/dramTimeDependencies/dbEntries/specialized/DDR3dbphaseentry.h" +#include "businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR3.h" -class DDR3Configuration : public ConfigurationBase { - public: +class DDR3Configuration : public ConfigurationBase +{ +public: DDR3Configuration(const TraceDB& tdb); QString getQueryStr(const std::vector& commands) const override; std::shared_ptr makePhaseEntry(const QSqlQuery&) const override; - }; diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR4Configuration.cpp b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR4Configuration.cpp index b043a052..05302de9 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR4Configuration.cpp +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR4Configuration.cpp @@ -37,24 +37,28 @@ DDR4Configuration::DDR4Configuration(const TraceDB& tdb) { - mDeviceDeps = std::make_shared(std::forward(mGetMemspec(tdb)), mGetClk(tdb)); + mDeviceDeps = std::make_shared( + std::forward(mGetMemspec(tdb)), mGetClk(tdb)); } QString DDR4Configuration::getQueryStr(const std::vector& commands) const { - QString queryStr = "SELECT Phases.ID, Phases.PhaseName, Phases.PhaseBegin, Phases.PhaseEnd, Phases.Transact, Phases.Bank, Phases.Bankgroup, Phases.Rank " - " FROM Phases " - " WHERE PhaseName IN ("; - - for (const auto& cmd : commands) { + QString queryStr = "SELECT Phases.ID, Phases.PhaseName, Phases.PhaseBegin, Phases.PhaseEnd, " + "Phases.Transact, Phases.Bank, Phases.Bankgroup, Phases.Rank " + " FROM Phases " + " WHERE PhaseName IN ("; + + for (const auto& cmd : commands) + { queryStr = queryStr + '\"' + cmd + "\","; } - queryStr.back() = ')'; + queryStr.back() = ')'; queryStr += " ORDER BY PhaseBegin; "; return queryStr; } -std::shared_ptr DDR4Configuration::makePhaseEntry(const QSqlQuery& query) const { +std::shared_ptr DDR4Configuration::makePhaseEntry(const QSqlQuery& query) const +{ return std::make_shared(query); } diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR4Configuration.h b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR4Configuration.h index e184602a..b6b95e10 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR4Configuration.h +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR4Configuration.h @@ -36,14 +36,14 @@ #pragma once #include "businessObjects/dramTimeDependencies/configurations/configurationBase.h" -#include "businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR4.h" #include "businessObjects/dramTimeDependencies/dbEntries/specialized/DDR4dbphaseentry.h" +#include "businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR4.h" -class DDR4Configuration : public ConfigurationBase { - public: +class DDR4Configuration : public ConfigurationBase +{ +public: DDR4Configuration(const TraceDB& tdb); QString getQueryStr(const std::vector& commands) const override; std::shared_ptr makePhaseEntry(const QSqlQuery&) const override; - }; diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR5Configuration.cpp b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR5Configuration.cpp index cb3ed7fb..bdc6e67e 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR5Configuration.cpp +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR5Configuration.cpp @@ -36,31 +36,37 @@ #include "DDR5Configuration.h" #include -DDR5Configuration::DDR5Configuration(const TraceDB& tdb) { - mDeviceDeps = std::make_shared(std::forward(mGetMemspec(tdb)), mGetClk(tdb)); - +DDR5Configuration::DDR5Configuration(const TraceDB& tdb) +{ + mDeviceDeps = std::make_shared( + std::forward(mGetMemspec(tdb)), mGetClk(tdb)); } QString DDR5Configuration::getQueryStr(const std::vector& commands) const { - QString queryStr = "SELECT Phases.ID, Phases.PhaseName, Phases.PhaseBegin, Phases.PhaseEnd, Phases.Transact, Phases.Bank, Phases.Bankgroup, Phases.Rank, Phases.BurstLength " - " FROM Phases " - " WHERE PhaseName IN ("; - - for (const auto& cmd : commands) { + QString queryStr = + "SELECT Phases.ID, Phases.PhaseName, Phases.PhaseBegin, Phases.PhaseEnd, Phases.Transact, " + "Phases.Bank, Phases.Bankgroup, Phases.Rank, Phases.BurstLength " + " FROM Phases " + " WHERE PhaseName IN ("; + + for (const auto& cmd : commands) + { queryStr = queryStr + '\"' + cmd + "\","; } - queryStr.back() = ')'; + queryStr.back() = ')'; queryStr += " ORDER BY PhaseBegin; "; return queryStr; } -std::shared_ptr DDR5Configuration::makePhaseEntry(const QSqlQuery& query) const { +std::shared_ptr DDR5Configuration::makePhaseEntry(const QSqlQuery& query) const +{ auto phase = std::make_shared(query); - + auto device = std::dynamic_pointer_cast(mDeviceDeps); - device->rankIDToRankIDs(phase->tRank, phase->tLogicalRank, phase->tPhysicalRank, phase->tDIMMRank); + device->rankIDToRankIDs( + phase->tRank, phase->tLogicalRank, phase->tPhysicalRank, phase->tDIMMRank); device->bankIDToBankInGroup(phase->tLogicalRank, phase->tBank, phase->tBankInGroup); return phase; diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR5Configuration.h b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR5Configuration.h index 47582fb0..c65d60be 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR5Configuration.h +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR5Configuration.h @@ -36,14 +36,14 @@ #pragma once #include "businessObjects/dramTimeDependencies/configurations/configurationBase.h" -#include "businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.h" #include "businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.h" +#include "businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.h" -class DDR5Configuration : public ConfigurationBase { - public: +class DDR5Configuration : public ConfigurationBase +{ +public: DDR5Configuration(const TraceDB& tdb); QString getQueryStr(const std::vector& commands) const override; std::shared_ptr makePhaseEntry(const QSqlQuery&) const override; - }; diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/HBM2Configuration.cpp b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/HBM2Configuration.cpp index 5bfda560..8cb38cca 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/HBM2Configuration.cpp +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/HBM2Configuration.cpp @@ -35,26 +35,30 @@ #include "HBM2Configuration.h" -HBM2Configuration::HBM2Configuration(const TraceDB& tdb) { - mDeviceDeps = std::make_shared(std::forward(mGetMemspec(tdb)), mGetClk(tdb)); - +HBM2Configuration::HBM2Configuration(const TraceDB& tdb) +{ + mDeviceDeps = std::make_shared( + std::forward(mGetMemspec(tdb)), mGetClk(tdb)); } QString HBM2Configuration::getQueryStr(const std::vector& commands) const { - QString queryStr = "SELECT Phases.ID, Phases.PhaseName, Phases.PhaseBegin, Phases.PhaseEnd, Phases.Transact, Phases.Bank, Phases.Bankgroup, Phases.Rank " - " FROM Phases " - " WHERE PhaseName IN ("; - - for (const auto& cmd : commands) { + QString queryStr = "SELECT Phases.ID, Phases.PhaseName, Phases.PhaseBegin, Phases.PhaseEnd, " + "Phases.Transact, Phases.Bank, Phases.Bankgroup, Phases.Rank " + " FROM Phases " + " WHERE PhaseName IN ("; + + for (const auto& cmd : commands) + { queryStr = queryStr + '\"' + cmd + "\","; } - queryStr.back() = ')'; + queryStr.back() = ')'; queryStr += " ORDER BY PhaseBegin; "; return queryStr; } -std::shared_ptr HBM2Configuration::makePhaseEntry(const QSqlQuery& query) const { +std::shared_ptr HBM2Configuration::makePhaseEntry(const QSqlQuery& query) const +{ return std::make_shared(query); } diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/HBM2Configuration.h b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/HBM2Configuration.h index 85dfc567..7182b179 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/HBM2Configuration.h +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/HBM2Configuration.h @@ -36,14 +36,14 @@ #pragma once #include "businessObjects/dramTimeDependencies/configurations/configurationBase.h" -#include "businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoHBM2.h" #include "businessObjects/dramTimeDependencies/dbEntries/specialized/HBM2dbphaseentry.h" +#include "businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoHBM2.h" -class HBM2Configuration : public ConfigurationBase { - public: +class HBM2Configuration : public ConfigurationBase +{ +public: HBM2Configuration(const TraceDB& tdb); QString getQueryStr(const std::vector& commands) const override; std::shared_ptr makePhaseEntry(const QSqlQuery&) const override; - }; diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/LPDDR4Configuration.cpp b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/LPDDR4Configuration.cpp index 0859503f..f30add31 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/LPDDR4Configuration.cpp +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/LPDDR4Configuration.cpp @@ -35,27 +35,32 @@ #include "LPDDR4Configuration.h" -LPDDR4Configuration::LPDDR4Configuration(const TraceDB& tdb) { - // mDeviceDeps = std::make_shared(std::forward(mGetMemspec(tdb)), mGetClk(tdb)); - mDeviceDeps = std::make_shared(std::forward(mGetMemspec(tdb)), mGetClk(tdb)); - +LPDDR4Configuration::LPDDR4Configuration(const TraceDB& tdb) +{ + // mDeviceDeps = std::make_shared(std::forward(mGetMemspec(tdb)), mGetClk(tdb)); + mDeviceDeps = std::make_shared( + std::forward(mGetMemspec(tdb)), mGetClk(tdb)); } QString LPDDR4Configuration::getQueryStr(const std::vector& commands) const { - QString queryStr = "SELECT Phases.ID, Phases.PhaseName, Phases.PhaseBegin, Phases.PhaseEnd, Phases.Transact, Phases.Bank, Phases.Rank " - " FROM Phases " - " WHERE PhaseName IN ("; - - for (const auto& cmd : commands) { + QString queryStr = "SELECT Phases.ID, Phases.PhaseName, Phases.PhaseBegin, Phases.PhaseEnd, " + "Phases.Transact, Phases.Bank, Phases.Rank " + " FROM Phases " + " WHERE PhaseName IN ("; + + for (const auto& cmd : commands) + { queryStr = queryStr + '\"' + cmd + "\","; } - queryStr.back() = ')'; + queryStr.back() = ')'; queryStr += " ORDER BY PhaseBegin; "; return queryStr; } -std::shared_ptr LPDDR4Configuration::makePhaseEntry(const QSqlQuery& query) const { +std::shared_ptr LPDDR4Configuration::makePhaseEntry(const QSqlQuery& query) const +{ return std::make_shared(query); } diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/LPDDR4Configuration.h b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/LPDDR4Configuration.h index d2ec4651..0fbf8306 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/LPDDR4Configuration.h +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/LPDDR4Configuration.h @@ -36,14 +36,14 @@ #pragma once #include "businessObjects/dramTimeDependencies/configurations/configurationBase.h" -#include "businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR4.h" #include "businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR4dbphaseentry.h" +#include "businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR4.h" -class LPDDR4Configuration : public ConfigurationBase { - public: +class LPDDR4Configuration : public ConfigurationBase +{ +public: LPDDR4Configuration(const TraceDB& tdb); QString getQueryStr(const std::vector& commands) const override; std::shared_ptr makePhaseEntry(const QSqlQuery&) const override; - }; diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/LPDDR5Configuration.cpp b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/LPDDR5Configuration.cpp index 453e7fdc..41b14bbe 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/LPDDR5Configuration.cpp +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/LPDDR5Configuration.cpp @@ -36,29 +36,34 @@ #include "LPDDR5Configuration.h" #include -LPDDR5Configuration::LPDDR5Configuration(const TraceDB& tdb) { - mDeviceDeps = std::make_shared(std::forward(mGetMemspec(tdb)), mGetClk(tdb)); - +LPDDR5Configuration::LPDDR5Configuration(const TraceDB& tdb) +{ + mDeviceDeps = std::make_shared( + std::forward(mGetMemspec(tdb)), mGetClk(tdb)); } QString LPDDR5Configuration::getQueryStr(const std::vector& commands) const { - QString queryStr = "SELECT Phases.ID, Phases.PhaseName, Phases.PhaseBegin, Phases.PhaseEnd, Phases.Transact, Phases.Bank, Phases.Bankgroup, Phases.Rank, Phases.BurstLength " - " FROM Phases " - " WHERE PhaseName IN ("; - - for (const auto& cmd : commands) { + QString queryStr = + "SELECT Phases.ID, Phases.PhaseName, Phases.PhaseBegin, Phases.PhaseEnd, Phases.Transact, " + "Phases.Bank, Phases.Bankgroup, Phases.Rank, Phases.BurstLength " + " FROM Phases " + " WHERE PhaseName IN ("; + + for (const auto& cmd : commands) + { queryStr = queryStr + '\"' + cmd + "\","; } - queryStr.back() = ')'; + queryStr.back() = ')'; queryStr += " ORDER BY PhaseBegin; "; return queryStr; } -std::shared_ptr LPDDR5Configuration::makePhaseEntry(const QSqlQuery& query) const { +std::shared_ptr LPDDR5Configuration::makePhaseEntry(const QSqlQuery& query) const +{ auto phase = std::make_shared(query); - + auto device = std::dynamic_pointer_cast(mDeviceDeps); phase->bankOffsetREFP2B = device->getPer2BankOffset(); diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/LPDDR5Configuration.h b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/LPDDR5Configuration.h index c243297a..c3aaa7e9 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/LPDDR5Configuration.h +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/LPDDR5Configuration.h @@ -36,14 +36,14 @@ #pragma once #include "businessObjects/dramTimeDependencies/configurations/configurationBase.h" -#include "businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR5.h" #include "businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR5dbphaseentry.h" +#include "businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR5.h" -class LPDDR5Configuration : public ConfigurationBase { - public: +class LPDDR5Configuration : public ConfigurationBase +{ +public: LPDDR5Configuration(const TraceDB& tdb); QString getQueryStr(const std::vector& commands) const override; std::shared_ptr makePhaseEntry(const QSqlQuery&) const override; - }; diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/dbphaseentryBase.h b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/dbphaseentryBase.h index 9ef0464e..4a153eb5 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/dbphaseentryBase.h +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/dbphaseentryBase.h @@ -37,15 +37,20 @@ #include -#include "businessObjects/phases/phasedependency.h" #include "businessObjects/dramTimeDependencies/common/common.h" +#include "businessObjects/phases/phasedependency.h" -class DBPhaseEntryBase : public std::enable_shared_from_this{ - public: +class DBPhaseEntryBase : public std::enable_shared_from_this +{ +public: DBPhaseEntryBase() = default; virtual ~DBPhaseEntryBase() = default; - - virtual bool potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) { return false; } + + virtual bool potentialDependency(const TimeDependency& dep, + const std::shared_ptr otherPhase) + { + return false; + } size_t id; StringMapper phaseName; diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR3dbphaseentry.cpp b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR3dbphaseentry.cpp index 16f0f143..bfead666 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR3dbphaseentry.cpp +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR3dbphaseentry.cpp @@ -35,7 +35,8 @@ #include "DDR3dbphaseentry.h" -DDR3DBPhaseEntry::DDR3DBPhaseEntry(const QSqlQuery& query) { +DDR3DBPhaseEntry::DDR3DBPhaseEntry(const QSqlQuery& query) +{ id = query.value(0).toLongLong(); phaseName = StringMapper(query.value(1).toString()); phaseBegin = query.value(2).toLongLong(); @@ -45,25 +46,22 @@ DDR3DBPhaseEntry::DDR3DBPhaseEntry(const QSqlQuery& query) { tRank = query.value(6).toLongLong(); } -bool DDR3DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) { +bool DDR3DBPhaseEntry::potentialDependency(const TimeDependency& dep, + const std::shared_ptr otherPhase) +{ auto other = std::dynamic_pointer_cast(otherPhase); - if (!other) return false; + if (!other) + return false; bool isCmdPool = dep.phaseDep == StringMapper::Identifier::CMD_BUS; - bool const skipOnIntraBankAndDifferentBanks = { - dep.depType == DependencyType::IntraBank - && tBank != other->tBank - }; - bool const skipOnIntraRankAndDifferentRanks = { - dep.depType == DependencyType::IntraRank - && tRank != other->tRank - }; - bool const skipOnInterRankAndSameRank = { - dep.depType == DependencyType::InterRank - && tRank == other->tRank - && !isCmdPool - }; - - return !(skipOnIntraBankAndDifferentBanks || skipOnIntraRankAndDifferentRanks || skipOnInterRankAndSameRank); + bool const skipOnIntraBankAndDifferentBanks = {dep.depType == DependencyType::IntraBank && + tBank != other->tBank}; + bool const skipOnIntraRankAndDifferentRanks = {dep.depType == DependencyType::IntraRank && + tRank != other->tRank}; + bool const skipOnInterRankAndSameRank = {dep.depType == DependencyType::InterRank && + tRank == other->tRank && !isCmdPool}; + + return !(skipOnIntraBankAndDifferentBanks || skipOnIntraRankAndDifferentRanks || + skipOnInterRankAndSameRank); } diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR3dbphaseentry.h b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR3dbphaseentry.h index d3440a23..979efc5a 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR3dbphaseentry.h +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR3dbphaseentry.h @@ -37,11 +37,13 @@ #include "businessObjects/dramTimeDependencies/dbEntries/dbphaseentryBase.h" -class DDR3DBPhaseEntry : public DBPhaseEntryBase { - public: +class DDR3DBPhaseEntry : public DBPhaseEntryBase +{ +public: DDR3DBPhaseEntry(const QSqlQuery&); size_t tRank; - bool potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) override; + bool potentialDependency(const TimeDependency& dep, + const std::shared_ptr otherPhase) override; }; diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR4dbphaseentry.cpp b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR4dbphaseentry.cpp index 43d1d999..80c2963a 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR4dbphaseentry.cpp +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR4dbphaseentry.cpp @@ -35,7 +35,8 @@ #include "DDR4dbphaseentry.h" -DDR4DBPhaseEntry::DDR4DBPhaseEntry(const QSqlQuery& query) { +DDR4DBPhaseEntry::DDR4DBPhaseEntry(const QSqlQuery& query) +{ id = query.value(0).toLongLong(); phaseName = StringMapper(query.value(1).toString()); phaseBegin = query.value(2).toLongLong(); @@ -46,34 +47,24 @@ DDR4DBPhaseEntry::DDR4DBPhaseEntry(const QSqlQuery& query) { tRank = query.value(7).toLongLong(); } -bool DDR4DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) { +bool DDR4DBPhaseEntry::potentialDependency(const TimeDependency& dep, + const std::shared_ptr otherPhase) +{ auto other = std::dynamic_pointer_cast(otherPhase); - if (!other) return false; + if (!other) + return false; bool isCmdPool = dep.phaseDep == StringMapper::Identifier::CMD_BUS; - bool const skipOnIntraBankAndDifferentBanks = { - dep.depType == DependencyType::IntraBank - && tBank != other->tBank - }; + bool const skipOnIntraBankAndDifferentBanks = {dep.depType == DependencyType::IntraBank && + tBank != other->tBank}; bool const skipOnIntraBankgroupAndDifferentBankgroup = { - dep.depType == DependencyType::IntraBankGroup - && tBankgroup != other->tBankgroup - }; - bool const skipOnIntraRankAndDifferentRanks = { - dep.depType == DependencyType::IntraRank - && tRank != other->tRank - }; - bool const skipOnInterRankAndSameRank = { - dep.depType == DependencyType::InterRank - && tRank == other->tRank - && !isCmdPool - }; - - return !( - skipOnIntraBankAndDifferentBanks - || skipOnIntraBankgroupAndDifferentBankgroup - || skipOnIntraRankAndDifferentRanks - || skipOnInterRankAndSameRank - ); + dep.depType == DependencyType::IntraBankGroup && tBankgroup != other->tBankgroup}; + bool const skipOnIntraRankAndDifferentRanks = {dep.depType == DependencyType::IntraRank && + tRank != other->tRank}; + bool const skipOnInterRankAndSameRank = {dep.depType == DependencyType::InterRank && + tRank == other->tRank && !isCmdPool}; + + return !(skipOnIntraBankAndDifferentBanks || skipOnIntraBankgroupAndDifferentBankgroup || + skipOnIntraRankAndDifferentRanks || skipOnInterRankAndSameRank); } diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR4dbphaseentry.h b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR4dbphaseentry.h index 939d9506..e30d6a26 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR4dbphaseentry.h +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR4dbphaseentry.h @@ -37,12 +37,14 @@ #include "businessObjects/dramTimeDependencies/dbEntries/dbphaseentryBase.h" -class DDR4DBPhaseEntry : public DBPhaseEntryBase { - public: +class DDR4DBPhaseEntry : public DBPhaseEntryBase +{ +public: DDR4DBPhaseEntry(const QSqlQuery&); size_t tBankgroup; size_t tRank; - bool potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) override; + bool potentialDependency(const TimeDependency& dep, + const std::shared_ptr otherPhase) override; }; diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.cpp b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.cpp index cef343b8..f06be72a 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.cpp +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.cpp @@ -35,7 +35,8 @@ #include "DDR5dbphaseentry.h" -DDR5DBPhaseEntry::DDR5DBPhaseEntry(const QSqlQuery& query) { +DDR5DBPhaseEntry::DDR5DBPhaseEntry(const QSqlQuery& query) +{ id = query.value(0).toLongLong(); phaseName = StringMapper(query.value(1).toString()); phaseBegin = query.value(2).toLongLong(); @@ -45,54 +46,37 @@ DDR5DBPhaseEntry::DDR5DBPhaseEntry(const QSqlQuery& query) { tBankgroup = query.value(6).toLongLong(); tRank = query.value(7).toLongLong(); tBurstLength = query.value(8).toLongLong(); - } -bool DDR5DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) { +bool DDR5DBPhaseEntry::potentialDependency(const TimeDependency& dep, + const std::shared_ptr otherPhase) +{ auto other = std::dynamic_pointer_cast(otherPhase); - if (!other) return false; + if (!other) + return false; - if (dep.passFunction && !dep.passFunction->execute(shared_from_this(), other)) return false; + if (dep.passFunction && !dep.passFunction->execute(shared_from_this(), other)) + return false; bool isCmdPool = dep.phaseDep == StringMapper::Identifier::CMD_BUS; - bool const skipOnIntraBankAndDifferentBanks = { - dep.depType == DependencyType::IntraBank - && tBank != other->tBank - }; + bool const skipOnIntraBankAndDifferentBanks = {dep.depType == DependencyType::IntraBank && + tBank != other->tBank}; bool const skipOnIntraBankgroupAndDifferentBankgroup = { - dep.depType == DependencyType::IntraBankGroup - && tBankgroup != other->tBankgroup - }; + dep.depType == DependencyType::IntraBankGroup && tBankgroup != other->tBankgroup}; bool const skipOnIntraBankInGroupAndDifferentBankInGroup = { - dep.depType == DependencyType::IntraBankInGroup - && tBankInGroup != other->tBankInGroup - }; + dep.depType == DependencyType::IntraBankInGroup && tBankInGroup != other->tBankInGroup}; bool const skipOnIntraLogRankAndDifferentRanks = { - dep.depType == DependencyType::IntraLogicalRank - && tLogicalRank != other->tLogicalRank - }; + dep.depType == DependencyType::IntraLogicalRank && tLogicalRank != other->tLogicalRank}; bool const skipOnIntraPhysRankAndDifferentRanks = { - dep.depType == DependencyType::IntraPhysicalRank - && tPhysicalRank != other->tPhysicalRank - }; + dep.depType == DependencyType::IntraPhysicalRank && tPhysicalRank != other->tPhysicalRank}; bool const skipOnIntraDIMMRankAndDifferentRanks = { - dep.depType == DependencyType::IntraDIMMRank - && tDIMMRank != other->tDIMMRank - }; - bool const skipOnInterDIMMRankAndSameRank = { - dep.depType == DependencyType::InterDIMMRank - && tDIMMRank == other->tDIMMRank - && !isCmdPool - }; - - return !( - skipOnIntraBankAndDifferentBanks - || skipOnIntraBankgroupAndDifferentBankgroup - || skipOnIntraBankInGroupAndDifferentBankInGroup - || skipOnIntraLogRankAndDifferentRanks - || skipOnIntraPhysRankAndDifferentRanks - || skipOnIntraDIMMRankAndDifferentRanks - || skipOnInterDIMMRankAndSameRank - ); + dep.depType == DependencyType::IntraDIMMRank && tDIMMRank != other->tDIMMRank}; + bool const skipOnInterDIMMRankAndSameRank = {dep.depType == DependencyType::InterDIMMRank && + tDIMMRank == other->tDIMMRank && !isCmdPool}; + + return !(skipOnIntraBankAndDifferentBanks || skipOnIntraBankgroupAndDifferentBankgroup || + skipOnIntraBankInGroupAndDifferentBankInGroup || skipOnIntraLogRankAndDifferentRanks || + skipOnIntraPhysRankAndDifferentRanks || skipOnIntraDIMMRankAndDifferentRanks || + skipOnInterDIMMRankAndSameRank); } diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.h b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.h index 97f57dd4..89212d58 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.h +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.h @@ -37,8 +37,9 @@ #include "businessObjects/dramTimeDependencies/dbEntries/dbphaseentryBase.h" -class DDR5DBPhaseEntry : public DBPhaseEntryBase { - public: +class DDR5DBPhaseEntry : public DBPhaseEntryBase +{ +public: DDR5DBPhaseEntry(const QSqlQuery&); size_t tBankgroup; @@ -50,5 +51,6 @@ class DDR5DBPhaseEntry : public DBPhaseEntryBase { size_t tPhysicalRank; size_t tDIMMRank; - bool potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) override; + bool potentialDependency(const TimeDependency& dep, + const std::shared_ptr otherPhase) override; }; diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/HBM2dbphaseentry.cpp b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/HBM2dbphaseentry.cpp index 0e69268f..fa654140 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/HBM2dbphaseentry.cpp +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/HBM2dbphaseentry.cpp @@ -35,7 +35,8 @@ #include "HBM2dbphaseentry.h" -HBM2DBPhaseEntry::HBM2DBPhaseEntry(const QSqlQuery& query) { +HBM2DBPhaseEntry::HBM2DBPhaseEntry(const QSqlQuery& query) +{ id = query.value(0).toLongLong(); phaseName = StringMapper(query.value(1).toString()); phaseBegin = query.value(2).toLongLong(); @@ -46,34 +47,24 @@ HBM2DBPhaseEntry::HBM2DBPhaseEntry(const QSqlQuery& query) { tRank = query.value(7).toLongLong(); } -bool HBM2DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) { +bool HBM2DBPhaseEntry::potentialDependency(const TimeDependency& dep, + const std::shared_ptr otherPhase) +{ auto other = std::dynamic_pointer_cast(otherPhase); - if (!other) return false; + if (!other) + return false; bool isCmdPool = dep.phaseDep == StringMapper::Identifier::CMD_BUS; - bool const skipOnIntraBankAndDifferentBanks = { - dep.depType == DependencyType::IntraBank - && tBank != other->tBank - }; + bool const skipOnIntraBankAndDifferentBanks = {dep.depType == DependencyType::IntraBank && + tBank != other->tBank}; bool const skipOnIntraBankgroupAndDifferentBankgroup = { - dep.depType == DependencyType::IntraBankGroup - && tBankgroup != other->tBankgroup - }; - bool const skipOnIntraRankAndDifferentRanks = { - dep.depType == DependencyType::IntraRank - && tRank != other->tRank - }; - bool const skipOnInterRankAndSameRank = { - dep.depType == DependencyType::InterRank - && tRank == other->tRank - && !isCmdPool - }; - - return !( - skipOnIntraBankAndDifferentBanks - || skipOnIntraBankgroupAndDifferentBankgroup - || skipOnIntraRankAndDifferentRanks - || skipOnInterRankAndSameRank - ); + dep.depType == DependencyType::IntraBankGroup && tBankgroup != other->tBankgroup}; + bool const skipOnIntraRankAndDifferentRanks = {dep.depType == DependencyType::IntraRank && + tRank != other->tRank}; + bool const skipOnInterRankAndSameRank = {dep.depType == DependencyType::InterRank && + tRank == other->tRank && !isCmdPool}; + + return !(skipOnIntraBankAndDifferentBanks || skipOnIntraBankgroupAndDifferentBankgroup || + skipOnIntraRankAndDifferentRanks || skipOnInterRankAndSameRank); } diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/HBM2dbphaseentry.h b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/HBM2dbphaseentry.h index 92633713..67d6f71f 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/HBM2dbphaseentry.h +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/HBM2dbphaseentry.h @@ -37,12 +37,14 @@ #include "businessObjects/dramTimeDependencies/dbEntries/dbphaseentryBase.h" -class HBM2DBPhaseEntry : public DBPhaseEntryBase { - public: +class HBM2DBPhaseEntry : public DBPhaseEntryBase +{ +public: HBM2DBPhaseEntry(const QSqlQuery&); size_t tBankgroup; size_t tRank; - bool potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) override; + bool potentialDependency(const TimeDependency& dep, + const std::shared_ptr otherPhase) override; }; diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR4dbphaseentry.cpp b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR4dbphaseentry.cpp index 14020bf2..4f81c229 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR4dbphaseentry.cpp +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR4dbphaseentry.cpp @@ -35,7 +35,8 @@ #include "LPDDR4dbphaseentry.h" -LPDDR4DBPhaseEntry::LPDDR4DBPhaseEntry(const QSqlQuery& query) { +LPDDR4DBPhaseEntry::LPDDR4DBPhaseEntry(const QSqlQuery& query) +{ id = query.value(0).toLongLong(); phaseName = StringMapper(query.value(1).toString()); phaseBegin = query.value(2).toLongLong(); @@ -45,25 +46,22 @@ LPDDR4DBPhaseEntry::LPDDR4DBPhaseEntry(const QSqlQuery& query) { tRank = query.value(6).toLongLong(); } -bool LPDDR4DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) { +bool LPDDR4DBPhaseEntry::potentialDependency(const TimeDependency& dep, + const std::shared_ptr otherPhase) +{ auto other = std::dynamic_pointer_cast(otherPhase); - if (!other) return false; + if (!other) + return false; bool isCmdPool = dep.phaseDep == StringMapper::Identifier::CMD_BUS; - bool const skipOnIntraBankAndDifferentBanks = { - dep.depType == DependencyType::IntraBank - && tBank != other->tBank - }; - bool const skipOnIntraRankAndDifferentRanks = { - dep.depType == DependencyType::IntraRank - && tRank != other->tRank - }; - bool const skipOnInterRankAndSameRank = { - dep.depType == DependencyType::InterRank - && tRank == other->tRank - && !isCmdPool - }; - - return !(skipOnIntraBankAndDifferentBanks || skipOnIntraRankAndDifferentRanks || skipOnInterRankAndSameRank); + bool const skipOnIntraBankAndDifferentBanks = {dep.depType == DependencyType::IntraBank && + tBank != other->tBank}; + bool const skipOnIntraRankAndDifferentRanks = {dep.depType == DependencyType::IntraRank && + tRank != other->tRank}; + bool const skipOnInterRankAndSameRank = {dep.depType == DependencyType::InterRank && + tRank == other->tRank && !isCmdPool}; + + return !(skipOnIntraBankAndDifferentBanks || skipOnIntraRankAndDifferentRanks || + skipOnInterRankAndSameRank); } diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR4dbphaseentry.h b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR4dbphaseentry.h index 013a98b5..6bfa71f8 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR4dbphaseentry.h +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR4dbphaseentry.h @@ -38,11 +38,13 @@ #include "businessObjects/dramTimeDependencies/dbEntries/dbphaseentryBase.h" -class LPDDR4DBPhaseEntry : public DBPhaseEntryBase { - public: +class LPDDR4DBPhaseEntry : public DBPhaseEntryBase +{ +public: LPDDR4DBPhaseEntry(const QSqlQuery&); size_t tRank; - bool potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) override; + bool potentialDependency(const TimeDependency& dep, + const std::shared_ptr otherPhase) override; }; diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR5dbphaseentry.cpp b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR5dbphaseentry.cpp index 1a2b0ae3..3cdbf00e 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR5dbphaseentry.cpp +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR5dbphaseentry.cpp @@ -35,7 +35,8 @@ #include "LPDDR5dbphaseentry.h" -LPDDR5DBPhaseEntry::LPDDR5DBPhaseEntry(const QSqlQuery& query) { +LPDDR5DBPhaseEntry::LPDDR5DBPhaseEntry(const QSqlQuery& query) +{ id = query.value(0).toLongLong(); phaseName = StringMapper(query.value(1).toString()); phaseBegin = query.value(2).toLongLong(); @@ -47,54 +48,36 @@ LPDDR5DBPhaseEntry::LPDDR5DBPhaseEntry(const QSqlQuery& query) { tBurstLength = query.value(8).toLongLong(); } -bool LPDDR5DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) { +bool LPDDR5DBPhaseEntry::potentialDependency(const TimeDependency& dep, + const std::shared_ptr otherPhase) +{ auto other = std::dynamic_pointer_cast(otherPhase); - if (!other) return false; - - if (dep.passFunction && !dep.passFunction->execute(shared_from_this(), other)) return false; + if (!other) + return false; + if (dep.passFunction && !dep.passFunction->execute(shared_from_this(), other)) + return false; bool isCmdPool = dep.phaseDep == StringMapper::Identifier::CMD_BUS; bool thisIsREFP2B = phaseName == StringMapper::Identifier::REFP2B; bool otherIsREFP2B = dep.phaseDep == StringMapper::Identifier::REFP2B; bool const skipOnIntraBankAndNoBankDep = { - dep.depType == DependencyType::IntraBank - && - ( - ( // If phase is not REFP2B or both are REFP2B, intra bank dependency must occur in the same bank - (!thisIsREFP2B || (thisIsREFP2B && otherIsREFP2B)) - && tBank != other->tBank - ) - || - ( // If phase is REFP2B, "intra bank" dependency must occur in the same bank or in the offset bank - (thisIsREFP2B && !otherIsREFP2B) - && - ( - tBank != other->tBank - && tBank != (other->tBank - bankOffsetREFP2B) - ) - ) - ) - }; + dep.depType == DependencyType::IntraBank && + (( // If phase is not REFP2B or both are REFP2B, intra bank dependency must occur in the + // same bank + (!thisIsREFP2B || (thisIsREFP2B && otherIsREFP2B)) && tBank != other->tBank) || + ( // If phase is REFP2B, "intra bank" dependency must occur in the same bank or in the + // offset bank + (thisIsREFP2B && !otherIsREFP2B) && + (tBank != other->tBank && tBank != (other->tBank - bankOffsetREFP2B))))}; bool const skipOnIntraBankgroupAndDifferentBankgroup = { - dep.depType == DependencyType::IntraBankGroup - && tBankgroup != other->tBankgroup - }; - bool const skipOnIntraRankAndDifferentRanks = { - dep.depType == DependencyType::IntraRank - && tRank != other->tRank - }; - bool const skipOnInterRankAndSameRank = { - dep.depType == DependencyType::InterRank - && tRank == other->tRank - && !isCmdPool - }; - - return !( - skipOnIntraBankAndNoBankDep - || skipOnIntraBankgroupAndDifferentBankgroup - || skipOnIntraRankAndDifferentRanks - || skipOnInterRankAndSameRank - ); + dep.depType == DependencyType::IntraBankGroup && tBankgroup != other->tBankgroup}; + bool const skipOnIntraRankAndDifferentRanks = {dep.depType == DependencyType::IntraRank && + tRank != other->tRank}; + bool const skipOnInterRankAndSameRank = {dep.depType == DependencyType::InterRank && + tRank == other->tRank && !isCmdPool}; + + return !(skipOnIntraBankAndNoBankDep || skipOnIntraBankgroupAndDifferentBankgroup || + skipOnIntraRankAndDifferentRanks || skipOnInterRankAndSameRank); } diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR5dbphaseentry.h b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR5dbphaseentry.h index e5204cd8..038aabe8 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR5dbphaseentry.h +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR5dbphaseentry.h @@ -37,8 +37,9 @@ #include "businessObjects/dramTimeDependencies/dbEntries/dbphaseentryBase.h" -class LPDDR5DBPhaseEntry : public DBPhaseEntryBase { - public: +class LPDDR5DBPhaseEntry : public DBPhaseEntryBase +{ +public: LPDDR5DBPhaseEntry(const QSqlQuery&); size_t tBankgroup; @@ -46,5 +47,6 @@ class LPDDR5DBPhaseEntry : public DBPhaseEntryBase { size_t tBurstLength; size_t bankOffsetREFP2B; - bool potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) override; + bool potentialDependency(const TimeDependency& dep, + const std::shared_ptr otherPhase) override; }; diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/dramtimedependenciesbase.cpp b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/dramtimedependenciesbase.cpp index a3ce9db2..8fa2c438 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/dramtimedependenciesbase.cpp +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/dramtimedependenciesbase.cpp @@ -37,28 +37,28 @@ #include -DRAMTimeDependenciesBase::DRAMTimeDependenciesBase(const QJsonObject& memspec, const uint inTCK) { +DRAMTimeDependenciesBase::DRAMTimeDependenciesBase(const QJsonObject& memspec, const uint inTCK) +{ mMemspecJson = memspec; tCK = inTCK; - } DependencyMap -DRAMTimeDependenciesBase::getDependencies(std::vector& dependencyFilter) const { +DRAMTimeDependenciesBase::getDependencies(std::vector& dependencyFilter) const +{ DependencyMap dependenciesMap; - std::vector dependencyFilterStrMapper(dependencyFilter.begin(), dependencyFilter.end()); - std::sort( - dependencyFilterStrMapper.begin(), - dependencyFilterStrMapper.end() - ); - + std::vector dependencyFilterStrMapper(dependencyFilter.begin(), + dependencyFilter.end()); + std::sort(dependencyFilterStrMapper.begin(), dependencyFilterStrMapper.end()); + dependenciesMap = mSpecializedGetDependencies(); - + mFilterDependencyMap(dependenciesMap, dependencyFilterStrMapper); auto it = dependenciesMap.begin(); - while (it != dependenciesMap.end()) { + while (it != dependenciesMap.end()) + { mFilterDependencyList(it->second.dependencies, dependencyFilterStrMapper); it->second.maxTime = mFindVectorMaximum(it->second.dependencies); @@ -68,13 +68,17 @@ DRAMTimeDependenciesBase::getDependencies(std::vector& dependencyFilter return dependenciesMap; } -PoolControllerMap DRAMTimeDependenciesBase::getPools() const { +PoolControllerMap DRAMTimeDependenciesBase::getPools() const +{ return PoolControllerMap(mPools); } -void DRAMTimeDependenciesBase::mFilterDependencyList(std::vector& dependencyList, const std::vector& dependencyFilter) const { +void DRAMTimeDependenciesBase::mFilterDependencyList( + std::vector& dependencyList, + const std::vector& dependencyFilter) const +{ std::vector newDepList(dependencyList.size()); - + // TODO - probably there is a smarter way to filter these values, // although the lists are not to be greater than 20-50 elements @@ -82,93 +86,87 @@ void DRAMTimeDependenciesBase::mFilterDependencyList(std::vector dependencyList.begin(), dependencyList.end(), newDepList.begin(), - [ dependencyFilter ](const TimeDependency& dep) { - auto it = std::lower_bound( - dependencyFilter.begin(), - dependencyFilter.end(), - dep.phaseDep, - [](const StringMapper& cmd, const StringMapper& depName){ - return depName.isPool() || cmd < depName; - } - ); + [dependencyFilter](const TimeDependency& dep) + { + auto it = std::lower_bound(dependencyFilter.begin(), + dependencyFilter.end(), + dep.phaseDep, + [](const StringMapper& cmd, const StringMapper& depName) + { return depName.isPool() || cmd < depName; }); - if (dep.phaseDep.isPool() || it != dependencyFilter.end() && *it == dep.phaseDep) + if (dep.phaseDep.isPool() || it != dependencyFilter.end() && *it == dep.phaseDep) return true; return false; - } - ); + }); newDepList.shrink_to_fit(); dependencyList = newDepList; - std::sort( - dependencyList.begin(), - dependencyList.end(), - [](const TimeDependency& v1, const TimeDependency& v2) { - return v1.timeValue < v2.timeValue; - } - ); - + std::sort(dependencyList.begin(), + dependencyList.end(), + [](const TimeDependency& v1, const TimeDependency& v2) + { return v1.timeValue < v2.timeValue; }); } -void DRAMTimeDependenciesBase::mFilterDependencyMap(DependencyMap& dependencyMap, const std::vector& dependencyFilter) const { - if (!dependencyMap.empty()) { +void DRAMTimeDependenciesBase::mFilterDependencyMap( + DependencyMap& dependencyMap, const std::vector& dependencyFilter) const +{ + if (!dependencyMap.empty()) + { auto itFilter = dependencyFilter.begin(); auto itFilterLast = std::lower_bound( - dependencyFilter.begin(), - dependencyFilter.end(), - dependencyMap.rbegin()->first - ); + dependencyFilter.begin(), dependencyFilter.end(), dependencyMap.rbegin()->first); auto itDependencyMap = dependencyMap.begin(); - while (true) { + while (true) + { - auto pair = std::mismatch( - itFilter, - itFilterLast, - itDependencyMap, - [](const StringMapper& cmd, const std::pair& vpair) { - return cmd == vpair.first; - } - ); + auto pair = + std::mismatch(itFilter, + itFilterLast, + itDependencyMap, + [](const StringMapper& cmd, + const std::pair& vpair) + { return cmd == vpair.first; }); - if (pair.first == dependencyFilter.end() || pair.second == dependencyMap.end()) { + if (pair.first == dependencyFilter.end() || pair.second == dependencyMap.end()) + { dependencyMap.erase(pair.second, dependencyMap.end()); break; - - } else if (*(pair.first) < pair.second->first) { + } + else if (*(pair.first) < pair.second->first) + { ++(pair.first); - - } else if (*(pair.first) == pair.second->first) { + } + else if (*(pair.first) == pair.second->first) + { ++(pair.second); - - } else { + } + else + { pair.second = dependencyMap.erase(pair.second); - } itFilter = pair.first; itDependencyMap = pair.second; - } } - } -uint DRAMTimeDependenciesBase::mFindVectorMaximum(const std::vector& dependencyList) const { - auto maxElement = std::max_element( - dependencyList.begin(), - dependencyList.end(), - [](const TimeDependency& dep1, const TimeDependency& dep2) { - return dep1.timeValue < dep2.timeValue; - } - ); +uint DRAMTimeDependenciesBase::mFindVectorMaximum( + const std::vector& dependencyList) const +{ + auto maxElement = std::max_element(dependencyList.begin(), + dependencyList.end(), + [](const TimeDependency& dep1, const TimeDependency& dep2) + { return dep1.timeValue < dep2.timeValue; }); - if (maxElement == dependencyList.end()) return 0; + if (maxElement == dependencyList.end()) + return 0; return maxElement->timeValue; } diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/dramtimedependenciesbase.h b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/dramtimedependenciesbase.h index c5d31cd9..f3edc13d 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/dramtimedependenciesbase.h +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/dramtimedependenciesbase.h @@ -35,11 +35,12 @@ #pragma once -#include "data/tracedb.h" #include "businessObjects/dramTimeDependencies/common/common.h" +#include "data/tracedb.h" #include "poolcontrollermap.h" -class DRAMTimeDependenciesBase { +class DRAMTimeDependenciesBase +{ public: DRAMTimeDependenciesBase(const QJsonObject& memspec, const uint tCK); virtual ~DRAMTimeDependenciesBase() = default; @@ -51,21 +52,25 @@ public: PoolControllerMap getPools() const; protected: - void mFilterDependencyList(std::vector& dependencyList, const std::vector& dependencyFilter) const; - void mFilterDependencyMap(DependencyMap& dependencyMap, const std::vector& dependencyFilter) const; + void mFilterDependencyList(std::vector& dependencyList, + const std::vector& dependencyFilter) const; + void mFilterDependencyMap(DependencyMap& dependencyMap, + const std::vector& dependencyFilter) const; uint mFindVectorMaximum(const std::vector& dependencyList) const; - + protected: QJsonObject mMemspecJson; -// To be implemented by the specializing class + // To be implemented by the specializing class protected: - virtual void mInitializeValues() {} ; - virtual DependencyMap mSpecializedGetDependencies() const { DependencyMap map; return map; } ; - + virtual void mInitializeValues(){}; + virtual DependencyMap mSpecializedGetDependencies() const + { + DependencyMap map; + return map; + }; + uint tCK = 0; std::map mPools; - }; - diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontroller.cpp b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontroller.cpp index 93f5f438..d0e2ede8 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontroller.cpp +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontroller.cpp @@ -36,62 +36,62 @@ #include "poolcontroller.h" #include -PoolController::PoolController(const uint poolSize, const std::vector& dependencies) -: mDependencies(mAuxSortInput(dependencies)) +PoolController::PoolController(const uint poolSize, const std::vector& dependencies) : + mDependencies(mAuxSortInput(dependencies)) { mPoolSize = poolSize; - } -void PoolController::clear() { +void PoolController::clear() +{ mPool.clear(); mCount = 0; - } -void PoolController::push(DBDependencyEntry dep) { +void PoolController::push(DBDependencyEntry dep) +{ mPool.push_back(dep); mCount++; - } -void PoolController::increment() { +void PoolController::increment() +{ mCount++; } -void PoolController::merge(std::vector& depEntries) { - if(mCount >= mPoolSize) { - depEntries.insert( depEntries.end(), mPool.begin(), mPool.end() ); +void PoolController::merge(std::vector& depEntries) +{ + if (mCount >= mPoolSize) + { + depEntries.insert(depEntries.end(), mPool.begin(), mPool.end()); } } -uint PoolController::getBusyTime(const StringMapper& phaseName) { +uint PoolController::getBusyTime(const StringMapper& phaseName) +{ PoolEntry v{phaseName, 0}; - auto entryIt = std::lower_bound( - mDependencies.begin(), - mDependencies.end(), - v, - [](const PoolEntry& e1, const PoolEntry& e2) { - return e1.first < e2.first; - } - ); + auto entryIt = std::lower_bound(mDependencies.begin(), + mDependencies.end(), + v, + [](const PoolEntry& e1, const PoolEntry& e2) + { return e1.first < e2.first; }); - if (entryIt->first == phaseName) { + if (entryIt->first == phaseName) + { return entryIt->second; - } else { + } + else + { return 0; } } -std::vector PoolController::mAuxSortInput(std::vector vec) { - std::sort( - vec.begin(), - vec.end(), - [](const PoolEntry& e1, const PoolEntry& e2) { - return e1.first < e2.first; - } - ); +std::vector PoolController::mAuxSortInput(std::vector vec) +{ + std::sort(vec.begin(), + vec.end(), + [](const PoolEntry& e1, const PoolEntry& e2) { return e1.first < e2.first; }); return vec; } \ No newline at end of file diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontroller.h b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontroller.h index 954f4e3b..384ef4ee 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontroller.h +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontroller.h @@ -39,7 +39,8 @@ typedef std::pair PoolEntry; -class PoolController { +class PoolController +{ public: PoolController(const uint poolSize, const std::vector& dependencies); ~PoolController() = default; @@ -49,7 +50,7 @@ public: void increment(); void merge(std::vector& depEntries); size_t count() { return mCount; } - + uint getBusyTime(const StringMapper& phaseName); protected: diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontrollermap.cpp b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontrollermap.cpp index 04997fa8..ce1e40e3 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontrollermap.cpp +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontrollermap.cpp @@ -35,63 +35,77 @@ #include "poolcontrollermap.h" -PoolControllerMap::PoolControllerMap(const std::map& pools) { +PoolControllerMap::PoolControllerMap(const std::map& pools) +{ mPools = pools; } -void PoolControllerMap::clear() { - for (auto& p : mPools) { +void PoolControllerMap::clear() +{ + for (auto& p : mPools) + { p.second.clear(); } - } -void PoolControllerMap::push(const StringMapper& poolName, DBDependencyEntry dep) { +void PoolControllerMap::push(const StringMapper& poolName, DBDependencyEntry dep) +{ auto pool = mPools.find(poolName); - if (pool != mPools.end()) { + if (pool != mPools.end()) + { pool->second.push(dep); - - } else { + } + else + { // TODO throw? } } -void PoolControllerMap::increment(const StringMapper& poolName) { +void PoolControllerMap::increment(const StringMapper& poolName) +{ auto pool = mPools.find(poolName); - if (pool != mPools.end()) { + if (pool != mPools.end()) + { pool->second.increment(); - - } else { + } + else + { // TODO throw? } } -void PoolControllerMap::merge(std::vector& depEntries) { - for (auto& p : mPools) { +void PoolControllerMap::merge(std::vector& depEntries) +{ + for (auto& p : mPools) + { p.second.merge(depEntries); } } -uint PoolControllerMap::getBusyTime(const StringMapper& poolName, const StringMapper& phaseName) { +uint PoolControllerMap::getBusyTime(const StringMapper& poolName, const StringMapper& phaseName) +{ auto pool = mPools.find(poolName); - if (pool != mPools.end()) { + if (pool != mPools.end()) + { return pool->second.getBusyTime(phaseName); - - } else { + } + else + { // TODO throw? return 0; - } } -size_t PoolControllerMap::count(const StringMapper& poolName) { +size_t PoolControllerMap::count(const StringMapper& poolName) +{ auto pool = mPools.find(poolName); - if (pool != mPools.end()) { + if (pool != mPools.end()) + { return pool->second.count(); - - } else { + } + else + { // TODO throw? return 0; - } } diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontrollermap.h b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontrollermap.h index 6fa6350c..fe7d5764 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontrollermap.h +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontrollermap.h @@ -37,7 +37,8 @@ #include "poolcontroller.h" -class PoolControllerMap { +class PoolControllerMap +{ public: PoolControllerMap(const std::map& pools); ~PoolControllerMap() = default; @@ -50,8 +51,6 @@ public: uint getBusyTime(const StringMapper& poolName, const StringMapper& phaseName); - protected: std::map mPools; - }; diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/DDR3TimeDependencies.cpp b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/DDR3TimeDependencies.cpp index b2f5896c..8d46adc6 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/DDR3TimeDependencies.cpp +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/DDR3TimeDependencies.cpp @@ -37,11 +37,14 @@ using namespace std; -DDR3TimeDependencies::DDR3TimeDependencies(const QJsonObject& memspec, const uint tCK) : DRAMTimeDependenciesBase(memspec, tCK) { +DDR3TimeDependencies::DDR3TimeDependencies(const QJsonObject& memspec, const uint tCK) : + DRAMTimeDependenciesBase(memspec, tCK) +{ mInitializeValues(); } -void DDR3TimeDependencies::mInitializeValues() { +void DDR3TimeDependencies::mInitializeValues() +{ burstLength = mMemspecJson["memarchitecturespec"].toObject()["burstLength"].toInt(); dataRate = mMemspecJson["memarchitecturespec"].toObject()["dataRate"].toInt(); @@ -71,9 +74,9 @@ void DDR3TimeDependencies::mInitializeValues() { tPRPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["PRPDEN"].toInt(); tREFPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["REFPDEN"].toInt(); tCKE = tCK * mMemspecJson["memtimingspec"].toObject()["CKE"].toInt(); - + tPD = tCKE; - tBURST = (uint) ((burstLength / (float) dataRate) * tCK); + tBURST = (uint)((burstLength / (float)dataRate) * tCK); tRDWR = tRL + tBURST + 2 * tCK - tWL; tRDWR_R = tRL + tBURST + tRTRS - tWL; tWRRD = tWL + tBURST + tWTR; @@ -83,31 +86,29 @@ void DDR3TimeDependencies::mInitializeValues() { tWRPDEN = tWL + tBURST + tWR; tWRAPDEN = tWL + tBURST + tWR + tCK; - mPools.insert({ - "CMD_BUS", { - 1, { - {"ACT", tCK}, - {"RD", tCK}, - {"WR", tCK}, - {"PREPB", tCK}, - {"RDA", tCK}, - {"WRA", tCK}, - {"REFAB", tCK}, - {"PREAB", tCK}, - {"PDEP", tCK}, - {"PDXP", tCK}, - {"SREFEN", tCK}, - {"SREFEX", tCK}, - {"PDEA", tCK}, - {"PDXA", tCK}, - } - } - }); + mPools.insert({"CMD_BUS", + {1, + { + {"ACT", tCK}, + {"RD", tCK}, + {"WR", tCK}, + {"PREPB", tCK}, + {"RDA", tCK}, + {"WRA", tCK}, + {"REFAB", tCK}, + {"PREAB", tCK}, + {"PDEP", tCK}, + {"PDXP", tCK}, + {"SREFEN", tCK}, + {"SREFEX", tCK}, + {"PDEA", tCK}, + {"PDXA", tCK}, + }}}); mPools.insert({"NAW", {4, {{"ACT", tFAW}}}}); - } -const vector DDR3TimeDependencies::getPossiblePhases() { +const vector DDR3TimeDependencies::getPossiblePhases() +{ return {"ACT", "RD", "RDA", @@ -121,252 +122,202 @@ const vector DDR3TimeDependencies::getPossiblePhases() { "PDEP", "PDXP", "SREFEN", - "SREFEX" - }; + "SREFEX"}; } -DependencyMap DDR3TimeDependencies::mSpecializedGetDependencies() const { +DependencyMap DDR3TimeDependencies::mSpecializedGetDependencies() const +{ DependencyMap dmap; - dmap.emplace( - piecewise_construct, - forward_as_tuple("ACT"), - forward_as_tuple( - initializer_list{ - {tRC, "ACT", DependencyType::IntraBank, "tRC"}, - {tAL + tRTP + tRP, "RDA", DependencyType::IntraBank, "tAL + tRTP + tRP"}, - {tWRPRE + tRP, "WRA", DependencyType::IntraBank, "tWRPRE + tRP"}, - {tRP, "PREPB", DependencyType::IntraBank, "tRP"}, - {tRRD, "ACT", DependencyType::IntraRank, "tRRD"}, - {tRP, "PREAB", DependencyType::IntraRank, "tRP"}, - {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, - {tXP, "PDXP", DependencyType::IntraRank, "tXP"}, - {tRFC, "REFAB", DependencyType::IntraRank, "tRFC"}, - {tXS, "SREFEX", DependencyType::IntraRank, "tXS"}, - {tCK, "CMD_BUS", DependencyType::InterRank, "CMD_BUS"}, - {tFAW, "NAW", DependencyType::IntraRank, "tFAW"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("ACT"), + forward_as_tuple(initializer_list{ + {tRC, "ACT", DependencyType::IntraBank, "tRC"}, + {tAL + tRTP + tRP, "RDA", DependencyType::IntraBank, "tAL + tRTP + tRP"}, + {tWRPRE + tRP, "WRA", DependencyType::IntraBank, "tWRPRE + tRP"}, + {tRP, "PREPB", DependencyType::IntraBank, "tRP"}, + {tRRD, "ACT", DependencyType::IntraRank, "tRRD"}, + {tRP, "PREAB", DependencyType::IntraRank, "tRP"}, + {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, + {tXP, "PDXP", DependencyType::IntraRank, "tXP"}, + {tRFC, "REFAB", DependencyType::IntraRank, "tRFC"}, + {tXS, "SREFEX", DependencyType::IntraRank, "tXS"}, + {tCK, "CMD_BUS", DependencyType::InterRank, "CMD_BUS"}, + {tFAW, "NAW", DependencyType::IntraRank, "tFAW"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("RD"), - forward_as_tuple( - initializer_list{ - {tRCD - tAL, "ACT", DependencyType::IntraBank, "tRCD - tAL"}, - {tCCD, "RD", DependencyType::IntraRank, "tCCD"}, - {tCCD, "RDA", DependencyType::IntraRank, "tCCD"}, - {tWRRD, "WR", DependencyType::IntraRank, "tWRRD"}, - {tWRRD, "WRA", DependencyType::IntraRank, "tWRRD"}, - {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, - {tXSDLL, "SREFEX", DependencyType::IntraRank, "tXSDLL"}, - {tBURST + tRTRS, "RD", DependencyType::InterRank, "tBURST + tRTRS"}, - {tBURST + tRTRS, "RDA", DependencyType::InterRank, "tBURST + tRTRS"}, - {tWRRD_R, "WR", DependencyType::InterRank, "tWRRD_R"}, - {tWRRD_R, "WRA", DependencyType::InterRank, "tWRRD_R"}, - {tCK, "CMD_BUS", DependencyType::InterRank, "CMD_BUS"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("RD"), + forward_as_tuple(initializer_list{ + {tRCD - tAL, "ACT", DependencyType::IntraBank, "tRCD - tAL"}, + {tCCD, "RD", DependencyType::IntraRank, "tCCD"}, + {tCCD, "RDA", DependencyType::IntraRank, "tCCD"}, + {tWRRD, "WR", DependencyType::IntraRank, "tWRRD"}, + {tWRRD, "WRA", DependencyType::IntraRank, "tWRRD"}, + {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, + {tXSDLL, "SREFEX", DependencyType::IntraRank, "tXSDLL"}, + {tBURST + tRTRS, "RD", DependencyType::InterRank, "tBURST + tRTRS"}, + {tBURST + tRTRS, "RDA", DependencyType::InterRank, "tBURST + tRTRS"}, + {tWRRD_R, "WR", DependencyType::InterRank, "tWRRD_R"}, + {tWRRD_R, "WRA", DependencyType::InterRank, "tWRRD_R"}, + {tCK, "CMD_BUS", DependencyType::InterRank, "CMD_BUS"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("RDA"), - forward_as_tuple( - initializer_list{ - {tRCD - tAL, "ACT", DependencyType::IntraBank, "tRCD - tAL"}, - {tWRPRE - tRTP, "WR", DependencyType::IntraBank, "tWRPRE - tRTP"}, - {tCCD, "RD", DependencyType::IntraRank, "tCCD"}, - {tCCD, "RDA", DependencyType::IntraRank, "tCCD"}, - {tWRRD, "WR", DependencyType::IntraRank, "tWRRD"}, - {tWRRD, "WRA", DependencyType::IntraRank, "tWRRD"}, - {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, - {tXSDLL, "SREFEX", DependencyType::IntraRank, "tXSDLL"}, - {tBURST + tRTRS, "RD", DependencyType::InterRank, "tBURST + tRTRS"}, - {tBURST + tRTRS, "RDA", DependencyType::InterRank, "tBURST + tRTRS"}, - {tWRRD_R, "WR", DependencyType::InterRank, "tWRRD_R"}, - {tWRRD_R, "WRA", DependencyType::InterRank, "tWRRD_R"}, - {tCK, "CMD_BUS", DependencyType::InterRank, "CMD_BUS"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("RDA"), + forward_as_tuple(initializer_list{ + {tRCD - tAL, "ACT", DependencyType::IntraBank, "tRCD - tAL"}, + {tWRPRE - tRTP, "WR", DependencyType::IntraBank, "tWRPRE - tRTP"}, + {tCCD, "RD", DependencyType::IntraRank, "tCCD"}, + {tCCD, "RDA", DependencyType::IntraRank, "tCCD"}, + {tWRRD, "WR", DependencyType::IntraRank, "tWRRD"}, + {tWRRD, "WRA", DependencyType::IntraRank, "tWRRD"}, + {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, + {tXSDLL, "SREFEX", DependencyType::IntraRank, "tXSDLL"}, + {tBURST + tRTRS, "RD", DependencyType::InterRank, "tBURST + tRTRS"}, + {tBURST + tRTRS, "RDA", DependencyType::InterRank, "tBURST + tRTRS"}, + {tWRRD_R, "WR", DependencyType::InterRank, "tWRRD_R"}, + {tWRRD_R, "WRA", DependencyType::InterRank, "tWRRD_R"}, + {tCK, "CMD_BUS", DependencyType::InterRank, "CMD_BUS"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("WR"), - forward_as_tuple( - initializer_list{ - {tRCD - tAL, "ACT", DependencyType::IntraBank, "tRCD - tAL"}, - {tRDWR, "RD", DependencyType::IntraRank, "tRDWR"}, - {tRDWR, "RDA", DependencyType::IntraRank, "tRDWR"}, - {tCCD, "WR", DependencyType::IntraRank, "tCCD"}, - {tCCD, "WRA", DependencyType::IntraRank, "tCCD"}, - {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, - {tXSDLL, "SREFEX", DependencyType::IntraRank, "tXSDLL"}, - {tRDWR_R, "RD", DependencyType::InterRank, "tRDWR_R"}, - {tRDWR_R, "RDA", DependencyType::InterRank, "tRDWR_R"}, - {tBURST + tRTRS, "WR", DependencyType::InterRank, "tBURST + tRTRS"}, - {tBURST + tRTRS, "WRA", DependencyType::InterRank, "tBURST + tRTRS"}, - {tCK, "CMD_BUS", DependencyType::InterRank, "CMD_BUS"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("WR"), + forward_as_tuple(initializer_list{ + {tRCD - tAL, "ACT", DependencyType::IntraBank, "tRCD - tAL"}, + {tRDWR, "RD", DependencyType::IntraRank, "tRDWR"}, + {tRDWR, "RDA", DependencyType::IntraRank, "tRDWR"}, + {tCCD, "WR", DependencyType::IntraRank, "tCCD"}, + {tCCD, "WRA", DependencyType::IntraRank, "tCCD"}, + {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, + {tXSDLL, "SREFEX", DependencyType::IntraRank, "tXSDLL"}, + {tRDWR_R, "RD", DependencyType::InterRank, "tRDWR_R"}, + {tRDWR_R, "RDA", DependencyType::InterRank, "tRDWR_R"}, + {tBURST + tRTRS, "WR", DependencyType::InterRank, "tBURST + tRTRS"}, + {tBURST + tRTRS, "WRA", DependencyType::InterRank, "tBURST + tRTRS"}, + {tCK, "CMD_BUS", DependencyType::InterRank, "CMD_BUS"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("WRA"), - forward_as_tuple( - initializer_list{ - {tRCD - tAL, "ACT", DependencyType::IntraBank, "tRCD - tAL"}, - {tRDWR, "RD", DependencyType::IntraRank, "tRDWR"}, - {tRDWR, "RDA", DependencyType::IntraRank, "tRDWR"}, - {tCCD, "WR", DependencyType::IntraRank, "tCCD"}, - {tCCD, "WRA", DependencyType::IntraRank, "tCCD"}, - {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, - {tXSDLL, "SREFEX", DependencyType::IntraRank, "tXSDLL"}, - {tRDWR_R, "RD", DependencyType::InterRank, "tRDWR_R"}, - {tRDWR_R, "RDA", DependencyType::InterRank, "tRDWR_R"}, - {tBURST + tRTRS, "WR", DependencyType::InterRank, "tBURST + tRTRS"}, - {tBURST + tRTRS, "WRA", DependencyType::InterRank, "tBURST + tRTRS"}, - {tCK, "CMD_BUS", DependencyType::InterRank, "CMD_BUS"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("WRA"), + forward_as_tuple(initializer_list{ + {tRCD - tAL, "ACT", DependencyType::IntraBank, "tRCD - tAL"}, + {tRDWR, "RD", DependencyType::IntraRank, "tRDWR"}, + {tRDWR, "RDA", DependencyType::IntraRank, "tRDWR"}, + {tCCD, "WR", DependencyType::IntraRank, "tCCD"}, + {tCCD, "WRA", DependencyType::IntraRank, "tCCD"}, + {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, + {tXSDLL, "SREFEX", DependencyType::IntraRank, "tXSDLL"}, + {tRDWR_R, "RD", DependencyType::InterRank, "tRDWR_R"}, + {tRDWR_R, "RDA", DependencyType::InterRank, "tRDWR_R"}, + {tBURST + tRTRS, "WR", DependencyType::InterRank, "tBURST + tRTRS"}, + {tBURST + tRTRS, "WRA", DependencyType::InterRank, "tBURST + tRTRS"}, + {tCK, "CMD_BUS", DependencyType::InterRank, "CMD_BUS"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("PREPB"), - forward_as_tuple( - initializer_list{ - {tRAS, "ACT", DependencyType::IntraBank, "tRAS"}, - {tAL + tRTP, "RD", DependencyType::IntraBank, "tAL + tRTP"}, - {tWRPRE, "WR", DependencyType::IntraBank, "tWRPRE"}, - {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, - {tCK, "CMD_BUS", DependencyType::InterRank, "CMD_BUS"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("PREPB"), + forward_as_tuple(initializer_list{ + {tRAS, "ACT", DependencyType::IntraBank, "tRAS"}, + {tAL + tRTP, "RD", DependencyType::IntraBank, "tAL + tRTP"}, + {tWRPRE, "WR", DependencyType::IntraBank, "tWRPRE"}, + {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, + {tCK, "CMD_BUS", DependencyType::InterRank, "CMD_BUS"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("PREAB"), - forward_as_tuple( - initializer_list{ - {tRAS, "ACT", DependencyType::IntraRank, "tRAS"}, - {tAL + tRTP, "RD", DependencyType::IntraRank, "tAL + tRTP"}, - {tAL + tRTP, "RDA", DependencyType::IntraRank, "tAL + tRTP"}, - {tWRPRE, "WR", DependencyType::IntraRank, "tWRPRE"}, - {tWRPRE, "WRA", DependencyType::IntraRank, "tWRPRE"}, - {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, - {tCK, "CMD_BUS", DependencyType::InterRank, "CMD_BUS"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("PREAB"), + forward_as_tuple(initializer_list{ + {tRAS, "ACT", DependencyType::IntraRank, "tRAS"}, + {tAL + tRTP, "RD", DependencyType::IntraRank, "tAL + tRTP"}, + {tAL + tRTP, "RDA", DependencyType::IntraRank, "tAL + tRTP"}, + {tWRPRE, "WR", DependencyType::IntraRank, "tWRPRE"}, + {tWRPRE, "WRA", DependencyType::IntraRank, "tWRPRE"}, + {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, + {tCK, "CMD_BUS", DependencyType::InterRank, "CMD_BUS"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("REFAB"), - forward_as_tuple( - initializer_list{ - {tRC, "ACT", DependencyType::IntraRank, "tRC"}, - {tAL + tRTP + tRP, "RDA", DependencyType::IntraRank, "tAL + tRTP + tRP"}, - {tWRPRE + tRP, "WRA", DependencyType::IntraRank, "tWRPRE + tRP"}, - {tRP, "PREPB", DependencyType::IntraRank, "tRP"}, - {tRP, "PREAB", DependencyType::IntraRank, "tRP"}, - {tXP, "PDXP", DependencyType::IntraRank, "tXP"}, - {tRFC, "REFAB", DependencyType::IntraRank, "tRFC"}, - {tXS, "SREFEX", DependencyType::IntraRank, "tXS"}, - {tCK, "CMD_BUS", DependencyType::InterRank, "CMD_BUS"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("REFAB"), + forward_as_tuple(initializer_list{ + {tRC, "ACT", DependencyType::IntraRank, "tRC"}, + {tAL + tRTP + tRP, "RDA", DependencyType::IntraRank, "tAL + tRTP + tRP"}, + {tWRPRE + tRP, "WRA", DependencyType::IntraRank, "tWRPRE + tRP"}, + {tRP, "PREPB", DependencyType::IntraRank, "tRP"}, + {tRP, "PREAB", DependencyType::IntraRank, "tRP"}, + {tXP, "PDXP", DependencyType::IntraRank, "tXP"}, + {tRFC, "REFAB", DependencyType::IntraRank, "tRFC"}, + {tXS, "SREFEX", DependencyType::IntraRank, "tXS"}, + {tCK, "CMD_BUS", DependencyType::InterRank, "CMD_BUS"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("PDEA"), - forward_as_tuple( - initializer_list{ - {tACTPDEN, "ACT", DependencyType::IntraRank, "tACTPDEN"}, - {tRDPDEN, "RD", DependencyType::IntraRank, "tRDPDEN"}, - {tRDPDEN, "RDA", DependencyType::IntraRank, "tRDPDEN"}, - {tWRPDEN, "WR", DependencyType::IntraRank, "tWRPDEN"}, - {tWRAPDEN, "WRA", DependencyType::IntraRank, "tWRAPDEN"}, - {tPRPDEN, "PREPB", DependencyType::IntraRank, "tPRPDEN"}, - {tCKE, "PDXA", DependencyType::IntraRank, "tCKE"}, - {tCK, "CMD_BUS", DependencyType::InterRank, "CMD_BUS"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("PDEA"), + forward_as_tuple(initializer_list{ + {tACTPDEN, "ACT", DependencyType::IntraRank, "tACTPDEN"}, + {tRDPDEN, "RD", DependencyType::IntraRank, "tRDPDEN"}, + {tRDPDEN, "RDA", DependencyType::IntraRank, "tRDPDEN"}, + {tWRPDEN, "WR", DependencyType::IntraRank, "tWRPDEN"}, + {tWRAPDEN, "WRA", DependencyType::IntraRank, "tWRAPDEN"}, + {tPRPDEN, "PREPB", DependencyType::IntraRank, "tPRPDEN"}, + {tCKE, "PDXA", DependencyType::IntraRank, "tCKE"}, + {tCK, "CMD_BUS", DependencyType::InterRank, "CMD_BUS"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("PDXA"), - forward_as_tuple( - initializer_list{ - {tPD, "PDEA", DependencyType::IntraRank, "tPD"}, - {tCK, "CMD_BUS", DependencyType::InterRank, "CMD_BUS"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("PDXA"), + forward_as_tuple(initializer_list{ + {tPD, "PDEA", DependencyType::IntraRank, "tPD"}, + {tCK, "CMD_BUS", DependencyType::InterRank, "CMD_BUS"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("PDEP"), - forward_as_tuple( - initializer_list{ - {tRDPDEN, "RD", DependencyType::IntraRank, "tRDPDEN"}, - {tRDPDEN, "RDA", DependencyType::IntraRank, "tRDPDEN"}, - {tWRAPDEN, "WRA", DependencyType::IntraRank, "tWRAPDEN"}, - {tPRPDEN, "PREPB", DependencyType::IntraRank, "tPRPDEN"}, - {tPRPDEN, "PREAB", DependencyType::IntraRank, "tPRPDEN"}, - {tCKE, "PDXP", DependencyType::IntraRank, "tCKE"}, - {tREFPDEN, "REFAB", DependencyType::IntraRank, "tREFPDEN"}, - {tXS, "SREFEX", DependencyType::IntraRank, "tXS"}, - {tCK, "CMD_BUS", DependencyType::InterRank, "CMD_BUS"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("PDEP"), + forward_as_tuple(initializer_list{ + {tRDPDEN, "RD", DependencyType::IntraRank, "tRDPDEN"}, + {tRDPDEN, "RDA", DependencyType::IntraRank, "tRDPDEN"}, + {tWRAPDEN, "WRA", DependencyType::IntraRank, "tWRAPDEN"}, + {tPRPDEN, "PREPB", DependencyType::IntraRank, "tPRPDEN"}, + {tPRPDEN, "PREAB", DependencyType::IntraRank, "tPRPDEN"}, + {tCKE, "PDXP", DependencyType::IntraRank, "tCKE"}, + {tREFPDEN, "REFAB", DependencyType::IntraRank, "tREFPDEN"}, + {tXS, "SREFEX", DependencyType::IntraRank, "tXS"}, + {tCK, "CMD_BUS", DependencyType::InterRank, "CMD_BUS"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("PDXP"), - forward_as_tuple( - initializer_list{ - {tPD, "PDEP", DependencyType::IntraRank, "tPD"}, - {tCK, "CMD_BUS", DependencyType::InterRank, "CMD_BUS"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("PDXP"), + forward_as_tuple(initializer_list{ + {tPD, "PDEP", DependencyType::IntraRank, "tPD"}, + {tCK, "CMD_BUS", DependencyType::InterRank, "CMD_BUS"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("SREFEN"), - forward_as_tuple( - initializer_list{ - {tRC, "ACT", DependencyType::IntraRank, "tRC"}, - {max({tRDPDEN, tAL + tRTP + tRP}), "RDA", DependencyType::IntraRank, "max(tRDPDEN, tAL + tRTP + tRP)"}, - {max({tWRAPDEN, tWRPRE + tRP}), "WRA", DependencyType::IntraRank, "max(tWRAPDEN, tWRPRE + tRP)"}, - {tRP, "PREPB", DependencyType::IntraRank, "tRP"}, - {tRP, "PREAB", DependencyType::IntraRank, "tRP"}, - {tXP, "PDXP", DependencyType::IntraRank, "tXP"}, - {tRFC, "REFAB", DependencyType::IntraRank, "tRFC"}, - {tXS, "SREFEX", DependencyType::IntraRank, "tXS"}, - {tCK, "CMD_BUS", DependencyType::InterRank, "CMD_BUS"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("SREFEN"), + forward_as_tuple(initializer_list{ + {tRC, "ACT", DependencyType::IntraRank, "tRC"}, + {max({tRDPDEN, tAL + tRTP + tRP}), + "RDA", + DependencyType::IntraRank, + "max(tRDPDEN, tAL + tRTP + tRP)"}, + {max({tWRAPDEN, tWRPRE + tRP}), + "WRA", + DependencyType::IntraRank, + "max(tWRAPDEN, tWRPRE + tRP)"}, + {tRP, "PREPB", DependencyType::IntraRank, "tRP"}, + {tRP, "PREAB", DependencyType::IntraRank, "tRP"}, + {tXP, "PDXP", DependencyType::IntraRank, "tXP"}, + {tRFC, "REFAB", DependencyType::IntraRank, "tRFC"}, + {tXS, "SREFEX", DependencyType::IntraRank, "tXS"}, + {tCK, "CMD_BUS", DependencyType::InterRank, "CMD_BUS"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("SREFEX"), - forward_as_tuple( - initializer_list{ - {tCKESR, "SREFEN", DependencyType::IntraRank, "tCKESR"}, - {tCK, "CMD_BUS", DependencyType::InterRank, "CMD_BUS"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("SREFEX"), + forward_as_tuple(initializer_list{ + {tCKESR, "SREFEN", DependencyType::IntraRank, "tCKESR"}, + {tCK, "CMD_BUS", DependencyType::InterRank, "CMD_BUS"}, + })); return dmap; } diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/DDR3TimeDependencies.h b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/DDR3TimeDependencies.h index e62a3732..01fb06c6 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/DDR3TimeDependencies.h +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/DDR3TimeDependencies.h @@ -37,7 +37,8 @@ #include "businessObjects/dramTimeDependencies/deviceDependencies/dramtimedependenciesbase.h" -class DDR3TimeDependencies final : public DRAMTimeDependenciesBase { +class DDR3TimeDependencies final : public DRAMTimeDependenciesBase +{ public: DDR3TimeDependencies(const QJsonObject& memspec, const uint tCK); @@ -46,7 +47,7 @@ public: protected: void mInitializeValues() override; DependencyMap mSpecializedGetDependencies() const override; - + protected: uint burstLength; uint dataRate; @@ -88,5 +89,4 @@ protected: uint tRDPDEN; uint tWRPDEN; uint tWRAPDEN; - }; diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR3.cpp b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR3.cpp index 41071e4f..6331795d 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR3.cpp +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR3.cpp @@ -37,351 +37,304 @@ using namespace std; -TimeDependenciesInfoDDR3::TimeDependenciesInfoDDR3(const QJsonObject& memspec, const uint tCK) : DRAMTimeDependenciesBase(memspec, tCK) { - mInitializeValues(); +TimeDependenciesInfoDDR3::TimeDependenciesInfoDDR3(const QJsonObject& memspec, const uint tCK) : + DRAMTimeDependenciesBase(memspec, tCK) +{ + mInitializeValues(); } -void TimeDependenciesInfoDDR3::mInitializeValues() { - burstLength = mMemspecJson["memarchitecturespec"].toObject()["burstLength"].toInt(); - dataRate = mMemspecJson["memarchitecturespec"].toObject()["dataRate"].toInt(); +void TimeDependenciesInfoDDR3::mInitializeValues() +{ + burstLength = mMemspecJson["memarchitecturespec"].toObject()["burstLength"].toInt(); + dataRate = mMemspecJson["memarchitecturespec"].toObject()["dataRate"].toInt(); - tCCD = tCK * mMemspecJson["memtimingspec"].toObject()["CCD"].toInt(); - tRCD = tCK * mMemspecJson["memtimingspec"].toObject()["RCD"].toInt(); - tRP = tCK * mMemspecJson["memtimingspec"].toObject()["RP"].toInt(); - tRAS = tCK * mMemspecJson["memtimingspec"].toObject()["RAS"].toInt(); - tCL = tCK * mMemspecJson["memtimingspec"].toObject()["CL"].toInt(); - tCWL = tCK * mMemspecJson["memtimingspec"].toObject()["CWL"].toInt(); - tAL = tCK * mMemspecJson["memtimingspec"].toObject()["AL"].toInt(); - tRL = tCK * mMemspecJson["memtimingspec"].toObject()["RL"].toInt(); - tWL = tCK * mMemspecJson["memtimingspec"].toObject()["WL"].toInt(); - tRTP = tCK * mMemspecJson["memtimingspec"].toObject()["RTP"].toInt(); - tWTR = tCK * mMemspecJson["memtimingspec"].toObject()["WTR"].toInt(); - tRRD = tCK * mMemspecJson["memtimingspec"].toObject()["RRD"].toInt(); - tWR = tCK * mMemspecJson["memtimingspec"].toObject()["WR"].toInt(); - tFAW = tCK * mMemspecJson["memtimingspec"].toObject()["FAW"].toInt(); - tRFC = tCK * mMemspecJson["memtimingspec"].toObject()["RFC"].toInt(); - tRC = tCK * mMemspecJson["memtimingspec"].toObject()["RC"].toInt(); - tXP = tCK * mMemspecJson["memtimingspec"].toObject()["XP"].toInt(); - tXS = tCK * mMemspecJson["memtimingspec"].toObject()["XS"].toInt(); - tXSDLL = tCK * mMemspecJson["memtimingspec"].toObject()["XSDLL"].toInt(); - tCKE = tCK * mMemspecJson["memtimingspec"].toObject()["CKE"].toInt(); - tCKESR = tCK * mMemspecJson["memtimingspec"].toObject()["CKESR"].toInt(); - tREFPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["REFPDEN"].toInt(); - tACTPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["ACTPDEN"].toInt(); - tPRPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["PRPDEN"].toInt(); - tRTRS = tCK * mMemspecJson["memtimingspec"].toObject()["RTRS"].toInt(); + tCCD = tCK * mMemspecJson["memtimingspec"].toObject()["CCD"].toInt(); + tRCD = tCK * mMemspecJson["memtimingspec"].toObject()["RCD"].toInt(); + tRP = tCK * mMemspecJson["memtimingspec"].toObject()["RP"].toInt(); + tRAS = tCK * mMemspecJson["memtimingspec"].toObject()["RAS"].toInt(); + tCL = tCK * mMemspecJson["memtimingspec"].toObject()["CL"].toInt(); + tCWL = tCK * mMemspecJson["memtimingspec"].toObject()["CWL"].toInt(); + tAL = tCK * mMemspecJson["memtimingspec"].toObject()["AL"].toInt(); + tRL = tCK * mMemspecJson["memtimingspec"].toObject()["RL"].toInt(); + tWL = tCK * mMemspecJson["memtimingspec"].toObject()["WL"].toInt(); + tRTP = tCK * mMemspecJson["memtimingspec"].toObject()["RTP"].toInt(); + tWTR = tCK * mMemspecJson["memtimingspec"].toObject()["WTR"].toInt(); + tRRD = tCK * mMemspecJson["memtimingspec"].toObject()["RRD"].toInt(); + tWR = tCK * mMemspecJson["memtimingspec"].toObject()["WR"].toInt(); + tFAW = tCK * mMemspecJson["memtimingspec"].toObject()["FAW"].toInt(); + tRFC = tCK * mMemspecJson["memtimingspec"].toObject()["RFC"].toInt(); + tRC = tCK * mMemspecJson["memtimingspec"].toObject()["RC"].toInt(); + tXP = tCK * mMemspecJson["memtimingspec"].toObject()["XP"].toInt(); + tXS = tCK * mMemspecJson["memtimingspec"].toObject()["XS"].toInt(); + tXSDLL = tCK * mMemspecJson["memtimingspec"].toObject()["XSDLL"].toInt(); + tCKE = tCK * mMemspecJson["memtimingspec"].toObject()["CKE"].toInt(); + tCKESR = tCK * mMemspecJson["memtimingspec"].toObject()["CKESR"].toInt(); + tREFPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["REFPDEN"].toInt(); + tACTPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["ACTPDEN"].toInt(); + tPRPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["PRPDEN"].toInt(); + tRTRS = tCK * mMemspecJson["memtimingspec"].toObject()["RTRS"].toInt(); - tPD = tCKE; + tPD = tCKE; - tBURST = (uint) (burstLength / (float) dataRate) * tCK; - tRDWR = tRL + tBURST + 2 * tCK - tWL; - tRDWR_R = tRL + tBURST + tRTRS - tWL; - tWRRD = tWL + tBURST + tWTR - tAL; - tWRPRE = tWL + tBURST + tWR; - tWRRD_R = tWL + tBURST + tRTRS - tRL; - tRDPDEN = tRL + tBURST + tCK; - tWRPDEN = tWL + tBURST + tWR; - tWRAPDEN = tWL + tBURST + tWR + tCK; + tBURST = (uint)(burstLength / (float)dataRate) * tCK; + tRDWR = tRL + tBURST + 2 * tCK - tWL; + tRDWR_R = tRL + tBURST + tRTRS - tWL; + tWRRD = tWL + tBURST + tWTR - tAL; + tWRPRE = tWL + tBURST + tWR; + tWRRD_R = tWL + tBURST + tRTRS - tRL; + tRDPDEN = tRL + tBURST + tCK; + tWRPDEN = tWL + tBURST + tWR; + tWRAPDEN = tWL + tBURST + tWR + tCK; - mPools.insert({ - "CMD_BUS", { - 1, { - {"ACT", tCK}, - {"RD", tCK}, - {"WR", tCK}, - {"PREPB", tCK}, - {"RDA", tCK}, - {"WRA", tCK}, - {"REFAB", tCK}, - {"PREAB", tCK}, - {"PDEP", tCK}, - {"PDXP", tCK}, - {"SREFEN", tCK}, - {"SREFEX", tCK}, - {"PDEA", tCK}, - {"PDXA", tCK}, - } - } - }); + mPools.insert({"CMD_BUS", + {1, + { + {"ACT", tCK}, + {"RD", tCK}, + {"WR", tCK}, + {"PREPB", tCK}, + {"RDA", tCK}, + {"WRA", tCK}, + {"REFAB", tCK}, + {"PREAB", tCK}, + {"PDEP", tCK}, + {"PDXP", tCK}, + {"SREFEN", tCK}, + {"SREFEX", tCK}, + {"PDEA", tCK}, + {"PDXA", tCK}, + }}}); - mPools.insert({ - "NAW", { - 4, { - {"ACT", tFAW}, - } - } - }); - + mPools.insert({"NAW", + {4, + { + {"ACT", tFAW}, + }}}); } -const std::vector TimeDependenciesInfoDDR3::getPossiblePhases() { - return { - "ACT", - "RD", - "WR", - "PREPB", - "RDA", - "WRA", - "REFAB", - "PREAB", - "PDEP", - "PDXP", - "SREFEN", - "SREFEX", - "PDEA", - "PDXA", - }; +const std::vector TimeDependenciesInfoDDR3::getPossiblePhases() +{ + return { + "ACT", + "RD", + "WR", + "PREPB", + "RDA", + "WRA", + "REFAB", + "PREAB", + "PDEP", + "PDXP", + "SREFEN", + "SREFEX", + "PDEA", + "PDXA", + }; } -DependencyMap TimeDependenciesInfoDDR3::mSpecializedGetDependencies() const { - DependencyMap dmap; +DependencyMap TimeDependenciesInfoDDR3::mSpecializedGetDependencies() const +{ + DependencyMap dmap; - dmap.emplace( - piecewise_construct, - forward_as_tuple("ACT"), - forward_as_tuple( - initializer_list{ - {tRC, "ACT", DependencyType::IntraBank, "tRC"}, - {tRRD, "ACT", DependencyType::IntraRank, "tRRD"}, - {tAL + tRTP + tRP, "RDA", DependencyType::IntraBank, "tAL + tRTP + tRP"}, - {tWRPRE + tRP, "WRA", DependencyType::IntraBank, "tWRPRE + tRP"}, - {tRP, "PREPB", DependencyType::IntraBank, "tRP"}, - {tRP, "PREAB", DependencyType::IntraRank, "tRP"}, - {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, - {tXP, "PDXP", DependencyType::IntraRank, "tXP"}, - {tRFC, "REFAB", DependencyType::IntraRank, "tRFC"}, - {tXS, "SREFEX", DependencyType::IntraRank, "tXS"}, - {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, - {tFAW, "NAW", DependencyType::IntraRank, "tFAW"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("ACT"), + forward_as_tuple(initializer_list{ + {tRC, "ACT", DependencyType::IntraBank, "tRC"}, + {tRRD, "ACT", DependencyType::IntraRank, "tRRD"}, + {tAL + tRTP + tRP, "RDA", DependencyType::IntraBank, "tAL + tRTP + tRP"}, + {tWRPRE + tRP, "WRA", DependencyType::IntraBank, "tWRPRE + tRP"}, + {tRP, "PREPB", DependencyType::IntraBank, "tRP"}, + {tRP, "PREAB", DependencyType::IntraRank, "tRP"}, + {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, + {tXP, "PDXP", DependencyType::IntraRank, "tXP"}, + {tRFC, "REFAB", DependencyType::IntraRank, "tRFC"}, + {tXS, "SREFEX", DependencyType::IntraRank, "tXS"}, + {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, + {tFAW, "NAW", DependencyType::IntraRank, "tFAW"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("RD"), - forward_as_tuple( - initializer_list{ - {tRCD - tAL, "ACT", DependencyType::IntraBank, "tRCD - tAL"}, - {tCCD, "RD", DependencyType::IntraBank, "tCCD"}, - {tCCD, "RD", DependencyType::IntraRank, "tCCD"}, - {tBURST + tRTRS, "RD", DependencyType::InterRank, "tBURST + tRTRS"}, - {tCCD, "RDA", DependencyType::IntraRank, "tCCD"}, - {tBURST + tRTRS, "RDA", DependencyType::InterRank, "tBURST + tRTRS"}, - {tWRRD, "WR", DependencyType::IntraBank, "tWRRD"}, - {tWRRD, "WR", DependencyType::IntraRank, "tWRRD"}, - {tWRRD_R, "WR", DependencyType::InterRank, "tWRRD_R"}, - {tWRRD, "WRA", DependencyType::IntraRank, "tWRRD"}, - {tWRRD_R, "WRA", DependencyType::InterRank, "tWRRD_R"}, - {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, - {tXSDLL, "SREFEX", DependencyType::IntraRank, "tXSDLL"}, - {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("RD"), + forward_as_tuple(initializer_list{ + {tRCD - tAL, "ACT", DependencyType::IntraBank, "tRCD - tAL"}, + {tCCD, "RD", DependencyType::IntraBank, "tCCD"}, + {tCCD, "RD", DependencyType::IntraRank, "tCCD"}, + {tBURST + tRTRS, "RD", DependencyType::InterRank, "tBURST + tRTRS"}, + {tCCD, "RDA", DependencyType::IntraRank, "tCCD"}, + {tBURST + tRTRS, "RDA", DependencyType::InterRank, "tBURST + tRTRS"}, + {tWRRD, "WR", DependencyType::IntraBank, "tWRRD"}, + {tWRRD, "WR", DependencyType::IntraRank, "tWRRD"}, + {tWRRD_R, "WR", DependencyType::InterRank, "tWRRD_R"}, + {tWRRD, "WRA", DependencyType::IntraRank, "tWRRD"}, + {tWRRD_R, "WRA", DependencyType::InterRank, "tWRRD_R"}, + {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, + {tXSDLL, "SREFEX", DependencyType::IntraRank, "tXSDLL"}, + {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("WR"), - forward_as_tuple( - initializer_list{ - {tRCD - tAL, "ACT", DependencyType::IntraBank, "tRCD - tAL"}, - {tRDWR, "RD", DependencyType::IntraBank, "tRDWR"}, - {tRDWR, "RD", DependencyType::IntraRank, "tRDWR"}, - {tRDWR_R, "RD", DependencyType::InterRank, "tRDWR_R"}, - {tRDWR, "RDA", DependencyType::IntraRank, "tRDWR"}, - {tRDWR_R, "RDA", DependencyType::InterRank, "tRDWR_R"}, - {tCCD, "WR", DependencyType::IntraBank, "tCCD"}, - {tCCD, "WR", DependencyType::IntraRank, "tCCD"}, - {tBURST + tRTRS, "WR", DependencyType::InterRank, "tBURST + tRTRS"}, - {tCCD, "WRA", DependencyType::IntraRank, "tCCD"}, - {tBURST + tRTRS, "WRA", DependencyType::InterRank, "tBURST + tRTRS"}, - {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, - {tXSDLL, "SREFEX", DependencyType::IntraRank, "tXSDLL"}, - {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("WR"), + forward_as_tuple(initializer_list{ + {tRCD - tAL, "ACT", DependencyType::IntraBank, "tRCD - tAL"}, + {tRDWR, "RD", DependencyType::IntraBank, "tRDWR"}, + {tRDWR, "RD", DependencyType::IntraRank, "tRDWR"}, + {tRDWR_R, "RD", DependencyType::InterRank, "tRDWR_R"}, + {tRDWR, "RDA", DependencyType::IntraRank, "tRDWR"}, + {tRDWR_R, "RDA", DependencyType::InterRank, "tRDWR_R"}, + {tCCD, "WR", DependencyType::IntraBank, "tCCD"}, + {tCCD, "WR", DependencyType::IntraRank, "tCCD"}, + {tBURST + tRTRS, "WR", DependencyType::InterRank, "tBURST + tRTRS"}, + {tCCD, "WRA", DependencyType::IntraRank, "tCCD"}, + {tBURST + tRTRS, "WRA", DependencyType::InterRank, "tBURST + tRTRS"}, + {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, + {tXSDLL, "SREFEX", DependencyType::IntraRank, "tXSDLL"}, + {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("PREPB"), - forward_as_tuple( - initializer_list{ - {tRAS, "ACT", DependencyType::IntraBank, "tRAS"}, - {tAL + tRTP, "RD", DependencyType::IntraBank, "tAL + tRTP"}, - {tWRPRE, "WR", DependencyType::IntraBank, "tWRPRE"}, - {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, - {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("PREPB"), + forward_as_tuple(initializer_list{ + {tRAS, "ACT", DependencyType::IntraBank, "tRAS"}, + {tAL + tRTP, "RD", DependencyType::IntraBank, "tAL + tRTP"}, + {tWRPRE, "WR", DependencyType::IntraBank, "tWRPRE"}, + {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, + {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("RDA"), - forward_as_tuple( - initializer_list{ - {tRCD - tAL, "ACT", DependencyType::IntraBank, "tRCD - tAL"}, - {tCCD, "RD", DependencyType::IntraBank, "tCCD"}, - {tCCD, "RD", DependencyType::IntraRank, "tCCD"}, - {tBURST + tRTRS, "RD", DependencyType::InterRank, "tBURST + tRTRS"}, - {tCCD, "RDA", DependencyType::IntraRank, "tCCD"}, - {tBURST + tRTRS, "RDA", DependencyType::InterRank, "tBURST + tRTRS"}, - {max({tWRRD, tWRPRE - tRTP - tAL}), "WR", DependencyType::IntraBank, "max(tWRRD, tWRPRE - tRTP - tAL)"}, - {tWRRD, "WR", DependencyType::IntraRank, "tWRRD"}, - {tWRRD_R, "WR", DependencyType::InterRank, "tWRRD_R"}, - {tWRRD, "WRA", DependencyType::IntraRank, "tWRRD"}, - {tWRRD_R, "WRA", DependencyType::InterRank, "tWRRD_R"}, - {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, - {tXSDLL, "SREFEX", DependencyType::IntraRank, "tXSDLL"}, - {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("RDA"), + forward_as_tuple(initializer_list{ + {tRCD - tAL, "ACT", DependencyType::IntraBank, "tRCD - tAL"}, + {tCCD, "RD", DependencyType::IntraBank, "tCCD"}, + {tCCD, "RD", DependencyType::IntraRank, "tCCD"}, + {tBURST + tRTRS, "RD", DependencyType::InterRank, "tBURST + tRTRS"}, + {tCCD, "RDA", DependencyType::IntraRank, "tCCD"}, + {tBURST + tRTRS, "RDA", DependencyType::InterRank, "tBURST + tRTRS"}, + {max({tWRRD, tWRPRE - tRTP - tAL}), + "WR", + DependencyType::IntraBank, + "max(tWRRD, tWRPRE - tRTP - tAL)"}, + {tWRRD, "WR", DependencyType::IntraRank, "tWRRD"}, + {tWRRD_R, "WR", DependencyType::InterRank, "tWRRD_R"}, + {tWRRD, "WRA", DependencyType::IntraRank, "tWRRD"}, + {tWRRD_R, "WRA", DependencyType::InterRank, "tWRRD_R"}, + {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, + {tXSDLL, "SREFEX", DependencyType::IntraRank, "tXSDLL"}, + {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("WRA"), - forward_as_tuple( - initializer_list{ - {tRCD - tAL, "ACT", DependencyType::IntraBank, "tRCD - tAL"}, - {tRDWR, "RD", DependencyType::IntraBank, "tRDWR"}, - {tRDWR, "RD", DependencyType::IntraRank, "tRDWR"}, - {tRDWR_R, "RD", DependencyType::InterRank, "tRDWR_R"}, - {tRDWR, "RDA", DependencyType::IntraRank, "tRDWR"}, - {tRDWR_R, "RDA", DependencyType::InterRank, "tRDWR_R"}, - {tCCD, "WR", DependencyType::IntraBank, "tCCD"}, - {tCCD, "WR", DependencyType::IntraRank, "tCCD"}, - {tBURST + tRTRS, "WR", DependencyType::InterRank, "tBURST + tRTRS"}, - {tCCD, "WRA", DependencyType::IntraRank, "tCCD"}, - {tBURST + tRTRS, "WRA", DependencyType::InterRank, "tBURST + tRTRS"}, - {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, - {tXSDLL, "SREFEX", DependencyType::IntraRank, "tXSDLL"}, - {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("WRA"), + forward_as_tuple(initializer_list{ + {tRCD - tAL, "ACT", DependencyType::IntraBank, "tRCD - tAL"}, + {tRDWR, "RD", DependencyType::IntraBank, "tRDWR"}, + {tRDWR, "RD", DependencyType::IntraRank, "tRDWR"}, + {tRDWR_R, "RD", DependencyType::InterRank, "tRDWR_R"}, + {tRDWR, "RDA", DependencyType::IntraRank, "tRDWR"}, + {tRDWR_R, "RDA", DependencyType::InterRank, "tRDWR_R"}, + {tCCD, "WR", DependencyType::IntraBank, "tCCD"}, + {tCCD, "WR", DependencyType::IntraRank, "tCCD"}, + {tBURST + tRTRS, "WR", DependencyType::InterRank, "tBURST + tRTRS"}, + {tCCD, "WRA", DependencyType::IntraRank, "tCCD"}, + {tBURST + tRTRS, "WRA", DependencyType::InterRank, "tBURST + tRTRS"}, + {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, + {tXSDLL, "SREFEX", DependencyType::IntraRank, "tXSDLL"}, + {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("REFAB"), - forward_as_tuple( - initializer_list{ - {tRC, "ACT", DependencyType::IntraRank, "tRC"}, - {tAL + tRTP + tRP, "RDA", DependencyType::IntraRank, "tAL + tRTP + tRP"}, - {tWRPRE + tRP, "WRA", DependencyType::IntraRank, "tWRPRE + tRP"}, - {tRP, "PREPB", DependencyType::IntraRank, "tRP"}, - {tRP, "PREAB", DependencyType::IntraRank, "tRP"}, - {tXP, "PDXP", DependencyType::IntraRank, "tXP"}, - {tRFC, "REFAB", DependencyType::IntraRank, "tRFC"}, - {tXS, "SREFEX", DependencyType::IntraRank, "tXS"}, - {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("REFAB"), + forward_as_tuple(initializer_list{ + {tRC, "ACT", DependencyType::IntraRank, "tRC"}, + {tAL + tRTP + tRP, "RDA", DependencyType::IntraRank, "tAL + tRTP + tRP"}, + {tWRPRE + tRP, "WRA", DependencyType::IntraRank, "tWRPRE + tRP"}, + {tRP, "PREPB", DependencyType::IntraRank, "tRP"}, + {tRP, "PREAB", DependencyType::IntraRank, "tRP"}, + {tXP, "PDXP", DependencyType::IntraRank, "tXP"}, + {tRFC, "REFAB", DependencyType::IntraRank, "tRFC"}, + {tXS, "SREFEX", DependencyType::IntraRank, "tXS"}, + {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("PREAB"), - forward_as_tuple( - initializer_list{ - {tRAS, "ACT", DependencyType::IntraRank, "tRAS"}, - {tAL + tRTP, "RD", DependencyType::IntraRank, "tAL + tRTP"}, - {tAL + tRTP, "RDA", DependencyType::IntraRank, "tAL + tRTP"}, - {tWRPRE, "WR", DependencyType::IntraRank, "tWRPRE"}, - {tWRPRE, "WRA", DependencyType::IntraRank, "tWRPRE"}, - {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, - {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("PREAB"), + forward_as_tuple(initializer_list{ + {tRAS, "ACT", DependencyType::IntraRank, "tRAS"}, + {tAL + tRTP, "RD", DependencyType::IntraRank, "tAL + tRTP"}, + {tAL + tRTP, "RDA", DependencyType::IntraRank, "tAL + tRTP"}, + {tWRPRE, "WR", DependencyType::IntraRank, "tWRPRE"}, + {tWRPRE, "WRA", DependencyType::IntraRank, "tWRPRE"}, + {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, + {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("PDEP"), - forward_as_tuple( - initializer_list{ - {tRDPDEN, "RD", DependencyType::IntraRank, "tRDPDEN"}, - {tRDPDEN, "RDA", DependencyType::IntraRank, "tRDPDEN"}, - {tWRAPDEN, "WRA", DependencyType::IntraRank, "tWRAPDEN"}, - {tPRPDEN, "PREPB", DependencyType::IntraRank, "tPRPDEN"}, - {tPRPDEN, "PREAB", DependencyType::IntraRank, "tPRPDEN"}, - {tCKE, "PDXP", DependencyType::IntraRank, "tCKE"}, - {tREFPDEN, "REFAB", DependencyType::IntraRank, "tREFPDEN"}, - {tXS, "SREFEX", DependencyType::IntraRank, "tXS"}, - {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("PDEP"), + forward_as_tuple(initializer_list{ + {tRDPDEN, "RD", DependencyType::IntraRank, "tRDPDEN"}, + {tRDPDEN, "RDA", DependencyType::IntraRank, "tRDPDEN"}, + {tWRAPDEN, "WRA", DependencyType::IntraRank, "tWRAPDEN"}, + {tPRPDEN, "PREPB", DependencyType::IntraRank, "tPRPDEN"}, + {tPRPDEN, "PREAB", DependencyType::IntraRank, "tPRPDEN"}, + {tCKE, "PDXP", DependencyType::IntraRank, "tCKE"}, + {tREFPDEN, "REFAB", DependencyType::IntraRank, "tREFPDEN"}, + {tXS, "SREFEX", DependencyType::IntraRank, "tXS"}, + {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("PDXP"), - forward_as_tuple( - initializer_list{ - {tPD, "PDEP", DependencyType::IntraRank, "tPD"}, - {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("PDXP"), + forward_as_tuple(initializer_list{ + {tPD, "PDEP", DependencyType::IntraRank, "tPD"}, + {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("SREFEN"), - forward_as_tuple( - initializer_list{ - {tRC, "ACT", DependencyType::IntraRank, "tRC"}, - {max({tRDPDEN, tAL + tRTP + tRP}), "RDA", DependencyType::IntraRank, "max(tRDPDEN, tAL + tRTP + tRP)"}, - {max({tWRAPDEN, tWRPRE + tRP}), "WRA", DependencyType::IntraRank, "max(tWRAPDEN, tWRPRE + tRP)"}, - {tRP, "PREPB", DependencyType::IntraRank, "tRP"}, - {tRP, "PREAB", DependencyType::IntraRank, "tRP"}, - {tXP, "PDXP", DependencyType::IntraRank, "tXP"}, - {tRFC, "REFAB", DependencyType::IntraRank, "tRFC"}, - {tXS, "SREFEX", DependencyType::IntraRank, "tXS"}, - {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("SREFEN"), + forward_as_tuple(initializer_list{ + {tRC, "ACT", DependencyType::IntraRank, "tRC"}, + {max({tRDPDEN, tAL + tRTP + tRP}), + "RDA", + DependencyType::IntraRank, + "max(tRDPDEN, tAL + tRTP + tRP)"}, + {max({tWRAPDEN, tWRPRE + tRP}), + "WRA", + DependencyType::IntraRank, + "max(tWRAPDEN, tWRPRE + tRP)"}, + {tRP, "PREPB", DependencyType::IntraRank, "tRP"}, + {tRP, "PREAB", DependencyType::IntraRank, "tRP"}, + {tXP, "PDXP", DependencyType::IntraRank, "tXP"}, + {tRFC, "REFAB", DependencyType::IntraRank, "tRFC"}, + {tXS, "SREFEX", DependencyType::IntraRank, "tXS"}, + {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("SREFEX"), - forward_as_tuple( - initializer_list{ - {tCKESR, "SREFEN", DependencyType::IntraRank, "tCKESR"}, - {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("SREFEX"), + forward_as_tuple(initializer_list{ + {tCKESR, "SREFEN", DependencyType::IntraRank, "tCKESR"}, + {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("PDEA"), - forward_as_tuple( - initializer_list{ - {tACTPDEN, "ACT", DependencyType::IntraRank, "tACTPDEN"}, - {tRDPDEN, "RD", DependencyType::IntraRank, "tRDPDEN"}, - {tRDPDEN, "RDA", DependencyType::IntraRank, "tRDPDEN"}, - {tWRPDEN, "WR", DependencyType::IntraRank, "tWRPDEN"}, - {tWRAPDEN, "WRA", DependencyType::IntraRank, "tWRAPDEN"}, - {tPRPDEN, "PREPB", DependencyType::IntraRank, "tPRPDEN"}, - {tCKE, "PDXA", DependencyType::IntraRank, "tCKE"}, - {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("PDEA"), + forward_as_tuple(initializer_list{ + {tACTPDEN, "ACT", DependencyType::IntraRank, "tACTPDEN"}, + {tRDPDEN, "RD", DependencyType::IntraRank, "tRDPDEN"}, + {tRDPDEN, "RDA", DependencyType::IntraRank, "tRDPDEN"}, + {tWRPDEN, "WR", DependencyType::IntraRank, "tWRPDEN"}, + {tWRAPDEN, "WRA", DependencyType::IntraRank, "tWRAPDEN"}, + {tPRPDEN, "PREPB", DependencyType::IntraRank, "tPRPDEN"}, + {tCKE, "PDXA", DependencyType::IntraRank, "tCKE"}, + {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("PDXA"), - forward_as_tuple( - initializer_list{ - {tPD, "PDEA", DependencyType::IntraRank, "tPD"}, - {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("PDXA"), + forward_as_tuple(initializer_list{ + {tPD, "PDEA", DependencyType::IntraRank, "tPD"}, + {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, + })); - return dmap; + return dmap; } diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR3.h b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR3.h index 88143614..201ff237 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR3.h +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR3.h @@ -37,17 +37,18 @@ #include "../dramtimedependenciesbase.h" -class TimeDependenciesInfoDDR3 final : public DRAMTimeDependenciesBase { - public: +class TimeDependenciesInfoDDR3 final : public DRAMTimeDependenciesBase +{ +public: TimeDependenciesInfoDDR3(const QJsonObject& memspec, const uint clk); static const std::vector getPossiblePhases(); - protected: +protected: void mInitializeValues() override; DependencyMap mSpecializedGetDependencies() const override; - protected: +protected: uint burstLength; uint dataRate; @@ -87,5 +88,4 @@ class TimeDependenciesInfoDDR3 final : public DRAMTimeDependenciesBase { uint tRDPDEN; uint tWRPDEN; uint tWRAPDEN; - }; diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR4.cpp b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR4.cpp index 11e2382b..68df192c 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR4.cpp +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR4.cpp @@ -37,384 +37,333 @@ using namespace std; -TimeDependenciesInfoDDR4::TimeDependenciesInfoDDR4(const QJsonObject& memspec, const uint tCK) : DRAMTimeDependenciesBase(memspec, tCK) { - mInitializeValues(); +TimeDependenciesInfoDDR4::TimeDependenciesInfoDDR4(const QJsonObject& memspec, const uint tCK) : + DRAMTimeDependenciesBase(memspec, tCK) +{ + mInitializeValues(); } -void TimeDependenciesInfoDDR4::mInitializeValues() { - burstLength = mMemspecJson["memarchitecturespec"].toObject()["burstLength"].toInt(); - dataRate = mMemspecJson["memarchitecturespec"].toObject()["dataRate"].toInt(); +void TimeDependenciesInfoDDR4::mInitializeValues() +{ + burstLength = mMemspecJson["memarchitecturespec"].toObject()["burstLength"].toInt(); + dataRate = mMemspecJson["memarchitecturespec"].toObject()["dataRate"].toInt(); - tRCD = tCK * mMemspecJson["memtimingspec"].toObject()["RCD"].toInt(); - tRP = tCK * mMemspecJson["memtimingspec"].toObject()["RP"].toInt(); - tRAS = tCK * mMemspecJson["memtimingspec"].toObject()["RAS"].toInt(); - tRC = tCK * mMemspecJson["memtimingspec"].toObject()["RC"].toInt(); - tCL = tCK * mMemspecJson["memtimingspec"].toObject()["CL"].toInt(); - tCWL = tCK * mMemspecJson["memtimingspec"].toObject()["CWL"].toInt(); - tAL = tCK * mMemspecJson["memtimingspec"].toObject()["AL"].toInt(); - tRL = tCK * mMemspecJson["memtimingspec"].toObject()["RL"].toInt(); - tRPRE = tCK * mMemspecJson["memtimingspec"].toObject()["RPRE"].toInt(); - tWPRE = tCK * mMemspecJson["memtimingspec"].toObject()["WPRE"].toInt(); - tWL = tCK * mMemspecJson["memtimingspec"].toObject()["WL"].toInt(); - tCCD_S = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_S"].toInt(); - tCCD_L = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_L"].toInt(); - tRRD_S = tCK * mMemspecJson["memtimingspec"].toObject()["RRD_S"].toInt(); - tRRD_L = tCK * mMemspecJson["memtimingspec"].toObject()["RRD_L"].toInt(); - tFAW = tCK * mMemspecJson["memtimingspec"].toObject()["FAW"].toInt(); - tWTR_S = tCK * mMemspecJson["memtimingspec"].toObject()["WTR_S"].toInt(); - tWTR_L = tCK * mMemspecJson["memtimingspec"].toObject()["WTR_L"].toInt(); - tRTP = tCK * mMemspecJson["memtimingspec"].toObject()["RTP"].toInt(); - tWR = tCK * mMemspecJson["memtimingspec"].toObject()["WR"].toInt(); - tXS = tCK * mMemspecJson["memtimingspec"].toObject()["XS"].toInt(); - tXSDLL = tCK * mMemspecJson["memtimingspec"].toObject()["XSDLL"].toInt(); - tXP = tCK * mMemspecJson["memtimingspec"].toObject()["XP"].toInt(); - tCKE = tCK * mMemspecJson["memtimingspec"].toObject()["CKE"].toInt(); - tCKESR = tCK * mMemspecJson["memtimingspec"].toObject()["CKESR"].toInt(); - tACTPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["ACTPDEN"].toInt(); - tPRPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["PRPDEN"].toInt(); - tREFPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["REFPDEN"].toInt(); - tRTRS = tCK * mMemspecJson["memtimingspec"].toObject()["RTRS"].toInt(); + tRCD = tCK * mMemspecJson["memtimingspec"].toObject()["RCD"].toInt(); + tRP = tCK * mMemspecJson["memtimingspec"].toObject()["RP"].toInt(); + tRAS = tCK * mMemspecJson["memtimingspec"].toObject()["RAS"].toInt(); + tRC = tCK * mMemspecJson["memtimingspec"].toObject()["RC"].toInt(); + tCL = tCK * mMemspecJson["memtimingspec"].toObject()["CL"].toInt(); + tCWL = tCK * mMemspecJson["memtimingspec"].toObject()["CWL"].toInt(); + tAL = tCK * mMemspecJson["memtimingspec"].toObject()["AL"].toInt(); + tRL = tCK * mMemspecJson["memtimingspec"].toObject()["RL"].toInt(); + tRPRE = tCK * mMemspecJson["memtimingspec"].toObject()["RPRE"].toInt(); + tWPRE = tCK * mMemspecJson["memtimingspec"].toObject()["WPRE"].toInt(); + tWL = tCK * mMemspecJson["memtimingspec"].toObject()["WL"].toInt(); + tCCD_S = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_S"].toInt(); + tCCD_L = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_L"].toInt(); + tRRD_S = tCK * mMemspecJson["memtimingspec"].toObject()["RRD_S"].toInt(); + tRRD_L = tCK * mMemspecJson["memtimingspec"].toObject()["RRD_L"].toInt(); + tFAW = tCK * mMemspecJson["memtimingspec"].toObject()["FAW"].toInt(); + tWTR_S = tCK * mMemspecJson["memtimingspec"].toObject()["WTR_S"].toInt(); + tWTR_L = tCK * mMemspecJson["memtimingspec"].toObject()["WTR_L"].toInt(); + tRTP = tCK * mMemspecJson["memtimingspec"].toObject()["RTP"].toInt(); + tWR = tCK * mMemspecJson["memtimingspec"].toObject()["WR"].toInt(); + tXS = tCK * mMemspecJson["memtimingspec"].toObject()["XS"].toInt(); + tXSDLL = tCK * mMemspecJson["memtimingspec"].toObject()["XSDLL"].toInt(); + tXP = tCK * mMemspecJson["memtimingspec"].toObject()["XP"].toInt(); + tCKE = tCK * mMemspecJson["memtimingspec"].toObject()["CKE"].toInt(); + tCKESR = tCK * mMemspecJson["memtimingspec"].toObject()["CKESR"].toInt(); + tACTPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["ACTPDEN"].toInt(); + tPRPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["PRPDEN"].toInt(); + tREFPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["REFPDEN"].toInt(); + tRTRS = tCK * mMemspecJson["memtimingspec"].toObject()["RTRS"].toInt(); - tPD = tCKE; - tRFC = tCK * ( - (mMemspecJson["memtimingspec"].toObject()["REFM"].toInt() == 4) ? - (mMemspecJson["memtimingspec"].toObject()["RFC4"].toInt(1)) : - ( - (mMemspecJson["memtimingspec"].toObject()["REFM"].toInt() == 2) ? - (mMemspecJson["memtimingspec"].toObject()["RFC2"].toInt(1)) : - (mMemspecJson["memtimingspec"].toObject()["RFC"].toInt(1)) - ) - ); - - tBURST = (uint) (burstLength / (float) dataRate) * tCK; - tRDWR = tRL + tBURST + tCK - tWL + tWPRE; - tRDWR_R = tRL + tBURST + tRTRS - tWL + tWPRE; - tWRRD_S = tWL + tBURST + tWTR_S - tAL; - tWRRD_L = tWL + tBURST + tWTR_L - tAL; - tWRRD_R = tWL + tBURST + tRTRS - tRL + tRPRE; - tRDAACT = tAL + tRTP + tRP; - tWRPRE = tWL + tBURST + tWR; - tWRAACT = tWRPRE + tRP; - tRDPDEN = tRL + tBURST + tCK; - tWRPDEN = tWL + tBURST + tWR; - tWRAPDEN = tWL + tBURST + tWR + tCK; + tPD = tCKE; + tRFC = tCK * ((mMemspecJson["memtimingspec"].toObject()["REFM"].toInt() == 4) + ? (mMemspecJson["memtimingspec"].toObject()["RFC4"].toInt(1)) + : ((mMemspecJson["memtimingspec"].toObject()["REFM"].toInt() == 2) + ? (mMemspecJson["memtimingspec"].toObject()["RFC2"].toInt(1)) + : (mMemspecJson["memtimingspec"].toObject()["RFC"].toInt(1)))); - mPools.insert({ - "CMD_BUS", { - 1, { - {"ACT", tCK}, - {"RD", tCK}, - {"WR", tCK}, - {"PREPB", tCK}, - {"RDA", tCK}, - {"WRA", tCK}, - {"REFAB", tCK}, - {"PREAB", tCK}, - {"PDEP", tCK}, - {"PDXP", tCK}, - {"SREFEN", tCK}, - {"SREFEX", tCK}, - {"PDEA", tCK}, - {"PDXA", tCK}, - } - } - }); + tBURST = (uint)(burstLength / (float)dataRate) * tCK; + tRDWR = tRL + tBURST + tCK - tWL + tWPRE; + tRDWR_R = tRL + tBURST + tRTRS - tWL + tWPRE; + tWRRD_S = tWL + tBURST + tWTR_S - tAL; + tWRRD_L = tWL + tBURST + tWTR_L - tAL; + tWRRD_R = tWL + tBURST + tRTRS - tRL + tRPRE; + tRDAACT = tAL + tRTP + tRP; + tWRPRE = tWL + tBURST + tWR; + tWRAACT = tWRPRE + tRP; + tRDPDEN = tRL + tBURST + tCK; + tWRPDEN = tWL + tBURST + tWR; + tWRAPDEN = tWL + tBURST + tWR + tCK; - mPools.insert({ - "NAW", { - 4, { - {"ACT", tFAW}, - } - } - }); + mPools.insert({"CMD_BUS", + {1, + { + {"ACT", tCK}, + {"RD", tCK}, + {"WR", tCK}, + {"PREPB", tCK}, + {"RDA", tCK}, + {"WRA", tCK}, + {"REFAB", tCK}, + {"PREAB", tCK}, + {"PDEP", tCK}, + {"PDXP", tCK}, + {"SREFEN", tCK}, + {"SREFEX", tCK}, + {"PDEA", tCK}, + {"PDXA", tCK}, + }}}); + mPools.insert({"NAW", + {4, + { + {"ACT", tFAW}, + }}}); } -const std::vector TimeDependenciesInfoDDR4::getPossiblePhases() { - return { - "ACT", - "RD", - "WR", - "PREPB", - "RDA", - "WRA", - "REFAB", - "PREAB", - "PDEP", - "PDXP", - "SREFEN", - "SREFEX", - "PDEA", - "PDXA", - }; +const std::vector TimeDependenciesInfoDDR4::getPossiblePhases() +{ + return { + "ACT", + "RD", + "WR", + "PREPB", + "RDA", + "WRA", + "REFAB", + "PREAB", + "PDEP", + "PDXP", + "SREFEN", + "SREFEX", + "PDEA", + "PDXA", + }; } -DependencyMap TimeDependenciesInfoDDR4::mSpecializedGetDependencies() const { - DependencyMap dmap; +DependencyMap TimeDependenciesInfoDDR4::mSpecializedGetDependencies() const +{ + DependencyMap dmap; - dmap.emplace( - piecewise_construct, - forward_as_tuple("ACT"), - forward_as_tuple( - initializer_list{ - {tRC, "ACT", DependencyType::IntraBank, "tRC"}, - {tRRD_L, "ACT", DependencyType::IntraBankGroup, "tRRD_L"}, - {tRRD_S, "ACT", DependencyType::IntraRank, "tRRD_S"}, - {tRDAACT, "RDA", DependencyType::IntraBank, "tRDAACT"}, - {tWRAACT, "WRA", DependencyType::IntraBank, "tWRAACT"}, - {tRP, "PREPB", DependencyType::IntraBank, "tRP"}, - {tRP, "PREAB", DependencyType::IntraRank, "tRP"}, - {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, - {tXP, "PDXP", DependencyType::IntraRank, "tXP"}, - {tRFC, "REFAB", DependencyType::IntraRank, "tRFC"}, - {tXS, "SREFEX", DependencyType::IntraRank, "tXS"}, - {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, - {tFAW, "NAW", DependencyType::IntraRank, "tFAW"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("ACT"), + forward_as_tuple(initializer_list{ + {tRC, "ACT", DependencyType::IntraBank, "tRC"}, + {tRRD_L, "ACT", DependencyType::IntraBankGroup, "tRRD_L"}, + {tRRD_S, "ACT", DependencyType::IntraRank, "tRRD_S"}, + {tRDAACT, "RDA", DependencyType::IntraBank, "tRDAACT"}, + {tWRAACT, "WRA", DependencyType::IntraBank, "tWRAACT"}, + {tRP, "PREPB", DependencyType::IntraBank, "tRP"}, + {tRP, "PREAB", DependencyType::IntraRank, "tRP"}, + {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, + {tXP, "PDXP", DependencyType::IntraRank, "tXP"}, + {tRFC, "REFAB", DependencyType::IntraRank, "tRFC"}, + {tXS, "SREFEX", DependencyType::IntraRank, "tXS"}, + {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, + {tFAW, "NAW", DependencyType::IntraRank, "tFAW"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("RD"), - forward_as_tuple( - initializer_list{ - {tRCD - tAL, "ACT", DependencyType::IntraBank, "tRCD - tAL"}, - {tCCD_L, "RD", DependencyType::IntraBank, "tCCD_L"}, // - {tCCD_L, "RD", DependencyType::IntraBankGroup, "tCCD_L"}, - {tCCD_S, "RD", DependencyType::IntraRank, "tCCD_S"}, - {tBURST + tRTRS, "RD", DependencyType::InterRank, "tBURST + tRTRS"}, - {tCCD_L, "RDA", DependencyType::IntraBankGroup, "tCCD_L"}, - {tCCD_S, "RDA", DependencyType::IntraRank, "tCCD_S"}, - {tBURST + tRTRS, "RDA", DependencyType::InterRank, "tBURST + tRTRS"}, - {tWRRD_L, "WR", DependencyType::IntraBank, "tWRRD_L"}, // - {tWRRD_L, "WR", DependencyType::IntraBankGroup, "tWRRD_L"}, - {tWRRD_S, "WR", DependencyType::IntraRank, "tWRRD_S"}, - {tWRRD_R, "WR", DependencyType::InterRank, "tWRRD_R"}, - {tWRRD_L, "WRA", DependencyType::IntraBankGroup, "tWRRD_L"}, - {tWRRD_S, "WRA", DependencyType::IntraRank, "tWRRD_S"}, - {tWRRD_R, "WRA", DependencyType::InterRank, "tWRRD_R"}, - {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, - {tXSDLL, "SREFEX", DependencyType::IntraRank, "tXSDLL"}, - {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("RD"), + forward_as_tuple(initializer_list{ + {tRCD - tAL, "ACT", DependencyType::IntraBank, "tRCD - tAL"}, + {tCCD_L, "RD", DependencyType::IntraBank, "tCCD_L"}, // + {tCCD_L, "RD", DependencyType::IntraBankGroup, "tCCD_L"}, + {tCCD_S, "RD", DependencyType::IntraRank, "tCCD_S"}, + {tBURST + tRTRS, "RD", DependencyType::InterRank, "tBURST + tRTRS"}, + {tCCD_L, "RDA", DependencyType::IntraBankGroup, "tCCD_L"}, + {tCCD_S, "RDA", DependencyType::IntraRank, "tCCD_S"}, + {tBURST + tRTRS, "RDA", DependencyType::InterRank, "tBURST + tRTRS"}, + {tWRRD_L, "WR", DependencyType::IntraBank, "tWRRD_L"}, // + {tWRRD_L, "WR", DependencyType::IntraBankGroup, "tWRRD_L"}, + {tWRRD_S, "WR", DependencyType::IntraRank, "tWRRD_S"}, + {tWRRD_R, "WR", DependencyType::InterRank, "tWRRD_R"}, + {tWRRD_L, "WRA", DependencyType::IntraBankGroup, "tWRRD_L"}, + {tWRRD_S, "WRA", DependencyType::IntraRank, "tWRRD_S"}, + {tWRRD_R, "WRA", DependencyType::InterRank, "tWRRD_R"}, + {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, + {tXSDLL, "SREFEX", DependencyType::IntraRank, "tXSDLL"}, + {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("WR"), - forward_as_tuple( - initializer_list{ - {tRCD - tAL, "ACT", DependencyType::IntraBank, "tRCD - tAL"}, - {tRDWR, "RD", DependencyType::IntraBank, "tRDWR"}, // - {tRDWR, "RD", DependencyType::IntraBankGroup, "tRDWR"}, // - {tRDWR, "RD", DependencyType::IntraRank, "tRDWR"}, - {tRDWR_R, "RD", DependencyType::InterRank, "tRDWR_R"}, - {tRDWR, "RDA", DependencyType::IntraBankGroup, "tRDWR"}, // - {tRDWR, "RDA", DependencyType::IntraRank, "tRDWR"}, - {tRDWR_R, "RDA", DependencyType::InterRank, "tRDWR_R"}, - {tCCD_L, "WR", DependencyType::IntraBank, "tCCD_L"}, // - {tCCD_L, "WR", DependencyType::IntraBankGroup, "tCCD_L"}, - {tCCD_S, "WR", DependencyType::IntraRank, "tCCD_S"}, - {tBURST + tRTRS, "WR", DependencyType::InterRank, "tBURST + tRTRS"}, - {tCCD_L, "WRA", DependencyType::IntraBankGroup, "tCCD_L"}, - {tCCD_S, "WRA", DependencyType::IntraRank, "tCCD_S"}, - {tBURST + tRTRS, "WRA", DependencyType::InterRank, "tBURST + tRTRS"}, - {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, - {tXSDLL, "SREFEX", DependencyType::IntraRank, "tXSDLL"}, - {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("WR"), + forward_as_tuple(initializer_list{ + {tRCD - tAL, "ACT", DependencyType::IntraBank, "tRCD - tAL"}, + {tRDWR, "RD", DependencyType::IntraBank, "tRDWR"}, // + {tRDWR, "RD", DependencyType::IntraBankGroup, "tRDWR"}, // + {tRDWR, "RD", DependencyType::IntraRank, "tRDWR"}, + {tRDWR_R, "RD", DependencyType::InterRank, "tRDWR_R"}, + {tRDWR, "RDA", DependencyType::IntraBankGroup, "tRDWR"}, // + {tRDWR, "RDA", DependencyType::IntraRank, "tRDWR"}, + {tRDWR_R, "RDA", DependencyType::InterRank, "tRDWR_R"}, + {tCCD_L, "WR", DependencyType::IntraBank, "tCCD_L"}, // + {tCCD_L, "WR", DependencyType::IntraBankGroup, "tCCD_L"}, + {tCCD_S, "WR", DependencyType::IntraRank, "tCCD_S"}, + {tBURST + tRTRS, "WR", DependencyType::InterRank, "tBURST + tRTRS"}, + {tCCD_L, "WRA", DependencyType::IntraBankGroup, "tCCD_L"}, + {tCCD_S, "WRA", DependencyType::IntraRank, "tCCD_S"}, + {tBURST + tRTRS, "WRA", DependencyType::InterRank, "tBURST + tRTRS"}, + {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, + {tXSDLL, "SREFEX", DependencyType::IntraRank, "tXSDLL"}, + {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("PREPB"), - forward_as_tuple( - initializer_list{ - {tRAS, "ACT", DependencyType::IntraBank, "tRAS"}, - {tAL + tRTP, "RD", DependencyType::IntraBank, "tAL + tRTP"}, - {tWRPRE, "WR", DependencyType::IntraBank, "tWRPRE"}, - {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, - {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("PREPB"), + forward_as_tuple(initializer_list{ + {tRAS, "ACT", DependencyType::IntraBank, "tRAS"}, + {tAL + tRTP, "RD", DependencyType::IntraBank, "tAL + tRTP"}, + {tWRPRE, "WR", DependencyType::IntraBank, "tWRPRE"}, + {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, + {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("RDA"), - forward_as_tuple( - initializer_list{ - {tRCD - tAL, "ACT", DependencyType::IntraBank, "tRCD - tAL"}, - {tCCD_L, "RD", DependencyType::IntraBank, "tCCD_L"}, - {tCCD_L, "RD", DependencyType::IntraBankGroup, "tCCD_L"}, - {tCCD_S, "RD", DependencyType::IntraRank, "tCCD_S"}, - {tBURST + tRTRS, "RD", DependencyType::InterRank, "tBURST + tRTRS"}, - {tCCD_L, "RDA", DependencyType::IntraBankGroup, "tCCD_L"}, - {tCCD_S, "RDA", DependencyType::IntraRank, "tCCD_S"}, - {tBURST + tRTRS, "RDA", DependencyType::InterRank, "tBURST + tRTRS"}, - {max({tWRRD_L, tWRPRE - tRTP - tAL}), "WR", DependencyType::IntraBank, "max(tWRRD_L, tWRPRE - tRTP - tAL)"}, - {tWRRD_L, "WR", DependencyType::IntraBankGroup, "tWRRD_L"}, - {tWRRD_S, "WR", DependencyType::IntraRank, "tWRRD_S"}, - {tWRRD_R, "WR", DependencyType::InterRank, "tWRRD_R"}, - {tWRRD_L, "WRA", DependencyType::IntraBankGroup, "tWRRD_L"}, - {tWRRD_S, "WRA", DependencyType::IntraRank, "tWRRD_S"}, - {tWRRD_R, "WRA", DependencyType::InterRank, "tWRRD_R"}, - {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, - {tXSDLL, "SREFEX", DependencyType::IntraRank, "tXSDLL"}, - {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("RDA"), + forward_as_tuple(initializer_list{ + {tRCD - tAL, "ACT", DependencyType::IntraBank, "tRCD - tAL"}, + {tCCD_L, "RD", DependencyType::IntraBank, "tCCD_L"}, + {tCCD_L, "RD", DependencyType::IntraBankGroup, "tCCD_L"}, + {tCCD_S, "RD", DependencyType::IntraRank, "tCCD_S"}, + {tBURST + tRTRS, "RD", DependencyType::InterRank, "tBURST + tRTRS"}, + {tCCD_L, "RDA", DependencyType::IntraBankGroup, "tCCD_L"}, + {tCCD_S, "RDA", DependencyType::IntraRank, "tCCD_S"}, + {tBURST + tRTRS, "RDA", DependencyType::InterRank, "tBURST + tRTRS"}, + {max({tWRRD_L, tWRPRE - tRTP - tAL}), + "WR", + DependencyType::IntraBank, + "max(tWRRD_L, tWRPRE - tRTP - tAL)"}, + {tWRRD_L, "WR", DependencyType::IntraBankGroup, "tWRRD_L"}, + {tWRRD_S, "WR", DependencyType::IntraRank, "tWRRD_S"}, + {tWRRD_R, "WR", DependencyType::InterRank, "tWRRD_R"}, + {tWRRD_L, "WRA", DependencyType::IntraBankGroup, "tWRRD_L"}, + {tWRRD_S, "WRA", DependencyType::IntraRank, "tWRRD_S"}, + {tWRRD_R, "WRA", DependencyType::InterRank, "tWRRD_R"}, + {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, + {tXSDLL, "SREFEX", DependencyType::IntraRank, "tXSDLL"}, + {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("WRA"), - forward_as_tuple( - initializer_list{ - {tRCD - tAL, "ACT", DependencyType::IntraBank, "tRCD - tAL"}, - {tRDWR, "RD", DependencyType::IntraBank, "tRDWR"}, - {tRDWR, "RD", DependencyType::IntraBankGroup, "tRDWR"}, - {tRDWR, "RD", DependencyType::IntraRank, "tRDWR"}, - {tRDWR_R, "RD", DependencyType::InterRank, "tRDWR_R"}, - {tRDWR, "RDA", DependencyType::IntraBankGroup, "tRDWR"}, - {tRDWR, "RDA", DependencyType::IntraRank, "tRDWR"}, - {tRDWR_R, "RDA", DependencyType::InterRank, "tRDWR_R"}, - {tCCD_L, "WR", DependencyType::IntraBank, "tCCD_L"}, - {tCCD_L, "WR", DependencyType::IntraBankGroup, "tCCD_L"}, - {tCCD_S, "WR", DependencyType::IntraRank, "tCCD_S"}, - {tBURST + tRTRS, "WR", DependencyType::InterRank, "tBURST + tRTRS"}, - {tCCD_L, "WRA", DependencyType::IntraBankGroup, "tCCD_L"}, - {tCCD_S, "WRA", DependencyType::IntraRank, "tCCD_S"}, - {tBURST + tRTRS, "WRA", DependencyType::InterRank, "tBURST + tRTRS"}, - {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, - {tXSDLL, "SREFEX", DependencyType::IntraRank, "tXSDLL"}, - {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("WRA"), + forward_as_tuple(initializer_list{ + {tRCD - tAL, "ACT", DependencyType::IntraBank, "tRCD - tAL"}, + {tRDWR, "RD", DependencyType::IntraBank, "tRDWR"}, + {tRDWR, "RD", DependencyType::IntraBankGroup, "tRDWR"}, + {tRDWR, "RD", DependencyType::IntraRank, "tRDWR"}, + {tRDWR_R, "RD", DependencyType::InterRank, "tRDWR_R"}, + {tRDWR, "RDA", DependencyType::IntraBankGroup, "tRDWR"}, + {tRDWR, "RDA", DependencyType::IntraRank, "tRDWR"}, + {tRDWR_R, "RDA", DependencyType::InterRank, "tRDWR_R"}, + {tCCD_L, "WR", DependencyType::IntraBank, "tCCD_L"}, + {tCCD_L, "WR", DependencyType::IntraBankGroup, "tCCD_L"}, + {tCCD_S, "WR", DependencyType::IntraRank, "tCCD_S"}, + {tBURST + tRTRS, "WR", DependencyType::InterRank, "tBURST + tRTRS"}, + {tCCD_L, "WRA", DependencyType::IntraBankGroup, "tCCD_L"}, + {tCCD_S, "WRA", DependencyType::IntraRank, "tCCD_S"}, + {tBURST + tRTRS, "WRA", DependencyType::InterRank, "tBURST + tRTRS"}, + {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, + {tXSDLL, "SREFEX", DependencyType::IntraRank, "tXSDLL"}, + {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("REFAB"), - forward_as_tuple( - initializer_list{ - {tRC, "ACT", DependencyType::IntraRank, "tRC"}, - {tRDAACT, "RDA", DependencyType::IntraRank, "tRDAACT"}, - {tWRPRE + tRP, "WRA", DependencyType::IntraRank, "tWRPRE + tRP"}, - {tRP, "PREPB", DependencyType::IntraRank, "tRP"}, - {tRP, "PREAB", DependencyType::IntraRank, "tRP"}, - {tXP, "PDXP", DependencyType::IntraRank, "tXP"}, - {tRFC, "REFAB", DependencyType::IntraRank, "tRFC"}, - {tXS, "SREFEX", DependencyType::IntraRank, "tXS"}, - {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("REFAB"), + forward_as_tuple(initializer_list{ + {tRC, "ACT", DependencyType::IntraRank, "tRC"}, + {tRDAACT, "RDA", DependencyType::IntraRank, "tRDAACT"}, + {tWRPRE + tRP, "WRA", DependencyType::IntraRank, "tWRPRE + tRP"}, + {tRP, "PREPB", DependencyType::IntraRank, "tRP"}, + {tRP, "PREAB", DependencyType::IntraRank, "tRP"}, + {tXP, "PDXP", DependencyType::IntraRank, "tXP"}, + {tRFC, "REFAB", DependencyType::IntraRank, "tRFC"}, + {tXS, "SREFEX", DependencyType::IntraRank, "tXS"}, + {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("PREAB"), - forward_as_tuple( - initializer_list{ - {tRAS, "ACT", DependencyType::IntraRank, "tRAS"}, - {tAL + tRTP, "RD", DependencyType::IntraRank, "tAL + tRTP"}, - {tAL + tRTP, "RDA", DependencyType::IntraRank, "tAL + tRTP"}, - {tWRPRE, "WR", DependencyType::IntraRank, "tWRPRE"}, - {tWRPRE, "WRA", DependencyType::IntraRank, "tWRPRE"}, - {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, - {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("PREAB"), + forward_as_tuple(initializer_list{ + {tRAS, "ACT", DependencyType::IntraRank, "tRAS"}, + {tAL + tRTP, "RD", DependencyType::IntraRank, "tAL + tRTP"}, + {tAL + tRTP, "RDA", DependencyType::IntraRank, "tAL + tRTP"}, + {tWRPRE, "WR", DependencyType::IntraRank, "tWRPRE"}, + {tWRPRE, "WRA", DependencyType::IntraRank, "tWRPRE"}, + {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, + {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("PDEP"), - forward_as_tuple( - initializer_list{ - {tRDPDEN, "RD", DependencyType::IntraRank, "tRDPDEN"}, - {tRDPDEN, "RDA", DependencyType::IntraRank, "tRDPDEN"}, - {tWRAPDEN, "WRA", DependencyType::IntraRank, "tWRAPDEN"}, - {tPRPDEN, "PREPB", DependencyType::IntraRank, "tPRPDEN"}, - {tPRPDEN, "PREAB", DependencyType::IntraRank, "tPRPDEN"}, - {tCKE, "PDXP", DependencyType::IntraRank, "tCKE"}, - {tREFPDEN, "REFAB", DependencyType::IntraRank, "tREFPDEN"}, - {tXS, "SREFEX", DependencyType::IntraRank, "tXS"}, - {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("PDEP"), + forward_as_tuple(initializer_list{ + {tRDPDEN, "RD", DependencyType::IntraRank, "tRDPDEN"}, + {tRDPDEN, "RDA", DependencyType::IntraRank, "tRDPDEN"}, + {tWRAPDEN, "WRA", DependencyType::IntraRank, "tWRAPDEN"}, + {tPRPDEN, "PREPB", DependencyType::IntraRank, "tPRPDEN"}, + {tPRPDEN, "PREAB", DependencyType::IntraRank, "tPRPDEN"}, + {tCKE, "PDXP", DependencyType::IntraRank, "tCKE"}, + {tREFPDEN, "REFAB", DependencyType::IntraRank, "tREFPDEN"}, + {tXS, "SREFEX", DependencyType::IntraRank, "tXS"}, + {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("PDXP"), - forward_as_tuple( - initializer_list{ - {tPD, "PDEP", DependencyType::IntraRank, "tPD"}, - {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("PDXP"), + forward_as_tuple(initializer_list{ + {tPD, "PDEP", DependencyType::IntraRank, "tPD"}, + {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("SREFEN"), - forward_as_tuple( - initializer_list{ - {tRC, "ACT", DependencyType::IntraRank, "tRC"}, - {max({tRDPDEN, tAL + tRTP + tRP}), "RDA", DependencyType::IntraRank, "max(tRDPDEN, tAL + tRTP + tRP)"}, - {max({tWRAPDEN, tWRPRE + tRP}), "WRA", DependencyType::IntraRank, "max(tWRAPDEN, tWRPRE + tRP)"}, - {tRP, "PREPB", DependencyType::IntraRank, "tRP"}, - {tRP, "PREAB", DependencyType::IntraRank, "tRP"}, - {tXP, "PDXP", DependencyType::IntraRank, "tXP"}, - {tRFC, "REFAB", DependencyType::IntraRank, "tRFC"}, - {tXS, "SREFEX", DependencyType::IntraRank, "tXS"}, - {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("SREFEN"), + forward_as_tuple(initializer_list{ + {tRC, "ACT", DependencyType::IntraRank, "tRC"}, + {max({tRDPDEN, tAL + tRTP + tRP}), + "RDA", + DependencyType::IntraRank, + "max(tRDPDEN, tAL + tRTP + tRP)"}, + {max({tWRAPDEN, tWRPRE + tRP}), + "WRA", + DependencyType::IntraRank, + "max(tWRAPDEN, tWRPRE + tRP)"}, + {tRP, "PREPB", DependencyType::IntraRank, "tRP"}, + {tRP, "PREAB", DependencyType::IntraRank, "tRP"}, + {tXP, "PDXP", DependencyType::IntraRank, "tXP"}, + {tRFC, "REFAB", DependencyType::IntraRank, "tRFC"}, + {tXS, "SREFEX", DependencyType::IntraRank, "tXS"}, + {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("SREFEX"), - forward_as_tuple( - initializer_list{ - {tCKESR, "SREFEN", DependencyType::IntraRank, "tCKESR"}, - {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("SREFEX"), + forward_as_tuple(initializer_list{ + {tCKESR, "SREFEN", DependencyType::IntraRank, "tCKESR"}, + {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("PDEA"), - forward_as_tuple( - initializer_list{ - {tACTPDEN, "ACT", DependencyType::IntraRank, "tACTPDEN"}, - {tRDPDEN, "RD", DependencyType::IntraRank, "tRDPDEN"}, - {tRDPDEN, "RDA", DependencyType::IntraRank, "tRDPDEN"}, - {tWRPDEN, "WR", DependencyType::IntraRank, "tWRPDEN"}, - {tWRAPDEN, "WRA", DependencyType::IntraRank, "tWRAPDEN"}, - {tPRPDEN, "PREPB", DependencyType::IntraRank, "tPRPDEN"}, - {tCKE, "PDXA", DependencyType::IntraRank, "tCKE"}, - {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("PDEA"), + forward_as_tuple(initializer_list{ + {tACTPDEN, "ACT", DependencyType::IntraRank, "tACTPDEN"}, + {tRDPDEN, "RD", DependencyType::IntraRank, "tRDPDEN"}, + {tRDPDEN, "RDA", DependencyType::IntraRank, "tRDPDEN"}, + {tWRPDEN, "WR", DependencyType::IntraRank, "tWRPDEN"}, + {tWRAPDEN, "WRA", DependencyType::IntraRank, "tWRAPDEN"}, + {tPRPDEN, "PREPB", DependencyType::IntraRank, "tPRPDEN"}, + {tCKE, "PDXA", DependencyType::IntraRank, "tCKE"}, + {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("PDXA"), - forward_as_tuple( - initializer_list{ - {tPD, "PDEA", DependencyType::IntraRank, "tPD"}, - {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("PDXA"), + forward_as_tuple(initializer_list{ + {tPD, "PDEA", DependencyType::IntraRank, "tPD"}, + {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, + })); - return dmap; + return dmap; } diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR4.h b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR4.h index f9be625e..81672e1c 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR4.h +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR4.h @@ -37,17 +37,18 @@ #include "../dramtimedependenciesbase.h" -class TimeDependenciesInfoDDR4 final : public DRAMTimeDependenciesBase { - public: +class TimeDependenciesInfoDDR4 final : public DRAMTimeDependenciesBase +{ +public: TimeDependenciesInfoDDR4(const QJsonObject& memspec, const uint clk); static const std::vector getPossiblePhases(); - protected: +protected: void mInitializeValues() override; DependencyMap mSpecializedGetDependencies() const override; - protected: +protected: uint burstLength; uint dataRate; @@ -95,5 +96,4 @@ class TimeDependenciesInfoDDR4 final : public DRAMTimeDependenciesBase { uint tRDPDEN; uint tWRPDEN; uint tWRAPDEN; - }; diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.cpp b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.cpp index 037b5b80..43227bf4 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.cpp +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.cpp @@ -38,629 +38,1103 @@ using namespace std; -TimeDependenciesInfoDDR5::TimeDependenciesInfoDDR5(const QJsonObject& memspec, const uint tCK) : DRAMTimeDependenciesBase(memspec, tCK) { - mInitializeValues(); - +TimeDependenciesInfoDDR5::TimeDependenciesInfoDDR5(const QJsonObject& memspec, const uint tCK) : + DRAMTimeDependenciesBase(memspec, tCK) +{ + mInitializeValues(); } -void TimeDependenciesInfoDDR5::rankIDToRankIDs(size_t rankID, size_t& dimmRID, size_t& physRID, size_t& logRID) const { - logRID = rankID; - physRID = logRID / mNumLogicalRanksPerPhysicalRank; - dimmRID = physRID / mNumPhysicalRanksPerDIMMRank; +void TimeDependenciesInfoDDR5::rankIDToRankIDs(size_t rankID, + size_t& dimmRID, + size_t& physRID, + size_t& logRID) const +{ + logRID = rankID; + physRID = logRID / mNumLogicalRanksPerPhysicalRank; + dimmRID = physRID / mNumPhysicalRanksPerDIMMRank; } -void TimeDependenciesInfoDDR5::bankIDToBankInGroup(size_t logicalRankID, size_t bankID, size_t& bankInGroup) const { - bankInGroup = logicalRankID * mNumBanksPerGroup + bankID % mNumBanksPerGroup; - +void TimeDependenciesInfoDDR5::bankIDToBankInGroup(size_t logicalRankID, + size_t bankID, + size_t& bankInGroup) const +{ + bankInGroup = logicalRankID * mNumBanksPerGroup + bankID % mNumBanksPerGroup; } -void TimeDependenciesInfoDDR5::mInitializeValues() { - mNumOfRanks = mMemspecJson["memarchitecturespec"].toObject()["nbrOfRanks"].toInt(); - mNumOfDIMMRanks = mMemspecJson["memarchitecturespec"].toObject()["nbrOfDIMMRanks"].toInt(); - mNumPhysicalRanksPerDIMMRank = mMemspecJson["memarchitecturespec"].toObject()["nbrOfPhysicalRanks"].toInt(); - mNumLogicalRanksPerPhysicalRank = mMemspecJson["memarchitecturespec"].toObject()["nbrOfLogicalRanks"].toInt(); +void TimeDependenciesInfoDDR5::mInitializeValues() +{ + mNumOfRanks = mMemspecJson["memarchitecturespec"].toObject()["nbrOfRanks"].toInt(); + mNumOfDIMMRanks = mMemspecJson["memarchitecturespec"].toObject()["nbrOfDIMMRanks"].toInt(); + mNumPhysicalRanksPerDIMMRank = + mMemspecJson["memarchitecturespec"].toObject()["nbrOfPhysicalRanks"].toInt(); + mNumLogicalRanksPerPhysicalRank = + mMemspecJson["memarchitecturespec"].toObject()["nbrOfLogicalRanks"].toInt(); - mNumBanksPerGroup = mMemspecJson["memarchitecturespec"].toObject()["nbrOfBanks"].toInt(1); - mNumBanksPerGroup /= mMemspecJson["memarchitecturespec"].toObject()["nbrOfBankGroups"].toInt(1); + mNumBanksPerGroup = mMemspecJson["memarchitecturespec"].toObject()["nbrOfBanks"].toInt(1); + mNumBanksPerGroup /= mMemspecJson["memarchitecturespec"].toObject()["nbrOfBankGroups"].toInt(1); - burstLength = mMemspecJson["memarchitecturespec"].toObject()["burstLength"].toInt(); - dataRate = mMemspecJson["memarchitecturespec"].toObject()["dataRate"].toInt(); - refMode = mMemspecJson["memarchitecturespec"].toObject()["refMode"].toInt(); - cmdMode = mMemspecJson["memarchitecturespec"].toObject()["cmdMode"].toInt(); - bitWidth = mMemspecJson["memarchitecturespec"].toObject()["width"].toInt(); + burstLength = mMemspecJson["memarchitecturespec"].toObject()["burstLength"].toInt(); + dataRate = mMemspecJson["memarchitecturespec"].toObject()["dataRate"].toInt(); + refMode = mMemspecJson["memarchitecturespec"].toObject()["refMode"].toInt(); + cmdMode = mMemspecJson["memarchitecturespec"].toObject()["cmdMode"].toInt(); + bitWidth = mMemspecJson["memarchitecturespec"].toObject()["width"].toInt(); - tRCD = tCK * mMemspecJson["memtimingspec"].toObject()["RCD"].toInt(); - tPPD = tCK * mMemspecJson["memtimingspec"].toObject()["PPD"].toInt(); - tRP = tCK * mMemspecJson["memtimingspec"].toObject()["RP"].toInt(); - tRAS = tCK * mMemspecJson["memtimingspec"].toObject()["RAS"].toInt(); - tRL = tCK * mMemspecJson["memtimingspec"].toObject()["RL"].toInt(); - RBL = tCK * mMemspecJson["memtimingspec"].toObject()["BL"].toInt(); - tRTP = tCK * mMemspecJson["memtimingspec"].toObject()["RTP"].toInt(); - tRPRE = tCK * mMemspecJson["memtimingspec"].toObject()["RPRE"].toInt(); - tRPST = tCK * mMemspecJson["memtimingspec"].toObject()["RPST"].toInt(); - tRDDQS = tCK * mMemspecJson["memtimingspec"].toObject()["RDDQS"].toInt(); - tWL = tCK * mMemspecJson["memtimingspec"].toObject()["WL"].toInt(); - WBL = tCK * mMemspecJson["memtimingspec"].toObject()["BL"].toInt(); - tWPRE = tCK * mMemspecJson["memtimingspec"].toObject()["WPRE"].toInt(); - tWPST = tCK * mMemspecJson["memtimingspec"].toObject()["WPST"].toInt(); - tWR = tCK * mMemspecJson["memtimingspec"].toObject()["WR"].toInt(); - tCCD_L_slr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_L_slr"].toInt(); - tCCD_L_WR_slr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_L_WR_slr"].toInt(); - tCCD_L_WR2_slr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_L_WR2_slr"].toInt(); - tCCD_S_slr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_S_slr"].toInt(); - tCCD_S_WR_slr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_S_WR_slr"].toInt(); - tCCD_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_dlr"].toInt(); - tCCD_WR_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_WR_dlr"].toInt(); - tCCD_WR_dpr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_WR_dpr"].toInt(); - tRRD_S_slr = tCK * mMemspecJson["memtimingspec"].toObject()["RRD_S_slr"].toInt(); - tRRD_L_slr = tCK * mMemspecJson["memtimingspec"].toObject()["RRD_L_slr"].toInt(); - tRRD_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["RRD_dlr"].toInt(); - tFAW_slr = tCK * mMemspecJson["memtimingspec"].toObject()["FAW_slr"].toInt(); - tFAW_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["FAW_dlr"].toInt(); - tWTR_L = tCK * mMemspecJson["memtimingspec"].toObject()["WTR_L"].toInt(); - tWTR_S = tCK * mMemspecJson["memtimingspec"].toObject()["WTR_S"].toInt(); - tRFC_slr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC_slr"].toInt(); - tRFC_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC_dlr"].toInt(); - tRFC_dpr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC_dpr"].toInt(); - tRFCsb_slr = tCK * mMemspecJson["memtimingspec"].toObject()["RFCsb_slr"].toInt(); - tRFCsb_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["RFCsb_dlr"].toInt(); - tREFI = tCK * mMemspecJson["memtimingspec"].toObject()["REFI"].toInt(); - tREFSBRD_slr = tCK * mMemspecJson["memtimingspec"].toObject()["REFSBRD_slr"].toInt(); - tREFSBRD_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["REFSBRD_dlr"].toInt(); - tRTRS = tCK * mMemspecJson["memtimingspec"].toObject()["RTRS"].toInt(); - UNKNOWN = tCK * mMemspecJson["memtimingspec"].toObject()["NKNOWN"].toInt(); - tCPDED = tCK * mMemspecJson["memtimingspec"].toObject()["CPDED"].toInt(); - tPD = tCK * mMemspecJson["memtimingspec"].toObject()["PD"].toInt(); - tXP = tCK * mMemspecJson["memtimingspec"].toObject()["XP"].toInt(); - tACTPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["ACTPDEN"].toInt(); - tPRPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["PRPDEN"].toInt(); - tREFPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["REFPDEN"].toInt(); + tRCD = tCK * mMemspecJson["memtimingspec"].toObject()["RCD"].toInt(); + tPPD = tCK * mMemspecJson["memtimingspec"].toObject()["PPD"].toInt(); + tRP = tCK * mMemspecJson["memtimingspec"].toObject()["RP"].toInt(); + tRAS = tCK * mMemspecJson["memtimingspec"].toObject()["RAS"].toInt(); + tRL = tCK * mMemspecJson["memtimingspec"].toObject()["RL"].toInt(); + RBL = tCK * mMemspecJson["memtimingspec"].toObject()["BL"].toInt(); + tRTP = tCK * mMemspecJson["memtimingspec"].toObject()["RTP"].toInt(); + tRPRE = tCK * mMemspecJson["memtimingspec"].toObject()["RPRE"].toInt(); + tRPST = tCK * mMemspecJson["memtimingspec"].toObject()["RPST"].toInt(); + tRDDQS = tCK * mMemspecJson["memtimingspec"].toObject()["RDDQS"].toInt(); + tWL = tCK * mMemspecJson["memtimingspec"].toObject()["WL"].toInt(); + WBL = tCK * mMemspecJson["memtimingspec"].toObject()["BL"].toInt(); + tWPRE = tCK * mMemspecJson["memtimingspec"].toObject()["WPRE"].toInt(); + tWPST = tCK * mMemspecJson["memtimingspec"].toObject()["WPST"].toInt(); + tWR = tCK * mMemspecJson["memtimingspec"].toObject()["WR"].toInt(); + tCCD_L_slr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_L_slr"].toInt(); + tCCD_L_WR_slr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_L_WR_slr"].toInt(); + tCCD_L_WR2_slr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_L_WR2_slr"].toInt(); + tCCD_S_slr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_S_slr"].toInt(); + tCCD_S_WR_slr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_S_WR_slr"].toInt(); + tCCD_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_dlr"].toInt(); + tCCD_WR_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_WR_dlr"].toInt(); + tCCD_WR_dpr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_WR_dpr"].toInt(); + tRRD_S_slr = tCK * mMemspecJson["memtimingspec"].toObject()["RRD_S_slr"].toInt(); + tRRD_L_slr = tCK * mMemspecJson["memtimingspec"].toObject()["RRD_L_slr"].toInt(); + tRRD_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["RRD_dlr"].toInt(); + tFAW_slr = tCK * mMemspecJson["memtimingspec"].toObject()["FAW_slr"].toInt(); + tFAW_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["FAW_dlr"].toInt(); + tWTR_L = tCK * mMemspecJson["memtimingspec"].toObject()["WTR_L"].toInt(); + tWTR_S = tCK * mMemspecJson["memtimingspec"].toObject()["WTR_S"].toInt(); + tRFC_slr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC_slr"].toInt(); + tRFC_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC_dlr"].toInt(); + tRFC_dpr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC_dpr"].toInt(); + tRFCsb_slr = tCK * mMemspecJson["memtimingspec"].toObject()["RFCsb_slr"].toInt(); + tRFCsb_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["RFCsb_dlr"].toInt(); + tREFI = tCK * mMemspecJson["memtimingspec"].toObject()["REFI"].toInt(); + tREFSBRD_slr = tCK * mMemspecJson["memtimingspec"].toObject()["REFSBRD_slr"].toInt(); + tREFSBRD_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["REFSBRD_dlr"].toInt(); + tRTRS = tCK * mMemspecJson["memtimingspec"].toObject()["RTRS"].toInt(); + UNKNOWN = tCK * mMemspecJson["memtimingspec"].toObject()["NKNOWN"].toInt(); + tCPDED = tCK * mMemspecJson["memtimingspec"].toObject()["CPDED"].toInt(); + tPD = tCK * mMemspecJson["memtimingspec"].toObject()["PD"].toInt(); + tXP = tCK * mMemspecJson["memtimingspec"].toObject()["XP"].toInt(); + tACTPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["ACTPDEN"].toInt(); + tPRPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["PRPDEN"].toInt(); + tREFPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["REFPDEN"].toInt(); - tRC = tRAS + tRP; - - if (refMode == 1) { - tRFC_slr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC1_slr"].toInt(); - tRFC_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC1_dlr"].toInt(); - tRFC_dpr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC1_dpr"].toInt(); - tREFI = tCK * mMemspecJson["memtimingspec"].toObject()["REFI1"].toInt(); - } else { - tRFC_slr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC2_slr"].toInt(); - tRFC_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC2_dlr"].toInt(); - tRFC_dpr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC2_dpr"].toInt(); - tREFI = tCK * mMemspecJson["memtimingspec"].toObject()["REFI2"].toInt(); - } + tRC = tRAS + tRP; - if (cmdMode == 2) { - shortCmdOffset = 1 * tCK; - longCmdOffset = 3 * tCK; - } else { - shortCmdOffset = 0 * tCK; - longCmdOffset = 1 * tCK; - } - - cmdLengthDiff = tCK * mMemspecJson["memarchitecturespec"].toObject()["cmdMode"].toInt(); - - tBURST16 = 8 * tCK; - tBURST32 = 16 * tCK; - - tRD_BURST = (uint) (RBL / (float) dataRate) * tCK; - tWR_BURST = (uint) (WBL / (float) dataRate) * tCK; - tWTRA = tWR - tRTP; - tWRRDA = tWL + tBURST16 + tWTRA; - tWRPRE = tWL + tBURST16 + tWR; - tRDAACT = tRTP + tRP; - tWRAACT = tWRPRE + tRP; - tCCD_L_RTW_slr = tRL - tWL + tBURST16 + 2 * tCK - tRDDQS + tRPST + tWPRE; - tCCD_S_RTW_slr = tRL - tWL + tBURST16 + 2 * tCK - tRDDQS + tRPST + tWPRE; - tCCD_RTW_dlr = tRL - tWL + tBURST16 + 2 * tCK - tRDDQS + tRPST + tWPRE; - tRDRD_dpr = tRD_BURST + tRTRS; - tRDRD_ddr = tRD_BURST + tRTRS; - tRDWR_dpr = tRL - tWL + tRD_BURST + tRTRS - tRDDQS + tRPST + tWPRE; - tRDWR_ddr = tRL - tWL + tRD_BURST + tRTRS - tRDDQS + tRPST + tWPRE; - tCCD_L_WTR_slr = tWL + tBURST16 + tWTR_L; - tCCD_S_WTR_slr = tWL + tBURST16 + tWTR_S; - tCCD_WTR_dlr = tWL + tBURST16 + tWTR_S; - tWRWR_dpr = max(tCCD_WR_dpr, tBURST16 + tRTRS); - tWRWR_ddr = tBURST16 + tRTRS; - tWRRD_dpr = tWL - tRL + tBURST16 + tRTRS + tRDDQS + tWPST + tRPRE; - tWRRD_ddr = tWL - tRL + tBURST16 + tRTRS + tRDDQS + tWPST + tRPRE; - tRDPDEN = tRL + tBURST16 + cmdLengthDiff; - tWRPDEN = tWL + tBURST16 + tWR + cmdLengthDiff; - tWRAPDEN = tWL + tBURST16 + tWR + cmdLengthDiff; - - mPools.insert({ - "CMD_BUS", { - 1, { - {"ACT", 2 * tCK}, - {"RD", 2 * tCK}, - {"WR", 2 * tCK}, - {"RDA", 2 * tCK}, - {"WRA", 2 * tCK}, - {"PREPB", tCK}, - {"PREAB", tCK}, - {"REFAB", tCK}, - {"PRESB", tCK}, - {"RFMAB", tCK}, - {"REFSB", tCK}, - {"RFMSB", tCK}, - } + if (refMode == 1) + { + tRFC_slr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC1_slr"].toInt(); + tRFC_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC1_dlr"].toInt(); + tRFC_dpr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC1_dpr"].toInt(); + tREFI = tCK * mMemspecJson["memtimingspec"].toObject()["REFI1"].toInt(); } - }); - - mPools.insert({ - "FAW_LOGICAL", { - 4, { - {"ACT", tFAW_slr - longCmdOffset}, - {"REFSB", tFAW_slr - shortCmdOffset}, - {"RFMSB", tFAW_slr - shortCmdOffset}, - } + else + { + tRFC_slr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC2_slr"].toInt(); + tRFC_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC2_dlr"].toInt(); + tRFC_dpr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC2_dpr"].toInt(); + tREFI = tCK * mMemspecJson["memtimingspec"].toObject()["REFI2"].toInt(); } - }); - mPools.insert({ - "FAW_PHYSICAL", { - 4, { - {"ACT", tFAW_dlr - longCmdOffset}, - {"REFSB", tFAW_dlr - shortCmdOffset}, - {"RFMSB", tFAW_dlr - shortCmdOffset}, - } + if (cmdMode == 2) + { + shortCmdOffset = 1 * tCK; + longCmdOffset = 3 * tCK; + } + else + { + shortCmdOffset = 0 * tCK; + longCmdOffset = 1 * tCK; } - }); + cmdLengthDiff = tCK * mMemspecJson["memarchitecturespec"].toObject()["cmdMode"].toInt(); + + tBURST16 = 8 * tCK; + tBURST32 = 16 * tCK; + + tRD_BURST = (uint)(RBL / (float)dataRate) * tCK; + tWR_BURST = (uint)(WBL / (float)dataRate) * tCK; + tWTRA = tWR - tRTP; + tWRRDA = tWL + tBURST16 + tWTRA; + tWRPRE = tWL + tBURST16 + tWR; + tRDAACT = tRTP + tRP; + tWRAACT = tWRPRE + tRP; + tCCD_L_RTW_slr = tRL - tWL + tBURST16 + 2 * tCK - tRDDQS + tRPST + tWPRE; + tCCD_S_RTW_slr = tRL - tWL + tBURST16 + 2 * tCK - tRDDQS + tRPST + tWPRE; + tCCD_RTW_dlr = tRL - tWL + tBURST16 + 2 * tCK - tRDDQS + tRPST + tWPRE; + tRDRD_dpr = tRD_BURST + tRTRS; + tRDRD_ddr = tRD_BURST + tRTRS; + tRDWR_dpr = tRL - tWL + tRD_BURST + tRTRS - tRDDQS + tRPST + tWPRE; + tRDWR_ddr = tRL - tWL + tRD_BURST + tRTRS - tRDDQS + tRPST + tWPRE; + tCCD_L_WTR_slr = tWL + tBURST16 + tWTR_L; + tCCD_S_WTR_slr = tWL + tBURST16 + tWTR_S; + tCCD_WTR_dlr = tWL + tBURST16 + tWTR_S; + tWRWR_dpr = max(tCCD_WR_dpr, tBURST16 + tRTRS); + tWRWR_ddr = tBURST16 + tRTRS; + tWRRD_dpr = tWL - tRL + tBURST16 + tRTRS + tRDDQS + tWPST + tRPRE; + tWRRD_ddr = tWL - tRL + tBURST16 + tRTRS + tRDDQS + tWPST + tRPRE; + tRDPDEN = tRL + tBURST16 + cmdLengthDiff; + tWRPDEN = tWL + tBURST16 + tWR + cmdLengthDiff; + tWRAPDEN = tWL + tBURST16 + tWR + cmdLengthDiff; + + mPools.insert({"CMD_BUS", + {1, + { + {"ACT", 2 * tCK}, + {"RD", 2 * tCK}, + {"WR", 2 * tCK}, + {"RDA", 2 * tCK}, + {"WRA", 2 * tCK}, + {"PREPB", tCK}, + {"PREAB", tCK}, + {"REFAB", tCK}, + {"PRESB", tCK}, + {"RFMAB", tCK}, + {"REFSB", tCK}, + {"RFMSB", tCK}, + }}}); + + mPools.insert({"FAW_LOGICAL", + {4, + { + {"ACT", tFAW_slr - longCmdOffset}, + {"REFSB", tFAW_slr - shortCmdOffset}, + {"RFMSB", tFAW_slr - shortCmdOffset}, + }}}); + + mPools.insert({"FAW_PHYSICAL", + {4, + { + {"ACT", tFAW_dlr - longCmdOffset}, + {"REFSB", tFAW_dlr - shortCmdOffset}, + {"RFMSB", tFAW_dlr - shortCmdOffset}, + }}}); } -const std::vector TimeDependenciesInfoDDR5::getPossiblePhases() { - return { - "ACT", - "RD", - "WR", - "PRESB", - "PREPB", - "RDA", - "WRA", - "RFMAB", - "REFSB", - "RFMSB", - "REFAB", - "PREAB", - "PDEP", - "PDXP", - "SREFEN", - "SREFEX", - "PDEA", - "PDXA", - }; +const std::vector TimeDependenciesInfoDDR5::getPossiblePhases() +{ + return { + "ACT", + "RD", + "WR", + "PRESB", + "PREPB", + "RDA", + "WRA", + "RFMAB", + "REFSB", + "RFMSB", + "REFAB", + "PREAB", + "PDEP", + "PDXP", + "SREFEN", + "SREFEX", + "PDEA", + "PDXA", + }; } -DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const { - DependencyMap dmap; +DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const +{ + DependencyMap dmap; - auto passBurstLength16 = std::make_shared( - [] PASSFUNCTIONDECL { - auto other = std::dynamic_pointer_cast(otherPhase); - if (!other) return false; - return other->tBurstLength == 16; - } - ); - auto passBurstLength32 = std::make_shared( - [] PASSFUNCTIONDECL { - auto other = std::dynamic_pointer_cast(otherPhase); - if (!other) return false; - return other->tBurstLength == 32; - } - ); - const auto localBitWidth = bitWidth; - auto passThisBL16AndBW4 = std::make_shared( - [localBitWidth] PASSFUNCTIONDECL { - auto thisP = std::dynamic_pointer_cast(thisPhase); - if (!thisP) return false; - return thisP->tBurstLength == 16 && localBitWidth == 4; - } - ); - auto passOtherBL32ThisBL16BW4 = std::make_shared( - [passBurstLength32, passThisBL16AndBW4] PASSFUNCTIONDECL { - return passBurstLength32->execute(thisPhase, otherPhase) && passThisBL16AndBW4->execute(thisPhase, otherPhase); - } - ); - auto passOtherBL32ThisNotBL16BW4 = std::make_shared( - [passBurstLength32, passThisBL16AndBW4] PASSFUNCTIONDECL { - return passBurstLength32->execute(thisPhase, otherPhase) && !passThisBL16AndBW4->execute(thisPhase, otherPhase); - } - ); - auto passOtherBL16ThisBL16BW4 = std::make_shared( - [passBurstLength16, passThisBL16AndBW4] PASSFUNCTIONDECL { - return passBurstLength16->execute(thisPhase, otherPhase) && passThisBL16AndBW4->execute(thisPhase, otherPhase); - } - ); - auto passOtherBL16ThisNotBL16BW4 = std::make_shared( - [passBurstLength16, passThisBL16AndBW4] PASSFUNCTIONDECL { - return passBurstLength16->execute(thisPhase, otherPhase) && !passThisBL16AndBW4->execute(thisPhase, otherPhase); - } - ); + auto passBurstLength16 = std::make_shared( + [] PASSFUNCTIONDECL + { + auto other = std::dynamic_pointer_cast(otherPhase); + if (!other) + return false; + return other->tBurstLength == 16; + }); + auto passBurstLength32 = std::make_shared( + [] PASSFUNCTIONDECL + { + auto other = std::dynamic_pointer_cast(otherPhase); + if (!other) + return false; + return other->tBurstLength == 32; + }); + const auto localBitWidth = bitWidth; + auto passThisBL16AndBW4 = std::make_shared( + [localBitWidth] PASSFUNCTIONDECL + { + auto thisP = std::dynamic_pointer_cast(thisPhase); + if (!thisP) + return false; + return thisP->tBurstLength == 16 && localBitWidth == 4; + }); + auto passOtherBL32ThisBL16BW4 = std::make_shared( + [passBurstLength32, passThisBL16AndBW4] PASSFUNCTIONDECL + { + return passBurstLength32->execute(thisPhase, otherPhase) && + passThisBL16AndBW4->execute(thisPhase, otherPhase); + }); + auto passOtherBL32ThisNotBL16BW4 = std::make_shared( + [passBurstLength32, passThisBL16AndBW4] PASSFUNCTIONDECL + { + return passBurstLength32->execute(thisPhase, otherPhase) && + !passThisBL16AndBW4->execute(thisPhase, otherPhase); + }); + auto passOtherBL16ThisBL16BW4 = std::make_shared( + [passBurstLength16, passThisBL16AndBW4] PASSFUNCTIONDECL + { + return passBurstLength16->execute(thisPhase, otherPhase) && + passThisBL16AndBW4->execute(thisPhase, otherPhase); + }); + auto passOtherBL16ThisNotBL16BW4 = std::make_shared( + [passBurstLength16, passThisBL16AndBW4] PASSFUNCTIONDECL + { + return passBurstLength16->execute(thisPhase, otherPhase) && + !passThisBL16AndBW4->execute(thisPhase, otherPhase); + }); - dmap.emplace( - piecewise_construct, - forward_as_tuple("ACT"), - forward_as_tuple( - initializer_list{ - {tRC, "ACT", DependencyType::IntraBank, "tRC"}, - {tRRD_L_slr, "ACT", DependencyType::IntraBankGroup, "tRRD_L_slr"}, - {tRRD_S_slr, "ACT", DependencyType::IntraLogicalRank, "tRRD_S_slr"}, - {tRRD_dlr, "ACT", DependencyType::IntraPhysicalRank, "tRRD_dlr"}, - {tRDAACT, "RDA", DependencyType::IntraBank, "tRDAACT"}, - {tWRAACT, "WRA", DependencyType::IntraBank, "tWRAACT", passBurstLength16}, - {tWRAACT + tBURST16, "WRA", DependencyType::IntraBank, "tWRAACT + tBURST16", passBurstLength32}, - {tRP - cmdLengthDiff, "PREPB", DependencyType::IntraBank, "tRP - tCK"}, - {tRP - cmdLengthDiff, "PRESB", DependencyType::IntraBankInGroup, "tRP - tCK"}, - {tRP - cmdLengthDiff, "PREAB", DependencyType::IntraLogicalRank, "tRP - tCK"}, - {tRFC_slr - cmdLengthDiff, "REFAB", DependencyType::IntraLogicalRank, "tRFC_slr - tCK"}, - {tRFC_slr - cmdLengthDiff, "RFMAB", DependencyType::IntraLogicalRank, "tRFC_slr - tCK"}, - {tRFCsb_slr - cmdLengthDiff, "REFSB", DependencyType::IntraBankInGroup, "tRFCsb_slr - tCK"}, - {tREFSBRD_slr - cmdLengthDiff, "REFSB", DependencyType::IntraLogicalRank, "tREFSBRD_slr - tCK"}, - {tREFSBRD_dlr - cmdLengthDiff, "REFSB", DependencyType::IntraPhysicalRank, "tREFSBRD_dlr - tCK"}, - {tRFCsb_slr - cmdLengthDiff, "RFMSB", DependencyType::IntraBankInGroup, "tRFCsb_slr - tCK"}, - {tREFSBRD_slr - cmdLengthDiff, "RFMSB", DependencyType::IntraLogicalRank, "tREFSBRD_slr - tCK"}, - {tREFSBRD_dlr - cmdLengthDiff, "RFMSB", DependencyType::IntraPhysicalRank, "tREFSBRD_dlr - tCK"}, - {2 * tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"}, - {tFAW_slr - longCmdOffset, "FAW_LOGICAL", DependencyType::IntraLogicalRank, "tFAW_slr"}, - {tFAW_dlr - longCmdOffset, "FAW_PHYSICAL", DependencyType::IntraPhysicalRank, "tFAW_dlr"}, - } - ) - ); + dmap.emplace( + piecewise_construct, + forward_as_tuple("ACT"), + forward_as_tuple(initializer_list{ + {tRC, "ACT", DependencyType::IntraBank, "tRC"}, + {tRRD_L_slr, "ACT", DependencyType::IntraBankGroup, "tRRD_L_slr"}, + {tRRD_S_slr, "ACT", DependencyType::IntraLogicalRank, "tRRD_S_slr"}, + {tRRD_dlr, "ACT", DependencyType::IntraPhysicalRank, "tRRD_dlr"}, + {tRDAACT, "RDA", DependencyType::IntraBank, "tRDAACT"}, + {tWRAACT, "WRA", DependencyType::IntraBank, "tWRAACT", passBurstLength16}, + {tWRAACT + tBURST16, + "WRA", + DependencyType::IntraBank, + "tWRAACT + tBURST16", + passBurstLength32}, + {tRP - cmdLengthDiff, "PREPB", DependencyType::IntraBank, "tRP - tCK"}, + {tRP - cmdLengthDiff, "PRESB", DependencyType::IntraBankInGroup, "tRP - tCK"}, + {tRP - cmdLengthDiff, "PREAB", DependencyType::IntraLogicalRank, "tRP - tCK"}, + {tRFC_slr - cmdLengthDiff, "REFAB", DependencyType::IntraLogicalRank, "tRFC_slr - tCK"}, + {tRFC_slr - cmdLengthDiff, "RFMAB", DependencyType::IntraLogicalRank, "tRFC_slr - tCK"}, + {tRFCsb_slr - cmdLengthDiff, + "REFSB", + DependencyType::IntraBankInGroup, + "tRFCsb_slr - tCK"}, + {tREFSBRD_slr - cmdLengthDiff, + "REFSB", + DependencyType::IntraLogicalRank, + "tREFSBRD_slr - tCK"}, + {tREFSBRD_dlr - cmdLengthDiff, + "REFSB", + DependencyType::IntraPhysicalRank, + "tREFSBRD_dlr - tCK"}, + {tRFCsb_slr - cmdLengthDiff, + "RFMSB", + DependencyType::IntraBankInGroup, + "tRFCsb_slr - tCK"}, + {tREFSBRD_slr - cmdLengthDiff, + "RFMSB", + DependencyType::IntraLogicalRank, + "tREFSBRD_slr - tCK"}, + {tREFSBRD_dlr - cmdLengthDiff, + "RFMSB", + DependencyType::IntraPhysicalRank, + "tREFSBRD_dlr - tCK"}, + {2 * tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"}, + {tFAW_slr - longCmdOffset, "FAW_LOGICAL", DependencyType::IntraLogicalRank, "tFAW_slr"}, + {tFAW_dlr - longCmdOffset, + "FAW_PHYSICAL", + DependencyType::IntraPhysicalRank, + "tFAW_dlr"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("RD"), - forward_as_tuple( - initializer_list{ - {tRCD, "ACT", DependencyType::IntraBank, "tRCD"}, - {tCCD_L_slr, "RD", DependencyType::IntraBankGroup, "tCCD_L_slr"}, - {tCCD_S_slr, "RD", DependencyType::IntraLogicalRank, "tCCD_S_slr"}, - {tCCD_dlr, "RD", DependencyType::IntraPhysicalRank, "tCCD_dlr", passBurstLength16}, - {tBURST32, "RD", DependencyType::IntraPhysicalRank, "tBURST32", passBurstLength32}, - {tRDRD_dpr, "RD", DependencyType::IntraDIMMRank, "tRDRD_dpr", passBurstLength16}, - {tRDRD_dpr + tBURST16, "RD", DependencyType::IntraDIMMRank, "tRDRD_dpr + tBURST16", passBurstLength32}, - {tRDRD_ddr, "RD", DependencyType::InterDIMMRank, "tRDRD_ddr", passBurstLength16}, - {tRDRD_ddr + tBURST16, "RD", DependencyType::InterDIMMRank, "tRDRD_ddr + tBURST16", passBurstLength32}, - {tCCD_L_slr, "RDA", DependencyType::IntraBankGroup, "tCCD_L_slr"}, - {tCCD_S_slr, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_slr"}, - {tCCD_dlr, "RDA", DependencyType::IntraPhysicalRank, "tCCD_dlr", passBurstLength16}, - {tBURST32, "RDA", DependencyType::IntraPhysicalRank, "tBURST32", passBurstLength32}, - {tRDRD_dpr, "RDA", DependencyType::IntraDIMMRank, "tRDRD_dpr", passBurstLength16}, - {tRDRD_dpr + tBURST16, "RDA", DependencyType::IntraDIMMRank, "tRDRD_dpr + tBURST16", passBurstLength32}, - {tRDRD_ddr, "RDA", DependencyType::InterDIMMRank, "tRDRD_ddr", passBurstLength16}, - {tRDRD_ddr + tBURST16, "RDA", DependencyType::InterDIMMRank, "tRDRD_ddr + tBURST16", passBurstLength32}, - {tCCD_L_WTR_slr, "WR", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr", passBurstLength16}, - {tCCD_L_WTR_slr + tBURST16, "WR", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr + tBURST16", passBurstLength32}, - {tCCD_S_WTR_slr, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr", passBurstLength16}, - {tCCD_S_WTR_slr + tBURST16, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr + tBURST16", passBurstLength32}, - {tCCD_WTR_dlr, "WR", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr", passBurstLength16}, - {tCCD_WTR_dlr + tBURST16, "WR", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr + tBURST16", passBurstLength32}, - {tWRRD_dpr, "WR", DependencyType::IntraDIMMRank, "tWRRD_dpr", passBurstLength16}, - {tWRRD_dpr + tBURST16, "WR", DependencyType::IntraDIMMRank, "tWRRD_dpr + tBURST16", passBurstLength32}, - {tWRRD_ddr, "WR", DependencyType::InterDIMMRank, "tWRRD_ddr", passBurstLength16}, - {tWRRD_ddr + tBURST16, "WR", DependencyType::InterDIMMRank, "tWRRD_ddr + tBURST16", passBurstLength32}, - {tCCD_L_WTR_slr, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr", passBurstLength16}, - {tCCD_L_WTR_slr + tBURST16, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr + tBURST16", passBurstLength32}, - {tCCD_S_WTR_slr, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr", passBurstLength16}, - {tCCD_S_WTR_slr + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr + tBURST16", passBurstLength32}, - {tCCD_WTR_dlr, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr", passBurstLength16}, - {tCCD_WTR_dlr + tBURST16, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr + tBURST16", passBurstLength32}, - {tWRRD_dpr, "WRA", DependencyType::IntraDIMMRank, "tWRRD_dpr", passBurstLength16}, - {tWRRD_dpr + tBURST16, "WRA", DependencyType::IntraDIMMRank, "tWRRD_dpr + tBURST16", passBurstLength32}, - {tWRRD_ddr, "WRA", DependencyType::InterDIMMRank, "tWRRD_ddr", passBurstLength16}, - {tWRRD_ddr + tBURST16, "WRA", DependencyType::InterDIMMRank, "tWRRD_ddr + tBURST16", passBurstLength32}, - {2 * tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"}, - } - ) - ); + dmap.emplace( + piecewise_construct, + forward_as_tuple("RD"), + forward_as_tuple(initializer_list{ + {tRCD, "ACT", DependencyType::IntraBank, "tRCD"}, + {tCCD_L_slr, "RD", DependencyType::IntraBankGroup, "tCCD_L_slr"}, + {tCCD_S_slr, "RD", DependencyType::IntraLogicalRank, "tCCD_S_slr"}, + {tCCD_dlr, "RD", DependencyType::IntraPhysicalRank, "tCCD_dlr", passBurstLength16}, + {tBURST32, "RD", DependencyType::IntraPhysicalRank, "tBURST32", passBurstLength32}, + {tRDRD_dpr, "RD", DependencyType::IntraDIMMRank, "tRDRD_dpr", passBurstLength16}, + {tRDRD_dpr + tBURST16, + "RD", + DependencyType::IntraDIMMRank, + "tRDRD_dpr + tBURST16", + passBurstLength32}, + {tRDRD_ddr, "RD", DependencyType::InterDIMMRank, "tRDRD_ddr", passBurstLength16}, + {tRDRD_ddr + tBURST16, + "RD", + DependencyType::InterDIMMRank, + "tRDRD_ddr + tBURST16", + passBurstLength32}, + {tCCD_L_slr, "RDA", DependencyType::IntraBankGroup, "tCCD_L_slr"}, + {tCCD_S_slr, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_slr"}, + {tCCD_dlr, "RDA", DependencyType::IntraPhysicalRank, "tCCD_dlr", passBurstLength16}, + {tBURST32, "RDA", DependencyType::IntraPhysicalRank, "tBURST32", passBurstLength32}, + {tRDRD_dpr, "RDA", DependencyType::IntraDIMMRank, "tRDRD_dpr", passBurstLength16}, + {tRDRD_dpr + tBURST16, + "RDA", + DependencyType::IntraDIMMRank, + "tRDRD_dpr + tBURST16", + passBurstLength32}, + {tRDRD_ddr, "RDA", DependencyType::InterDIMMRank, "tRDRD_ddr", passBurstLength16}, + {tRDRD_ddr + tBURST16, + "RDA", + DependencyType::InterDIMMRank, + "tRDRD_ddr + tBURST16", + passBurstLength32}, + {tCCD_L_WTR_slr, + "WR", + DependencyType::IntraBankGroup, + "tCCD_L_WTR_slr", + passBurstLength16}, + {tCCD_L_WTR_slr + tBURST16, + "WR", + DependencyType::IntraBankGroup, + "tCCD_L_WTR_slr + tBURST16", + passBurstLength32}, + {tCCD_S_WTR_slr, + "WR", + DependencyType::IntraLogicalRank, + "tCCD_S_WTR_slr", + passBurstLength16}, + {tCCD_S_WTR_slr + tBURST16, + "WR", + DependencyType::IntraLogicalRank, + "tCCD_S_WTR_slr + tBURST16", + passBurstLength32}, + {tCCD_WTR_dlr, + "WR", + DependencyType::IntraPhysicalRank, + "tCCD_WTR_dlr", + passBurstLength16}, + {tCCD_WTR_dlr + tBURST16, + "WR", + DependencyType::IntraPhysicalRank, + "tCCD_WTR_dlr + tBURST16", + passBurstLength32}, + {tWRRD_dpr, "WR", DependencyType::IntraDIMMRank, "tWRRD_dpr", passBurstLength16}, + {tWRRD_dpr + tBURST16, + "WR", + DependencyType::IntraDIMMRank, + "tWRRD_dpr + tBURST16", + passBurstLength32}, + {tWRRD_ddr, "WR", DependencyType::InterDIMMRank, "tWRRD_ddr", passBurstLength16}, + {tWRRD_ddr + tBURST16, + "WR", + DependencyType::InterDIMMRank, + "tWRRD_ddr + tBURST16", + passBurstLength32}, + {tCCD_L_WTR_slr, + "WRA", + DependencyType::IntraBankGroup, + "tCCD_L_WTR_slr", + passBurstLength16}, + {tCCD_L_WTR_slr + tBURST16, + "WRA", + DependencyType::IntraBankGroup, + "tCCD_L_WTR_slr + tBURST16", + passBurstLength32}, + {tCCD_S_WTR_slr, + "WRA", + DependencyType::IntraLogicalRank, + "tCCD_S_WTR_slr", + passBurstLength16}, + {tCCD_S_WTR_slr + tBURST16, + "WRA", + DependencyType::IntraLogicalRank, + "tCCD_S_WTR_slr + tBURST16", + passBurstLength32}, + {tCCD_WTR_dlr, + "WRA", + DependencyType::IntraPhysicalRank, + "tCCD_WTR_dlr", + passBurstLength16}, + {tCCD_WTR_dlr + tBURST16, + "WRA", + DependencyType::IntraPhysicalRank, + "tCCD_WTR_dlr + tBURST16", + passBurstLength32}, + {tWRRD_dpr, "WRA", DependencyType::IntraDIMMRank, "tWRRD_dpr", passBurstLength16}, + {tWRRD_dpr + tBURST16, + "WRA", + DependencyType::IntraDIMMRank, + "tWRRD_dpr + tBURST16", + passBurstLength32}, + {tWRRD_ddr, "WRA", DependencyType::InterDIMMRank, "tWRRD_ddr", passBurstLength16}, + {tWRRD_ddr + tBURST16, + "WRA", + DependencyType::InterDIMMRank, + "tWRRD_ddr + tBURST16", + passBurstLength32}, + {2 * tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("WR"), - forward_as_tuple( - initializer_list{ - {tRCD, "ACT", DependencyType::IntraBank, "tRCD"}, - {tCCD_L_RTW_slr, "RD", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr", passBurstLength16}, - {tCCD_L_RTW_slr + tBURST16, "RD", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr + tBURST16", passBurstLength32}, - {tCCD_S_RTW_slr, "RD", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr", passBurstLength16}, - {tCCD_S_RTW_slr + tBURST16, "RD", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr + tBURST16", passBurstLength32}, - {tCCD_RTW_dlr, "RD", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr", passBurstLength16}, - {tCCD_RTW_dlr + tBURST16, "RD", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr + tBURST16", passBurstLength32}, - {tRDWR_dpr, "RD", DependencyType::IntraDIMMRank, "tRDWR_dpr", passBurstLength16}, - {tRDWR_dpr + tBURST16, "RD", DependencyType::IntraDIMMRank, "tRDWR_dpr + tBURST16", passBurstLength32}, - {tRDWR_ddr, "RD", DependencyType::InterDIMMRank, "tRDWR_ddr", passBurstLength16}, - {tRDWR_ddr + tBURST16, "RD", DependencyType::InterDIMMRank, "tRDWR_ddr + tBURST16", passBurstLength32}, - {tCCD_L_RTW_slr, "RDA", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr", passBurstLength16}, - {tCCD_L_RTW_slr + tBURST16, "RDA", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr + tBURST16", passBurstLength32}, - {tCCD_S_RTW_slr, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr", passBurstLength16}, - {tCCD_S_RTW_slr + tBURST16, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr + tBURST16", passBurstLength32}, - {tCCD_RTW_dlr, "RDA", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr", passBurstLength16}, - {tCCD_RTW_dlr + tBURST16, "RDA", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr + tBURST16", passBurstLength32}, - {tRDWR_dpr, "RDA", DependencyType::IntraDIMMRank, "tRDWR_dpr", passBurstLength16}, - {tRDWR_dpr + tBURST16, "RDA", DependencyType::IntraDIMMRank, "tRDWR_dpr + tBURST16", passBurstLength32}, - {tRDWR_ddr, "RDA", DependencyType::InterDIMMRank, "tRDWR_ddr", passBurstLength16}, - {tRDWR_ddr + tBURST16, "RDA", DependencyType::InterDIMMRank, "tRDWR_ddr + tBURST16", passBurstLength32}, - {tCCD_L_WR_slr, "WR", DependencyType::IntraBankGroup, "tCCD_L_WR_slr", passOtherBL16ThisBL16BW4}, - {tCCD_L_WR_slr + tBURST16, "WR", DependencyType::IntraBankGroup, "tCCD_L_WR_slr + tBURST16", passOtherBL32ThisBL16BW4}, - {tCCD_L_WR2_slr, "WR", DependencyType::IntraBankGroup, "tCCD_L_WR2_slr", passOtherBL16ThisNotBL16BW4}, - {tCCD_L_WR2_slr + tBURST16, "WR", DependencyType::IntraBankGroup, "tCCD_L_WR2_slr + tBURST16", passOtherBL32ThisNotBL16BW4}, - {tCCD_S_WR_slr, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WR_slr"}, - {tCCD_WR_dlr, "WR", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr", passBurstLength16}, - {tBURST32, "WR", DependencyType::IntraPhysicalRank, "tBURST32", passBurstLength32}, - {tWRWR_dpr, "WR", DependencyType::IntraDIMMRank, "tWRWR_dpr", passBurstLength16}, - {tWRWR_dpr + tBURST16, "WR", DependencyType::IntraDIMMRank, "tWRWR_dpr + tBURST16", passBurstLength32}, - {tWRWR_ddr, "WR", DependencyType::InterDIMMRank, "tWRWR_ddr", passBurstLength16}, - {tWRWR_ddr + tBURST16, "WR", DependencyType::InterDIMMRank, "tWRWR_ddr + tBURST16", passBurstLength32}, - {tCCD_L_WR_slr, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR_slr", passOtherBL16ThisBL16BW4}, - {tCCD_L_WR_slr + tBURST16, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR_slr + tBURST16", passOtherBL32ThisBL16BW4}, - {tCCD_L_WR2_slr, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR2_slr", passOtherBL16ThisNotBL16BW4}, - {tCCD_L_WR2_slr + tBURST16, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR2_slr + tBURST16", passOtherBL32ThisNotBL16BW4}, - {tCCD_S_WR_slr, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WR_slr"}, - {tCCD_WR_dlr, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr", passBurstLength16}, - {tBURST32, "WRA", DependencyType::IntraPhysicalRank, "tBURST32", passBurstLength32}, - {tWRWR_dpr, "WRA", DependencyType::IntraDIMMRank, "tWRWR_dpr", passBurstLength16}, - {tWRWR_dpr + tBURST16, "WRA", DependencyType::IntraDIMMRank, "tWRWR_dpr + tBURST16", passBurstLength32}, - {tWRWR_ddr, "WRA", DependencyType::InterDIMMRank, "tWRWR_ddr", passBurstLength16}, - {tWRWR_ddr + tBURST16, "WRA", DependencyType::InterDIMMRank, "tWRWR_ddr + tBURST16", passBurstLength32}, - {2 * tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"}, - } - ) - ); + dmap.emplace( + piecewise_construct, + forward_as_tuple("WR"), + forward_as_tuple(initializer_list{ + {tRCD, "ACT", DependencyType::IntraBank, "tRCD"}, + {tCCD_L_RTW_slr, + "RD", + DependencyType::IntraBankGroup, + "tCCD_L_RTW_slr", + passBurstLength16}, + {tCCD_L_RTW_slr + tBURST16, + "RD", + DependencyType::IntraBankGroup, + "tCCD_L_RTW_slr + tBURST16", + passBurstLength32}, + {tCCD_S_RTW_slr, + "RD", + DependencyType::IntraLogicalRank, + "tCCD_S_RTW_slr", + passBurstLength16}, + {tCCD_S_RTW_slr + tBURST16, + "RD", + DependencyType::IntraLogicalRank, + "tCCD_S_RTW_slr + tBURST16", + passBurstLength32}, + {tCCD_RTW_dlr, + "RD", + DependencyType::IntraPhysicalRank, + "tCCD_RTW_dlr", + passBurstLength16}, + {tCCD_RTW_dlr + tBURST16, + "RD", + DependencyType::IntraPhysicalRank, + "tCCD_RTW_dlr + tBURST16", + passBurstLength32}, + {tRDWR_dpr, "RD", DependencyType::IntraDIMMRank, "tRDWR_dpr", passBurstLength16}, + {tRDWR_dpr + tBURST16, + "RD", + DependencyType::IntraDIMMRank, + "tRDWR_dpr + tBURST16", + passBurstLength32}, + {tRDWR_ddr, "RD", DependencyType::InterDIMMRank, "tRDWR_ddr", passBurstLength16}, + {tRDWR_ddr + tBURST16, + "RD", + DependencyType::InterDIMMRank, + "tRDWR_ddr + tBURST16", + passBurstLength32}, + {tCCD_L_RTW_slr, + "RDA", + DependencyType::IntraBankGroup, + "tCCD_L_RTW_slr", + passBurstLength16}, + {tCCD_L_RTW_slr + tBURST16, + "RDA", + DependencyType::IntraBankGroup, + "tCCD_L_RTW_slr + tBURST16", + passBurstLength32}, + {tCCD_S_RTW_slr, + "RDA", + DependencyType::IntraLogicalRank, + "tCCD_S_RTW_slr", + passBurstLength16}, + {tCCD_S_RTW_slr + tBURST16, + "RDA", + DependencyType::IntraLogicalRank, + "tCCD_S_RTW_slr + tBURST16", + passBurstLength32}, + {tCCD_RTW_dlr, + "RDA", + DependencyType::IntraPhysicalRank, + "tCCD_RTW_dlr", + passBurstLength16}, + {tCCD_RTW_dlr + tBURST16, + "RDA", + DependencyType::IntraPhysicalRank, + "tCCD_RTW_dlr + tBURST16", + passBurstLength32}, + {tRDWR_dpr, "RDA", DependencyType::IntraDIMMRank, "tRDWR_dpr", passBurstLength16}, + {tRDWR_dpr + tBURST16, + "RDA", + DependencyType::IntraDIMMRank, + "tRDWR_dpr + tBURST16", + passBurstLength32}, + {tRDWR_ddr, "RDA", DependencyType::InterDIMMRank, "tRDWR_ddr", passBurstLength16}, + {tRDWR_ddr + tBURST16, + "RDA", + DependencyType::InterDIMMRank, + "tRDWR_ddr + tBURST16", + passBurstLength32}, + {tCCD_L_WR_slr, + "WR", + DependencyType::IntraBankGroup, + "tCCD_L_WR_slr", + passOtherBL16ThisBL16BW4}, + {tCCD_L_WR_slr + tBURST16, + "WR", + DependencyType::IntraBankGroup, + "tCCD_L_WR_slr + tBURST16", + passOtherBL32ThisBL16BW4}, + {tCCD_L_WR2_slr, + "WR", + DependencyType::IntraBankGroup, + "tCCD_L_WR2_slr", + passOtherBL16ThisNotBL16BW4}, + {tCCD_L_WR2_slr + tBURST16, + "WR", + DependencyType::IntraBankGroup, + "tCCD_L_WR2_slr + tBURST16", + passOtherBL32ThisNotBL16BW4}, + {tCCD_S_WR_slr, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WR_slr"}, + {tCCD_WR_dlr, + "WR", + DependencyType::IntraPhysicalRank, + "tCCD_WR_dlr", + passBurstLength16}, + {tBURST32, "WR", DependencyType::IntraPhysicalRank, "tBURST32", passBurstLength32}, + {tWRWR_dpr, "WR", DependencyType::IntraDIMMRank, "tWRWR_dpr", passBurstLength16}, + {tWRWR_dpr + tBURST16, + "WR", + DependencyType::IntraDIMMRank, + "tWRWR_dpr + tBURST16", + passBurstLength32}, + {tWRWR_ddr, "WR", DependencyType::InterDIMMRank, "tWRWR_ddr", passBurstLength16}, + {tWRWR_ddr + tBURST16, + "WR", + DependencyType::InterDIMMRank, + "tWRWR_ddr + tBURST16", + passBurstLength32}, + {tCCD_L_WR_slr, + "WRA", + DependencyType::IntraBankGroup, + "tCCD_L_WR_slr", + passOtherBL16ThisBL16BW4}, + {tCCD_L_WR_slr + tBURST16, + "WRA", + DependencyType::IntraBankGroup, + "tCCD_L_WR_slr + tBURST16", + passOtherBL32ThisBL16BW4}, + {tCCD_L_WR2_slr, + "WRA", + DependencyType::IntraBankGroup, + "tCCD_L_WR2_slr", + passOtherBL16ThisNotBL16BW4}, + {tCCD_L_WR2_slr + tBURST16, + "WRA", + DependencyType::IntraBankGroup, + "tCCD_L_WR2_slr + tBURST16", + passOtherBL32ThisNotBL16BW4}, + {tCCD_S_WR_slr, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WR_slr"}, + {tCCD_WR_dlr, + "WRA", + DependencyType::IntraPhysicalRank, + "tCCD_WR_dlr", + passBurstLength16}, + {tBURST32, "WRA", DependencyType::IntraPhysicalRank, "tBURST32", passBurstLength32}, + {tWRWR_dpr, "WRA", DependencyType::IntraDIMMRank, "tWRWR_dpr", passBurstLength16}, + {tWRWR_dpr + tBURST16, + "WRA", + DependencyType::IntraDIMMRank, + "tWRWR_dpr + tBURST16", + passBurstLength32}, + {tWRWR_ddr, "WRA", DependencyType::InterDIMMRank, "tWRWR_ddr", passBurstLength16}, + {tWRWR_ddr + tBURST16, + "WRA", + DependencyType::InterDIMMRank, + "tWRWR_ddr + tBURST16", + passBurstLength32}, + {2 * tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("PREPB"), - forward_as_tuple( - initializer_list{ - {tRAS + cmdLengthDiff, "ACT", DependencyType::IntraBank, "tRAS + tCK"}, - {tRTP + cmdLengthDiff, "RD", DependencyType::IntraBank, "tRTP + tCK"}, - {tWRPRE + cmdLengthDiff, "WR", DependencyType::IntraBank, "tWRPRE + tCK", passBurstLength16}, - {tWRPRE + cmdLengthDiff + tBURST16, "WR", DependencyType::IntraBank, "tWRPRE + tCK + tBURST16", passBurstLength32}, - {tPPD, "PREPB", DependencyType::IntraPhysicalRank, "tPPD"}, - {tPPD, "PREAB", DependencyType::IntraPhysicalRank, "tPPD"}, - {tPPD, "PRESB", DependencyType::IntraPhysicalRank, "tPPD"}, - {tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("PREPB"), + forward_as_tuple(initializer_list{ + {tRAS + cmdLengthDiff, "ACT", DependencyType::IntraBank, "tRAS + tCK"}, + {tRTP + cmdLengthDiff, "RD", DependencyType::IntraBank, "tRTP + tCK"}, + {tWRPRE + cmdLengthDiff, + "WR", + DependencyType::IntraBank, + "tWRPRE + tCK", + passBurstLength16}, + {tWRPRE + cmdLengthDiff + tBURST16, + "WR", + DependencyType::IntraBank, + "tWRPRE + tCK + tBURST16", + passBurstLength32}, + {tPPD, "PREPB", DependencyType::IntraPhysicalRank, "tPPD"}, + {tPPD, "PREAB", DependencyType::IntraPhysicalRank, "tPPD"}, + {tPPD, "PRESB", DependencyType::IntraPhysicalRank, "tPPD"}, + {tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("RDA"), - forward_as_tuple( - initializer_list{ - {tRCD, "ACT", DependencyType::IntraBank, "tRCD"}, - {tCCD_L_slr, "RD", DependencyType::IntraBankGroup, "tCCD_L_slr"}, - {tCCD_S_slr, "RD", DependencyType::IntraLogicalRank, "tCCD_S_slr"}, - {tCCD_dlr, "RD", DependencyType::IntraPhysicalRank, "tCCD_dlr", passBurstLength16}, - {tBURST32, "RD", DependencyType::IntraPhysicalRank, "tBURST32", passBurstLength32}, - {tRDRD_dpr, "RD", DependencyType::IntraDIMMRank, "tRDRD_dpr", passBurstLength16}, - {tRDRD_dpr + tBURST16, "RD", DependencyType::IntraDIMMRank, "tRDRD_dpr + tBURST16", passBurstLength32}, - {tRDRD_ddr, "RD", DependencyType::InterDIMMRank, "tRDRD_ddr", passBurstLength16}, - {tRDRD_ddr + tBURST16, "RD", DependencyType::InterDIMMRank, "tRDRD_ddr + tBURST16", passBurstLength32}, - {tCCD_L_slr, "RDA", DependencyType::IntraBankGroup, "tCCD_L_slr"}, - {tCCD_S_slr, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_slr"}, - {tCCD_dlr, "RDA", DependencyType::IntraPhysicalRank, "tCCD_dlr", passBurstLength16}, - {tBURST32, "RDA", DependencyType::IntraPhysicalRank, "tBURST32", passBurstLength32}, - {tRDRD_dpr, "RDA", DependencyType::IntraDIMMRank, "tRDRD_dpr", passBurstLength16}, - {tRDRD_dpr + tBURST16, "RDA", DependencyType::IntraDIMMRank, "tRDRD_dpr + tBURST16", passBurstLength32}, - {tRDRD_ddr, "RDA", DependencyType::InterDIMMRank, "tRDRD_ddr", passBurstLength16}, - {tRDRD_ddr + tBURST16, "RDA", DependencyType::InterDIMMRank, "tRDRD_ddr + tBURST16", passBurstLength32}, - {tWRRDA, "WR", DependencyType::IntraBank, "tWRRDA", passBurstLength16}, - {tWRRDA + tBURST16, "WR", DependencyType::IntraBank, "tWRRDA + tBURST16", passBurstLength32}, - {tCCD_L_WTR_slr, "WR", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr", passBurstLength16}, - {tCCD_L_WTR_slr + tBURST16, "WR", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr + tBURST16", passBurstLength32}, - {tCCD_S_WTR_slr, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr", passBurstLength16}, - {tCCD_S_WTR_slr + tBURST16, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr + tBURST16", passBurstLength32}, - {tCCD_WTR_dlr, "WR", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr", passBurstLength16}, - {tCCD_WTR_dlr + tBURST16, "WR", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr + tBURST16", passBurstLength32}, - {tWRRD_dpr, "WR", DependencyType::IntraDIMMRank, "tWRRD_dpr", passBurstLength16}, - {tWRRD_dpr + tBURST16, "WR", DependencyType::IntraDIMMRank, "tWRRD_dpr + tBURST16", passBurstLength32}, - {tWRRD_ddr, "WR", DependencyType::InterDIMMRank, "tWRRD_ddr", passBurstLength16}, - {tWRRD_ddr + tBURST16, "WR", DependencyType::InterDIMMRank, "tWRRD_ddr + tBURST16", passBurstLength32}, - {tCCD_L_WTR_slr, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr", passBurstLength16}, - {tCCD_L_WTR_slr + tBURST16, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr + tBURST16", passBurstLength32}, - {tCCD_S_WTR_slr, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr", passBurstLength16}, - {tCCD_S_WTR_slr + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr + tBURST16", passBurstLength32}, - {tCCD_WTR_dlr, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr", passBurstLength16}, - {tCCD_WTR_dlr + tBURST16, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr + tBURST16", passBurstLength32}, - {tWRRD_dpr, "WRA", DependencyType::IntraDIMMRank, "tWRRD_dpr", passBurstLength16}, - {tWRRD_dpr + tBURST16, "WRA", DependencyType::IntraDIMMRank, "tWRRD_dpr + tBURST16", passBurstLength32}, - {tWRRD_ddr, "WRA", DependencyType::InterDIMMRank, "tWRRD_ddr", passBurstLength16}, - {tWRRD_ddr + tBURST16, "WRA", DependencyType::InterDIMMRank, "tWRRD_ddr + tBURST16", passBurstLength32}, - {2 * tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"}, - } - ) - ); + dmap.emplace( + piecewise_construct, + forward_as_tuple("RDA"), + forward_as_tuple(initializer_list{ + {tRCD, "ACT", DependencyType::IntraBank, "tRCD"}, + {tCCD_L_slr, "RD", DependencyType::IntraBankGroup, "tCCD_L_slr"}, + {tCCD_S_slr, "RD", DependencyType::IntraLogicalRank, "tCCD_S_slr"}, + {tCCD_dlr, "RD", DependencyType::IntraPhysicalRank, "tCCD_dlr", passBurstLength16}, + {tBURST32, "RD", DependencyType::IntraPhysicalRank, "tBURST32", passBurstLength32}, + {tRDRD_dpr, "RD", DependencyType::IntraDIMMRank, "tRDRD_dpr", passBurstLength16}, + {tRDRD_dpr + tBURST16, + "RD", + DependencyType::IntraDIMMRank, + "tRDRD_dpr + tBURST16", + passBurstLength32}, + {tRDRD_ddr, "RD", DependencyType::InterDIMMRank, "tRDRD_ddr", passBurstLength16}, + {tRDRD_ddr + tBURST16, + "RD", + DependencyType::InterDIMMRank, + "tRDRD_ddr + tBURST16", + passBurstLength32}, + {tCCD_L_slr, "RDA", DependencyType::IntraBankGroup, "tCCD_L_slr"}, + {tCCD_S_slr, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_slr"}, + {tCCD_dlr, "RDA", DependencyType::IntraPhysicalRank, "tCCD_dlr", passBurstLength16}, + {tBURST32, "RDA", DependencyType::IntraPhysicalRank, "tBURST32", passBurstLength32}, + {tRDRD_dpr, "RDA", DependencyType::IntraDIMMRank, "tRDRD_dpr", passBurstLength16}, + {tRDRD_dpr + tBURST16, + "RDA", + DependencyType::IntraDIMMRank, + "tRDRD_dpr + tBURST16", + passBurstLength32}, + {tRDRD_ddr, "RDA", DependencyType::InterDIMMRank, "tRDRD_ddr", passBurstLength16}, + {tRDRD_ddr + tBURST16, + "RDA", + DependencyType::InterDIMMRank, + "tRDRD_ddr + tBURST16", + passBurstLength32}, + {tWRRDA, "WR", DependencyType::IntraBank, "tWRRDA", passBurstLength16}, + {tWRRDA + tBURST16, + "WR", + DependencyType::IntraBank, + "tWRRDA + tBURST16", + passBurstLength32}, + {tCCD_L_WTR_slr, + "WR", + DependencyType::IntraBankGroup, + "tCCD_L_WTR_slr", + passBurstLength16}, + {tCCD_L_WTR_slr + tBURST16, + "WR", + DependencyType::IntraBankGroup, + "tCCD_L_WTR_slr + tBURST16", + passBurstLength32}, + {tCCD_S_WTR_slr, + "WR", + DependencyType::IntraLogicalRank, + "tCCD_S_WTR_slr", + passBurstLength16}, + {tCCD_S_WTR_slr + tBURST16, + "WR", + DependencyType::IntraLogicalRank, + "tCCD_S_WTR_slr + tBURST16", + passBurstLength32}, + {tCCD_WTR_dlr, + "WR", + DependencyType::IntraPhysicalRank, + "tCCD_WTR_dlr", + passBurstLength16}, + {tCCD_WTR_dlr + tBURST16, + "WR", + DependencyType::IntraPhysicalRank, + "tCCD_WTR_dlr + tBURST16", + passBurstLength32}, + {tWRRD_dpr, "WR", DependencyType::IntraDIMMRank, "tWRRD_dpr", passBurstLength16}, + {tWRRD_dpr + tBURST16, + "WR", + DependencyType::IntraDIMMRank, + "tWRRD_dpr + tBURST16", + passBurstLength32}, + {tWRRD_ddr, "WR", DependencyType::InterDIMMRank, "tWRRD_ddr", passBurstLength16}, + {tWRRD_ddr + tBURST16, + "WR", + DependencyType::InterDIMMRank, + "tWRRD_ddr + tBURST16", + passBurstLength32}, + {tCCD_L_WTR_slr, + "WRA", + DependencyType::IntraBankGroup, + "tCCD_L_WTR_slr", + passBurstLength16}, + {tCCD_L_WTR_slr + tBURST16, + "WRA", + DependencyType::IntraBankGroup, + "tCCD_L_WTR_slr + tBURST16", + passBurstLength32}, + {tCCD_S_WTR_slr, + "WRA", + DependencyType::IntraLogicalRank, + "tCCD_S_WTR_slr", + passBurstLength16}, + {tCCD_S_WTR_slr + tBURST16, + "WRA", + DependencyType::IntraLogicalRank, + "tCCD_S_WTR_slr + tBURST16", + passBurstLength32}, + {tCCD_WTR_dlr, + "WRA", + DependencyType::IntraPhysicalRank, + "tCCD_WTR_dlr", + passBurstLength16}, + {tCCD_WTR_dlr + tBURST16, + "WRA", + DependencyType::IntraPhysicalRank, + "tCCD_WTR_dlr + tBURST16", + passBurstLength32}, + {tWRRD_dpr, "WRA", DependencyType::IntraDIMMRank, "tWRRD_dpr", passBurstLength16}, + {tWRRD_dpr + tBURST16, + "WRA", + DependencyType::IntraDIMMRank, + "tWRRD_dpr + tBURST16", + passBurstLength32}, + {tWRRD_ddr, "WRA", DependencyType::InterDIMMRank, "tWRRD_ddr", passBurstLength16}, + {tWRRD_ddr + tBURST16, + "WRA", + DependencyType::InterDIMMRank, + "tWRRD_ddr + tBURST16", + passBurstLength32}, + {2 * tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("WRA"), - forward_as_tuple( - initializer_list{ - {tRCD, "ACT", DependencyType::IntraBank, "tRCD"}, - {tCCD_L_RTW_slr, "RD", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr", passBurstLength16}, - {tCCD_L_RTW_slr + tBURST16, "RD", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr + tBURST16", passBurstLength32}, - {tCCD_S_RTW_slr, "RD", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr", passBurstLength16}, - {tCCD_S_RTW_slr + tBURST16, "RD", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr + tBURST16", passBurstLength32}, - {tCCD_RTW_dlr, "RD", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr", passBurstLength16}, - {tCCD_RTW_dlr + tBURST16, "RD", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr + tBURST16", passBurstLength32}, - {tRDWR_dpr, "RD", DependencyType::IntraDIMMRank, "tRDWR_dpr", passBurstLength16}, - {tRDWR_dpr + tBURST16, "RD", DependencyType::IntraDIMMRank, "tRDWR_dpr + tBURST16", passBurstLength32}, - {tRDWR_ddr, "RD", DependencyType::InterDIMMRank, "tRDWR_ddr", passBurstLength16}, - {tRDWR_ddr + tBURST16, "RD", DependencyType::InterDIMMRank, "tRDWR_ddr + tBURST16", passBurstLength32}, - {tCCD_L_RTW_slr, "RDA", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr", passBurstLength16}, - {tCCD_L_RTW_slr + tBURST16, "RDA", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr + tBURST16", passBurstLength32}, - {tCCD_S_RTW_slr, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr", passBurstLength16}, - {tCCD_S_RTW_slr + tBURST16, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr + tBURST16", passBurstLength32}, - {tCCD_RTW_dlr, "RDA", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr", passBurstLength16}, - {tCCD_RTW_dlr + tBURST16, "RDA", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr + tBURST16", passBurstLength32}, - {tRDWR_dpr, "RDA", DependencyType::IntraDIMMRank, "tRDWR_dpr", passBurstLength16}, - {tRDWR_dpr + tBURST16, "RDA", DependencyType::IntraDIMMRank, "tRDWR_dpr + tBURST16", passBurstLength32}, - {tRDWR_ddr, "RDA", DependencyType::InterDIMMRank, "tRDWR_ddr", passBurstLength16}, - {tRDWR_ddr + tBURST16, "RDA", DependencyType::InterDIMMRank, "tRDWR_ddr + tBURST16", passBurstLength32}, - {tCCD_L_WR_slr, "WR", DependencyType::IntraBankGroup, "tCCD_L_WR_slr"}, - {tCCD_S_WR_slr, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WR_slr"}, - {tCCD_WR_dlr, "WR", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr", passBurstLength16}, - {tBURST32, "WR", DependencyType::IntraPhysicalRank, "tBURST32", passBurstLength32}, - {tWRWR_dpr, "WR", DependencyType::IntraDIMMRank, "tWRWR_dpr", passBurstLength16}, - {tWRWR_dpr + tBURST16, "WR", DependencyType::IntraDIMMRank, "tWRWR_dpr + tBURST16", passBurstLength32}, - {tWRWR_ddr, "WR", DependencyType::InterDIMMRank, "tWRWR_ddr", passBurstLength16}, - {tWRWR_ddr + tBURST16, "WR", DependencyType::InterDIMMRank, "tWRWR_ddr + tBURST16", passBurstLength32}, - {tCCD_L_WR_slr, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR_slr", passBurstLength16}, - {tCCD_L_WR_slr + tBURST16, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR_slr + tBURST16", passBurstLength32}, - {tCCD_S_WR_slr, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WR_slr"}, - {tCCD_WR_dlr, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr", passBurstLength16}, - {tBURST32, "WRA", DependencyType::IntraPhysicalRank, "tBURST32", passBurstLength32}, - {tWRWR_dpr, "WRA", DependencyType::IntraDIMMRank, "tWRWR_dpr", passBurstLength16}, - {tWRWR_dpr + tBURST16, "WRA", DependencyType::IntraDIMMRank, "tWRWR_dpr + tBURST16", passBurstLength32}, - {tWRWR_ddr, "WRA", DependencyType::InterDIMMRank, "tWRWR_ddr", passBurstLength16}, - {tWRWR_ddr + tBURST16, "WRA", DependencyType::InterDIMMRank, "tWRWR_ddr + tBURST16", passBurstLength32}, - {2 * tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"}, - } - ) - ); + dmap.emplace( + piecewise_construct, + forward_as_tuple("WRA"), + forward_as_tuple(initializer_list{ + {tRCD, "ACT", DependencyType::IntraBank, "tRCD"}, + {tCCD_L_RTW_slr, + "RD", + DependencyType::IntraBankGroup, + "tCCD_L_RTW_slr", + passBurstLength16}, + {tCCD_L_RTW_slr + tBURST16, + "RD", + DependencyType::IntraBankGroup, + "tCCD_L_RTW_slr + tBURST16", + passBurstLength32}, + {tCCD_S_RTW_slr, + "RD", + DependencyType::IntraLogicalRank, + "tCCD_S_RTW_slr", + passBurstLength16}, + {tCCD_S_RTW_slr + tBURST16, + "RD", + DependencyType::IntraLogicalRank, + "tCCD_S_RTW_slr + tBURST16", + passBurstLength32}, + {tCCD_RTW_dlr, + "RD", + DependencyType::IntraPhysicalRank, + "tCCD_RTW_dlr", + passBurstLength16}, + {tCCD_RTW_dlr + tBURST16, + "RD", + DependencyType::IntraPhysicalRank, + "tCCD_RTW_dlr + tBURST16", + passBurstLength32}, + {tRDWR_dpr, "RD", DependencyType::IntraDIMMRank, "tRDWR_dpr", passBurstLength16}, + {tRDWR_dpr + tBURST16, + "RD", + DependencyType::IntraDIMMRank, + "tRDWR_dpr + tBURST16", + passBurstLength32}, + {tRDWR_ddr, "RD", DependencyType::InterDIMMRank, "tRDWR_ddr", passBurstLength16}, + {tRDWR_ddr + tBURST16, + "RD", + DependencyType::InterDIMMRank, + "tRDWR_ddr + tBURST16", + passBurstLength32}, + {tCCD_L_RTW_slr, + "RDA", + DependencyType::IntraBankGroup, + "tCCD_L_RTW_slr", + passBurstLength16}, + {tCCD_L_RTW_slr + tBURST16, + "RDA", + DependencyType::IntraBankGroup, + "tCCD_L_RTW_slr + tBURST16", + passBurstLength32}, + {tCCD_S_RTW_slr, + "RDA", + DependencyType::IntraLogicalRank, + "tCCD_S_RTW_slr", + passBurstLength16}, + {tCCD_S_RTW_slr + tBURST16, + "RDA", + DependencyType::IntraLogicalRank, + "tCCD_S_RTW_slr + tBURST16", + passBurstLength32}, + {tCCD_RTW_dlr, + "RDA", + DependencyType::IntraPhysicalRank, + "tCCD_RTW_dlr", + passBurstLength16}, + {tCCD_RTW_dlr + tBURST16, + "RDA", + DependencyType::IntraPhysicalRank, + "tCCD_RTW_dlr + tBURST16", + passBurstLength32}, + {tRDWR_dpr, "RDA", DependencyType::IntraDIMMRank, "tRDWR_dpr", passBurstLength16}, + {tRDWR_dpr + tBURST16, + "RDA", + DependencyType::IntraDIMMRank, + "tRDWR_dpr + tBURST16", + passBurstLength32}, + {tRDWR_ddr, "RDA", DependencyType::InterDIMMRank, "tRDWR_ddr", passBurstLength16}, + {tRDWR_ddr + tBURST16, + "RDA", + DependencyType::InterDIMMRank, + "tRDWR_ddr + tBURST16", + passBurstLength32}, + {tCCD_L_WR_slr, "WR", DependencyType::IntraBankGroup, "tCCD_L_WR_slr"}, + {tCCD_S_WR_slr, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WR_slr"}, + {tCCD_WR_dlr, + "WR", + DependencyType::IntraPhysicalRank, + "tCCD_WR_dlr", + passBurstLength16}, + {tBURST32, "WR", DependencyType::IntraPhysicalRank, "tBURST32", passBurstLength32}, + {tWRWR_dpr, "WR", DependencyType::IntraDIMMRank, "tWRWR_dpr", passBurstLength16}, + {tWRWR_dpr + tBURST16, + "WR", + DependencyType::IntraDIMMRank, + "tWRWR_dpr + tBURST16", + passBurstLength32}, + {tWRWR_ddr, "WR", DependencyType::InterDIMMRank, "tWRWR_ddr", passBurstLength16}, + {tWRWR_ddr + tBURST16, + "WR", + DependencyType::InterDIMMRank, + "tWRWR_ddr + tBURST16", + passBurstLength32}, + {tCCD_L_WR_slr, + "WRA", + DependencyType::IntraBankGroup, + "tCCD_L_WR_slr", + passBurstLength16}, + {tCCD_L_WR_slr + tBURST16, + "WRA", + DependencyType::IntraBankGroup, + "tCCD_L_WR_slr + tBURST16", + passBurstLength32}, + {tCCD_S_WR_slr, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WR_slr"}, + {tCCD_WR_dlr, + "WRA", + DependencyType::IntraPhysicalRank, + "tCCD_WR_dlr", + passBurstLength16}, + {tBURST32, "WRA", DependencyType::IntraPhysicalRank, "tBURST32", passBurstLength32}, + {tWRWR_dpr, "WRA", DependencyType::IntraDIMMRank, "tWRWR_dpr", passBurstLength16}, + {tWRWR_dpr + tBURST16, + "WRA", + DependencyType::IntraDIMMRank, + "tWRWR_dpr + tBURST16", + passBurstLength32}, + {tWRWR_ddr, "WRA", DependencyType::InterDIMMRank, "tWRWR_ddr", passBurstLength16}, + {tWRWR_ddr + tBURST16, + "WRA", + DependencyType::InterDIMMRank, + "tWRWR_ddr + tBURST16", + passBurstLength32}, + {2 * tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("REFAB"), - forward_as_tuple( - initializer_list{ - {tRC + cmdLengthDiff, "ACT", DependencyType::IntraLogicalRank, "tRC + tCK"}, - {tRDAACT + cmdLengthDiff, "RDA", DependencyType::IntraPhysicalRank, "tRDAACT + tCK"}, - {tWRPRE + tRP + cmdLengthDiff, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tRP + tCK", passBurstLength16}, - {tWRPRE + tRP + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tRP + tCK + tBURST16", passBurstLength32}, - {tRP, "PREPB", DependencyType::IntraLogicalRank, "tRP"}, - {tRP, "PREAB", DependencyType::IntraLogicalRank, "tRP"}, - {tRFC_slr, "REFAB", DependencyType::IntraLogicalRank, "tRFC_slr"}, - {tRFC_dlr, "REFAB", DependencyType::IntraPhysicalRank, "tRFC_dlr"}, - {tRFC_dpr, "REFAB", DependencyType::IntraDIMMRank, "tRFC_dpr"}, - {tRFC_slr, "RFMAB", DependencyType::IntraLogicalRank, "tRFC_slr"}, - {tRFC_dlr, "RFMAB", DependencyType::IntraPhysicalRank, "tRFC_dlr"}, - {tRFC_dpr, "RFMAB", DependencyType::IntraDIMMRank, "tRFC_dpr"}, - {tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"}, - } - ) - ); + dmap.emplace( + piecewise_construct, + forward_as_tuple("REFAB"), + forward_as_tuple(initializer_list{ + {tRC + cmdLengthDiff, "ACT", DependencyType::IntraLogicalRank, "tRC + tCK"}, + {tRDAACT + cmdLengthDiff, "RDA", DependencyType::IntraPhysicalRank, "tRDAACT + tCK"}, + {tWRPRE + tRP + cmdLengthDiff, + "WRA", + DependencyType::IntraLogicalRank, + "tWRPRE + tRP + tCK", + passBurstLength16}, + {tWRPRE + tRP + cmdLengthDiff + tBURST16, + "WRA", + DependencyType::IntraLogicalRank, + "tWRPRE + tRP + tCK + tBURST16", + passBurstLength32}, + {tRP, "PREPB", DependencyType::IntraLogicalRank, "tRP"}, + {tRP, "PREAB", DependencyType::IntraLogicalRank, "tRP"}, + {tRFC_slr, "REFAB", DependencyType::IntraLogicalRank, "tRFC_slr"}, + {tRFC_dlr, "REFAB", DependencyType::IntraPhysicalRank, "tRFC_dlr"}, + {tRFC_dpr, "REFAB", DependencyType::IntraDIMMRank, "tRFC_dpr"}, + {tRFC_slr, "RFMAB", DependencyType::IntraLogicalRank, "tRFC_slr"}, + {tRFC_dlr, "RFMAB", DependencyType::IntraPhysicalRank, "tRFC_dlr"}, + {tRFC_dpr, "RFMAB", DependencyType::IntraDIMMRank, "tRFC_dpr"}, + {tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("RFMAB"), - forward_as_tuple( - initializer_list{ - {tRC + cmdLengthDiff, "ACT", DependencyType::IntraLogicalRank, "tRC + tCK"}, - {tRDAACT + cmdLengthDiff, "RDA", DependencyType::IntraPhysicalRank, "tRDAACT + tCK"}, - {tWRPRE + tRP + cmdLengthDiff, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tRP + tCK", passBurstLength16}, - {tWRPRE + tRP + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tRP + tCK + tBURST16", passBurstLength32}, - {tRP, "PREPB", DependencyType::IntraLogicalRank, "tRP"}, - {tRP, "PREAB", DependencyType::IntraLogicalRank, "tRP"}, - {tRFC_slr, "REFAB", DependencyType::IntraLogicalRank, "tRFC_slr"}, - {tRFC_dlr, "REFAB", DependencyType::IntraPhysicalRank, "tRFC_dlr"}, - {tRFC_dpr, "REFAB", DependencyType::IntraDIMMRank, "tRFC_dpr"}, - {tRFC_slr, "RFMAB", DependencyType::IntraLogicalRank, "tRFC_slr"}, - {tRFC_dlr, "RFMAB", DependencyType::IntraPhysicalRank, "tRFC_dlr"}, - {tRFC_dpr, "RFMAB", DependencyType::IntraDIMMRank, "tRFC_dpr"}, - {tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"}, - } - ) - ); + dmap.emplace( + piecewise_construct, + forward_as_tuple("RFMAB"), + forward_as_tuple(initializer_list{ + {tRC + cmdLengthDiff, "ACT", DependencyType::IntraLogicalRank, "tRC + tCK"}, + {tRDAACT + cmdLengthDiff, "RDA", DependencyType::IntraPhysicalRank, "tRDAACT + tCK"}, + {tWRPRE + tRP + cmdLengthDiff, + "WRA", + DependencyType::IntraLogicalRank, + "tWRPRE + tRP + tCK", + passBurstLength16}, + {tWRPRE + tRP + cmdLengthDiff + tBURST16, + "WRA", + DependencyType::IntraLogicalRank, + "tWRPRE + tRP + tCK + tBURST16", + passBurstLength32}, + {tRP, "PREPB", DependencyType::IntraLogicalRank, "tRP"}, + {tRP, "PREAB", DependencyType::IntraLogicalRank, "tRP"}, + {tRFC_slr, "REFAB", DependencyType::IntraLogicalRank, "tRFC_slr"}, + {tRFC_dlr, "REFAB", DependencyType::IntraPhysicalRank, "tRFC_dlr"}, + {tRFC_dpr, "REFAB", DependencyType::IntraDIMMRank, "tRFC_dpr"}, + {tRFC_slr, "RFMAB", DependencyType::IntraLogicalRank, "tRFC_slr"}, + {tRFC_dlr, "RFMAB", DependencyType::IntraPhysicalRank, "tRFC_dlr"}, + {tRFC_dpr, "RFMAB", DependencyType::IntraDIMMRank, "tRFC_dpr"}, + {tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("REFSB"), - forward_as_tuple( - initializer_list{ - {tRC + cmdLengthDiff, "ACT", DependencyType::IntraBankInGroup, "tRC + tCK"}, - {tRRD_L_slr + cmdLengthDiff, "ACT", DependencyType::IntraLogicalRank, "tRRD_L_slr + tCK"}, - {tRDAACT + cmdLengthDiff, "RDA", DependencyType::IntraBankInGroup, "tRDAACT + tCK"}, - {tWRAACT + tRP + cmdLengthDiff, "WRA", DependencyType::IntraBankInGroup, "tWRAACT + tRP + tCK", passBurstLength16}, - {tWRAACT + tRP + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraBankInGroup, "tWRAACT + tRP + tCK + tBURST16", passBurstLength32}, - {tRP, "PREPB", DependencyType::IntraBankInGroup, "tRP"}, - {tRP, "PRESB", DependencyType::IntraBankInGroup, "tRP"}, - {tRFC_slr, "REFAB", DependencyType::IntraLogicalRank, "tRFC_slr"}, - {tRFC_dlr, "REFAB", DependencyType::IntraPhysicalRank, "tRFC_dlr"}, - {tRFC_dpr, "REFAB", DependencyType::IntraDIMMRank, "tRFC_dpr"}, - {tRFC_slr, "RFMAB", DependencyType::IntraLogicalRank, "tRFC_slr"}, - {tRFC_dlr, "RFMAB", DependencyType::IntraPhysicalRank, "tRFC_dlr"}, - {tRFC_dpr, "RFMAB", DependencyType::IntraDIMMRank, "tRFC_dpr"}, - {tRFCsb_slr, "REFSB", DependencyType::IntraLogicalRank, "tRFCsb_slr"}, - {tRFCsb_dlr, "REFSB", DependencyType::IntraPhysicalRank, "tRFCsb_dlr"}, - {tRFCsb_slr, "RFMSB", DependencyType::IntraLogicalRank, "tRFCsb_slr"}, - {tRFCsb_dlr, "RFMSB", DependencyType::IntraPhysicalRank, "tRFCsb_dlr"}, - {tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"}, - {tFAW_slr - shortCmdOffset, "FAW_LOGICAL", DependencyType::IntraLogicalRank, "tFAW_slr"}, - {tFAW_dlr - shortCmdOffset, "FAW_PHYSICAL", DependencyType::IntraPhysicalRank, "tFAW_dlr"}, - } - ) - ); + dmap.emplace( + piecewise_construct, + forward_as_tuple("REFSB"), + forward_as_tuple(initializer_list{ + {tRC + cmdLengthDiff, "ACT", DependencyType::IntraBankInGroup, "tRC + tCK"}, + {tRRD_L_slr + cmdLengthDiff, + "ACT", + DependencyType::IntraLogicalRank, + "tRRD_L_slr + tCK"}, + {tRDAACT + cmdLengthDiff, "RDA", DependencyType::IntraBankInGroup, "tRDAACT + tCK"}, + {tWRAACT + tRP + cmdLengthDiff, + "WRA", + DependencyType::IntraBankInGroup, + "tWRAACT + tRP + tCK", + passBurstLength16}, + {tWRAACT + tRP + cmdLengthDiff + tBURST16, + "WRA", + DependencyType::IntraBankInGroup, + "tWRAACT + tRP + tCK + tBURST16", + passBurstLength32}, + {tRP, "PREPB", DependencyType::IntraBankInGroup, "tRP"}, + {tRP, "PRESB", DependencyType::IntraBankInGroup, "tRP"}, + {tRFC_slr, "REFAB", DependencyType::IntraLogicalRank, "tRFC_slr"}, + {tRFC_dlr, "REFAB", DependencyType::IntraPhysicalRank, "tRFC_dlr"}, + {tRFC_dpr, "REFAB", DependencyType::IntraDIMMRank, "tRFC_dpr"}, + {tRFC_slr, "RFMAB", DependencyType::IntraLogicalRank, "tRFC_slr"}, + {tRFC_dlr, "RFMAB", DependencyType::IntraPhysicalRank, "tRFC_dlr"}, + {tRFC_dpr, "RFMAB", DependencyType::IntraDIMMRank, "tRFC_dpr"}, + {tRFCsb_slr, "REFSB", DependencyType::IntraLogicalRank, "tRFCsb_slr"}, + {tRFCsb_dlr, "REFSB", DependencyType::IntraPhysicalRank, "tRFCsb_dlr"}, + {tRFCsb_slr, "RFMSB", DependencyType::IntraLogicalRank, "tRFCsb_slr"}, + {tRFCsb_dlr, "RFMSB", DependencyType::IntraPhysicalRank, "tRFCsb_dlr"}, + {tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"}, + {tFAW_slr - shortCmdOffset, + "FAW_LOGICAL", + DependencyType::IntraLogicalRank, + "tFAW_slr"}, + {tFAW_dlr - shortCmdOffset, + "FAW_PHYSICAL", + DependencyType::IntraPhysicalRank, + "tFAW_dlr"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("RFMSB"), - forward_as_tuple( - initializer_list{ - {tRC + cmdLengthDiff, "ACT", DependencyType::IntraBankGroup, "tRC + tCK"}, - {tRRD_L_slr + cmdLengthDiff, "ACT", DependencyType::IntraLogicalRank, "tRRD_L_slr + tCK"}, - {tRDAACT + cmdLengthDiff, "RDA", DependencyType::IntraBankGroup, "tRDAACT + tCK"}, - {tWRAACT + tRP + cmdLengthDiff, "WRA", DependencyType::IntraBankGroup, "tWRAACT + tRP + tCK", passBurstLength16}, - {tWRAACT + tRP + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraBankGroup, "tWRAACT + tRP + tCK + tBURST16", passBurstLength32}, - {tRP, "PREPB", DependencyType::IntraBankGroup, "tRP"}, - {tRP, "PRESB", DependencyType::IntraBankGroup, "tRP"}, - {tRFC_slr, "REFAB", DependencyType::IntraLogicalRank, "tRFC_slr"}, - {tRFC_dlr, "REFAB", DependencyType::IntraPhysicalRank, "tRFC_dlr"}, - {tRFC_dpr, "REFAB", DependencyType::IntraDIMMRank, "tRFC_dpr"}, - {tRFC_slr, "RFMAB", DependencyType::IntraLogicalRank, "tRFC_slr"}, - {tRFC_dlr, "RFMAB", DependencyType::IntraPhysicalRank, "tRFC_dlr"}, - {tRFC_dpr, "RFMAB", DependencyType::IntraDIMMRank, "tRFC_dpr"}, - {tRFCsb_slr, "REFSB", DependencyType::IntraLogicalRank, "tRFCsb_slr"}, - {tRFCsb_dlr, "REFSB", DependencyType::IntraPhysicalRank, "tRFCsb_dlr"}, - {tRFCsb_slr, "RFMSB", DependencyType::IntraLogicalRank, "tRFCsb_slr"}, - {tRFCsb_dlr, "RFMSB", DependencyType::IntraPhysicalRank, "tRFCsb_dlr"}, - {tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"}, - {tFAW_slr - shortCmdOffset, "FAW_LOGICAL", DependencyType::IntraLogicalRank, "tFAW_slr"}, - {tFAW_dlr - shortCmdOffset, "FAW_PHYSICAL", DependencyType::IntraPhysicalRank, "tFAW_dlr"}, - } - ) - ); + dmap.emplace( + piecewise_construct, + forward_as_tuple("RFMSB"), + forward_as_tuple(initializer_list{ + {tRC + cmdLengthDiff, "ACT", DependencyType::IntraBankGroup, "tRC + tCK"}, + {tRRD_L_slr + cmdLengthDiff, + "ACT", + DependencyType::IntraLogicalRank, + "tRRD_L_slr + tCK"}, + {tRDAACT + cmdLengthDiff, "RDA", DependencyType::IntraBankGroup, "tRDAACT + tCK"}, + {tWRAACT + tRP + cmdLengthDiff, + "WRA", + DependencyType::IntraBankGroup, + "tWRAACT + tRP + tCK", + passBurstLength16}, + {tWRAACT + tRP + cmdLengthDiff + tBURST16, + "WRA", + DependencyType::IntraBankGroup, + "tWRAACT + tRP + tCK + tBURST16", + passBurstLength32}, + {tRP, "PREPB", DependencyType::IntraBankGroup, "tRP"}, + {tRP, "PRESB", DependencyType::IntraBankGroup, "tRP"}, + {tRFC_slr, "REFAB", DependencyType::IntraLogicalRank, "tRFC_slr"}, + {tRFC_dlr, "REFAB", DependencyType::IntraPhysicalRank, "tRFC_dlr"}, + {tRFC_dpr, "REFAB", DependencyType::IntraDIMMRank, "tRFC_dpr"}, + {tRFC_slr, "RFMAB", DependencyType::IntraLogicalRank, "tRFC_slr"}, + {tRFC_dlr, "RFMAB", DependencyType::IntraPhysicalRank, "tRFC_dlr"}, + {tRFC_dpr, "RFMAB", DependencyType::IntraDIMMRank, "tRFC_dpr"}, + {tRFCsb_slr, "REFSB", DependencyType::IntraLogicalRank, "tRFCsb_slr"}, + {tRFCsb_dlr, "REFSB", DependencyType::IntraPhysicalRank, "tRFCsb_dlr"}, + {tRFCsb_slr, "RFMSB", DependencyType::IntraLogicalRank, "tRFCsb_slr"}, + {tRFCsb_dlr, "RFMSB", DependencyType::IntraPhysicalRank, "tRFCsb_dlr"}, + {tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"}, + {tFAW_slr - shortCmdOffset, + "FAW_LOGICAL", + DependencyType::IntraLogicalRank, + "tFAW_slr"}, + {tFAW_dlr - shortCmdOffset, + "FAW_PHYSICAL", + DependencyType::IntraPhysicalRank, + "tFAW_dlr"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("PREAB"), - forward_as_tuple( - initializer_list{ - {tRAS + cmdLengthDiff, "ACT", DependencyType::IntraLogicalRank, "tRAS + tCK"}, - {tRTP + cmdLengthDiff, "RD", DependencyType::IntraLogicalRank, "tRTP + tCK"}, - {tRTP + cmdLengthDiff, "RDA", DependencyType::IntraLogicalRank, "tRTP + tCK"}, - {tWRPRE + cmdLengthDiff, "WR", DependencyType::IntraLogicalRank, "tWRPRE + tCK", passBurstLength16}, - {tWRPRE + cmdLengthDiff + tBURST16, "WR", DependencyType::IntraLogicalRank, "tWRPRE + tCK + tBURST16", passBurstLength32}, - {tWRPRE + cmdLengthDiff, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tCK", passBurstLength16}, - {tWRPRE + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tCK + tBURST16", passBurstLength32}, - {tPPD, "PREPB", DependencyType::IntraPhysicalRank, "tPPD"}, - {tPPD, "PREAB", DependencyType::IntraPhysicalRank, "tPPD"}, - {tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("PREAB"), + forward_as_tuple(initializer_list{ + {tRAS + cmdLengthDiff, "ACT", DependencyType::IntraLogicalRank, "tRAS + tCK"}, + {tRTP + cmdLengthDiff, "RD", DependencyType::IntraLogicalRank, "tRTP + tCK"}, + {tRTP + cmdLengthDiff, "RDA", DependencyType::IntraLogicalRank, "tRTP + tCK"}, + {tWRPRE + cmdLengthDiff, + "WR", + DependencyType::IntraLogicalRank, + "tWRPRE + tCK", + passBurstLength16}, + {tWRPRE + cmdLengthDiff + tBURST16, + "WR", + DependencyType::IntraLogicalRank, + "tWRPRE + tCK + tBURST16", + passBurstLength32}, + {tWRPRE + cmdLengthDiff, + "WRA", + DependencyType::IntraLogicalRank, + "tWRPRE + tCK", + passBurstLength16}, + {tWRPRE + cmdLengthDiff + tBURST16, + "WRA", + DependencyType::IntraLogicalRank, + "tWRPRE + tCK + tBURST16", + passBurstLength32}, + {tPPD, "PREPB", DependencyType::IntraPhysicalRank, "tPPD"}, + {tPPD, "PREAB", DependencyType::IntraPhysicalRank, "tPPD"}, + {tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("PRESB"), - forward_as_tuple( - initializer_list{ - {tRAS + cmdLengthDiff, "ACT", DependencyType::IntraBankInGroup, "tRAS + tCK"}, - {tRTP + cmdLengthDiff, "RD", DependencyType::IntraBankInGroup, "tRTP + tCK"}, - {tRTP + cmdLengthDiff, "RDA", DependencyType::IntraBankInGroup, "tRTP + tCK"}, - {tWRPRE + cmdLengthDiff, "WR", DependencyType::IntraBankInGroup, "tWRPRE + tCK", passBurstLength16}, - {tWRPRE + cmdLengthDiff + tBURST16, "WR", DependencyType::IntraBankInGroup, "tWRPRE + tCK + tBURST16", passBurstLength32}, - {tWRPRE + cmdLengthDiff, "WRA", DependencyType::IntraBankInGroup, "tWRPRE + tCK", passBurstLength16}, - {tWRPRE + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraBankInGroup, "tWRPRE + tCK + tBURST16", passBurstLength32}, - {tPPD, "PREPB", DependencyType::IntraPhysicalRank, "tPPD"}, - {tPPD, "PREAB", DependencyType::IntraPhysicalRank, "tPPD"}, - {tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("PRESB"), + forward_as_tuple(initializer_list{ + {tRAS + cmdLengthDiff, "ACT", DependencyType::IntraBankInGroup, "tRAS + tCK"}, + {tRTP + cmdLengthDiff, "RD", DependencyType::IntraBankInGroup, "tRTP + tCK"}, + {tRTP + cmdLengthDiff, "RDA", DependencyType::IntraBankInGroup, "tRTP + tCK"}, + {tWRPRE + cmdLengthDiff, + "WR", + DependencyType::IntraBankInGroup, + "tWRPRE + tCK", + passBurstLength16}, + {tWRPRE + cmdLengthDiff + tBURST16, + "WR", + DependencyType::IntraBankInGroup, + "tWRPRE + tCK + tBURST16", + passBurstLength32}, + {tWRPRE + cmdLengthDiff, + "WRA", + DependencyType::IntraBankInGroup, + "tWRPRE + tCK", + passBurstLength16}, + {tWRPRE + cmdLengthDiff + tBURST16, + "WRA", + DependencyType::IntraBankInGroup, + "tWRPRE + tCK + tBURST16", + passBurstLength32}, + {tPPD, "PREPB", DependencyType::IntraPhysicalRank, "tPPD"}, + {tPPD, "PREAB", DependencyType::IntraPhysicalRank, "tPPD"}, + {tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"}, + })); - return dmap; + return dmap; } diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.h b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.h index 705885f9..f51aaff4 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.h +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.h @@ -38,8 +38,9 @@ #include "../dramtimedependenciesbase.h" #include "businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.h" -class TimeDependenciesInfoDDR5 final : public DRAMTimeDependenciesBase { - public: +class TimeDependenciesInfoDDR5 final : public DRAMTimeDependenciesBase +{ +public: TimeDependenciesInfoDDR5(const QJsonObject& memspec, const uint clk); static const std::vector getPossiblePhases(); @@ -47,11 +48,11 @@ class TimeDependenciesInfoDDR5 final : public DRAMTimeDependenciesBase { void rankIDToRankIDs(size_t rankID, size_t& dimmRID, size_t& physRID, size_t& logRID) const; void bankIDToBankInGroup(size_t logicalRankID, size_t bankID, size_t& bankInGroup) const; - protected: +protected: void mInitializeValues() override; DependencyMap mSpecializedGetDependencies() const override; - protected: +protected: uint mNumOfRanks; uint mNumOfDIMMRanks; uint mNumLogicalRanksPerPhysicalRank; @@ -143,5 +144,4 @@ class TimeDependenciesInfoDDR5 final : public DRAMTimeDependenciesBase { uint tBURST16; uint tBURST32; - }; diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoHBM2.cpp b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoHBM2.cpp index 61cc47a9..2f6ba067 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoHBM2.cpp +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoHBM2.cpp @@ -37,395 +37,339 @@ using namespace std; -TimeDependenciesInfoHBM2::TimeDependenciesInfoHBM2(const QJsonObject& memspec, const uint tCK) : DRAMTimeDependenciesBase(memspec, tCK) { - mInitializeValues(); +TimeDependenciesInfoHBM2::TimeDependenciesInfoHBM2(const QJsonObject& memspec, const uint tCK) : + DRAMTimeDependenciesBase(memspec, tCK) +{ + mInitializeValues(); } -void TimeDependenciesInfoHBM2::mInitializeValues() { - burstLength = mMemspecJson["memarchitecturespec"].toObject()["burstLength"].toInt(); - dataRate = mMemspecJson["memarchitecturespec"].toObject()["dataRate"].toInt(); +void TimeDependenciesInfoHBM2::mInitializeValues() +{ + burstLength = mMemspecJson["memarchitecturespec"].toObject()["burstLength"].toInt(); + dataRate = mMemspecJson["memarchitecturespec"].toObject()["dataRate"].toInt(); - tRP = tCK * mMemspecJson["memtimingspec"].toObject()["RP"].toInt(); - tRAS = tCK * mMemspecJson["memtimingspec"].toObject()["RAS"].toInt(); - tRC = tCK * mMemspecJson["memtimingspec"].toObject()["RC"].toInt(); - tRCDRD = tCK * mMemspecJson["memtimingspec"].toObject()["RCDRD"].toInt(); - tRCDWR = tCK * mMemspecJson["memtimingspec"].toObject()["RCDWR"].toInt(); - tRTP = tCK * mMemspecJson["memtimingspec"].toObject()["RTP"].toInt(); - tRRDS = tCK * mMemspecJson["memtimingspec"].toObject()["RRDS"].toInt(); - tRRDL = tCK * mMemspecJson["memtimingspec"].toObject()["RRDL"].toInt(); - tRL = tCK * mMemspecJson["memtimingspec"].toObject()["RL"].toInt(); - tPL = tCK * mMemspecJson["memtimingspec"].toObject()["PL"].toInt(); - tCCDS = tCK * mMemspecJson["memtimingspec"].toObject()["CCDS"].toInt(); - tCCDL = tCK * mMemspecJson["memtimingspec"].toObject()["CCDL"].toInt(); - tRTW = tCK * mMemspecJson["memtimingspec"].toObject()["RTW"].toInt(); - tWL = tCK * mMemspecJson["memtimingspec"].toObject()["WL"].toInt(); - tWR = tCK * mMemspecJson["memtimingspec"].toObject()["WR"].toInt(); - tWTRS = tCK * mMemspecJson["memtimingspec"].toObject()["WTRS"].toInt(); - tWTRL = tCK * mMemspecJson["memtimingspec"].toObject()["WTRL"].toInt(); - tCKE = tCK * mMemspecJson["memtimingspec"].toObject()["CKE"].toInt(); - tXP = tCK * mMemspecJson["memtimingspec"].toObject()["XP"].toInt(); - tRFC = tCK * mMemspecJson["memtimingspec"].toObject()["RFC"].toInt(); - tRFCSB = tCK * mMemspecJson["memtimingspec"].toObject()["RFCSB"].toInt(); - tRREFD = tCK * mMemspecJson["memtimingspec"].toObject()["RREFD"].toInt(); - tXS = tCK * mMemspecJson["memtimingspec"].toObject()["XS"].toInt(); - tFAW = tCK * mMemspecJson["memtimingspec"].toObject()["FAW"].toInt(); + tRP = tCK * mMemspecJson["memtimingspec"].toObject()["RP"].toInt(); + tRAS = tCK * mMemspecJson["memtimingspec"].toObject()["RAS"].toInt(); + tRC = tCK * mMemspecJson["memtimingspec"].toObject()["RC"].toInt(); + tRCDRD = tCK * mMemspecJson["memtimingspec"].toObject()["RCDRD"].toInt(); + tRCDWR = tCK * mMemspecJson["memtimingspec"].toObject()["RCDWR"].toInt(); + tRTP = tCK * mMemspecJson["memtimingspec"].toObject()["RTP"].toInt(); + tRRDS = tCK * mMemspecJson["memtimingspec"].toObject()["RRDS"].toInt(); + tRRDL = tCK * mMemspecJson["memtimingspec"].toObject()["RRDL"].toInt(); + tRL = tCK * mMemspecJson["memtimingspec"].toObject()["RL"].toInt(); + tPL = tCK * mMemspecJson["memtimingspec"].toObject()["PL"].toInt(); + tCCDS = tCK * mMemspecJson["memtimingspec"].toObject()["CCDS"].toInt(); + tCCDL = tCK * mMemspecJson["memtimingspec"].toObject()["CCDL"].toInt(); + tRTW = tCK * mMemspecJson["memtimingspec"].toObject()["RTW"].toInt(); + tWL = tCK * mMemspecJson["memtimingspec"].toObject()["WL"].toInt(); + tWR = tCK * mMemspecJson["memtimingspec"].toObject()["WR"].toInt(); + tWTRS = tCK * mMemspecJson["memtimingspec"].toObject()["WTRS"].toInt(); + tWTRL = tCK * mMemspecJson["memtimingspec"].toObject()["WTRL"].toInt(); + tCKE = tCK * mMemspecJson["memtimingspec"].toObject()["CKE"].toInt(); + tXP = tCK * mMemspecJson["memtimingspec"].toObject()["XP"].toInt(); + tRFC = tCK * mMemspecJson["memtimingspec"].toObject()["RFC"].toInt(); + tRFCSB = tCK * mMemspecJson["memtimingspec"].toObject()["RFCSB"].toInt(); + tRREFD = tCK * mMemspecJson["memtimingspec"].toObject()["RREFD"].toInt(); + tXS = tCK * mMemspecJson["memtimingspec"].toObject()["XS"].toInt(); + tFAW = tCK * mMemspecJson["memtimingspec"].toObject()["FAW"].toInt(); - tPD = tCKE; - tCKESR = tCKE + tCK; + tPD = tCKE; + tCKESR = tCKE + tCK; - tBURST = (uint) (burstLength / (float) dataRate) * tCK; - tRDPDE = tRL + tPL + tBURST + tCK; - tRDSRE = tRDPDE; - tWRPRE = tWL + tBURST + tWR; - tWRPDE = tWL + tPL + tBURST + tCK + tWR; - tWRAPDE = tWL + tPL + tBURST + tCK + tWR; - tWRRDS = tWL + tBURST + tWTRS; - tWRRDL = tWL + tBURST + tWTRL; + tBURST = (uint)(burstLength / (float)dataRate) * tCK; + tRDPDE = tRL + tPL + tBURST + tCK; + tRDSRE = tRDPDE; + tWRPRE = tWL + tBURST + tWR; + tWRPDE = tWL + tPL + tBURST + tCK + tWR; + tWRAPDE = tWL + tPL + tBURST + tCK + tWR; + tWRRDS = tWL + tBURST + tWTRS; + tWRRDL = tWL + tBURST + tWTRL; - mPools.insert({ - "RAS_BUS", { - 1, { - {"ACT", 2*tCK}, - {"PREPB", tCK}, - {"PREAB", tCK}, - {"REFPB", tCK}, - {"REFAB", tCK}, - {"PDEA", tCK}, - {"PDXA", tCK}, - {"PDEP", tCK}, - {"PDXP", tCK}, - {"SREFEN", tCK}, - {"SREFEX", tCK}, - } - } - }); + mPools.insert({"RAS_BUS", + {1, + { + {"ACT", 2 * tCK}, + {"PREPB", tCK}, + {"PREAB", tCK}, + {"REFPB", tCK}, + {"REFAB", tCK}, + {"PDEA", tCK}, + {"PDXA", tCK}, + {"PDEP", tCK}, + {"PDXP", tCK}, + {"SREFEN", tCK}, + {"SREFEX", tCK}, + }}}); - mPools.insert({ - "CAS_BUS", { - 1, { - {"RD", tCK}, - {"RDA", tCK}, - {"WR", tCK}, - {"WRA", tCK}, - {"PDEA", tCK}, - {"PDXA", tCK}, - {"PDEP", tCK}, - {"PDXP", tCK}, - {"SREFEN", tCK}, - {"SREFEX", tCK}, - } - } - }); + mPools.insert({"CAS_BUS", + {1, + { + {"RD", tCK}, + {"RDA", tCK}, + {"WR", tCK}, + {"WRA", tCK}, + {"PDEA", tCK}, + {"PDXA", tCK}, + {"PDEP", tCK}, + {"PDXP", tCK}, + {"SREFEN", tCK}, + {"SREFEX", tCK}, + }}}); - mPools.insert({ - "NAW", { - 4, { - {"ACT", tFAW}, - {"REFPB", tFAW}, - } - } - }); - + mPools.insert({"NAW", + {4, + { + {"ACT", tFAW}, + {"REFPB", tFAW}, + }}}); } -const std::vector TimeDependenciesInfoHBM2::getPossiblePhases() { - return { - "ACT", - "RD", - "WR", - "PREPB", - "RDA", - "WRA", - "REFPB", - "REFAB", - "PREAB", - "PDEP", - "PDXP", - "SREFEN", - "SREFEX", - "PDEA", - "PDXA", - }; +const std::vector TimeDependenciesInfoHBM2::getPossiblePhases() +{ + return { + "ACT", + "RD", + "WR", + "PREPB", + "RDA", + "WRA", + "REFPB", + "REFAB", + "PREAB", + "PDEP", + "PDXP", + "SREFEN", + "SREFEX", + "PDEA", + "PDXA", + }; } -DependencyMap TimeDependenciesInfoHBM2::mSpecializedGetDependencies() const { - DependencyMap dmap; +DependencyMap TimeDependenciesInfoHBM2::mSpecializedGetDependencies() const +{ + DependencyMap dmap; - dmap.emplace( - piecewise_construct, - forward_as_tuple("ACT"), - forward_as_tuple( - initializer_list{ - {tRC, "ACT", DependencyType::IntraBank, "tRC"}, - {tRRDL, "ACT", DependencyType::IntraBankGroup, "tRRDL"}, - {tRRDS, "ACT", DependencyType::IntraRank, "tRRDS"}, - {tRTP + tRP - tCK, "RDA", DependencyType::IntraBank, "tRTP + tRP - tCK"}, - {tWRPRE + tRP - tCK, "WRA", DependencyType::IntraBank, "tWRPRE + tRP - tCK"}, - {tRP - tCK, "PREPB", DependencyType::IntraBank, "tRP - tCK"}, - {tRP - tCK, "PREAB", DependencyType::IntraRank, "tRP - tCK"}, - {tXP - tCK, "PDXA", DependencyType::IntraRank, "tXP - tCK"}, - {tXP - tCK, "PDXP", DependencyType::IntraRank, "tXP - tCK"}, - {tRFC - tCK, "REFAB", DependencyType::IntraRank, "tRFC - tCK"}, - {tRFCSB - tCK, "REFPB", DependencyType::IntraBank, "tRFCSB - tCK"}, - {tRREFD - tCK, "REFPB", DependencyType::IntraBankGroup, "tRREFD - tCK"}, - {tRREFD - tCK, "REFPB", DependencyType::IntraRank, "tRREFD - tCK"}, - {tXS - tCK, "SREFEX", DependencyType::IntraRank, "tXS - tCK"}, - {2 * tCK, "RAS_BUS", DependencyType::InterRank, "2 * tCK"}, - {tFAW, "NAW", DependencyType::IntraRank, "tFAW"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("ACT"), + forward_as_tuple(initializer_list{ + {tRC, "ACT", DependencyType::IntraBank, "tRC"}, + {tRRDL, "ACT", DependencyType::IntraBankGroup, "tRRDL"}, + {tRRDS, "ACT", DependencyType::IntraRank, "tRRDS"}, + {tRTP + tRP - tCK, "RDA", DependencyType::IntraBank, "tRTP + tRP - tCK"}, + {tWRPRE + tRP - tCK, "WRA", DependencyType::IntraBank, "tWRPRE + tRP - tCK"}, + {tRP - tCK, "PREPB", DependencyType::IntraBank, "tRP - tCK"}, + {tRP - tCK, "PREAB", DependencyType::IntraRank, "tRP - tCK"}, + {tXP - tCK, "PDXA", DependencyType::IntraRank, "tXP - tCK"}, + {tXP - tCK, "PDXP", DependencyType::IntraRank, "tXP - tCK"}, + {tRFC - tCK, "REFAB", DependencyType::IntraRank, "tRFC - tCK"}, + {tRFCSB - tCK, "REFPB", DependencyType::IntraBank, "tRFCSB - tCK"}, + {tRREFD - tCK, "REFPB", DependencyType::IntraBankGroup, "tRREFD - tCK"}, + {tRREFD - tCK, "REFPB", DependencyType::IntraRank, "tRREFD - tCK"}, + {tXS - tCK, "SREFEX", DependencyType::IntraRank, "tXS - tCK"}, + {2 * tCK, "RAS_BUS", DependencyType::InterRank, "2 * tCK"}, + {tFAW, "NAW", DependencyType::IntraRank, "tFAW"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("RD"), - forward_as_tuple( - initializer_list{ - {tRCDRD + tCK, "ACT", DependencyType::IntraBank, "tRCDRD + tCK"}, - {tCCDL, "RD", DependencyType::IntraBank, "tCCDL"}, - {tCCDL, "RD", DependencyType::IntraBankGroup, "tCCDL"}, - {tCCDS, "RD", DependencyType::IntraRank, "tCCDS"}, - {tCCDL, "RDA", DependencyType::IntraBankGroup, "tCCDL"}, - {tCCDS, "RDA", DependencyType::IntraRank, "tCCDS"}, - {tWRRDL, "WR", DependencyType::IntraBank, "tWRRDL"}, - {tWRRDL, "WR", DependencyType::IntraBankGroup, "tWRRDL"}, - {tWRRDS, "WR", DependencyType::IntraRank, "tWRRDS"}, - {tWRRDL, "WRA", DependencyType::IntraBankGroup, "tWRRDL"}, - {tWRRDS, "WRA", DependencyType::IntraRank, "tWRRDS"}, - {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, - {tCK, "CAS_BUS", DependencyType::InterRank, "tCK"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("RD"), + forward_as_tuple(initializer_list{ + {tRCDRD + tCK, "ACT", DependencyType::IntraBank, "tRCDRD + tCK"}, + {tCCDL, "RD", DependencyType::IntraBank, "tCCDL"}, + {tCCDL, "RD", DependencyType::IntraBankGroup, "tCCDL"}, + {tCCDS, "RD", DependencyType::IntraRank, "tCCDS"}, + {tCCDL, "RDA", DependencyType::IntraBankGroup, "tCCDL"}, + {tCCDS, "RDA", DependencyType::IntraRank, "tCCDS"}, + {tWRRDL, "WR", DependencyType::IntraBank, "tWRRDL"}, + {tWRRDL, "WR", DependencyType::IntraBankGroup, "tWRRDL"}, + {tWRRDS, "WR", DependencyType::IntraRank, "tWRRDS"}, + {tWRRDL, "WRA", DependencyType::IntraBankGroup, "tWRRDL"}, + {tWRRDS, "WRA", DependencyType::IntraRank, "tWRRDS"}, + {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, + {tCK, "CAS_BUS", DependencyType::InterRank, "tCK"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("WR"), - forward_as_tuple( - initializer_list{ - {tRCDWR + tCK, "ACT", DependencyType::IntraBank, "tRCDWR + tCK"}, - {tRTW, "RD", DependencyType::IntraBank, "tRTW"}, - {tRTW, "RD", DependencyType::IntraBankGroup, "tRTW"}, - {tRTW, "RD", DependencyType::IntraRank, "tRTW"}, - {tRTW, "RDA", DependencyType::IntraBankGroup, "tRTW"}, - {tRTW, "RDA", DependencyType::IntraRank, "tRTW"}, - {tCCDL, "WR", DependencyType::IntraBank, "tCCDL"}, - {tCCDL, "WR", DependencyType::IntraBankGroup, "tCCDL"}, - {tCCDS, "WR", DependencyType::IntraRank, "tCCDS"}, - {tCCDL, "WRA", DependencyType::IntraBankGroup, "tCCDL"}, - {tCCDS, "WRA", DependencyType::IntraRank, "tCCDS"}, - {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, - {tCK, "CAS_BUS", DependencyType::InterRank, "tCK"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("WR"), + forward_as_tuple(initializer_list{ + {tRCDWR + tCK, "ACT", DependencyType::IntraBank, "tRCDWR + tCK"}, + {tRTW, "RD", DependencyType::IntraBank, "tRTW"}, + {tRTW, "RD", DependencyType::IntraBankGroup, "tRTW"}, + {tRTW, "RD", DependencyType::IntraRank, "tRTW"}, + {tRTW, "RDA", DependencyType::IntraBankGroup, "tRTW"}, + {tRTW, "RDA", DependencyType::IntraRank, "tRTW"}, + {tCCDL, "WR", DependencyType::IntraBank, "tCCDL"}, + {tCCDL, "WR", DependencyType::IntraBankGroup, "tCCDL"}, + {tCCDS, "WR", DependencyType::IntraRank, "tCCDS"}, + {tCCDL, "WRA", DependencyType::IntraBankGroup, "tCCDL"}, + {tCCDS, "WRA", DependencyType::IntraRank, "tCCDS"}, + {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, + {tCK, "CAS_BUS", DependencyType::InterRank, "tCK"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("PREPB"), - forward_as_tuple( - initializer_list{ - {tRAS + tCK, "ACT", DependencyType::IntraBank, "tRAS + tCK"}, - {tRTP, "RD", DependencyType::IntraBank, "tRTP"}, - {tWRPRE, "WR", DependencyType::IntraBank, "tWRPRE"}, - {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, - {tCK, "RAS_BUS", DependencyType::InterRank, "tCK"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("PREPB"), + forward_as_tuple(initializer_list{ + {tRAS + tCK, "ACT", DependencyType::IntraBank, "tRAS + tCK"}, + {tRTP, "RD", DependencyType::IntraBank, "tRTP"}, + {tWRPRE, "WR", DependencyType::IntraBank, "tWRPRE"}, + {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, + {tCK, "RAS_BUS", DependencyType::InterRank, "tCK"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("RDA"), - forward_as_tuple( - initializer_list{ - {tRCDRD + tCK, "ACT", DependencyType::IntraBank, "tRCDRD + tCK"}, - {tCCDL, "RD", DependencyType::IntraBank, "tCCDL"}, - {tCCDL, "RD", DependencyType::IntraBankGroup, "tCCDL"}, - {tCCDS, "RD", DependencyType::IntraRank, "tCCDS"}, - {tCCDL, "RDA", DependencyType::IntraBankGroup, "tCCDL"}, - {tCCDS, "RDA", DependencyType::IntraRank, "tCCDS"}, - {tWL + tBURST + max({tWR - tRTP, tWTRL}), "WR", DependencyType::IntraBank, "tWL + tBURST + max(tWR - tRTP, tWTRL)"}, - {tWRRDL, "WR", DependencyType::IntraBankGroup, "tWRRDL"}, - {tWRRDS, "WR", DependencyType::IntraRank, "tWRRDS"}, - {tWRRDL, "WRA", DependencyType::IntraBankGroup, "tWRRDL"}, - {tWRRDS, "WRA", DependencyType::IntraRank, "tWRRDS"}, - {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, - {tCK, "CAS_BUS", DependencyType::InterRank, "tCK"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("RDA"), + forward_as_tuple(initializer_list{ + {tRCDRD + tCK, "ACT", DependencyType::IntraBank, "tRCDRD + tCK"}, + {tCCDL, "RD", DependencyType::IntraBank, "tCCDL"}, + {tCCDL, "RD", DependencyType::IntraBankGroup, "tCCDL"}, + {tCCDS, "RD", DependencyType::IntraRank, "tCCDS"}, + {tCCDL, "RDA", DependencyType::IntraBankGroup, "tCCDL"}, + {tCCDS, "RDA", DependencyType::IntraRank, "tCCDS"}, + {tWL + tBURST + max({tWR - tRTP, tWTRL}), + "WR", + DependencyType::IntraBank, + "tWL + tBURST + max(tWR - tRTP, tWTRL)"}, + {tWRRDL, "WR", DependencyType::IntraBankGroup, "tWRRDL"}, + {tWRRDS, "WR", DependencyType::IntraRank, "tWRRDS"}, + {tWRRDL, "WRA", DependencyType::IntraBankGroup, "tWRRDL"}, + {tWRRDS, "WRA", DependencyType::IntraRank, "tWRRDS"}, + {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, + {tCK, "CAS_BUS", DependencyType::InterRank, "tCK"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("WRA"), - forward_as_tuple( - initializer_list{ - {tRCDWR + tCK, "ACT", DependencyType::IntraBank, "tRCDWR + tCK"}, - {tRTW, "RD", DependencyType::IntraBank, "tRTW"}, - {tRTW, "RD", DependencyType::IntraBankGroup, "tRTW"}, - {tRTW, "RD", DependencyType::IntraRank, "tRTW"}, - {tRTW, "RDA", DependencyType::IntraBankGroup, "tRTW"}, - {tRTW, "RDA", DependencyType::IntraRank, "tRTW"}, - {tCCDL, "WR", DependencyType::IntraBank, "tCCDL"}, - {tCCDL, "WR", DependencyType::IntraBankGroup, "tCCDL"}, - {tCCDS, "WR", DependencyType::IntraRank, "tCCDS"}, - {tCCDL, "WRA", DependencyType::IntraBankGroup, "tCCDL"}, - {tCCDS, "WRA", DependencyType::IntraRank, "tCCDS"}, - {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, - {tCK, "CAS_BUS", DependencyType::InterRank, "tCK"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("WRA"), + forward_as_tuple(initializer_list{ + {tRCDWR + tCK, "ACT", DependencyType::IntraBank, "tRCDWR + tCK"}, + {tRTW, "RD", DependencyType::IntraBank, "tRTW"}, + {tRTW, "RD", DependencyType::IntraBankGroup, "tRTW"}, + {tRTW, "RD", DependencyType::IntraRank, "tRTW"}, + {tRTW, "RDA", DependencyType::IntraBankGroup, "tRTW"}, + {tRTW, "RDA", DependencyType::IntraRank, "tRTW"}, + {tCCDL, "WR", DependencyType::IntraBank, "tCCDL"}, + {tCCDL, "WR", DependencyType::IntraBankGroup, "tCCDL"}, + {tCCDS, "WR", DependencyType::IntraRank, "tCCDS"}, + {tCCDL, "WRA", DependencyType::IntraBankGroup, "tCCDL"}, + {tCCDS, "WRA", DependencyType::IntraRank, "tCCDS"}, + {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, + {tCK, "CAS_BUS", DependencyType::InterRank, "tCK"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("REFPB"), - forward_as_tuple( - initializer_list{ - {tRC + tCK, "ACT", DependencyType::IntraBank, "tRC + tCK"}, - {tRRDL + tCK, "ACT", DependencyType::IntraBankGroup, "tRRDL + tCK"}, - {tRRDS + tCK, "ACT", DependencyType::IntraRank, "tRRDS + tCK"}, - {tRTP + tRP, "RDA", DependencyType::IntraBank, "tRTP + tRP"}, - {tWRPRE + tRP, "WRA", DependencyType::IntraBank, "tWRPRE + tRP"}, - {tRP, "PREPB", DependencyType::IntraBank, "tRP"}, - {tRP, "PREAB", DependencyType::IntraRank, "tRP"}, - {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, - {tXP, "PDXP", DependencyType::IntraRank, "tXP"}, - {tRFC, "REFAB", DependencyType::IntraRank, "tRFC"}, - {tRFCSB, "REFPB", DependencyType::IntraBank, "tRFCSB"}, - {tRREFD, "REFPB", DependencyType::IntraBankGroup, "tRREFD"}, - {tRREFD, "REFPB", DependencyType::IntraRank, "tRREFD"}, - {tXS, "SREFEX", DependencyType::IntraRank, "tXS"}, - {tCK, "RAS_BUS", DependencyType::InterRank, "tCK"}, - {tFAW, "NAW", DependencyType::IntraRank, "tFAW"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("REFPB"), + forward_as_tuple(initializer_list{ + {tRC + tCK, "ACT", DependencyType::IntraBank, "tRC + tCK"}, + {tRRDL + tCK, "ACT", DependencyType::IntraBankGroup, "tRRDL + tCK"}, + {tRRDS + tCK, "ACT", DependencyType::IntraRank, "tRRDS + tCK"}, + {tRTP + tRP, "RDA", DependencyType::IntraBank, "tRTP + tRP"}, + {tWRPRE + tRP, "WRA", DependencyType::IntraBank, "tWRPRE + tRP"}, + {tRP, "PREPB", DependencyType::IntraBank, "tRP"}, + {tRP, "PREAB", DependencyType::IntraRank, "tRP"}, + {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, + {tXP, "PDXP", DependencyType::IntraRank, "tXP"}, + {tRFC, "REFAB", DependencyType::IntraRank, "tRFC"}, + {tRFCSB, "REFPB", DependencyType::IntraBank, "tRFCSB"}, + {tRREFD, "REFPB", DependencyType::IntraBankGroup, "tRREFD"}, + {tRREFD, "REFPB", DependencyType::IntraRank, "tRREFD"}, + {tXS, "SREFEX", DependencyType::IntraRank, "tXS"}, + {tCK, "RAS_BUS", DependencyType::InterRank, "tCK"}, + {tFAW, "NAW", DependencyType::IntraRank, "tFAW"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("REFAB"), - forward_as_tuple( - initializer_list{ - {tRC + tCK, "ACT", DependencyType::IntraRank, "tRC + tCK"}, - {tRTP + tRP, "RDA", DependencyType::IntraRank, "tRTP + tRP"}, - {tWRPRE + tRP, "WRA", DependencyType::IntraRank, "tWRPRE + tRP"}, - {tRP, "PREPB", DependencyType::IntraRank, "tRP"}, - {tRP, "PREAB", DependencyType::IntraRank, "tRP"}, - {tXP, "PDXP", DependencyType::IntraRank, "tXP"}, - {tRFC, "REFAB", DependencyType::IntraRank, "tRFC"}, - {tRFCSB, "REFPB", DependencyType::IntraRank, "tRFCSB"}, - {tXS, "SREFEX", DependencyType::IntraRank, "tXS"}, - {tCK, "RAS_BUS", DependencyType::InterRank, "tCK"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("REFAB"), + forward_as_tuple(initializer_list{ + {tRC + tCK, "ACT", DependencyType::IntraRank, "tRC + tCK"}, + {tRTP + tRP, "RDA", DependencyType::IntraRank, "tRTP + tRP"}, + {tWRPRE + tRP, "WRA", DependencyType::IntraRank, "tWRPRE + tRP"}, + {tRP, "PREPB", DependencyType::IntraRank, "tRP"}, + {tRP, "PREAB", DependencyType::IntraRank, "tRP"}, + {tXP, "PDXP", DependencyType::IntraRank, "tXP"}, + {tRFC, "REFAB", DependencyType::IntraRank, "tRFC"}, + {tRFCSB, "REFPB", DependencyType::IntraRank, "tRFCSB"}, + {tXS, "SREFEX", DependencyType::IntraRank, "tXS"}, + {tCK, "RAS_BUS", DependencyType::InterRank, "tCK"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("PREAB"), - forward_as_tuple( - initializer_list{ - {tRAS + tCK, "ACT", DependencyType::IntraRank, "tRAS + tCK"}, - {tRTP, "RD", DependencyType::IntraRank, "tRTP"}, - {tRTP, "RDA", DependencyType::IntraRank, "tRTP"}, - {tWRPRE, "WR", DependencyType::IntraRank, "tWRPRE"}, - {tWRPRE, "WRA", DependencyType::IntraRank, "tWRPRE"}, - {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, - {tRFCSB, "REFPB", DependencyType::IntraRank, "tRFCSB"}, - {tCK, "RAS_BUS", DependencyType::InterRank, "tCK"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("PREAB"), + forward_as_tuple(initializer_list{ + {tRAS + tCK, "ACT", DependencyType::IntraRank, "tRAS + tCK"}, + {tRTP, "RD", DependencyType::IntraRank, "tRTP"}, + {tRTP, "RDA", DependencyType::IntraRank, "tRTP"}, + {tWRPRE, "WR", DependencyType::IntraRank, "tWRPRE"}, + {tWRPRE, "WRA", DependencyType::IntraRank, "tWRPRE"}, + {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, + {tRFCSB, "REFPB", DependencyType::IntraRank, "tRFCSB"}, + {tCK, "RAS_BUS", DependencyType::InterRank, "tCK"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("PDEP"), - forward_as_tuple( - initializer_list{ - {tRDPDE, "RD", DependencyType::IntraRank, "tRDPDE"}, - {tRDPDE, "RDA", DependencyType::IntraRank, "tRDPDE"}, - {tWRAPDE, "WRA", DependencyType::IntraRank, "tWRAPDE"}, - {tCKE, "PDXP", DependencyType::IntraRank, "tCKE"}, - {tXS, "SREFEX", DependencyType::IntraRank, "tXS"}, - {tCK, "RAS_BUS", DependencyType::InterRank, "tCK"}, - {tCK, "CAS_BUS", DependencyType::InterRank, "tCK"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("PDEP"), + forward_as_tuple(initializer_list{ + {tRDPDE, "RD", DependencyType::IntraRank, "tRDPDE"}, + {tRDPDE, "RDA", DependencyType::IntraRank, "tRDPDE"}, + {tWRAPDE, "WRA", DependencyType::IntraRank, "tWRAPDE"}, + {tCKE, "PDXP", DependencyType::IntraRank, "tCKE"}, + {tXS, "SREFEX", DependencyType::IntraRank, "tXS"}, + {tCK, "RAS_BUS", DependencyType::InterRank, "tCK"}, + {tCK, "CAS_BUS", DependencyType::InterRank, "tCK"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("PDXP"), - forward_as_tuple( - initializer_list{ - {tPD, "PDEP", DependencyType::IntraRank, "tPD"}, - {tCK, "RAS_BUS", DependencyType::InterRank, "tCK"}, - {tCK, "CAS_BUS", DependencyType::InterRank, "tCK"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("PDXP"), + forward_as_tuple(initializer_list{ + {tPD, "PDEP", DependencyType::IntraRank, "tPD"}, + {tCK, "RAS_BUS", DependencyType::InterRank, "tCK"}, + {tCK, "CAS_BUS", DependencyType::InterRank, "tCK"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("SREFEN"), - forward_as_tuple( - initializer_list{ - {tRC + tCK, "ACT", DependencyType::IntraRank, "tRC + tCK"}, - {max({tRTP + tRP, tRDSRE}), "RDA", DependencyType::IntraRank, "max(tRTP + tRP, tRDSRE)"}, - {tWRPRE + tRP, "WRA", DependencyType::IntraRank, "tWRPRE + tRP"}, - {tRP, "PREPB", DependencyType::IntraRank, "tRP"}, - {tRP, "PREAB", DependencyType::IntraRank, "tRP"}, - {tXP, "PDXP", DependencyType::IntraRank, "tXP"}, - {tRFC, "REFAB", DependencyType::IntraRank, "tRFC"}, - {tRFCSB, "REFPB", DependencyType::IntraRank, "tRFCSB"}, - {tXS, "SREFEX", DependencyType::IntraRank, "tXS"}, - {tCK, "RAS_BUS", DependencyType::InterRank, "tCK"}, - {tCK, "CAS_BUS", DependencyType::InterRank, "tCK"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("SREFEN"), + forward_as_tuple(initializer_list{ + {tRC + tCK, "ACT", DependencyType::IntraRank, "tRC + tCK"}, + {max({tRTP + tRP, tRDSRE}), + "RDA", + DependencyType::IntraRank, + "max(tRTP + tRP, tRDSRE)"}, + {tWRPRE + tRP, "WRA", DependencyType::IntraRank, "tWRPRE + tRP"}, + {tRP, "PREPB", DependencyType::IntraRank, "tRP"}, + {tRP, "PREAB", DependencyType::IntraRank, "tRP"}, + {tXP, "PDXP", DependencyType::IntraRank, "tXP"}, + {tRFC, "REFAB", DependencyType::IntraRank, "tRFC"}, + {tRFCSB, "REFPB", DependencyType::IntraRank, "tRFCSB"}, + {tXS, "SREFEX", DependencyType::IntraRank, "tXS"}, + {tCK, "RAS_BUS", DependencyType::InterRank, "tCK"}, + {tCK, "CAS_BUS", DependencyType::InterRank, "tCK"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("SREFEX"), - forward_as_tuple( - initializer_list{ - {tCKESR, "SREFEN", DependencyType::IntraRank, "tCKESR"}, - {tCK, "RAS_BUS", DependencyType::InterRank, "tCK"}, - {tCK, "CAS_BUS", DependencyType::InterRank, "tCK"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("SREFEX"), + forward_as_tuple(initializer_list{ + {tCKESR, "SREFEN", DependencyType::IntraRank, "tCKESR"}, + {tCK, "RAS_BUS", DependencyType::InterRank, "tCK"}, + {tCK, "CAS_BUS", DependencyType::InterRank, "tCK"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("PDEA"), - forward_as_tuple( - initializer_list{ - {tRDPDE, "RD", DependencyType::IntraRank, "tRDPDE"}, - {tRDPDE, "RDA", DependencyType::IntraRank, "tRDPDE"}, - {tWRPDE, "WR", DependencyType::IntraRank, "tWRPDE"}, - {tWRAPDE, "WRA", DependencyType::IntraRank, "tWRAPDE"}, - {tCKE, "PDXA", DependencyType::IntraRank, "tCKE"}, - {tCK, "RAS_BUS", DependencyType::InterRank, "tCK"}, - {tCK, "CAS_BUS", DependencyType::InterRank, "tCK"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("PDEA"), + forward_as_tuple(initializer_list{ + {tRDPDE, "RD", DependencyType::IntraRank, "tRDPDE"}, + {tRDPDE, "RDA", DependencyType::IntraRank, "tRDPDE"}, + {tWRPDE, "WR", DependencyType::IntraRank, "tWRPDE"}, + {tWRAPDE, "WRA", DependencyType::IntraRank, "tWRAPDE"}, + {tCKE, "PDXA", DependencyType::IntraRank, "tCKE"}, + {tCK, "RAS_BUS", DependencyType::InterRank, "tCK"}, + {tCK, "CAS_BUS", DependencyType::InterRank, "tCK"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("PDXA"), - forward_as_tuple( - initializer_list{ - {tPD, "PDEA", DependencyType::IntraRank, "tPD"}, - {tCK, "RAS_BUS", DependencyType::InterRank, "tCK"}, - {tCK, "CAS_BUS", DependencyType::InterRank, "tCK"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("PDXA"), + forward_as_tuple(initializer_list{ + {tPD, "PDEA", DependencyType::IntraRank, "tPD"}, + {tCK, "RAS_BUS", DependencyType::InterRank, "tCK"}, + {tCK, "CAS_BUS", DependencyType::InterRank, "tCK"}, + })); - return dmap; + return dmap; } diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoHBM2.h b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoHBM2.h index 53f41f22..cd789b9f 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoHBM2.h +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoHBM2.h @@ -37,17 +37,18 @@ #include "../dramtimedependenciesbase.h" -class TimeDependenciesInfoHBM2 final : public DRAMTimeDependenciesBase { - public: +class TimeDependenciesInfoHBM2 final : public DRAMTimeDependenciesBase +{ +public: TimeDependenciesInfoHBM2(const QJsonObject& memspec, const uint clk); static const std::vector getPossiblePhases(); - protected: +protected: void mInitializeValues() override; DependencyMap mSpecializedGetDependencies() const override; - protected: +protected: uint burstLength; uint dataRate; @@ -86,5 +87,4 @@ class TimeDependenciesInfoHBM2 final : public DRAMTimeDependenciesBase { uint tWRAPDE; uint tWRRDS; uint tWRRDL; - }; diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR4.cpp b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR4.cpp index 8fcb2aaf..4c69beb3 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR4.cpp +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR4.cpp @@ -37,406 +37,351 @@ using namespace std; -TimeDependenciesInfoLPDDR4::TimeDependenciesInfoLPDDR4(const QJsonObject& memspec, const uint tCK) : DRAMTimeDependenciesBase(memspec, tCK) { - mInitializeValues(); +TimeDependenciesInfoLPDDR4::TimeDependenciesInfoLPDDR4(const QJsonObject& memspec, const uint tCK) : + DRAMTimeDependenciesBase(memspec, tCK) +{ + mInitializeValues(); } -void TimeDependenciesInfoLPDDR4::mInitializeValues() { - burstLength = mMemspecJson["memarchitecturespec"].toObject()["burstLength"].toInt(); - dataRate = mMemspecJson["memarchitecturespec"].toObject()["dataRate"].toInt(); +void TimeDependenciesInfoLPDDR4::mInitializeValues() +{ + burstLength = mMemspecJson["memarchitecturespec"].toObject()["burstLength"].toInt(); + dataRate = mMemspecJson["memarchitecturespec"].toObject()["dataRate"].toInt(); - tRRD = tCK * mMemspecJson["memtimingspec"].toObject()["RRD"].toInt(); - tRCD = tCK * mMemspecJson["memtimingspec"].toObject()["RCD"].toInt(); - tRAS = tCK * mMemspecJson["memtimingspec"].toObject()["RAS"].toInt(); - tFAW = tCK * mMemspecJson["memtimingspec"].toObject()["FAW"].toInt(); - tRPpb = tCK * mMemspecJson["memtimingspec"].toObject()["RPpb"].toInt(); - tRPab = tCK * mMemspecJson["memtimingspec"].toObject()["RPab"].toInt(); - tRCpb = tCK * mMemspecJson["memtimingspec"].toObject()["RCpb"].toInt(); - tRCab = tCK * mMemspecJson["memtimingspec"].toObject()["RCab"].toInt(); - tCCD = tCK * mMemspecJson["memtimingspec"].toObject()["CCD"].toInt(); - tRTP = tCK * mMemspecJson["memtimingspec"].toObject()["RTP"].toInt(); - tWR = tCK * mMemspecJson["memtimingspec"].toObject()["WR"].toInt(); - tWTR = tCK * mMemspecJson["memtimingspec"].toObject()["WTR"].toInt(); - tPPD = tCK * mMemspecJson["memtimingspec"].toObject()["PPD"].toInt(); - tWPRE = tCK * mMemspecJson["memtimingspec"].toObject()["WPRE"].toInt(); - tRPST = tCK * mMemspecJson["memtimingspec"].toObject()["RPST"].toInt(); - tDQSCK = tCK * mMemspecJson["memtimingspec"].toObject()["DQSCK"].toInt(); - tDQSS = tCK * mMemspecJson["memtimingspec"].toObject()["DQSS"].toInt(); - tDQS2DQ = tCK * mMemspecJson["memtimingspec"].toObject()["DQS2DQ"].toInt(); - tRL = tCK * mMemspecJson["memtimingspec"].toObject()["RL"].toInt(); - tWL = tCK * mMemspecJson["memtimingspec"].toObject()["WL"].toInt(); - tRFCab = tCK * mMemspecJson["memtimingspec"].toObject()["RFCab"].toInt(); - tRFCpb = tCK * mMemspecJson["memtimingspec"].toObject()["RFCpb"].toInt(); - tESCKE = tCK * mMemspecJson["memtimingspec"].toObject()["ESCKE"].toInt(); - tSR = tCK * mMemspecJson["memtimingspec"].toObject()["SR"].toInt(); - tXSR = tCK * mMemspecJson["memtimingspec"].toObject()["XSR"].toInt(); - tXP = tCK * mMemspecJson["memtimingspec"].toObject()["XP"].toInt(); - tCKE = tCK * mMemspecJson["memtimingspec"].toObject()["CKE"].toInt(); - tCMDCKE = tCK * mMemspecJson["memtimingspec"].toObject()["CMDCKE"].toInt(); - tRTRS = tCK * mMemspecJson["memtimingspec"].toObject()["RTRS"].toInt(); + tRRD = tCK * mMemspecJson["memtimingspec"].toObject()["RRD"].toInt(); + tRCD = tCK * mMemspecJson["memtimingspec"].toObject()["RCD"].toInt(); + tRAS = tCK * mMemspecJson["memtimingspec"].toObject()["RAS"].toInt(); + tFAW = tCK * mMemspecJson["memtimingspec"].toObject()["FAW"].toInt(); + tRPpb = tCK * mMemspecJson["memtimingspec"].toObject()["RPpb"].toInt(); + tRPab = tCK * mMemspecJson["memtimingspec"].toObject()["RPab"].toInt(); + tRCpb = tCK * mMemspecJson["memtimingspec"].toObject()["RCpb"].toInt(); + tRCab = tCK * mMemspecJson["memtimingspec"].toObject()["RCab"].toInt(); + tCCD = tCK * mMemspecJson["memtimingspec"].toObject()["CCD"].toInt(); + tRTP = tCK * mMemspecJson["memtimingspec"].toObject()["RTP"].toInt(); + tWR = tCK * mMemspecJson["memtimingspec"].toObject()["WR"].toInt(); + tWTR = tCK * mMemspecJson["memtimingspec"].toObject()["WTR"].toInt(); + tPPD = tCK * mMemspecJson["memtimingspec"].toObject()["PPD"].toInt(); + tWPRE = tCK * mMemspecJson["memtimingspec"].toObject()["WPRE"].toInt(); + tRPST = tCK * mMemspecJson["memtimingspec"].toObject()["RPST"].toInt(); + tDQSCK = tCK * mMemspecJson["memtimingspec"].toObject()["DQSCK"].toInt(); + tDQSS = tCK * mMemspecJson["memtimingspec"].toObject()["DQSS"].toInt(); + tDQS2DQ = tCK * mMemspecJson["memtimingspec"].toObject()["DQS2DQ"].toInt(); + tRL = tCK * mMemspecJson["memtimingspec"].toObject()["RL"].toInt(); + tWL = tCK * mMemspecJson["memtimingspec"].toObject()["WL"].toInt(); + tRFCab = tCK * mMemspecJson["memtimingspec"].toObject()["RFCab"].toInt(); + tRFCpb = tCK * mMemspecJson["memtimingspec"].toObject()["RFCpb"].toInt(); + tESCKE = tCK * mMemspecJson["memtimingspec"].toObject()["ESCKE"].toInt(); + tSR = tCK * mMemspecJson["memtimingspec"].toObject()["SR"].toInt(); + tXSR = tCK * mMemspecJson["memtimingspec"].toObject()["XSR"].toInt(); + tXP = tCK * mMemspecJson["memtimingspec"].toObject()["XP"].toInt(); + tCKE = tCK * mMemspecJson["memtimingspec"].toObject()["CKE"].toInt(); + tCMDCKE = tCK * mMemspecJson["memtimingspec"].toObject()["CMDCKE"].toInt(); + tRTRS = tCK * mMemspecJson["memtimingspec"].toObject()["RTRS"].toInt(); - tBURST = (uint) (burstLength / (float) dataRate) * tCK; - tRDWR = tRL + tDQSCK + tBURST - tWL + tWPRE + tRPST; - tRDWR_R = tRL + tBURST + tRTRS - tWL; - tWRRD = tWL + tCK + tBURST + tWTR; - tWRRD_R = tWL + tBURST + tRTRS - tRL; - tRDPRE = tRTP + tBURST - 6 * tCK; - tRDAACT = tRTP + tRPpb + tBURST - 8 * tCK; - tWRPRE = 2 * tCK + tWL + tCK + tBURST + tWR; - tWRAACT = tWL + tBURST + tWR + tCK + tRPpb; - tACTPDEN = 3 * tCK + tCMDCKE; - tPRPDEN = tCK + tCMDCKE; - tRDPDEN = 3 * tCK + tRL + tDQSCK + tBURST + tRPST; - tWRPDEN = 3 * tCK + tWL + (ceil((uint) (tDQSS / (float) tCK)) + ceil((uint) (tDQS2DQ / (float) tCK))) * tCK + tBURST + tWR; - tWRAPDEN = 3 * tCK + tWL + (ceil((uint) (tDQSS / (float) tCK)) + ceil((uint) (tDQS2DQ / (float) tCK))) * tCK + tBURST + tWR + 2 * tCK; - tREFPDEN = tCK + tCMDCKE; - tSREFPDEN = tCK + tESCKE; + tBURST = (uint)(burstLength / (float)dataRate) * tCK; + tRDWR = tRL + tDQSCK + tBURST - tWL + tWPRE + tRPST; + tRDWR_R = tRL + tBURST + tRTRS - tWL; + tWRRD = tWL + tCK + tBURST + tWTR; + tWRRD_R = tWL + tBURST + tRTRS - tRL; + tRDPRE = tRTP + tBURST - 6 * tCK; + tRDAACT = tRTP + tRPpb + tBURST - 8 * tCK; + tWRPRE = 2 * tCK + tWL + tCK + tBURST + tWR; + tWRAACT = tWL + tBURST + tWR + tCK + tRPpb; + tACTPDEN = 3 * tCK + tCMDCKE; + tPRPDEN = tCK + tCMDCKE; + tRDPDEN = 3 * tCK + tRL + tDQSCK + tBURST + tRPST; + tWRPDEN = 3 * tCK + tWL + + (ceil((uint)(tDQSS / (float)tCK)) + ceil((uint)(tDQS2DQ / (float)tCK))) * tCK + + tBURST + tWR; + tWRAPDEN = 3 * tCK + tWL + + (ceil((uint)(tDQSS / (float)tCK)) + ceil((uint)(tDQS2DQ / (float)tCK))) * tCK + + tBURST + tWR + 2 * tCK; + tREFPDEN = tCK + tCMDCKE; + tSREFPDEN = tCK + tESCKE; - mPools.insert({ - "CMD_BUS", { - 1, { - {"ACT", 4 * tCK}, - {"RD", 4 * tCK}, - {"WR", 4 * tCK}, - {"RDA", 4 * tCK}, - {"WRA", 4 * tCK}, - {"PREPB", 2 * tCK}, - {"PREAB", 2 * tCK}, - {"REFAB", 2 * tCK}, - {"SREFEN", 2 * tCK}, - {"SREFEX", 2 * tCK}, - {"REFPB", 2 * tCK}, - } - } - }); - - mPools.insert({ - "NAW", { - 4, { - {"ACT", tFAW}, - {"REFPB", tFAW}, - } - } - }); + mPools.insert({"CMD_BUS", + {1, + { + {"ACT", 4 * tCK}, + {"RD", 4 * tCK}, + {"WR", 4 * tCK}, + {"RDA", 4 * tCK}, + {"WRA", 4 * tCK}, + {"PREPB", 2 * tCK}, + {"PREAB", 2 * tCK}, + {"REFAB", 2 * tCK}, + {"SREFEN", 2 * tCK}, + {"SREFEX", 2 * tCK}, + {"REFPB", 2 * tCK}, + }}}); + mPools.insert({"NAW", + {4, + { + {"ACT", tFAW}, + {"REFPB", tFAW}, + }}}); } -const std::vector TimeDependenciesInfoLPDDR4::getPossiblePhases() { - return { - "ACT", - "RD", - "WR", - "PREPB", - "RDA", - "WRA", - "REFPB", - "REFAB", - "PREAB", - "PDEP", - "PDXP", - "SREFEN", - "SREFEX", - "PDEA", - "PDXA", - "SRPDEN", - "SRPDEX", - }; +const std::vector TimeDependenciesInfoLPDDR4::getPossiblePhases() +{ + return { + "ACT", + "RD", + "WR", + "PREPB", + "RDA", + "WRA", + "REFPB", + "REFAB", + "PREAB", + "PDEP", + "PDXP", + "SREFEN", + "SREFEX", + "PDEA", + "PDXA", + "SRPDEN", + "SRPDEX", + }; } -DependencyMap TimeDependenciesInfoLPDDR4::mSpecializedGetDependencies() const { - DependencyMap dmap; +DependencyMap TimeDependenciesInfoLPDDR4::mSpecializedGetDependencies() const +{ + DependencyMap dmap; - dmap.emplace( - piecewise_construct, - forward_as_tuple("ACT"), - forward_as_tuple( - initializer_list{ - {tRCpb, "ACT", DependencyType::IntraBank, "tRCpb"}, - {tRRD, "ACT", DependencyType::IntraRank, "tRRD"}, - {tRDAACT, "RDA", DependencyType::IntraBank, "tRDAACT"}, - {tWRAACT, "WRA", DependencyType::IntraBank, "tWRAACT"}, - {tRPpb - 2 * tCK, "PREPB", DependencyType::IntraBank, "tRPpb - 2 * tCK"}, - {tRPab - 2 * tCK, "PREAB", DependencyType::IntraRank, "tRPab - 2 * tCK"}, - {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, - {tXP, "PDXP", DependencyType::IntraRank, "tXP"}, - {tRFCab - 2 * tCK, "REFAB", DependencyType::IntraRank, "tRFCab - 2 * tCK"}, - {tRFCpb - 2 * tCK, "REFPB", DependencyType::IntraBank, "tRFCpb - 2 * tCK"}, - {tRRD - 2 * tCK, "REFPB", DependencyType::IntraRank, "tRRD - 2 * tCK"}, - {tXSR - 2 * tCK, "SREFEX", DependencyType::IntraRank, "tXSR - 2 * tCK"}, - {4 * tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, - {tFAW, "NAW", DependencyType::IntraRank, "tFAW"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("ACT"), + forward_as_tuple(initializer_list{ + {tRCpb, "ACT", DependencyType::IntraBank, "tRCpb"}, + {tRRD, "ACT", DependencyType::IntraRank, "tRRD"}, + {tRDAACT, "RDA", DependencyType::IntraBank, "tRDAACT"}, + {tWRAACT, "WRA", DependencyType::IntraBank, "tWRAACT"}, + {tRPpb - 2 * tCK, "PREPB", DependencyType::IntraBank, "tRPpb - 2 * tCK"}, + {tRPab - 2 * tCK, "PREAB", DependencyType::IntraRank, "tRPab - 2 * tCK"}, + {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, + {tXP, "PDXP", DependencyType::IntraRank, "tXP"}, + {tRFCab - 2 * tCK, "REFAB", DependencyType::IntraRank, "tRFCab - 2 * tCK"}, + {tRFCpb - 2 * tCK, "REFPB", DependencyType::IntraBank, "tRFCpb - 2 * tCK"}, + {tRRD - 2 * tCK, "REFPB", DependencyType::IntraRank, "tRRD - 2 * tCK"}, + {tXSR - 2 * tCK, "SREFEX", DependencyType::IntraRank, "tXSR - 2 * tCK"}, + {4 * tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, + {tFAW, "NAW", DependencyType::IntraRank, "tFAW"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("RD"), - forward_as_tuple( - initializer_list{ - {tRCD, "ACT", DependencyType::IntraBank, "tRCD"}, - {tCCD, "RD", DependencyType::IntraBank, "tCCD"}, // - {tCCD, "RD", DependencyType::IntraRank, "tCCD"}, - {tBURST + tRTRS, "RD", DependencyType::InterRank, "tBURST + tRTRS"}, - {tCCD, "RDA", DependencyType::IntraRank, "tCCD"}, - {tBURST + tRTRS, "RDA", DependencyType::InterRank, "tBURST + tRTRS"}, - {tWRRD, "WR", DependencyType::IntraBank, "tWRRD"}, - {tWRRD, "WR", DependencyType::IntraRank, "tWRRD"}, - {tWRRD_R, "WR", DependencyType::InterRank, "tWRRD_R"}, - {tWRRD, "WRA", DependencyType::IntraRank, "tWRRD"}, - {tWRRD_R, "WRA", DependencyType::InterRank, "tWRRD_R"}, - {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, - {4 * tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("RD"), + forward_as_tuple(initializer_list{ + {tRCD, "ACT", DependencyType::IntraBank, "tRCD"}, + {tCCD, "RD", DependencyType::IntraBank, "tCCD"}, // + {tCCD, "RD", DependencyType::IntraRank, "tCCD"}, + {tBURST + tRTRS, "RD", DependencyType::InterRank, "tBURST + tRTRS"}, + {tCCD, "RDA", DependencyType::IntraRank, "tCCD"}, + {tBURST + tRTRS, "RDA", DependencyType::InterRank, "tBURST + tRTRS"}, + {tWRRD, "WR", DependencyType::IntraBank, "tWRRD"}, + {tWRRD, "WR", DependencyType::IntraRank, "tWRRD"}, + {tWRRD_R, "WR", DependencyType::InterRank, "tWRRD_R"}, + {tWRRD, "WRA", DependencyType::IntraRank, "tWRRD"}, + {tWRRD_R, "WRA", DependencyType::InterRank, "tWRRD_R"}, + {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, + {4 * tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("WR"), - forward_as_tuple( - initializer_list{ - {tRCD, "ACT", DependencyType::IntraBank, "tRCD"}, - {tRDWR, "RD", DependencyType::IntraBank, "tRDWR"}, // - {tRDWR, "RD", DependencyType::IntraRank, "tRDWR"}, - {tRDWR_R, "RD", DependencyType::InterRank, "tRDWR_R"}, - {tRDWR, "RDA", DependencyType::IntraRank, "tRDWR"}, - {tRDWR_R, "RDA", DependencyType::InterRank, "tRDWR_R"}, - {tCCD, "WR", DependencyType::IntraBank, "tCCD"}, - {tCCD, "WR", DependencyType::IntraRank, "tCCD"}, - {tBURST + tRTRS, "WR", DependencyType::InterRank, "tBURST + tRTRS"}, - {tCCD, "WRA", DependencyType::IntraRank, "tCCD"}, - {tBURST + tRTRS, "WRA", DependencyType::InterRank, "tBURST + tRTRS"}, - {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, - {4 * tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("WR"), + forward_as_tuple(initializer_list{ + {tRCD, "ACT", DependencyType::IntraBank, "tRCD"}, + {tRDWR, "RD", DependencyType::IntraBank, "tRDWR"}, // + {tRDWR, "RD", DependencyType::IntraRank, "tRDWR"}, + {tRDWR_R, "RD", DependencyType::InterRank, "tRDWR_R"}, + {tRDWR, "RDA", DependencyType::IntraRank, "tRDWR"}, + {tRDWR_R, "RDA", DependencyType::InterRank, "tRDWR_R"}, + {tCCD, "WR", DependencyType::IntraBank, "tCCD"}, + {tCCD, "WR", DependencyType::IntraRank, "tCCD"}, + {tBURST + tRTRS, "WR", DependencyType::InterRank, "tBURST + tRTRS"}, + {tCCD, "WRA", DependencyType::IntraRank, "tCCD"}, + {tBURST + tRTRS, "WRA", DependencyType::InterRank, "tBURST + tRTRS"}, + {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, + {4 * tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("PREPB"), - forward_as_tuple( - initializer_list{ - {tRAS + 2 * tCK, "ACT", DependencyType::IntraBank, "tRAS + 2 * tCK"}, - {tRDPRE, "RD", DependencyType::IntraBank, "tRDPRE"}, - {tWRPRE, "WR", DependencyType::IntraBank, "tWRPRE"}, - {tPPD, "PREPB", DependencyType::IntraRank, "tPPD"}, - {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, - {2 * tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("PREPB"), + forward_as_tuple(initializer_list{ + {tRAS + 2 * tCK, "ACT", DependencyType::IntraBank, "tRAS + 2 * tCK"}, + {tRDPRE, "RD", DependencyType::IntraBank, "tRDPRE"}, + {tWRPRE, "WR", DependencyType::IntraBank, "tWRPRE"}, + {tPPD, "PREPB", DependencyType::IntraRank, "tPPD"}, + {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, + {2 * tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("RDA"), - forward_as_tuple( - initializer_list{ - {tRCD, "ACT", DependencyType::IntraBank, "tRCD"}, - {tCCD, "RD", DependencyType::IntraBank, "tCCD"}, - {tCCD, "RD", DependencyType::IntraRank, "tCCD"}, - {tBURST + tRTRS, "RD", DependencyType::InterRank, "tBURST + tRTRS"}, - {tCCD, "RDA", DependencyType::IntraRank, "tCCD"}, - {tBURST + tRTRS, "RDA", DependencyType::InterRank, "tBURST + tRTRS"}, - {max({tWRRD, tWRPRE - tRDPRE}), "WR", DependencyType::IntraBank, "max(tWRRD, tWRPRE - tRDPRE)"}, - {tWRRD, "WR", DependencyType::IntraRank, "tWRRD"}, - {tWRRD_R, "WR", DependencyType::InterRank, "tWRRD_R"}, - {tWRRD, "WRA", DependencyType::IntraRank, "tWRRD"}, - {tWRRD_R, "WRA", DependencyType::InterRank, "tWRRD_R"}, - {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, - {4 * tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("RDA"), + forward_as_tuple(initializer_list{ + {tRCD, "ACT", DependencyType::IntraBank, "tRCD"}, + {tCCD, "RD", DependencyType::IntraBank, "tCCD"}, + {tCCD, "RD", DependencyType::IntraRank, "tCCD"}, + {tBURST + tRTRS, "RD", DependencyType::InterRank, "tBURST + tRTRS"}, + {tCCD, "RDA", DependencyType::IntraRank, "tCCD"}, + {tBURST + tRTRS, "RDA", DependencyType::InterRank, "tBURST + tRTRS"}, + {max({tWRRD, tWRPRE - tRDPRE}), + "WR", + DependencyType::IntraBank, + "max(tWRRD, tWRPRE - tRDPRE)"}, + {tWRRD, "WR", DependencyType::IntraRank, "tWRRD"}, + {tWRRD_R, "WR", DependencyType::InterRank, "tWRRD_R"}, + {tWRRD, "WRA", DependencyType::IntraRank, "tWRRD"}, + {tWRRD_R, "WRA", DependencyType::InterRank, "tWRRD_R"}, + {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, + {4 * tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("WRA"), - forward_as_tuple( - initializer_list{ - {tRCD, "ACT", DependencyType::IntraBank, "tRCD"}, - {tRDWR, "RD", DependencyType::IntraBank, "tRDWR"}, - {tRDWR, "RD", DependencyType::IntraRank, "tRDWR"}, - {tRDWR_R, "RD", DependencyType::InterRank, "tRDWR_R"}, - {tRDWR, "RDA", DependencyType::IntraRank, "tRDWR"}, - {tRDWR_R, "RDA", DependencyType::InterRank, "tRDWR_R"}, - {tCCD, "WR", DependencyType::IntraBank, "tCCD"}, - {tCCD, "WR", DependencyType::IntraRank, "tCCD"}, - {tBURST + tRTRS, "WR", DependencyType::InterRank, "tBURST + tRTRS"}, - {tCCD, "WRA", DependencyType::IntraRank, "tCCD"}, - {tBURST + tRTRS, "WRA", DependencyType::InterRank, "tBURST + tRTRS"}, - {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, - {4 * tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("WRA"), + forward_as_tuple(initializer_list{ + {tRCD, "ACT", DependencyType::IntraBank, "tRCD"}, + {tRDWR, "RD", DependencyType::IntraBank, "tRDWR"}, + {tRDWR, "RD", DependencyType::IntraRank, "tRDWR"}, + {tRDWR_R, "RD", DependencyType::InterRank, "tRDWR_R"}, + {tRDWR, "RDA", DependencyType::IntraRank, "tRDWR"}, + {tRDWR_R, "RDA", DependencyType::InterRank, "tRDWR_R"}, + {tCCD, "WR", DependencyType::IntraBank, "tCCD"}, + {tCCD, "WR", DependencyType::IntraRank, "tCCD"}, + {tBURST + tRTRS, "WR", DependencyType::InterRank, "tBURST + tRTRS"}, + {tCCD, "WRA", DependencyType::IntraRank, "tCCD"}, + {tBURST + tRTRS, "WRA", DependencyType::InterRank, "tBURST + tRTRS"}, + {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, + {4 * tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("REFPB"), - forward_as_tuple( - initializer_list{ - {tRCpb + 2 * tCK, "ACT", DependencyType::IntraBank, "tRCpb + 2 * tCK"}, - {tRRD + 2 * tCK, "ACT", DependencyType::IntraRank, "tRRD + 2 * tCK"}, - {tRDPRE + tRPpb, "RDA", DependencyType::IntraBank, "tRDPRE + tRPpb"}, - {tWRPRE + tRPpb, "WRA", DependencyType::IntraBank, "tWRPRE + tRPpb"}, - {tRPpb, "PREPB", DependencyType::IntraBank, "tRPpb"}, - {tRPab, "PREAB", DependencyType::IntraRank, "tRPab"}, - {tXP, "PDXP", DependencyType::IntraRank, "tXP"}, - {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, - {tRFCab, "REFAB", DependencyType::IntraRank, "tRFCab"}, - {tRFCpb, "REFPB", DependencyType::IntraBank, "tRFCpb"}, // - {tRFCpb, "REFPB", DependencyType::IntraRank, "tRFCpb"}, - {tXSR, "SREFEX", DependencyType::IntraRank, "tXSR"}, - {2 * tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, - {tFAW, "NAW", DependencyType::IntraRank, "tFAW"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("REFPB"), + forward_as_tuple(initializer_list{ + {tRCpb + 2 * tCK, "ACT", DependencyType::IntraBank, "tRCpb + 2 * tCK"}, + {tRRD + 2 * tCK, "ACT", DependencyType::IntraRank, "tRRD + 2 * tCK"}, + {tRDPRE + tRPpb, "RDA", DependencyType::IntraBank, "tRDPRE + tRPpb"}, + {tWRPRE + tRPpb, "WRA", DependencyType::IntraBank, "tWRPRE + tRPpb"}, + {tRPpb, "PREPB", DependencyType::IntraBank, "tRPpb"}, + {tRPab, "PREAB", DependencyType::IntraRank, "tRPab"}, + {tXP, "PDXP", DependencyType::IntraRank, "tXP"}, + {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, + {tRFCab, "REFAB", DependencyType::IntraRank, "tRFCab"}, + {tRFCpb, "REFPB", DependencyType::IntraBank, "tRFCpb"}, // + {tRFCpb, "REFPB", DependencyType::IntraRank, "tRFCpb"}, + {tXSR, "SREFEX", DependencyType::IntraRank, "tXSR"}, + {2 * tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, + {tFAW, "NAW", DependencyType::IntraRank, "tFAW"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("REFAB"), - forward_as_tuple( - initializer_list{ - {tRCpb + 2 * tCK, "ACT", DependencyType::IntraRank, "tRCpb + 2 * tCK"}, - {tRDPRE + tRPpb, "RDA", DependencyType::IntraRank, "tRDPRE + tRPpb"}, - {tWRPRE + tRPpb, "WRA", DependencyType::IntraRank, "tWRPRE + tRPpb"}, - {tRPpb, "PREPB", DependencyType::IntraRank, "tRPpb"}, - {tRPab, "PREAB", DependencyType::IntraRank, "tRPab"}, - {tXP, "PDXP", DependencyType::IntraRank, "tXP"}, - {tRFCab, "REFAB", DependencyType::IntraRank, "tRFCab"}, - {tRFCpb, "REFPB", DependencyType::IntraRank, "tRFCpb"}, - {tXSR, "SREFEX", DependencyType::IntraRank, "tXSR"}, - {2 * tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("REFAB"), + forward_as_tuple(initializer_list{ + {tRCpb + 2 * tCK, "ACT", DependencyType::IntraRank, "tRCpb + 2 * tCK"}, + {tRDPRE + tRPpb, "RDA", DependencyType::IntraRank, "tRDPRE + tRPpb"}, + {tWRPRE + tRPpb, "WRA", DependencyType::IntraRank, "tWRPRE + tRPpb"}, + {tRPpb, "PREPB", DependencyType::IntraRank, "tRPpb"}, + {tRPab, "PREAB", DependencyType::IntraRank, "tRPab"}, + {tXP, "PDXP", DependencyType::IntraRank, "tXP"}, + {tRFCab, "REFAB", DependencyType::IntraRank, "tRFCab"}, + {tRFCpb, "REFPB", DependencyType::IntraRank, "tRFCpb"}, + {tXSR, "SREFEX", DependencyType::IntraRank, "tXSR"}, + {2 * tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("PREAB"), - forward_as_tuple( - initializer_list{ - {tRAS + 2 * tCK, "ACT", DependencyType::IntraRank, "tRAS + 2 * tCK"}, - {tRDPRE, "RD", DependencyType::IntraRank, "tRDPRE"}, - {tRDPRE, "RDA", DependencyType::IntraRank, "tRDPRE"}, - {tWRPRE, "WR", DependencyType::IntraRank, "tWRPRE"}, - {tWRPRE, "WRA", DependencyType::IntraRank, "tWRPRE"}, - {tPPD, "PREPB", DependencyType::IntraRank, "tPPD"}, - {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, - {tRFCpb, "REFPB", DependencyType::IntraRank, "tRFCpb"}, - {2 * tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("PREAB"), + forward_as_tuple(initializer_list{ + {tRAS + 2 * tCK, "ACT", DependencyType::IntraRank, "tRAS + 2 * tCK"}, + {tRDPRE, "RD", DependencyType::IntraRank, "tRDPRE"}, + {tRDPRE, "RDA", DependencyType::IntraRank, "tRDPRE"}, + {tWRPRE, "WR", DependencyType::IntraRank, "tWRPRE"}, + {tWRPRE, "WRA", DependencyType::IntraRank, "tWRPRE"}, + {tPPD, "PREPB", DependencyType::IntraRank, "tPPD"}, + {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, + {tRFCpb, "REFPB", DependencyType::IntraRank, "tRFCpb"}, + {2 * tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("PDEP"), - forward_as_tuple( - initializer_list{ - {tRDPDEN, "RD", DependencyType::IntraRank, "tRDPDEN"}, - {tRDPDEN, "RDA", DependencyType::IntraRank, "tRDPDEN"}, - {tWRAPDEN, "WRA", DependencyType::IntraRank, "tWRAPDEN"}, - {tPRPDEN, "PREPB", DependencyType::IntraRank, "tPRPDEN"}, - {tPRPDEN, "PREAB", DependencyType::IntraRank, "tPRPDEN"}, - {tCKE, "PDXP", DependencyType::IntraRank, "tCKE"}, - {tREFPDEN, "REFAB", DependencyType::IntraRank, "tREFPDEN"}, - {tREFPDEN, "REFPB", DependencyType::IntraRank, "tREFPDEN"}, - {tXSR, "SREFEX", DependencyType::IntraRank, "tXSR"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("PDEP"), + forward_as_tuple(initializer_list{ + {tRDPDEN, "RD", DependencyType::IntraRank, "tRDPDEN"}, + {tRDPDEN, "RDA", DependencyType::IntraRank, "tRDPDEN"}, + {tWRAPDEN, "WRA", DependencyType::IntraRank, "tWRAPDEN"}, + {tPRPDEN, "PREPB", DependencyType::IntraRank, "tPRPDEN"}, + {tPRPDEN, "PREAB", DependencyType::IntraRank, "tPRPDEN"}, + {tCKE, "PDXP", DependencyType::IntraRank, "tCKE"}, + {tREFPDEN, "REFAB", DependencyType::IntraRank, "tREFPDEN"}, + {tREFPDEN, "REFPB", DependencyType::IntraRank, "tREFPDEN"}, + {tXSR, "SREFEX", DependencyType::IntraRank, "tXSR"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("PDXP"), - forward_as_tuple( - initializer_list{ - {tCKE, "PDEP", DependencyType::IntraRank, "tCKE"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("PDXP"), + forward_as_tuple(initializer_list{ + {tCKE, "PDEP", DependencyType::IntraRank, "tCKE"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("SREFEN"), - forward_as_tuple( - initializer_list{ - {tRCpb + 2 * tCK, "ACT", DependencyType::IntraRank, "tRCpb + 2 * tCK"}, - {max({tRDPDEN, tRDPRE + tRPpb}), "RDA", DependencyType::IntraRank, "max(tRDPDEN, tRDPRE + tRPpb)"}, - {max({tWRAPDEN, tWRPRE + tRPpb}), "WRA", DependencyType::IntraRank, "max(tWRAPDEN, tWRPRE + tRPpb)"}, - {tRPpb, "PREPB", DependencyType::IntraRank, "tRPpb"}, - {tRPab, "PREAB", DependencyType::IntraRank, "tRPab"}, - {tXP, "PDXP", DependencyType::IntraRank, "tXP"}, - {tRFCab, "REFAB", DependencyType::IntraRank, "tRFCab"}, - {tRFCpb, "REFPB", DependencyType::IntraRank, "tRFCpb"}, - {tXSR, "SREFEX", DependencyType::IntraRank, "tXSR"}, - {2 * tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("SREFEN"), + forward_as_tuple(initializer_list{ + {tRCpb + 2 * tCK, "ACT", DependencyType::IntraRank, "tRCpb + 2 * tCK"}, + {max({tRDPDEN, tRDPRE + tRPpb}), + "RDA", + DependencyType::IntraRank, + "max(tRDPDEN, tRDPRE + tRPpb)"}, + {max({tWRAPDEN, tWRPRE + tRPpb}), + "WRA", + DependencyType::IntraRank, + "max(tWRAPDEN, tWRPRE + tRPpb)"}, + {tRPpb, "PREPB", DependencyType::IntraRank, "tRPpb"}, + {tRPab, "PREAB", DependencyType::IntraRank, "tRPab"}, + {tXP, "PDXP", DependencyType::IntraRank, "tXP"}, + {tRFCab, "REFAB", DependencyType::IntraRank, "tRFCab"}, + {tRFCpb, "REFPB", DependencyType::IntraRank, "tRFCpb"}, + {tXSR, "SREFEX", DependencyType::IntraRank, "tXSR"}, + {2 * tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("SREFEX"), - forward_as_tuple( - initializer_list{ - {tSR, "SREFEN", DependencyType::IntraRank, "tSR"}, - {tXP, "SRPDEX", DependencyType::IntraRank, "tXP"}, // - {2 * tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("SREFEX"), + forward_as_tuple(initializer_list{ + {tSR, "SREFEN", DependencyType::IntraRank, "tSR"}, + {tXP, "SRPDEX", DependencyType::IntraRank, "tXP"}, // + {2 * tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("PDEA"), - forward_as_tuple( - initializer_list{ - {tACTPDEN, "ACT", DependencyType::IntraRank, "tACTPDEN"}, - {tRDPDEN, "RD", DependencyType::IntraRank, "tRDPDEN"}, - {tRDPDEN, "RDA", DependencyType::IntraRank, "tRDPDEN"}, - {tWRPDEN, "WR", DependencyType::IntraRank, "tWRPDEN"}, - {tWRAPDEN, "WRA", DependencyType::IntraRank, "tWRAPDEN"}, - {tPRPDEN, "PREPB", DependencyType::IntraRank, "tPRPDEN"}, - {tCKE, "PDXA", DependencyType::IntraRank, "tCKE"}, - {tREFPDEN, "REFPB", DependencyType::IntraRank, "tREFPDEN"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("PDEA"), + forward_as_tuple(initializer_list{ + {tACTPDEN, "ACT", DependencyType::IntraRank, "tACTPDEN"}, + {tRDPDEN, "RD", DependencyType::IntraRank, "tRDPDEN"}, + {tRDPDEN, "RDA", DependencyType::IntraRank, "tRDPDEN"}, + {tWRPDEN, "WR", DependencyType::IntraRank, "tWRPDEN"}, + {tWRAPDEN, "WRA", DependencyType::IntraRank, "tWRAPDEN"}, + {tPRPDEN, "PREPB", DependencyType::IntraRank, "tPRPDEN"}, + {tCKE, "PDXA", DependencyType::IntraRank, "tCKE"}, + {tREFPDEN, "REFPB", DependencyType::IntraRank, "tREFPDEN"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("PDXA"), - forward_as_tuple( - initializer_list{ - {tCKE, "PDEA", DependencyType::IntraRank, "tCKE"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("PDXA"), + forward_as_tuple(initializer_list{ + {tCKE, "PDEA", DependencyType::IntraRank, "tCKE"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("SRPDEN"), - forward_as_tuple( - initializer_list{ - {tSREFPDEN, "SREFEN", DependencyType::IntraRank, "tSREFPDEN"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("SRPDEN"), + forward_as_tuple(initializer_list{ + {tSREFPDEN, "SREFEN", DependencyType::IntraRank, "tSREFPDEN"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("SRPDEX"), - forward_as_tuple( - initializer_list{ - {tCKE, "SRPDEN", DependencyType::IntraRank, "tCKE"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("SRPDEX"), + forward_as_tuple(initializer_list{ + {tCKE, "SRPDEN", DependencyType::IntraRank, "tCKE"}, + })); - return dmap; + return dmap; } diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR4.h b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR4.h index b8b6d653..13b126c2 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR4.h +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR4.h @@ -37,17 +37,18 @@ #include "../dramtimedependenciesbase.h" -class TimeDependenciesInfoLPDDR4 final : public DRAMTimeDependenciesBase { - public: +class TimeDependenciesInfoLPDDR4 final : public DRAMTimeDependenciesBase +{ +public: TimeDependenciesInfoLPDDR4(const QJsonObject& memspec, const uint clk); static const std::vector getPossiblePhases(); - protected: +protected: void mInitializeValues() override; DependencyMap mSpecializedGetDependencies() const override; - protected: +protected: uint burstLength; uint dataRate; @@ -97,5 +98,4 @@ class TimeDependenciesInfoLPDDR4 final : public DRAMTimeDependenciesBase { uint tWRAPDEN; uint tREFPDEN; uint tSREFPDEN; - }; diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR5.cpp b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR5.cpp index ead9d71d..37903d07 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR5.cpp +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR5.cpp @@ -37,369 +37,639 @@ using namespace std; -TimeDependenciesInfoLPDDR5::TimeDependenciesInfoLPDDR5(const QJsonObject& memspec, const uint tCK) : DRAMTimeDependenciesBase(memspec, tCK) { - mInitializeValues(); +TimeDependenciesInfoLPDDR5::TimeDependenciesInfoLPDDR5(const QJsonObject& memspec, const uint tCK) : + DRAMTimeDependenciesBase(memspec, tCK) +{ + mInitializeValues(); } -void TimeDependenciesInfoLPDDR5::mInitializeValues() { - burstLength = mMemspecJson["memarchitecturespec"].toObject()["burstLength"].toInt(); - dataRate = mMemspecJson["memarchitecturespec"].toObject()["dataRate"].toInt(); - per2BankOffset = mMemspecJson["memarchitecturespec"].toObject()["per2BankOffset"].toInt(); +void TimeDependenciesInfoLPDDR5::mInitializeValues() +{ + burstLength = mMemspecJson["memarchitecturespec"].toObject()["burstLength"].toInt(); + dataRate = mMemspecJson["memarchitecturespec"].toObject()["dataRate"].toInt(); + per2BankOffset = mMemspecJson["memarchitecturespec"].toObject()["per2BankOffset"].toInt(); - tRCD = tCK * mMemspecJson["memtimingspec"].toObject()["RCD"].toInt(); - tRPpb = tCK * mMemspecJson["memtimingspec"].toObject()["RPpb"].toInt(); - tRPab = tCK * mMemspecJson["memtimingspec"].toObject()["RPab"].toInt(); - tRAS = tCK * mMemspecJson["memtimingspec"].toObject()["RAS"].toInt(); - tRCpb = tCK * mMemspecJson["memtimingspec"].toObject()["RCpb"].toInt(); - tRCab = tCK * mMemspecJson["memtimingspec"].toObject()["RCab"].toInt(); - tCL = tCK * mMemspecJson["memtimingspec"].toObject()["CL"].toInt(); - tCWL = tCK * mMemspecJson["memtimingspec"].toObject()["CWL"].toInt(); - tAL = tCK * mMemspecJson["memtimingspec"].toObject()["AL"].toInt(); - tRL = tCK * mMemspecJson["memtimingspec"].toObject()["RL"].toInt(); - tRPRE = tCK * mMemspecJson["memtimingspec"].toObject()["RPRE"].toInt(); - tWPRE = tCK * mMemspecJson["memtimingspec"].toObject()["WPRE"].toInt(); - tWL = tCK * mMemspecJson["memtimingspec"].toObject()["WL"].toInt(); - tCCD_S = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_S"].toInt(); - tCCD_L = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_L"].toInt(); - tRRD = tCK * mMemspecJson["memtimingspec"].toObject()["RRD"].toInt(); - tFAW = tCK * mMemspecJson["memtimingspec"].toObject()["FAW"].toInt(); - tWTR_S = tCK * mMemspecJson["memtimingspec"].toObject()["WTR_S"].toInt(); - tWTR_L = tCK * mMemspecJson["memtimingspec"].toObject()["WTR_L"].toInt(); - tRTP = tCK * mMemspecJson["memtimingspec"].toObject()["RTP"].toInt(); - tWR = tCK * mMemspecJson["memtimingspec"].toObject()["WR"].toInt(); - tRFCab = tCK * mMemspecJson["memtimingspec"].toObject()["RFCab"].toInt(); - tRFCpb = tCK * mMemspecJson["memtimingspec"].toObject()["RFCpb"].toInt(); - tXS = tCK * mMemspecJson["memtimingspec"].toObject()["XS"].toInt(); - tXSDLL = tCK * mMemspecJson["memtimingspec"].toObject()["XSDLL"].toInt(); - tXP = tCK * mMemspecJson["memtimingspec"].toObject()["XP"].toInt(); - tCKE = tCK * mMemspecJson["memtimingspec"].toObject()["CKE"].toInt(); - tCKESR = tCK * mMemspecJson["memtimingspec"].toObject()["CKESR"].toInt(); - tPD = tCK * mMemspecJson["memtimingspec"].toObject()["PD"].toInt(); - tPRPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["PRPDEN"].toInt(); - tREFPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["REFPDEN"].toInt(); - tRTRS = tCK * mMemspecJson["memtimingspec"].toObject()["RTRS"].toInt(); - tRBTP = tCK * mMemspecJson["memtimingspec"].toObject()["RBTP"].toInt(); - BL_n_min_16 = tCK * mMemspecJson["memtimingspec"].toObject()["BL_n_min_16"].toInt(); - BL_n_min_32 = tCK * mMemspecJson["memtimingspec"].toObject()["BL_n_min_32"].toInt(); - BL_n_max_16 = tCK * mMemspecJson["memtimingspec"].toObject()["BL_n_max_16"].toInt(); - BL_n_max_32 = tCK * mMemspecJson["memtimingspec"].toObject()["BL_n_max_32"].toInt(); - BL_n_S_16 = tCK * mMemspecJson["memtimingspec"].toObject()["BL_n_S_16"].toInt(); - BL_n_S_32 = tCK * mMemspecJson["memtimingspec"].toObject()["BL_n_S_32"].toInt(); - BL_n_L_16 = tCK * mMemspecJson["memtimingspec"].toObject()["BL_n_L_16"].toInt(); - BL_n_L_32 = tCK * mMemspecJson["memtimingspec"].toObject()["BL_n_L_32"].toInt(); - tWCK2DQO = tCK * mMemspecJson["memtimingspec"].toObject()["WCK2DQO"].toInt(); - tPPD = tCK * mMemspecJson["memtimingspec"].toObject()["PPD"].toInt(); - tpbR2act = tCK * mMemspecJson["memtimingspec"].toObject()["pbR2act"].toInt(); - tpbR2pbR = tCK * mMemspecJson["memtimingspec"].toObject()["pbR2pbR"].toInt(); + tRCD = tCK * mMemspecJson["memtimingspec"].toObject()["RCD"].toInt(); + tRPpb = tCK * mMemspecJson["memtimingspec"].toObject()["RPpb"].toInt(); + tRPab = tCK * mMemspecJson["memtimingspec"].toObject()["RPab"].toInt(); + tRAS = tCK * mMemspecJson["memtimingspec"].toObject()["RAS"].toInt(); + tRCpb = tCK * mMemspecJson["memtimingspec"].toObject()["RCpb"].toInt(); + tRCab = tCK * mMemspecJson["memtimingspec"].toObject()["RCab"].toInt(); + tCL = tCK * mMemspecJson["memtimingspec"].toObject()["CL"].toInt(); + tCWL = tCK * mMemspecJson["memtimingspec"].toObject()["CWL"].toInt(); + tAL = tCK * mMemspecJson["memtimingspec"].toObject()["AL"].toInt(); + tRL = tCK * mMemspecJson["memtimingspec"].toObject()["RL"].toInt(); + tRPRE = tCK * mMemspecJson["memtimingspec"].toObject()["RPRE"].toInt(); + tWPRE = tCK * mMemspecJson["memtimingspec"].toObject()["WPRE"].toInt(); + tWL = tCK * mMemspecJson["memtimingspec"].toObject()["WL"].toInt(); + tCCD_S = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_S"].toInt(); + tCCD_L = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_L"].toInt(); + tRRD = tCK * mMemspecJson["memtimingspec"].toObject()["RRD"].toInt(); + tFAW = tCK * mMemspecJson["memtimingspec"].toObject()["FAW"].toInt(); + tWTR_S = tCK * mMemspecJson["memtimingspec"].toObject()["WTR_S"].toInt(); + tWTR_L = tCK * mMemspecJson["memtimingspec"].toObject()["WTR_L"].toInt(); + tRTP = tCK * mMemspecJson["memtimingspec"].toObject()["RTP"].toInt(); + tWR = tCK * mMemspecJson["memtimingspec"].toObject()["WR"].toInt(); + tRFCab = tCK * mMemspecJson["memtimingspec"].toObject()["RFCab"].toInt(); + tRFCpb = tCK * mMemspecJson["memtimingspec"].toObject()["RFCpb"].toInt(); + tXS = tCK * mMemspecJson["memtimingspec"].toObject()["XS"].toInt(); + tXSDLL = tCK * mMemspecJson["memtimingspec"].toObject()["XSDLL"].toInt(); + tXP = tCK * mMemspecJson["memtimingspec"].toObject()["XP"].toInt(); + tCKE = tCK * mMemspecJson["memtimingspec"].toObject()["CKE"].toInt(); + tCKESR = tCK * mMemspecJson["memtimingspec"].toObject()["CKESR"].toInt(); + tPD = tCK * mMemspecJson["memtimingspec"].toObject()["PD"].toInt(); + tPRPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["PRPDEN"].toInt(); + tREFPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["REFPDEN"].toInt(); + tRTRS = tCK * mMemspecJson["memtimingspec"].toObject()["RTRS"].toInt(); + tRBTP = tCK * mMemspecJson["memtimingspec"].toObject()["RBTP"].toInt(); + BL_n_min_16 = tCK * mMemspecJson["memtimingspec"].toObject()["BL_n_min_16"].toInt(); + BL_n_min_32 = tCK * mMemspecJson["memtimingspec"].toObject()["BL_n_min_32"].toInt(); + BL_n_max_16 = tCK * mMemspecJson["memtimingspec"].toObject()["BL_n_max_16"].toInt(); + BL_n_max_32 = tCK * mMemspecJson["memtimingspec"].toObject()["BL_n_max_32"].toInt(); + BL_n_S_16 = tCK * mMemspecJson["memtimingspec"].toObject()["BL_n_S_16"].toInt(); + BL_n_S_32 = tCK * mMemspecJson["memtimingspec"].toObject()["BL_n_S_32"].toInt(); + BL_n_L_16 = tCK * mMemspecJson["memtimingspec"].toObject()["BL_n_L_16"].toInt(); + BL_n_L_32 = tCK * mMemspecJson["memtimingspec"].toObject()["BL_n_L_32"].toInt(); + tWCK2DQO = tCK * mMemspecJson["memtimingspec"].toObject()["WCK2DQO"].toInt(); + tPPD = tCK * mMemspecJson["memtimingspec"].toObject()["PPD"].toInt(); + tpbR2act = tCK * mMemspecJson["memtimingspec"].toObject()["pbR2act"].toInt(); + tpbR2pbR = tCK * mMemspecJson["memtimingspec"].toObject()["pbR2pbR"].toInt(); - tBURST16 = (uint) (16 / (float) dataRate) * tCK; - tBURST32 = (uint) (32 / (float) dataRate) * tCK; + tBURST16 = (uint)(16 / (float)dataRate) * tCK; + tBURST32 = (uint)(32 / (float)dataRate) * tCK; - mPools.insert({ - "CMD_BUS", { - 1, { - {"ACT", 2 * tCK}, - {"RD", tCK}, - {"WR", tCK}, - {"RDA", tCK}, - {"WRA", tCK}, - {"PREPB", tCK}, - {"PREAB", tCK}, - {"REFAB", tCK}, - {"REFPB", tCK}, - {"REFP2B", tCK}, - } - } - }); - - mPools.insert({ - "NAW", { - 4, { - {"ACT", tFAW}, - {"REFPB", tFAW}, - {"REFP2B", tFAW}, - } - } - }); + mPools.insert({"CMD_BUS", + {1, + { + {"ACT", 2 * tCK}, + {"RD", tCK}, + {"WR", tCK}, + {"RDA", tCK}, + {"WRA", tCK}, + {"PREPB", tCK}, + {"PREAB", tCK}, + {"REFAB", tCK}, + {"REFPB", tCK}, + {"REFP2B", tCK}, + }}}); + mPools.insert({"NAW", + {4, + { + {"ACT", tFAW}, + {"REFPB", tFAW}, + {"REFP2B", tFAW}, + }}}); } -const std::vector TimeDependenciesInfoLPDDR5::getPossiblePhases() { - return { - "ACT", - "RD", - "WR", - "PREPB", - "RDA", - "WRA", - "REFPB", - "REFP2B", - "REFAB", - "PREAB", - }; +const std::vector TimeDependenciesInfoLPDDR5::getPossiblePhases() +{ + return { + "ACT", + "RD", + "WR", + "PREPB", + "RDA", + "WRA", + "REFPB", + "REFP2B", + "REFAB", + "PREAB", + }; } -DependencyMap TimeDependenciesInfoLPDDR5::mSpecializedGetDependencies() const { - DependencyMap dmap; +DependencyMap TimeDependenciesInfoLPDDR5::mSpecializedGetDependencies() const +{ + DependencyMap dmap; - auto passBurstLength16 = std::make_shared( - [] PASSFUNCTIONDECL { - auto other = std::dynamic_pointer_cast(otherPhase); - if (!other) return false; - return other->tBurstLength == 16; - } - ); - auto passBurstLength32 = std::make_shared( - [] PASSFUNCTIONDECL { - auto other = std::dynamic_pointer_cast(otherPhase); - if (!other) return false; - return other->tBurstLength == 32; - } - ); + auto passBurstLength16 = std::make_shared( + [] PASSFUNCTIONDECL + { + auto other = std::dynamic_pointer_cast(otherPhase); + if (!other) + return false; + return other->tBurstLength == 16; + }); + auto passBurstLength32 = std::make_shared( + [] PASSFUNCTIONDECL + { + auto other = std::dynamic_pointer_cast(otherPhase); + if (!other) + return false; + return other->tBurstLength == 32; + }); - dmap.emplace( - piecewise_construct, - forward_as_tuple("ACT"), - forward_as_tuple( - initializer_list{ - {tRCpb, "ACT", DependencyType::IntraBank, "tRCpb"}, - {tRRD, "ACT", DependencyType::IntraRank, "tRRD"}, - {BL_n_min_16 + tRBTP + tRPpb - tCK, "RDA", DependencyType::IntraBank, "BL_n_min_16 + tRBTP + tRPpb - tCK", passBurstLength16}, - {BL_n_min_32 + tRBTP + tRPpb - tCK, "RDA", DependencyType::IntraBank, "BL_n_min_32 + tRBTP + tRPpb - tCK", passBurstLength32}, - {tWL + BL_n_min_16 + tCK + tWR + tRPpb - tCK, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_16 + tCK + tWR + tRPpb - tCK", passBurstLength16}, - {tWL + BL_n_min_32 + tCK + tWR + tRPpb - tCK, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_32 + tCK + tWR + tRPpb - tCK", passBurstLength32}, - {tRPpb - tCK, "PREPB", DependencyType::IntraBank, "tRPpb - tCK"}, - {tRPab - tCK, "PREAB", DependencyType::IntraRank, "tRPab - tCK"}, - {tRFCab - tCK, "REFAB", DependencyType::IntraRank, "tRFCab - tCK"}, - {tpbR2act - tCK, "REFPB", DependencyType::IntraRank, "tpbR2act - tCK"}, - {tpbR2act - tCK, "REFP2B", DependencyType::IntraRank, "tpbR2act - tCK"}, - {tRFCpb - tCK, "REFPB", DependencyType::IntraBank, "tRFCpb - tCK"}, - {tRFCpb - tCK, "REFP2B", DependencyType::IntraBank, "tRFCpb - tCK"}, - {0, "CMD_BUS", DependencyType::InterRank, "CMDBus"}, - {0, "NAW", DependencyType::IntraRank, "tFAW"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("ACT"), + forward_as_tuple(initializer_list{ + {tRCpb, "ACT", DependencyType::IntraBank, "tRCpb"}, + {tRRD, "ACT", DependencyType::IntraRank, "tRRD"}, + {BL_n_min_16 + tRBTP + tRPpb - tCK, + "RDA", + DependencyType::IntraBank, + "BL_n_min_16 + tRBTP + tRPpb - tCK", + passBurstLength16}, + {BL_n_min_32 + tRBTP + tRPpb - tCK, + "RDA", + DependencyType::IntraBank, + "BL_n_min_32 + tRBTP + tRPpb - tCK", + passBurstLength32}, + {tWL + BL_n_min_16 + tCK + tWR + tRPpb - tCK, + "WRA", + DependencyType::IntraBank, + "tWL + BL_n_min_16 + tCK + tWR + tRPpb - tCK", + passBurstLength16}, + {tWL + BL_n_min_32 + tCK + tWR + tRPpb - tCK, + "WRA", + DependencyType::IntraBank, + "tWL + BL_n_min_32 + tCK + tWR + tRPpb - tCK", + passBurstLength32}, + {tRPpb - tCK, "PREPB", DependencyType::IntraBank, "tRPpb - tCK"}, + {tRPab - tCK, "PREAB", DependencyType::IntraRank, "tRPab - tCK"}, + {tRFCab - tCK, "REFAB", DependencyType::IntraRank, "tRFCab - tCK"}, + {tpbR2act - tCK, "REFPB", DependencyType::IntraRank, "tpbR2act - tCK"}, + {tpbR2act - tCK, "REFP2B", DependencyType::IntraRank, "tpbR2act - tCK"}, + {tRFCpb - tCK, "REFPB", DependencyType::IntraBank, "tRFCpb - tCK"}, + {tRFCpb - tCK, "REFP2B", DependencyType::IntraBank, "tRFCpb - tCK"}, + {0, "CMD_BUS", DependencyType::InterRank, "CMDBus"}, + {0, "NAW", DependencyType::IntraRank, "tFAW"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("RD"), - forward_as_tuple( - initializer_list{ - {tRCD + tCK, "ACT", DependencyType::IntraBank, "tRCD + tCK"}, - {BL_n_L_16, "RD", DependencyType::IntraBankGroup, "BL_n_L_16", passBurstLength16}, - {BL_n_L_32, "RD", DependencyType::IntraBankGroup, "BL_n_L_32", passBurstLength32}, - {BL_n_S_16, "RD", DependencyType::IntraRank, "BL_n_S_16", passBurstLength16}, - {BL_n_S_32, "RD", DependencyType::IntraRank, "BL_n_S_32", passBurstLength32}, - {tBURST16 + tRTRS, "RD", DependencyType::InterRank, "tBURST16 + tRTRS", passBurstLength16}, - {tBURST32 + tRTRS, "RD", DependencyType::InterRank, "tBURST32 + tRTRS", passBurstLength32}, - {BL_n_L_16, "RDA", DependencyType::IntraBankGroup, "BL_n_L_16", passBurstLength16}, - {BL_n_L_32, "RDA", DependencyType::IntraBankGroup, "BL_n_L_32", passBurstLength32}, - {BL_n_S_16, "RDA", DependencyType::IntraRank, "BL_n_S_16", passBurstLength16}, - {BL_n_S_32, "RDA", DependencyType::IntraRank, "BL_n_S_32", passBurstLength32}, - {tBURST16 + tRTRS, "RDA", DependencyType::InterRank, "tBURST16 + tRTRS", passBurstLength16}, - {tBURST32 + tRTRS, "RDA", DependencyType::InterRank, "tBURST32 + tRTRS", passBurstLength32}, - {tWL + BL_n_max_16 + tWTR_L, "WR", DependencyType::IntraBankGroup, "tWL + BL_n_max_16 + tWTR_L", passBurstLength16}, - {tWL + BL_n_max_32 + tWTR_L, "WR", DependencyType::IntraBankGroup, "tWL + BL_n_max_32 + tWTR_L", passBurstLength32}, - {tWL + BL_n_min_16 + tWTR_S, "WR", DependencyType::IntraRank, "tWL + BL_n_min_16 + tWTR_S", passBurstLength16}, - {tWL + BL_n_min_32 + tWTR_S, "WR", DependencyType::IntraRank, "tWL + BL_n_min_32 + tWTR_S", passBurstLength32}, - {tWL + BL_n_max_16 + tWTR_L, "WRA", DependencyType::IntraBankGroup, "tWL + BL_n_max_16 + tWTR_L", passBurstLength16}, - {tWL + BL_n_max_32 + tWTR_L, "WRA", DependencyType::IntraBankGroup, "tWL + BL_n_max_32 + tWTR_L", passBurstLength32}, - {tWL + BL_n_min_16 + tWTR_S, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_16 + tWTR_S", passBurstLength16}, - {tWL + BL_n_min_32 + tWTR_S, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_32 + tWTR_S", passBurstLength32}, - {0, "CMD_BUS", DependencyType::InterRank, "CMDBus"}, - } - ) - ); + dmap.emplace( + piecewise_construct, + forward_as_tuple("RD"), + forward_as_tuple(initializer_list{ + {tRCD + tCK, "ACT", DependencyType::IntraBank, "tRCD + tCK"}, + {BL_n_L_16, "RD", DependencyType::IntraBankGroup, "BL_n_L_16", passBurstLength16}, + {BL_n_L_32, "RD", DependencyType::IntraBankGroup, "BL_n_L_32", passBurstLength32}, + {BL_n_S_16, "RD", DependencyType::IntraRank, "BL_n_S_16", passBurstLength16}, + {BL_n_S_32, "RD", DependencyType::IntraRank, "BL_n_S_32", passBurstLength32}, + {tBURST16 + tRTRS, + "RD", + DependencyType::InterRank, + "tBURST16 + tRTRS", + passBurstLength16}, + {tBURST32 + tRTRS, + "RD", + DependencyType::InterRank, + "tBURST32 + tRTRS", + passBurstLength32}, + {BL_n_L_16, "RDA", DependencyType::IntraBankGroup, "BL_n_L_16", passBurstLength16}, + {BL_n_L_32, "RDA", DependencyType::IntraBankGroup, "BL_n_L_32", passBurstLength32}, + {BL_n_S_16, "RDA", DependencyType::IntraRank, "BL_n_S_16", passBurstLength16}, + {BL_n_S_32, "RDA", DependencyType::IntraRank, "BL_n_S_32", passBurstLength32}, + {tBURST16 + tRTRS, + "RDA", + DependencyType::InterRank, + "tBURST16 + tRTRS", + passBurstLength16}, + {tBURST32 + tRTRS, + "RDA", + DependencyType::InterRank, + "tBURST32 + tRTRS", + passBurstLength32}, + {tWL + BL_n_max_16 + tWTR_L, + "WR", + DependencyType::IntraBankGroup, + "tWL + BL_n_max_16 + tWTR_L", + passBurstLength16}, + {tWL + BL_n_max_32 + tWTR_L, + "WR", + DependencyType::IntraBankGroup, + "tWL + BL_n_max_32 + tWTR_L", + passBurstLength32}, + {tWL + BL_n_min_16 + tWTR_S, + "WR", + DependencyType::IntraRank, + "tWL + BL_n_min_16 + tWTR_S", + passBurstLength16}, + {tWL + BL_n_min_32 + tWTR_S, + "WR", + DependencyType::IntraRank, + "tWL + BL_n_min_32 + tWTR_S", + passBurstLength32}, + {tWL + BL_n_max_16 + tWTR_L, + "WRA", + DependencyType::IntraBankGroup, + "tWL + BL_n_max_16 + tWTR_L", + passBurstLength16}, + {tWL + BL_n_max_32 + tWTR_L, + "WRA", + DependencyType::IntraBankGroup, + "tWL + BL_n_max_32 + tWTR_L", + passBurstLength32}, + {tWL + BL_n_min_16 + tWTR_S, + "WRA", + DependencyType::IntraRank, + "tWL + BL_n_min_16 + tWTR_S", + passBurstLength16}, + {tWL + BL_n_min_32 + tWTR_S, + "WRA", + DependencyType::IntraRank, + "tWL + BL_n_min_32 + tWTR_S", + passBurstLength32}, + {0, "CMD_BUS", DependencyType::InterRank, "CMDBus"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("WR"), - forward_as_tuple( - initializer_list{ - {tRCD + tCK, "ACT", DependencyType::IntraBank, "tRCD + tCK"}, - {tRL + BL_n_max_16 + tWCK2DQO - tWL, "RD", DependencyType::IntraBankGroup, "tRL + BL_n_max_16 + tWCK2DQO - tWL", passBurstLength16}, - {tRL + BL_n_max_32 + tWCK2DQO - tWL, "RD", DependencyType::IntraBankGroup, "tRL + BL_n_max_32 + tWCK2DQO - tWL", passBurstLength32}, - {tRL + BL_n_min_16 + tWCK2DQO - tWL, "RD", DependencyType::IntraRank, "tRL + BL_n_min_16 + tWCK2DQO - tWL", passBurstLength16}, - {tRL + BL_n_min_32 + tWCK2DQO - tWL, "RD", DependencyType::IntraRank, "tRL + BL_n_min_32 + tWCK2DQO - tWL", passBurstLength32}, - {tRL + BL_n_max_16 + tWCK2DQO - tWL, "RDA", DependencyType::IntraBankGroup, "tRL + BL_n_max_16 + tWCK2DQO - tWL", passBurstLength16}, - {tRL + BL_n_max_32 + tWCK2DQO - tWL, "RDA", DependencyType::IntraBankGroup, "tRL + BL_n_max_32 + tWCK2DQO - tWL", passBurstLength32}, - {tRL + BL_n_min_16 + tWCK2DQO - tWL, "RDA", DependencyType::IntraRank, "tRL + BL_n_min_16 + tWCK2DQO - tWL", passBurstLength16}, - {tRL + BL_n_min_32 + tWCK2DQO - tWL, "RDA", DependencyType::IntraRank, "tRL + BL_n_min_32 + tWCK2DQO - tWL", passBurstLength32}, - {BL_n_L_16, "WR", DependencyType::IntraBankGroup, "BL_n_L_16", passBurstLength16}, - {BL_n_L_32, "WR", DependencyType::IntraBankGroup, "BL_n_L_32", passBurstLength32}, - {BL_n_S_16, "WR", DependencyType::IntraRank, "BL_n_S_16", passBurstLength16}, - {BL_n_S_32, "WR", DependencyType::IntraRank, "BL_n_S_32", passBurstLength32}, - {tBURST16 + tRTRS, "WR", DependencyType::InterRank, "tBURST16 + tRTRS", passBurstLength16}, - {tBURST32 + tRTRS, "WR", DependencyType::InterRank, "tBURST32 + tRTRS", passBurstLength32}, - {BL_n_L_16, "WRA", DependencyType::IntraBankGroup, "BL_n_L_16", passBurstLength16}, - {BL_n_L_32, "WRA", DependencyType::IntraBankGroup, "BL_n_L_32", passBurstLength32}, - {BL_n_S_16, "WRA", DependencyType::IntraRank, "BL_n_S_16", passBurstLength16}, - {BL_n_S_32, "WRA", DependencyType::IntraRank, "BL_n_S_32", passBurstLength32}, - {tBURST16 + tRTRS, "WRA", DependencyType::InterRank, "tBURST16 + tRTRS", passBurstLength16}, - {tBURST32 + tRTRS, "WRA", DependencyType::InterRank, "tBURST32 + tRTRS", passBurstLength32}, - {0, "CMD_BUS", DependencyType::InterRank, "CMDBus"}, - } - ) - ); + dmap.emplace( + piecewise_construct, + forward_as_tuple("WR"), + forward_as_tuple(initializer_list{ + {tRCD + tCK, "ACT", DependencyType::IntraBank, "tRCD + tCK"}, + {tRL + BL_n_max_16 + tWCK2DQO - tWL, + "RD", + DependencyType::IntraBankGroup, + "tRL + BL_n_max_16 + tWCK2DQO - tWL", + passBurstLength16}, + {tRL + BL_n_max_32 + tWCK2DQO - tWL, + "RD", + DependencyType::IntraBankGroup, + "tRL + BL_n_max_32 + tWCK2DQO - tWL", + passBurstLength32}, + {tRL + BL_n_min_16 + tWCK2DQO - tWL, + "RD", + DependencyType::IntraRank, + "tRL + BL_n_min_16 + tWCK2DQO - tWL", + passBurstLength16}, + {tRL + BL_n_min_32 + tWCK2DQO - tWL, + "RD", + DependencyType::IntraRank, + "tRL + BL_n_min_32 + tWCK2DQO - tWL", + passBurstLength32}, + {tRL + BL_n_max_16 + tWCK2DQO - tWL, + "RDA", + DependencyType::IntraBankGroup, + "tRL + BL_n_max_16 + tWCK2DQO - tWL", + passBurstLength16}, + {tRL + BL_n_max_32 + tWCK2DQO - tWL, + "RDA", + DependencyType::IntraBankGroup, + "tRL + BL_n_max_32 + tWCK2DQO - tWL", + passBurstLength32}, + {tRL + BL_n_min_16 + tWCK2DQO - tWL, + "RDA", + DependencyType::IntraRank, + "tRL + BL_n_min_16 + tWCK2DQO - tWL", + passBurstLength16}, + {tRL + BL_n_min_32 + tWCK2DQO - tWL, + "RDA", + DependencyType::IntraRank, + "tRL + BL_n_min_32 + tWCK2DQO - tWL", + passBurstLength32}, + {BL_n_L_16, "WR", DependencyType::IntraBankGroup, "BL_n_L_16", passBurstLength16}, + {BL_n_L_32, "WR", DependencyType::IntraBankGroup, "BL_n_L_32", passBurstLength32}, + {BL_n_S_16, "WR", DependencyType::IntraRank, "BL_n_S_16", passBurstLength16}, + {BL_n_S_32, "WR", DependencyType::IntraRank, "BL_n_S_32", passBurstLength32}, + {tBURST16 + tRTRS, + "WR", + DependencyType::InterRank, + "tBURST16 + tRTRS", + passBurstLength16}, + {tBURST32 + tRTRS, + "WR", + DependencyType::InterRank, + "tBURST32 + tRTRS", + passBurstLength32}, + {BL_n_L_16, "WRA", DependencyType::IntraBankGroup, "BL_n_L_16", passBurstLength16}, + {BL_n_L_32, "WRA", DependencyType::IntraBankGroup, "BL_n_L_32", passBurstLength32}, + {BL_n_S_16, "WRA", DependencyType::IntraRank, "BL_n_S_16", passBurstLength16}, + {BL_n_S_32, "WRA", DependencyType::IntraRank, "BL_n_S_32", passBurstLength32}, + {tBURST16 + tRTRS, + "WRA", + DependencyType::InterRank, + "tBURST16 + tRTRS", + passBurstLength16}, + {tBURST32 + tRTRS, + "WRA", + DependencyType::InterRank, + "tBURST32 + tRTRS", + passBurstLength32}, + {0, "CMD_BUS", DependencyType::InterRank, "CMDBus"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("PREPB"), - forward_as_tuple( - initializer_list{ - {tRAS + tCK, "ACT", DependencyType::IntraBank, "tRAS + tCK"}, - {BL_n_min_16 + tRBTP, "RD", DependencyType::IntraBank, "BL_n_min_16 + tRBTP", passBurstLength16}, - {BL_n_min_32 + tRBTP, "RD", DependencyType::IntraBank, "BL_n_min_32 + tRBTP", passBurstLength32}, - {tWL + BL_n_min_16 + tCK + tWR, "WR", DependencyType::IntraBank, "tWL + BL_n_min_16 + tCK + tWR", passBurstLength16}, - {tWL + BL_n_min_32 + tCK + tWR, "WR", DependencyType::IntraBank, "tWL + BL_n_min_32 + tCK + tWR", passBurstLength32}, - {tPPD, "PREPB", DependencyType::IntraRank, "tPPD"}, - {0, "CMD_BUS", DependencyType::InterRank, "CMDBus"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("PREPB"), + forward_as_tuple(initializer_list{ + {tRAS + tCK, "ACT", DependencyType::IntraBank, "tRAS + tCK"}, + {BL_n_min_16 + tRBTP, + "RD", + DependencyType::IntraBank, + "BL_n_min_16 + tRBTP", + passBurstLength16}, + {BL_n_min_32 + tRBTP, + "RD", + DependencyType::IntraBank, + "BL_n_min_32 + tRBTP", + passBurstLength32}, + {tWL + BL_n_min_16 + tCK + tWR, + "WR", + DependencyType::IntraBank, + "tWL + BL_n_min_16 + tCK + tWR", + passBurstLength16}, + {tWL + BL_n_min_32 + tCK + tWR, + "WR", + DependencyType::IntraBank, + "tWL + BL_n_min_32 + tCK + tWR", + passBurstLength32}, + {tPPD, "PREPB", DependencyType::IntraRank, "tPPD"}, + {0, "CMD_BUS", DependencyType::InterRank, "CMDBus"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("RDA"), - forward_as_tuple( - initializer_list{ - {tRCD + tCK, "ACT", DependencyType::IntraBank, "tRCD + tCK"}, - {BL_n_L_16, "RD", DependencyType::IntraBankGroup, "BL_n_L_16", passBurstLength16}, - {BL_n_L_32, "RD", DependencyType::IntraBankGroup, "BL_n_L_32", passBurstLength32}, - {BL_n_S_16, "RD", DependencyType::IntraRank, "BL_n_S_16", passBurstLength16}, - {BL_n_S_32, "RD", DependencyType::IntraRank, "BL_n_S_32", passBurstLength32}, - {tBURST16 + tRTRS, "RD", DependencyType::InterRank, "tBURST16 + tRTRS", passBurstLength16}, - {tBURST32 + tRTRS, "RD", DependencyType::InterRank, "tBURST32 + tRTRS", passBurstLength32}, - {BL_n_L_16, "RDA", DependencyType::IntraBankGroup, "BL_n_L_16", passBurstLength16}, - {BL_n_L_32, "RDA", DependencyType::IntraBankGroup, "BL_n_L_32", passBurstLength32}, - {BL_n_S_16, "RDA", DependencyType::IntraRank, "BL_n_S_16", passBurstLength16}, - {BL_n_S_32, "RDA", DependencyType::IntraRank, "BL_n_S_32", passBurstLength32}, - {tBURST16 + tRTRS, "RDA", DependencyType::InterRank, "tBURST16 + tRTRS", passBurstLength16}, - {tBURST32 + tRTRS, "RDA", DependencyType::InterRank, "tBURST32 + tRTRS", passBurstLength32}, - {tWL + BL_n_max_16 + tWTR_L, "WR", DependencyType::IntraBankGroup, "tWL + BL_n_max_16 + tWTR_L", passBurstLength16}, - {tWL + BL_n_max_32 + tWTR_L, "WR", DependencyType::IntraBankGroup, "tWL + BL_n_max_32 + tWTR_L", passBurstLength32}, - {tWL + BL_n_min_16 + tWTR_S, "WR", DependencyType::IntraRank, "tWL + BL_n_min_16 + tWTR_S", passBurstLength16}, - {tWL + BL_n_min_32 + tWTR_S, "WR", DependencyType::IntraRank, "tWL + BL_n_min_32 + tWTR_S", passBurstLength32}, - {tWL + BL_n_max_16 + tWTR_L, "WRA", DependencyType::IntraBankGroup, "tWL + BL_n_max_16 + tWTR_L", passBurstLength16}, - {tWL + BL_n_max_32 + tWTR_L, "WRA", DependencyType::IntraBankGroup, "tWL + BL_n_max_32 + tWTR_L", passBurstLength32}, - {tWL + BL_n_min_16 + tWTR_S, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_16 + tWTR_S", passBurstLength16}, - {tWL + BL_n_min_32 + tWTR_S, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_32 + tWTR_S", passBurstLength32}, - {0, "CMD_BUS", DependencyType::InterRank, "CMDBus"}, - } - ) - ); + dmap.emplace( + piecewise_construct, + forward_as_tuple("RDA"), + forward_as_tuple(initializer_list{ + {tRCD + tCK, "ACT", DependencyType::IntraBank, "tRCD + tCK"}, + {BL_n_L_16, "RD", DependencyType::IntraBankGroup, "BL_n_L_16", passBurstLength16}, + {BL_n_L_32, "RD", DependencyType::IntraBankGroup, "BL_n_L_32", passBurstLength32}, + {BL_n_S_16, "RD", DependencyType::IntraRank, "BL_n_S_16", passBurstLength16}, + {BL_n_S_32, "RD", DependencyType::IntraRank, "BL_n_S_32", passBurstLength32}, + {tBURST16 + tRTRS, + "RD", + DependencyType::InterRank, + "tBURST16 + tRTRS", + passBurstLength16}, + {tBURST32 + tRTRS, + "RD", + DependencyType::InterRank, + "tBURST32 + tRTRS", + passBurstLength32}, + {BL_n_L_16, "RDA", DependencyType::IntraBankGroup, "BL_n_L_16", passBurstLength16}, + {BL_n_L_32, "RDA", DependencyType::IntraBankGroup, "BL_n_L_32", passBurstLength32}, + {BL_n_S_16, "RDA", DependencyType::IntraRank, "BL_n_S_16", passBurstLength16}, + {BL_n_S_32, "RDA", DependencyType::IntraRank, "BL_n_S_32", passBurstLength32}, + {tBURST16 + tRTRS, + "RDA", + DependencyType::InterRank, + "tBURST16 + tRTRS", + passBurstLength16}, + {tBURST32 + tRTRS, + "RDA", + DependencyType::InterRank, + "tBURST32 + tRTRS", + passBurstLength32}, + {tWL + BL_n_max_16 + tWTR_L, + "WR", + DependencyType::IntraBankGroup, + "tWL + BL_n_max_16 + tWTR_L", + passBurstLength16}, + {tWL + BL_n_max_32 + tWTR_L, + "WR", + DependencyType::IntraBankGroup, + "tWL + BL_n_max_32 + tWTR_L", + passBurstLength32}, + {tWL + BL_n_min_16 + tWTR_S, + "WR", + DependencyType::IntraRank, + "tWL + BL_n_min_16 + tWTR_S", + passBurstLength16}, + {tWL + BL_n_min_32 + tWTR_S, + "WR", + DependencyType::IntraRank, + "tWL + BL_n_min_32 + tWTR_S", + passBurstLength32}, + {tWL + BL_n_max_16 + tWTR_L, + "WRA", + DependencyType::IntraBankGroup, + "tWL + BL_n_max_16 + tWTR_L", + passBurstLength16}, + {tWL + BL_n_max_32 + tWTR_L, + "WRA", + DependencyType::IntraBankGroup, + "tWL + BL_n_max_32 + tWTR_L", + passBurstLength32}, + {tWL + BL_n_min_16 + tWTR_S, + "WRA", + DependencyType::IntraRank, + "tWL + BL_n_min_16 + tWTR_S", + passBurstLength16}, + {tWL + BL_n_min_32 + tWTR_S, + "WRA", + DependencyType::IntraRank, + "tWL + BL_n_min_32 + tWTR_S", + passBurstLength32}, + {0, "CMD_BUS", DependencyType::InterRank, "CMDBus"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("WRA"), - forward_as_tuple( - initializer_list{ - {tRCD + tCK, "ACT", DependencyType::IntraBank, "tRCD + tCK"}, - {tRL + BL_n_max_16 + tWCK2DQO - tWL, "RD", DependencyType::IntraBankGroup, "tRL + BL_n_max_16 + tWCK2DQO - tWL", passBurstLength16}, - {tRL + BL_n_max_32 + tWCK2DQO - tWL, "RD", DependencyType::IntraBankGroup, "tRL + BL_n_max_32 + tWCK2DQO - tWL", passBurstLength32}, - {tRL + BL_n_min_16 + tWCK2DQO - tWL, "RD", DependencyType::IntraRank, "tRL + BL_n_min_16 + tWCK2DQO - tWL", passBurstLength16}, - {tRL + BL_n_min_32 + tWCK2DQO - tWL, "RD", DependencyType::IntraRank, "tRL + BL_n_min_32 + tWCK2DQO - tWL", passBurstLength32}, - {tRL + BL_n_max_16 + tWCK2DQO - tWL, "RDA", DependencyType::IntraBankGroup, "tRL + BL_n_max_16 + tWCK2DQO - tWL", passBurstLength16}, - {tRL + BL_n_max_32 + tWCK2DQO - tWL, "RDA", DependencyType::IntraBankGroup, "tRL + BL_n_max_32 + tWCK2DQO - tWL", passBurstLength32}, - {tRL + BL_n_min_16 + tWCK2DQO - tWL, "RDA", DependencyType::IntraRank, "tRL + BL_n_min_16 + tWCK2DQO - tWL", passBurstLength16}, - {tRL + BL_n_min_32 + tWCK2DQO - tWL, "RDA", DependencyType::IntraRank, "tRL + BL_n_min_32 + tWCK2DQO - tWL", passBurstLength32}, - {BL_n_L_16, "WR", DependencyType::IntraBankGroup, "BL_n_L_16", passBurstLength16}, - {BL_n_L_32, "WR", DependencyType::IntraBankGroup, "BL_n_L_32", passBurstLength32}, - {BL_n_S_16, "WR", DependencyType::IntraRank, "BL_n_S_16", passBurstLength16}, - {BL_n_S_32, "WR", DependencyType::IntraRank, "BL_n_S_32", passBurstLength32}, - {tBURST16 + tRTRS, "WR", DependencyType::InterRank, "tBURST16 + tRTRS", passBurstLength16}, - {tBURST32 + tRTRS, "WR", DependencyType::InterRank, "tBURST32 + tRTRS", passBurstLength32}, - {BL_n_L_16, "WRA", DependencyType::IntraBankGroup, "BL_n_L_16", passBurstLength16}, - {BL_n_L_32, "WRA", DependencyType::IntraBankGroup, "BL_n_L_32", passBurstLength32}, - {BL_n_S_16, "WRA", DependencyType::IntraRank, "BL_n_S_16", passBurstLength16}, - {BL_n_S_32, "WRA", DependencyType::IntraRank, "BL_n_S_32", passBurstLength32}, - {tBURST16 + tRTRS, "WRA", DependencyType::InterRank, "tBURST16 + tRTRS", passBurstLength16}, - {tBURST32 + tRTRS, "WRA", DependencyType::InterRank, "tBURST32 + tRTRS", passBurstLength32}, - {0, "CMD_BUS", DependencyType::InterRank, "CMDBus"}, - } - ) - ); + dmap.emplace( + piecewise_construct, + forward_as_tuple("WRA"), + forward_as_tuple(initializer_list{ + {tRCD + tCK, "ACT", DependencyType::IntraBank, "tRCD + tCK"}, + {tRL + BL_n_max_16 + tWCK2DQO - tWL, + "RD", + DependencyType::IntraBankGroup, + "tRL + BL_n_max_16 + tWCK2DQO - tWL", + passBurstLength16}, + {tRL + BL_n_max_32 + tWCK2DQO - tWL, + "RD", + DependencyType::IntraBankGroup, + "tRL + BL_n_max_32 + tWCK2DQO - tWL", + passBurstLength32}, + {tRL + BL_n_min_16 + tWCK2DQO - tWL, + "RD", + DependencyType::IntraRank, + "tRL + BL_n_min_16 + tWCK2DQO - tWL", + passBurstLength16}, + {tRL + BL_n_min_32 + tWCK2DQO - tWL, + "RD", + DependencyType::IntraRank, + "tRL + BL_n_min_32 + tWCK2DQO - tWL", + passBurstLength32}, + {tRL + BL_n_max_16 + tWCK2DQO - tWL, + "RDA", + DependencyType::IntraBankGroup, + "tRL + BL_n_max_16 + tWCK2DQO - tWL", + passBurstLength16}, + {tRL + BL_n_max_32 + tWCK2DQO - tWL, + "RDA", + DependencyType::IntraBankGroup, + "tRL + BL_n_max_32 + tWCK2DQO - tWL", + passBurstLength32}, + {tRL + BL_n_min_16 + tWCK2DQO - tWL, + "RDA", + DependencyType::IntraRank, + "tRL + BL_n_min_16 + tWCK2DQO - tWL", + passBurstLength16}, + {tRL + BL_n_min_32 + tWCK2DQO - tWL, + "RDA", + DependencyType::IntraRank, + "tRL + BL_n_min_32 + tWCK2DQO - tWL", + passBurstLength32}, + {BL_n_L_16, "WR", DependencyType::IntraBankGroup, "BL_n_L_16", passBurstLength16}, + {BL_n_L_32, "WR", DependencyType::IntraBankGroup, "BL_n_L_32", passBurstLength32}, + {BL_n_S_16, "WR", DependencyType::IntraRank, "BL_n_S_16", passBurstLength16}, + {BL_n_S_32, "WR", DependencyType::IntraRank, "BL_n_S_32", passBurstLength32}, + {tBURST16 + tRTRS, + "WR", + DependencyType::InterRank, + "tBURST16 + tRTRS", + passBurstLength16}, + {tBURST32 + tRTRS, + "WR", + DependencyType::InterRank, + "tBURST32 + tRTRS", + passBurstLength32}, + {BL_n_L_16, "WRA", DependencyType::IntraBankGroup, "BL_n_L_16", passBurstLength16}, + {BL_n_L_32, "WRA", DependencyType::IntraBankGroup, "BL_n_L_32", passBurstLength32}, + {BL_n_S_16, "WRA", DependencyType::IntraRank, "BL_n_S_16", passBurstLength16}, + {BL_n_S_32, "WRA", DependencyType::IntraRank, "BL_n_S_32", passBurstLength32}, + {tBURST16 + tRTRS, + "WRA", + DependencyType::InterRank, + "tBURST16 + tRTRS", + passBurstLength16}, + {tBURST32 + tRTRS, + "WRA", + DependencyType::InterRank, + "tBURST32 + tRTRS", + passBurstLength32}, + {0, "CMD_BUS", DependencyType::InterRank, "CMDBus"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("REFAB"), - forward_as_tuple( - initializer_list{ - {tRCpb + tCK, "ACT", DependencyType::IntraRank, "tRCpb + tCK"}, - {BL_n_min_16 + tRBTP + tRPpb, "RDA", DependencyType::IntraRank, "BL_n_min_16 + tRBTP + tRPpb", passBurstLength16}, - {BL_n_min_32 + tRBTP + tRPpb, "RDA", DependencyType::IntraRank, "BL_n_min_32 + tRBTP + tRPpb", passBurstLength32}, - {tWL + BL_n_min_16 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_16 + tCK + tWR + tRPpb", passBurstLength16}, - {tWL + BL_n_min_32 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_32 + tCK + tWR + tRPpb", passBurstLength32}, - {tRPpb, "PREPB", DependencyType::IntraRank, "tRPpb"}, - {tRPab, "PREAB", DependencyType::IntraRank, "tRPab"}, - {tRFCab, "REFAB", DependencyType::IntraRank, "tRFCab"}, - {0, "CMD_BUS", DependencyType::InterRank, "CMDBus"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("REFAB"), + forward_as_tuple(initializer_list{ + {tRCpb + tCK, "ACT", DependencyType::IntraRank, "tRCpb + tCK"}, + {BL_n_min_16 + tRBTP + tRPpb, + "RDA", + DependencyType::IntraRank, + "BL_n_min_16 + tRBTP + tRPpb", + passBurstLength16}, + {BL_n_min_32 + tRBTP + tRPpb, + "RDA", + DependencyType::IntraRank, + "BL_n_min_32 + tRBTP + tRPpb", + passBurstLength32}, + {tWL + BL_n_min_16 + tCK + tWR + tRPpb, + "WRA", + DependencyType::IntraRank, + "tWL + BL_n_min_16 + tCK + tWR + tRPpb", + passBurstLength16}, + {tWL + BL_n_min_32 + tCK + tWR + tRPpb, + "WRA", + DependencyType::IntraRank, + "tWL + BL_n_min_32 + tCK + tWR + tRPpb", + passBurstLength32}, + {tRPpb, "PREPB", DependencyType::IntraRank, "tRPpb"}, + {tRPab, "PREAB", DependencyType::IntraRank, "tRPab"}, + {tRFCab, "REFAB", DependencyType::IntraRank, "tRFCab"}, + {0, "CMD_BUS", DependencyType::InterRank, "CMDBus"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("PREAB"), - forward_as_tuple( - initializer_list{ - {tRAS + tCK, "ACT", DependencyType::IntraRank, "tRAS + tCK"}, - {BL_n_min_16 + tRBTP, "RD", DependencyType::IntraRank, "BL_n_min_16 + tRBTP", passBurstLength16}, - {BL_n_min_32 + tRBTP, "RD", DependencyType::IntraRank, "BL_n_min_32 + tRBTP", passBurstLength32}, - {BL_n_min_16 + tRBTP, "RDA", DependencyType::IntraRank, "BL_n_min_16 + tRBTP", passBurstLength16}, - {BL_n_min_32 + tRBTP, "RDA", DependencyType::IntraRank, "BL_n_min_32 + tRBTP", passBurstLength32}, - {tWL + BL_n_min_16 + tCK + tWR, "WR", DependencyType::IntraRank, "tWL + BL_n_min_16 + tCK + tWR", passBurstLength16}, - {tWL + BL_n_min_32 + tCK + tWR, "WR", DependencyType::IntraRank, "tWL + BL_n_min_32 + tCK + tWR", passBurstLength32}, - {tWL + BL_n_min_16 + tCK + tWR, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_16 + tCK + tWR", passBurstLength16}, - {tWL + BL_n_min_32 + tCK + tWR, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_32 + tCK + tWR", passBurstLength32}, - {tPPD, "PREPB", DependencyType::IntraRank, "tPPD"}, - {0, "CMD_BUS", DependencyType::InterRank, "CMDBus"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("PREAB"), + forward_as_tuple(initializer_list{ + {tRAS + tCK, "ACT", DependencyType::IntraRank, "tRAS + tCK"}, + {BL_n_min_16 + tRBTP, + "RD", + DependencyType::IntraRank, + "BL_n_min_16 + tRBTP", + passBurstLength16}, + {BL_n_min_32 + tRBTP, + "RD", + DependencyType::IntraRank, + "BL_n_min_32 + tRBTP", + passBurstLength32}, + {BL_n_min_16 + tRBTP, + "RDA", + DependencyType::IntraRank, + "BL_n_min_16 + tRBTP", + passBurstLength16}, + {BL_n_min_32 + tRBTP, + "RDA", + DependencyType::IntraRank, + "BL_n_min_32 + tRBTP", + passBurstLength32}, + {tWL + BL_n_min_16 + tCK + tWR, + "WR", + DependencyType::IntraRank, + "tWL + BL_n_min_16 + tCK + tWR", + passBurstLength16}, + {tWL + BL_n_min_32 + tCK + tWR, + "WR", + DependencyType::IntraRank, + "tWL + BL_n_min_32 + tCK + tWR", + passBurstLength32}, + {tWL + BL_n_min_16 + tCK + tWR, + "WRA", + DependencyType::IntraRank, + "tWL + BL_n_min_16 + tCK + tWR", + passBurstLength16}, + {tWL + BL_n_min_32 + tCK + tWR, + "WRA", + DependencyType::IntraRank, + "tWL + BL_n_min_32 + tCK + tWR", + passBurstLength32}, + {tPPD, "PREPB", DependencyType::IntraRank, "tPPD"}, + {0, "CMD_BUS", DependencyType::InterRank, "CMDBus"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("REFPB"), - forward_as_tuple( - initializer_list{ - {tRCpb + tCK, "ACT", DependencyType::IntraBank, "tRCpb + tCK"}, - {tRRD + tCK, "ACT", DependencyType::IntraRank, "tRRD + tCK"}, - {BL_n_min_16 + tRBTP + tRPpb, "RDA", DependencyType::IntraBank, "BL_n_min_16 + tRBTP + tRPpb", passBurstLength16}, - {BL_n_min_32 + tRBTP + tRPpb, "RDA", DependencyType::IntraBank, "BL_n_min_32 + tRBTP + tRPpb", passBurstLength32}, - {tWL + BL_n_min_16 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_16 + tCK + tWR + tRPpb", passBurstLength16}, - {tWL + BL_n_min_32 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_32 + tCK + tWR + tRPpb", passBurstLength32}, - {tRPpb, "PREPB", DependencyType::IntraBank, "tRPpb"}, - {tRPab, "PREAB", DependencyType::IntraRank, "tRPab"}, - {tRFCpb, "REFPB", DependencyType::IntraBank, "tRFCpb"}, - {tpbR2pbR, "REFPB", DependencyType::IntraRank, "tpbR2pbR"}, - {0, "CMD_BUS", DependencyType::InterRank, "CMDBus"}, - {0, "NAW", DependencyType::IntraRank, "tFAW"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("REFPB"), + forward_as_tuple(initializer_list{ + {tRCpb + tCK, "ACT", DependencyType::IntraBank, "tRCpb + tCK"}, + {tRRD + tCK, "ACT", DependencyType::IntraRank, "tRRD + tCK"}, + {BL_n_min_16 + tRBTP + tRPpb, + "RDA", + DependencyType::IntraBank, + "BL_n_min_16 + tRBTP + tRPpb", + passBurstLength16}, + {BL_n_min_32 + tRBTP + tRPpb, + "RDA", + DependencyType::IntraBank, + "BL_n_min_32 + tRBTP + tRPpb", + passBurstLength32}, + {tWL + BL_n_min_16 + tCK + tWR + tRPpb, + "WRA", + DependencyType::IntraBank, + "tWL + BL_n_min_16 + tCK + tWR + tRPpb", + passBurstLength16}, + {tWL + BL_n_min_32 + tCK + tWR + tRPpb, + "WRA", + DependencyType::IntraBank, + "tWL + BL_n_min_32 + tCK + tWR + tRPpb", + passBurstLength32}, + {tRPpb, "PREPB", DependencyType::IntraBank, "tRPpb"}, + {tRPab, "PREAB", DependencyType::IntraRank, "tRPab"}, + {tRFCpb, "REFPB", DependencyType::IntraBank, "tRFCpb"}, + {tpbR2pbR, "REFPB", DependencyType::IntraRank, "tpbR2pbR"}, + {0, "CMD_BUS", DependencyType::InterRank, "CMDBus"}, + {0, "NAW", DependencyType::IntraRank, "tFAW"}, + })); - dmap.emplace( - piecewise_construct, - forward_as_tuple("REFP2B"), - forward_as_tuple( - initializer_list{ - {tRCpb + tCK, "ACT", DependencyType::IntraBank, "tRCpb + tCK"}, - {tRRD + tCK, "ACT", DependencyType::IntraRank, "tRRD + tCK"}, - {BL_n_min_16 + tRBTP + tRPpb, "RDA", DependencyType::IntraBank, "BL_n_min_16 + tRBTP + tRPpb", passBurstLength16}, - {BL_n_min_32 + tRBTP + tRPpb, "RDA", DependencyType::IntraBank, "BL_n_min_32 + tRBTP + tRPpb", passBurstLength32}, - {tWL + BL_n_min_16 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_16 + tCK + tWR + tRPpb", passBurstLength16}, - {tWL + BL_n_min_32 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_32 + tCK + tWR + tRPpb", passBurstLength32}, - {tRPpb, "PREPB", DependencyType::IntraBank, "tRPpb"}, - {tRPab, "PREAB", DependencyType::IntraRank, "tRPab"}, - {tRFCpb, "REFP2B", DependencyType::IntraBank, "tRFCpb"}, - {tpbR2pbR, "REFP2B", DependencyType::IntraRank, "tpbR2pbR"}, - {0, "CMD_BUS", DependencyType::InterRank, "CMDBus"}, - {0, "NAW", DependencyType::IntraRank, "tFAW"}, - } - ) - ); + dmap.emplace(piecewise_construct, + forward_as_tuple("REFP2B"), + forward_as_tuple(initializer_list{ + {tRCpb + tCK, "ACT", DependencyType::IntraBank, "tRCpb + tCK"}, + {tRRD + tCK, "ACT", DependencyType::IntraRank, "tRRD + tCK"}, + {BL_n_min_16 + tRBTP + tRPpb, + "RDA", + DependencyType::IntraBank, + "BL_n_min_16 + tRBTP + tRPpb", + passBurstLength16}, + {BL_n_min_32 + tRBTP + tRPpb, + "RDA", + DependencyType::IntraBank, + "BL_n_min_32 + tRBTP + tRPpb", + passBurstLength32}, + {tWL + BL_n_min_16 + tCK + tWR + tRPpb, + "WRA", + DependencyType::IntraBank, + "tWL + BL_n_min_16 + tCK + tWR + tRPpb", + passBurstLength16}, + {tWL + BL_n_min_32 + tCK + tWR + tRPpb, + "WRA", + DependencyType::IntraBank, + "tWL + BL_n_min_32 + tCK + tWR + tRPpb", + passBurstLength32}, + {tRPpb, "PREPB", DependencyType::IntraBank, "tRPpb"}, + {tRPab, "PREAB", DependencyType::IntraRank, "tRPab"}, + {tRFCpb, "REFP2B", DependencyType::IntraBank, "tRFCpb"}, + {tpbR2pbR, "REFP2B", DependencyType::IntraRank, "tpbR2pbR"}, + {0, "CMD_BUS", DependencyType::InterRank, "CMDBus"}, + {0, "NAW", DependencyType::IntraRank, "tFAW"}, + })); - return dmap; + return dmap; } diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR5.h b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR5.h index 4e750795..0206e141 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR5.h +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR5.h @@ -38,23 +38,24 @@ #include "../dramtimedependenciesbase.h" #include "businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR5dbphaseentry.h" -class TimeDependenciesInfoLPDDR5 final : public DRAMTimeDependenciesBase { - public: +class TimeDependenciesInfoLPDDR5 final : public DRAMTimeDependenciesBase +{ +public: TimeDependenciesInfoLPDDR5(const QJsonObject& memspec, const uint clk); static const std::vector getPossiblePhases(); uint getPer2BankOffset() { return per2BankOffset; } - protected: +protected: void mInitializeValues() override; DependencyMap mSpecializedGetDependencies() const override; - protected: +protected: uint burstLength; uint dataRate; uint per2BankOffset; - + uint tRCD; uint tRPpb; uint tRPab; @@ -115,5 +116,4 @@ class TimeDependenciesInfoLPDDR5 final : public DRAMTimeDependenciesBase { uint tRDPDEN; uint tWRPDEN; uint tWRAPDEN; - }; diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/phasedependenciestracker.cpp b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/phasedependenciestracker.cpp index 48d2f06b..93ddceab 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/phasedependenciestracker.cpp +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/phasedependenciestracker.cpp @@ -38,94 +38,115 @@ #include #include -void -PhaseDependenciesTracker::calculateDependencies(TraceDB& tdb, std::vector& commands) { - using std::chrono::high_resolution_clock; - using std::chrono::duration_cast; +void PhaseDependenciesTracker::calculateDependencies(TraceDB& tdb, std::vector& commands) +{ using std::chrono::duration; + using std::chrono::duration_cast; + using std::chrono::high_resolution_clock; using std::chrono::microseconds; auto deviceInstantiationTimeStart = high_resolution_clock::now(); - auto deviceConfig = ConfigurationFactory::make(tdb); + auto deviceConfig = ConfigurationFactory::make(tdb); auto deviceInstantiationTimeEnd = high_resolution_clock::now(); - auto deviceInstantiationTimeDuration = duration_cast(deviceInstantiationTimeEnd - deviceInstantiationTimeStart); + auto deviceInstantiationTimeDuration = + duration_cast(deviceInstantiationTimeEnd - deviceInstantiationTimeStart); mBeginTransaction(tdb); mDropTable(tdb); - if (commands.size() > 0) { + if (commands.size() > 0) + { auto phasesLoadingTimeStart = high_resolution_clock::now(); - auto& phases = mGetFilteredPhases(deviceConfig, tdb, commands); + auto& phases = mGetFilteredPhases(deviceConfig, tdb, commands); auto phasesLoadingTimeEnd = high_resolution_clock::now(); - auto phasesLoadingTimeDuration = duration_cast(phasesLoadingTimeEnd - phasesLoadingTimeStart); + auto phasesLoadingTimeDuration = + duration_cast(phasesLoadingTimeEnd - phasesLoadingTimeStart); - if (phases.size() != 0) { + if (phases.size() != 0) + { auto dependenciesCalcTimeStart = high_resolution_clock::now(); - auto& entries = mCalculateDependencies(deviceConfig, phases, commands); + auto& entries = mCalculateDependencies(deviceConfig, phases, commands); auto dependenciesCalcTimeEnd = high_resolution_clock::now(); - auto dependenciesCalcTimeDuration = duration_cast(dependenciesCalcTimeEnd - dependenciesCalcTimeStart); + auto dependenciesCalcTimeDuration = + duration_cast(dependenciesCalcTimeEnd - dependenciesCalcTimeStart); - if (entries.size() > 0) { + if (entries.size() > 0) + { mCreateTable(tdb); } auto tableInsertionTimeStart = high_resolution_clock::now(); - mInsertIntoTable(tdb, entries); + mInsertIntoTable(tdb, entries); auto tableInsertionTimeEnd = high_resolution_clock::now(); - auto tableInsertionTimeDuration = duration_cast(tableInsertionTimeEnd - tableInsertionTimeStart); + auto tableInsertionTimeDuration = + duration_cast(tableInsertionTimeEnd - tableInsertionTimeStart); - auto totalTime = deviceInstantiationTimeDuration + phasesLoadingTimeDuration + dependenciesCalcTimeDuration + tableInsertionTimeDuration; + auto totalTime = deviceInstantiationTimeDuration + phasesLoadingTimeDuration + + dependenciesCalcTimeDuration + tableInsertionTimeDuration; - - std::cout << "PhaseDependenciesTracker times (us):" << std::endl - << "\tDevice instantiation: " << deviceInstantiationTimeDuration.count() << std::endl - << "\tPhase loading: " << phasesLoadingTimeDuration.count() << std::endl - << "\tDependencies calculation: " << dependenciesCalcTimeDuration.count() << std::endl - << "\tDB table population: " << tableInsertionTimeDuration.count() << std::endl - << " - Total time: " << totalTime.count() << std::endl; - - } else { + std::cout << "PhaseDependenciesTracker times (us):" << std::endl + << "\tDevice instantiation: " << deviceInstantiationTimeDuration.count() + << std::endl + << "\tPhase loading: " << phasesLoadingTimeDuration.count() << std::endl + << "\tDependencies calculation: " << dependenciesCalcTimeDuration.count() + << std::endl + << "\tDB table population: " << tableInsertionTimeDuration.count() + << std::endl + << " - Total time: " << totalTime.count() << std::endl; + } + else + { // TODO - not sure if necessary. Still, a possibility // mRollbackChanges(tdb); // return; } - } mCommitTransaction(tdb); } -void PhaseDependenciesTracker::mDropTable(TraceDB& tdb) { +void PhaseDependenciesTracker::mDropTable(TraceDB& tdb) +{ QString command = "DROP TABLE IF EXISTS DirectDependencies; "; - + auto query = mExecuteQuery(tdb, command); query.finish(); } -void PhaseDependenciesTracker::mCreateTable(TraceDB& tdb) { - QString command = "CREATE TABLE DirectDependencies( DelayedPhaseID INT, DelayedPhaseName, DependencyType, TimeDependency, DependencyPhaseID INT, DependencyPhaseName ); "; - +void PhaseDependenciesTracker::mCreateTable(TraceDB& tdb) +{ + QString command = + "CREATE TABLE DirectDependencies( DelayedPhaseID INT, DelayedPhaseName, DependencyType, " + "TimeDependency, DependencyPhaseID INT, DependencyPhaseName ); "; + auto query = mExecuteQuery(tdb, command); query.finish(); } -void PhaseDependenciesTracker::mInsertIntoTable(TraceDB& tdb, const std::vector& entries) { +void PhaseDependenciesTracker::mInsertIntoTable(TraceDB& tdb, + const std::vector& entries) +{ static const size_t bulkInsertionSize = 30; - + auto numberOfEntries = entries.size(); QString command; size_t counter = 0; - for (const auto& entry : entries) { - if (counter == 0) { + for (const auto& entry : entries) + { + if (counter == 0) + { // Reset command string and add first entry - command = "INSERT INTO 'DirectDependencies' ('DelayedPhaseID', 'DelayedPhaseName', 'DependencyType', 'TimeDependency', 'DependencyPhaseID', 'DependencyPhaseName') "; + command = + "INSERT INTO 'DirectDependencies' ('DelayedPhaseID', 'DelayedPhaseName', " + "'DependencyType', 'TimeDependency', 'DependencyPhaseID', 'DependencyPhaseName') "; mAddFirstEntryCommandString(command, entry); - - counter++; - } else if (counter == bulkInsertionSize-1) { + counter++; + } + else if (counter == bulkInsertionSize - 1) + { // Write last entry and submit mAddEntryCommandString(command, entry); @@ -133,27 +154,27 @@ void PhaseDependenciesTracker::mInsertIntoTable(TraceDB& tdb, const std::vector< query.finish(); counter = 0; - - } else { + } + else + { // Write entry mAddEntryCommandString(command, entry); counter++; - - } - } - if (counter != 0) { + if (counter != 0) + { auto query = mExecuteQuery(tdb, command); query.finish(); } - } const std::vector> -PhaseDependenciesTracker::mGetFilteredPhases(const std::shared_ptr deviceConfig, TraceDB& tdb, const std::vector& commands) +PhaseDependenciesTracker::mGetFilteredPhases(const std::shared_ptr deviceConfig, + TraceDB& tdb, + const std::vector& commands) { std::vector> phases; QString queryStr = deviceConfig->getQueryStr(commands); @@ -162,31 +183,42 @@ PhaseDependenciesTracker::mGetFilteredPhases(const std::shared_ptrmakePhaseEntry(query); ++rowIt; } while (query.next()); - if (rowIt != nrows) { - throw std::runtime_error("An error occurred while fetching phases in 'PhaseDependenciesTracker::mGetFilteredPhases': expected " + std::to_string(nrows) + " rows, but found " + std::to_string(rowIt) + "\n"); + if (rowIt != nrows) + { + throw std::runtime_error("An error occurred while fetching phases in " + "'PhaseDependenciesTracker::mGetFilteredPhases': expected " + + std::to_string(nrows) + " rows, but found " + + std::to_string(rowIt) + "\n"); } query.finish(); @@ -194,96 +226,108 @@ PhaseDependenciesTracker::mGetFilteredPhases(const std::shared_ptr -PhaseDependenciesTracker::mCalculateDependencies(const std::shared_ptr deviceConfig, const std::vector>& phases, std::vector& commands) { +const std::vector PhaseDependenciesTracker::mCalculateDependencies( + const std::shared_ptr deviceConfig, + const std::vector>& phases, + std::vector& commands) +{ std::vector entries; - entries.reserve((size_t) (0.4 * phases.size())); + entries.reserve((size_t)(0.4 * phases.size())); // Get dependencies for device const DependencyMap deviceDependencies = deviceConfig->getDependencies(commands); // Tries to find all timing dependencies for each phase on the trace PoolControllerMap poolController = deviceConfig->getPools(); - for (size_t i = 1; i < phases.size(); i++) { + for (size_t i = 1; i < phases.size(); i++) + { // Pool dependencies variables reset poolController.clear(); // Auxiliary variables const auto phase = phases[i]; - if (phase == nullptr) continue; - + if (phase == nullptr) + continue; + // Get time dependency descriptions for the current phase const auto& deps = deviceDependencies.at(phase->phaseName); // Loop all previous phases until there cannot be any more time dependencies - for (int j = i-1; j >= 0; j--) { + for (int j = i - 1; j >= 0; j--) + { // Get next phase to analyse const auto& otherPhase = phases[j]; // Calculates the time difference in nanoseconds const auto timeDiff = phase->phaseBegin - otherPhase->phaseBegin; - // Time difference begin greater than the maximum possible dependency time ends the internal loop - if (timeDiff > deps.maxTime) break; + // Time difference begin greater than the maximum possible dependency time ends the + // internal loop + if (timeDiff > deps.maxTime) + break; // For each possible dependency for the current phase, // checks if otherPhase would match as a dependency - for (const auto& dep : deps.dependencies) { + for (const auto& dep : deps.dependencies) + { bool isPoolDep = dep.phaseDep.isPool(); - if (!isPoolDep && dep.phaseDep != otherPhase->phaseName) continue; - - if (!phase->potentialDependency(dep, otherPhase)) { + if (!isPoolDep && dep.phaseDep != otherPhase->phaseName) + continue; + + if (!phase->potentialDependency(dep, otherPhase)) + { continue; } - if (isPoolDep) { + if (isPoolDep) + { // Captures activate window and command bus dependencies auto busyTime = poolController.getBusyTime(dep.phaseDep, otherPhase->phaseName); - if (busyTime > 0 && timeDiff <= busyTime) { - if (timeDiff == busyTime) { + if (busyTime > 0 && timeDiff <= busyTime) + { + if (timeDiff == busyTime) + { // Captures only the first (exactly matching time) phase in // the pool window as a dependency - poolController.push(dep.phaseDep, DBDependencyEntry{ - phase->id, - phase->phaseName.getIDStr(), - PhaseDependency::dependencyTypeName(dep.depType), - dep.timeDepName, - otherPhase->id, - otherPhase->phaseName.getIDStr() - }); - } + poolController.push( + dep.phaseDep, + DBDependencyEntry{phase->id, + phase->phaseName.getIDStr(), + PhaseDependency::dependencyTypeName(dep.depType), + dep.timeDepName, + otherPhase->id, + otherPhase->phaseName.getIDStr()}); + } - if (timeDiff < busyTime) { + if (timeDiff < busyTime) + { poolController.increment(dep.phaseDep); } - } - continue; + continue; } - if (timeDiff == dep.timeValue) { - entries.emplace_back(DBDependencyEntry{ - phase->id, - phase->phaseName.getIDStr(), - PhaseDependency::dependencyTypeName(dep.depType), - dep.timeDepName, - otherPhase->id, - otherPhase->phaseName.getIDStr() - }); + if (timeDiff == dep.timeValue) + { + entries.emplace_back( + DBDependencyEntry{phase->id, + phase->phaseName.getIDStr(), + PhaseDependency::dependencyTypeName(dep.depType), + dep.timeDepName, + otherPhase->id, + otherPhase->phaseName.getIDStr()}); } - } - } poolController.merge(entries); - } return entries; } -QSqlQuery PhaseDependenciesTracker::mExecuteQuery(TraceDB& tdb, const QString queryStr) { +QSqlQuery PhaseDependenciesTracker::mExecuteQuery(TraceDB& tdb, const QString queryStr) +{ QSqlQuery query(tdb.database); query.prepare(queryStr); tdb.executeQuery(query); @@ -291,39 +335,43 @@ QSqlQuery PhaseDependenciesTracker::mExecuteQuery(TraceDB& tdb, const QString qu return query; } -void PhaseDependenciesTracker::mBeginTransaction(TraceDB& tdb) { +void PhaseDependenciesTracker::mBeginTransaction(TraceDB& tdb) +{ const QString queryStr = "BEGIN TRANSACTION;"; auto query = mExecuteQuery(tdb, queryStr); query.finish(); } -void PhaseDependenciesTracker::mRollbackChanges(TraceDB& tdb) { +void PhaseDependenciesTracker::mRollbackChanges(TraceDB& tdb) +{ const QString queryStr = "ROLLBACK;"; auto query = mExecuteQuery(tdb, queryStr); query.finish(); } -void PhaseDependenciesTracker::mCommitTransaction(TraceDB& tdb) { +void PhaseDependenciesTracker::mCommitTransaction(TraceDB& tdb) +{ const QString queryStr = "COMMIT;"; auto query = mExecuteQuery(tdb, queryStr); query.finish(); } -void PhaseDependenciesTracker::mAddFirstEntryCommandString(QString& command, const DBDependencyEntry& entry) { - command = command + " SELECT '" + QString::number(entry.delayedPhaseID) + "' AS 'DelayedPhaseID', '" - + entry.delayedPhaseName + "' AS 'DelayedPhaseName', '" - + entry.dependencyType + "' AS 'DependencyType', '" - + entry.timeDependency + "' AS 'TimeDependency', '" - + QString::number(entry.dependencyPhaseID) + "' AS 'DependencyPhaseID', '" - + entry.dependencyPhaseName + "' AS 'DependencyPhaseName' "; - +void PhaseDependenciesTracker::mAddFirstEntryCommandString(QString& command, + const DBDependencyEntry& entry) +{ + command = command + " SELECT '" + QString::number(entry.delayedPhaseID) + + "' AS 'DelayedPhaseID', '" + entry.delayedPhaseName + "' AS 'DelayedPhaseName', '" + + entry.dependencyType + "' AS 'DependencyType', '" + entry.timeDependency + + "' AS 'TimeDependency', '" + QString::number(entry.dependencyPhaseID) + + "' AS 'DependencyPhaseID', '" + entry.dependencyPhaseName + + "' AS 'DependencyPhaseName' "; } -void PhaseDependenciesTracker::mAddEntryCommandString(QString& command, const DBDependencyEntry& entry) { - command = command + " UNION ALL SELECT '" + QString::number(entry.delayedPhaseID) + "', '" - + entry.delayedPhaseName + "', '" - + entry.dependencyType + "', '" - + entry.timeDependency + "', '" - + QString::number(entry.dependencyPhaseID) + "', '" - + entry.dependencyPhaseName + "' "; +void PhaseDependenciesTracker::mAddEntryCommandString(QString& command, + const DBDependencyEntry& entry) +{ + command = command + " UNION ALL SELECT '" + QString::number(entry.delayedPhaseID) + "', '" + + entry.delayedPhaseName + "', '" + entry.dependencyType + "', '" + + entry.timeDependency + "', '" + QString::number(entry.dependencyPhaseID) + "', '" + + entry.dependencyPhaseName + "' "; } diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/phasedependenciestracker.h b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/phasedependenciestracker.h index 0e7b7d7a..df56e395 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/phasedependenciestracker.h +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/phasedependenciestracker.h @@ -35,15 +35,16 @@ #pragma once -#include -#include #include +#include +#include -#include "data/tracedb.h" -#include "configurations/configurationfactory.h" #include "common/common.h" +#include "configurations/configurationfactory.h" +#include "data/tracedb.h" -class PhaseDependenciesTracker { +class PhaseDependenciesTracker +{ public: static void calculateDependencies(TraceDB& tdb, std::vector& dependencyFilter); @@ -52,8 +53,14 @@ private: static void mCreateTable(TraceDB& tdb); static void mInsertIntoTable(TraceDB& tdb, const std::vector& entries); - static const std::vector> mGetFilteredPhases(const std::shared_ptr, TraceDB& tdb, const std::vector& commands); - static const std::vector mCalculateDependencies(const std::shared_ptr, const std::vector>& phases, std::vector& commands); + static const std::vector> + mGetFilteredPhases(const std::shared_ptr, + TraceDB& tdb, + const std::vector& commands); + static const std::vector + mCalculateDependencies(const std::shared_ptr, + const std::vector>& phases, + std::vector& commands); static QSqlQuery mExecuteQuery(TraceDB& tdb, const QString queryStr); @@ -63,9 +70,9 @@ private: private: static void mBeginTransaction(TraceDB& tdb); static void mRollbackChanges(TraceDB& tdb); - static void mCommitTransaction(TraceDB& tdb); + static void mCommitTransaction(TraceDB& tdb); - inline static void mAddFirstEntryCommandString(QString& command, const DBDependencyEntry& entry); + inline static void mAddFirstEntryCommandString(QString& command, + const DBDependencyEntry& entry); inline static void mAddEntryCommandString(QString& command, const DBDependencyEntry& entry); - }; diff --git a/extensions/apps/traceAnalyzer/businessObjects/generalinfo.h b/extensions/apps/traceAnalyzer/businessObjects/generalinfo.h index dd312576..521fed14 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/generalinfo.h +++ b/extensions/apps/traceAnalyzer/businessObjects/generalinfo.h @@ -67,19 +67,43 @@ struct GeneralInfo bool pseudoChannelMode = false; GeneralInfo() = default; - GeneralInfo(uint64_t numberOfTransactions, uint64_t numberOfPhases, Timespan span, unsigned int numberOfRanks, - unsigned int numberOfBankgroups, unsigned int numberOfBanks, QString description, QString unitOfTime, - uint64_t clkPeriod, uint64_t windowSize, unsigned int refreshMaxPostponed, - unsigned int refreshMaxPulledin, unsigned int controllerThread, unsigned int maxBufferDepth, - unsigned int per2BankOffset, bool rowColumnCommandBus, bool pseudoChannelMode) - : numberOfTransactions(numberOfTransactions), numberOfPhases(numberOfPhases), span(span), - numberOfRanks(numberOfRanks), numberOfBankGroups(numberOfBankgroups), numberOfBanks(numberOfBanks), - banksPerRank(numberOfBanks / numberOfRanks), groupsPerRank(numberOfBankgroups / numberOfRanks), - banksPerGroup(numberOfBanks / numberOfBankgroups), description(std::move(description)), - unitOfTime(std::move(unitOfTime)), clkPeriod(clkPeriod), windowSize(windowSize), - refreshMaxPostponed(refreshMaxPostponed), refreshMaxPulledin(refreshMaxPulledin), - controllerThread(controllerThread), maxBufferDepth(maxBufferDepth), per2BankOffset(per2BankOffset), - rowColumnCommandBus(rowColumnCommandBus), pseudoChannelMode(pseudoChannelMode) + GeneralInfo(uint64_t numberOfTransactions, + uint64_t numberOfPhases, + Timespan span, + unsigned int numberOfRanks, + unsigned int numberOfBankgroups, + unsigned int numberOfBanks, + QString description, + QString unitOfTime, + uint64_t clkPeriod, + uint64_t windowSize, + unsigned int refreshMaxPostponed, + unsigned int refreshMaxPulledin, + unsigned int controllerThread, + unsigned int maxBufferDepth, + unsigned int per2BankOffset, + bool rowColumnCommandBus, + bool pseudoChannelMode) : + numberOfTransactions(numberOfTransactions), + numberOfPhases(numberOfPhases), + span(span), + numberOfRanks(numberOfRanks), + numberOfBankGroups(numberOfBankgroups), + numberOfBanks(numberOfBanks), + banksPerRank(numberOfBanks / numberOfRanks), + groupsPerRank(numberOfBankgroups / numberOfRanks), + banksPerGroup(numberOfBanks / numberOfBankgroups), + description(std::move(description)), + unitOfTime(std::move(unitOfTime)), + clkPeriod(clkPeriod), + windowSize(windowSize), + refreshMaxPostponed(refreshMaxPostponed), + refreshMaxPulledin(refreshMaxPulledin), + controllerThread(controllerThread), + maxBufferDepth(maxBufferDepth), + per2BankOffset(per2BankOffset), + rowColumnCommandBus(rowColumnCommandBus), + pseudoChannelMode(pseudoChannelMode) { } }; diff --git a/extensions/apps/traceAnalyzer/businessObjects/phases/dependencyinfos.h b/extensions/apps/traceAnalyzer/businessObjects/phases/dependencyinfos.h index 538c5e77..0cbdadcb 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/phases/dependencyinfos.h +++ b/extensions/apps/traceAnalyzer/businessObjects/phases/dependencyinfos.h @@ -61,20 +61,11 @@ public: DependencyInfos(); ~DependencyInfos(); - void setType(Type type) - { - mType = type; - } + void setType(Type type) { mType = type; } void addInfo(DependencyInfo); - const std::vector &getInfos() const - { - return mInfos; - } - size_t size() const - { - return mInfos.size(); - } + const std::vector& getInfos() const { return mInfos; } + size_t size() const { return mInfos.size(); } private: Type mType; diff --git a/extensions/apps/traceAnalyzer/businessObjects/phases/phase.cpp b/extensions/apps/traceAnalyzer/businessObjects/phases/phase.cpp index 71fba87e..0f229ef6 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/phases/phase.cpp +++ b/extensions/apps/traceAnalyzer/businessObjects/phases/phase.cpp @@ -44,8 +44,12 @@ #include -void Phase::draw(QPainter *painter, const QwtScaleMap &xMap, const QwtScaleMap &yMap, const QRectF &canvasRect, - bool highlight, const TraceDrawingProperties &drawingProperties) const +void Phase::draw(QPainter* painter, + const QwtScaleMap& xMap, + const QwtScaleMap& yMap, + const QRectF& canvasRect, + bool highlight, + const TraceDrawingProperties& drawingProperties) const { Q_UNUSED(canvasRect); @@ -70,20 +74,28 @@ void Phase::draw(QPainter *painter, const QwtScaleMap &xMap, const QwtScaleMap & for (auto yVal : getYVals(drawingProperties)) { - drawPhaseSymbol(span.Begin(), span.End(), yVal, drawingProperties.drawText, getPhaseSymbol(), painter, xMap, - yMap, drawingProperties.textColor); + drawPhaseSymbol(span.Begin(), + span.End(), + yVal, + drawingProperties.drawText, + getPhaseSymbol(), + painter, + xMap, + yMap, + drawingProperties.textColor); DependencyOptions drawDependenciesOptions = drawingProperties.drawDependenciesOption; if (drawDependenciesOptions.draw == DependencyOption::All || (drawDependenciesOptions.draw == DependencyOption::Selected && highlight)) { - drawPhaseDependencies(span.Begin(), span.End(), yVal, drawingProperties, painter, xMap, yMap); + drawPhaseDependencies( + span.Begin(), span.End(), yVal, drawingProperties, painter, xMap, yMap); } } for (Timespan spanOnCommandBus : spansOnCommandBus) { - for (const auto &line : drawingProperties.getTracePlotLines()) + for (const auto& line : drawingProperties.getTracePlotLines()) { if (line->data.type == AbstractTracePlotLineModel::RowCommandBusLine) { @@ -98,14 +110,21 @@ void Phase::draw(QPainter *painter, const QwtScaleMap &xMap, const QwtScaleMap & else if (line->data.type != AbstractTracePlotLineModel::CommandBusLine) continue; - drawPhaseSymbol(spanOnCommandBus.Begin(), spanOnCommandBus.End(), line->data.yVal, false, PhaseSymbol::Hexagon, painter, xMap, yMap, + drawPhaseSymbol(spanOnCommandBus.Begin(), + spanOnCommandBus.End(), + line->data.yVal, + false, + PhaseSymbol::Hexagon, + painter, + xMap, + yMap, drawingProperties.textColor); } } if (spanOnDataStrobe.End() != 0) { - for (const auto &line : drawingProperties.getTracePlotLines()) + for (const auto& line : drawingProperties.getTracePlotLines()) { if (line->data.type == AbstractTracePlotLineModel::PseudoChannel0Line) { @@ -120,14 +139,28 @@ void Phase::draw(QPainter *painter, const QwtScaleMap &xMap, const QwtScaleMap & else if (line->data.type != AbstractTracePlotLineModel::DataBusLine) continue; - drawPhaseSymbol(spanOnDataStrobe.Begin(), spanOnDataStrobe.End(), line->data.yVal, false, - PhaseSymbol::Hexagon, painter, xMap, yMap, drawingProperties.textColor); + drawPhaseSymbol(spanOnDataStrobe.Begin(), + spanOnDataStrobe.End(), + line->data.yVal, + false, + PhaseSymbol::Hexagon, + painter, + xMap, + yMap, + drawingProperties.textColor); } } } -void Phase::drawPhaseSymbol(traceTime begin, traceTime end, double y, bool drawtext, PhaseSymbol symbol, - QPainter *painter, const QwtScaleMap &xMap, const QwtScaleMap &yMap, const QColor& textColor) const +void Phase::drawPhaseSymbol(traceTime begin, + traceTime end, + double y, + bool drawtext, + PhaseSymbol symbol, + QPainter* painter, + const QwtScaleMap& xMap, + const QwtScaleMap& yMap, + const QColor& textColor) const { double yVal = yMap.transform(y); double symbolHeight = yMap.transform(0) - yMap.transform(hexagonHeight); @@ -143,20 +176,29 @@ void Phase::drawPhaseSymbol(traceTime begin, traceTime end, double y, bool drawt } else { - QPoint upperLeft(static_cast(xMap.transform(begin)), static_cast(yVal - symbolHeight / 2)); - QPoint bottomRight(static_cast(xMap.transform(end)), static_cast(yVal + symbolHeight / 2)); + QPoint upperLeft(static_cast(xMap.transform(begin)), + static_cast(yVal - symbolHeight / 2)); + QPoint bottomRight(static_cast(xMap.transform(end)), + static_cast(yVal + symbolHeight / 2)); painter->drawRect(QRect(upperLeft, bottomRight)); } if (drawtext) - drawText(painter, Name(), - QPoint(static_cast(xMap.transform(begin)), static_cast(yVal + symbolHeight / 2)), - TextPositioning::bottomRight, textColor); + drawText(painter, + Name(), + QPoint(static_cast(xMap.transform(begin)), + static_cast(yVal + symbolHeight / 2)), + TextPositioning::bottomRight, + textColor); } -void Phase::drawPhaseDependencies(traceTime begin, traceTime end, double y, - const TraceDrawingProperties &drawingProperties, QPainter *painter, - const QwtScaleMap &xMap, const QwtScaleMap &yMap) const +void Phase::drawPhaseDependencies(traceTime begin, + traceTime end, + double y, + const TraceDrawingProperties& drawingProperties, + QPainter* painter, + const QwtScaleMap& xMap, + const QwtScaleMap& yMap) const { QPen pen; pen.setWidth(2); @@ -172,7 +214,8 @@ void Phase::drawPhaseDependencies(traceTime begin, traceTime end, double y, size_t invisibleDeps = 0; - QPoint depLineTo(static_cast(xMap.transform(begin /* + (end + offset - begin)/4*/)), static_cast(yVal)); + QPoint depLineTo(static_cast(xMap.transform(begin /* + (end + offset - begin)/4*/)), + static_cast(yVal)); for (const auto& dep : mDependencies) { @@ -192,19 +235,23 @@ void Phase::drawPhaseDependencies(traceTime begin, traceTime end, double y, if (invisibleDeps > 0) { - QPoint invisibleDepsPoint(static_cast(xMap.transform(begin + (end + offset - begin) / 2)), - static_cast(yVal + 0.1 * symbolHeight)); - drawText(painter, QString::number(invisibleDeps), invisibleDepsPoint, TextPositioning::centerCenter); + QPoint invisibleDepsPoint( + static_cast(xMap.transform(begin + (end + offset - begin) / 2)), + static_cast(yVal + 0.1 * symbolHeight)); + drawText(painter, + QString::number(invisibleDeps), + invisibleDepsPoint, + TextPositioning::centerCenter); } painter->restore(); } -std::vector Phase::getYVals(const TraceDrawingProperties &drawingProperties) const +std::vector Phase::getYVals(const TraceDrawingProperties& drawingProperties) const { std::vector yVals; - for (const auto &line : drawingProperties.getTracePlotLines()) + for (const auto& line : drawingProperties.getTracePlotLines()) { if (line->data.type != AbstractTracePlotLineModel::BankLine) continue; @@ -223,14 +270,15 @@ std::vector Phase::getYVals(const TraceDrawingProperties &drawingProperties break; case Granularity::Groupwise: shouldBeDrawn = (rank == drawnRank) && (bank % drawingProperties.banksPerGroup == - drawnBank % drawingProperties.banksPerGroup); + drawnBank % drawingProperties.banksPerGroup); break; case Granularity::Bankwise: shouldBeDrawn = (bank == drawnBank); break; case Granularity::TwoBankwise: - shouldBeDrawn = (bank == drawnBank) || ((bank + drawingProperties.per2BankOffset) == drawnBank); + shouldBeDrawn = + (bank == drawnBank) || ((bank + drawingProperties.per2BankOffset) == drawnBank); break; } @@ -241,11 +289,11 @@ std::vector Phase::getYVals(const TraceDrawingProperties &drawingProperties return yVals; } -std::vector REQ::getYVals(const TraceDrawingProperties &drawingProperties) const +std::vector REQ::getYVals(const TraceDrawingProperties& drawingProperties) const { std::vector yVals; - for (const auto &line : drawingProperties.getTracePlotLines()) + for (const auto& line : drawingProperties.getTracePlotLines()) { if (line->data.type != AbstractTracePlotLineModel::RequestLine) continue; @@ -256,11 +304,11 @@ std::vector REQ::getYVals(const TraceDrawingProperties &drawingProperties) return yVals; } -std::vector RESP::getYVals(const TraceDrawingProperties &drawingProperties) const +std::vector RESP::getYVals(const TraceDrawingProperties& drawingProperties) const { std::vector yVals; - for (const auto &line : drawingProperties.getTracePlotLines()) + for (const auto& line : drawingProperties.getTracePlotLines()) { if (line->data.type != AbstractTracePlotLineModel::ResponseLine) continue; @@ -271,9 +319,10 @@ std::vector RESP::getYVals(const TraceDrawingProperties &drawingProperties) return yVals; } -QColor Phase::getColor(const TraceDrawingProperties &drawingProperties) const +QColor Phase::getColor(const TraceDrawingProperties& drawingProperties) const { - switch (drawingProperties.colorGrouping) { + switch (drawingProperties.colorGrouping) + { case ColorGrouping::PhaseType: return getPhaseColor(); break; @@ -295,7 +344,9 @@ Qt::BrushStyle Phase::getBrushStyle() const return Qt::SolidPattern; } -bool Phase::isSelected(Timespan timespan, double yVal, const TraceDrawingProperties &drawingProperties) const +bool Phase::isSelected(Timespan timespan, + double yVal, + const TraceDrawingProperties& drawingProperties) const { if (span.overlaps(timespan)) { @@ -308,7 +359,7 @@ bool Phase::isSelected(Timespan timespan, double yVal, const TraceDrawingPropert { if (_span.overlaps(timespan)) { - for (const auto &line : drawingProperties.getTracePlotLines()) + for (const auto& line : drawingProperties.getTracePlotLines()) { if (line->data.type == AbstractTracePlotLineModel::RowCommandBusLine) { @@ -331,7 +382,7 @@ bool Phase::isSelected(Timespan timespan, double yVal, const TraceDrawingPropert if (spanOnDataStrobe.End() != 0 && spanOnDataStrobe.overlaps(timespan)) { - for (const auto &line : drawingProperties.getTracePlotLines()) + for (const auto& line : drawingProperties.getTracePlotLines()) { if (line->data.type == AbstractTracePlotLineModel::PseudoChannel0Line) { @@ -356,8 +407,8 @@ bool Phase::isSelected(Timespan timespan, double yVal, const TraceDrawingPropert bool Phase::isColumnCommand() const { - if (dynamic_cast(this) || dynamic_cast(this) || dynamic_cast(this) || - dynamic_cast(this)) + if (dynamic_cast(this) || dynamic_cast(this) || + dynamic_cast(this) || dynamic_cast(this)) return true; else return false; diff --git a/extensions/apps/traceAnalyzer/businessObjects/phases/phase.h b/extensions/apps/traceAnalyzer/businessObjects/phases/phase.h index 089ef799..4d3756b3 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/phases/phase.h +++ b/extensions/apps/traceAnalyzer/businessObjects/phases/phase.h @@ -51,7 +51,7 @@ #include typedef unsigned int ID; -//enum TextPositioning; +// enum TextPositioning; class Transaction; enum class RelevantAttributes @@ -77,61 +77,65 @@ inline RelevantAttributes operator&(RelevantAttributes a, RelevantAttributes b) class Phase { public: - Phase(ID id, Timespan span, Timespan spanOnDataStrobe, unsigned int rank, unsigned int bankGroup, - unsigned int bank, unsigned int row, unsigned int column, unsigned int burstLength, - traceTime clk, const std::shared_ptr &transaction, std::vector spansOnCommandBus, - unsigned int groupsPerRank, unsigned int banksPerGroup) : - id(id), span(span), spanOnDataStrobe(spanOnDataStrobe), - rank(rank), bankGroup(bankGroup), bank(bank), row(row), column(column), burstLength(burstLength), - clk(clk), transaction(transaction), spansOnCommandBus(std::move(spansOnCommandBus)), - groupsPerRank(groupsPerRank), banksPerGroup(banksPerGroup), - hexagonHeight(0.6), captionPosition(TextPositioning::bottomRight) {} + Phase(ID id, + Timespan span, + Timespan spanOnDataStrobe, + unsigned int rank, + unsigned int bankGroup, + unsigned int bank, + unsigned int row, + unsigned int column, + unsigned int burstLength, + traceTime clk, + const std::shared_ptr& transaction, + std::vector spansOnCommandBus, + unsigned int groupsPerRank, + unsigned int banksPerGroup) : + id(id), + span(span), + spanOnDataStrobe(spanOnDataStrobe), + rank(rank), + bankGroup(bankGroup), + bank(bank), + row(row), + column(column), + burstLength(burstLength), + clk(clk), + transaction(transaction), + spansOnCommandBus(std::move(spansOnCommandBus)), + groupsPerRank(groupsPerRank), + banksPerGroup(banksPerGroup), + hexagonHeight(0.6), + captionPosition(TextPositioning::bottomRight) + { + } - void draw(QPainter *painter, const QwtScaleMap &xMap, const QwtScaleMap &yMap, - const QRectF &canvasRect, bool highlight, - const TraceDrawingProperties &drawingProperties) const; - bool isSelected(Timespan timespan, double yVal, const TraceDrawingProperties &drawingproperties) const; + void draw(QPainter* painter, + const QwtScaleMap& xMap, + const QwtScaleMap& yMap, + const QRectF& canvasRect, + bool highlight, + const TraceDrawingProperties& drawingProperties) const; + bool isSelected(Timespan timespan, + double yVal, + const TraceDrawingProperties& drawingproperties) const; bool isColumnCommand() const; - const Timespan &Span() const - { - return span; - } + const Timespan& Span() const { return span; } - ID Id() const - { - return id; - } + ID Id() const { return id; } - unsigned int getRank() const - { - return rank; - } + unsigned int getRank() const { return rank; } - unsigned int getBankGroup() const - { - return bankGroup % groupsPerRank; - } + unsigned int getBankGroup() const { return bankGroup % groupsPerRank; } - unsigned int getBank() const - { - return bank % banksPerGroup; - } + unsigned int getBank() const { return bank % banksPerGroup; } - unsigned int getRow() const - { - return row; - } + unsigned int getRow() const { return row; } - unsigned int getColumn() const - { - return column; - } + unsigned int getColumn() const { return column; } - unsigned int getBurstLength() const - { - return burstLength; - } + unsigned int getBurstLength() const { return burstLength; } virtual RelevantAttributes getRelevantAttributes() const = 0; @@ -153,26 +157,43 @@ protected: double hexagonHeight; TextPositioning captionPosition; - enum PhaseSymbol {Hexagon, Rect}; + enum PhaseSymbol + { + Hexagon, + Rect + }; virtual PhaseSymbol getPhaseSymbol() const; virtual Qt::BrushStyle getBrushStyle() const; - virtual QColor getColor(const TraceDrawingProperties &drawingProperties) const; + virtual QColor getColor(const TraceDrawingProperties& drawingProperties) const; virtual QColor getPhaseColor() const = 0; - virtual std::vector getYVals(const TraceDrawingProperties &drawingProperties) const; - virtual void drawPhaseSymbol(traceTime begin, traceTime end, double y, - bool drawtext, PhaseSymbol symbol, QPainter *painter, const QwtScaleMap &xMap, - const QwtScaleMap &yMap, const QColor& textColor) const; - virtual void drawPhaseDependencies(traceTime begin, traceTime end, double y, - const TraceDrawingProperties &drawingProperties, QPainter *painter, - const QwtScaleMap &xMap, const QwtScaleMap &yMap) const; + virtual std::vector getYVals(const TraceDrawingProperties& drawingProperties) const; + virtual void drawPhaseSymbol(traceTime begin, + traceTime end, + double y, + bool drawtext, + PhaseSymbol symbol, + QPainter* painter, + const QwtScaleMap& xMap, + const QwtScaleMap& yMap, + const QColor& textColor) const; + virtual void drawPhaseDependencies(traceTime begin, + traceTime end, + double y, + const TraceDrawingProperties& drawingProperties, + QPainter* painter, + const QwtScaleMap& xMap, + const QwtScaleMap& yMap) const; - enum class Granularity {Bankwise, TwoBankwise, Groupwise, Rankwise}; - - virtual Granularity getGranularity() const + enum class Granularity { - return Granularity::Bankwise; - } + Bankwise, + TwoBankwise, + Groupwise, + Rankwise + }; + + virtual Granularity getGranularity() const { return Granularity::Bankwise; } friend class PhaseDependency; }; @@ -183,21 +204,15 @@ public: using Phase::Phase; protected: - QColor getPhaseColor() const override - { - return ColorGenerator::getColor(1); - } - QString Name() const final - { - return "REQ"; - } + QColor getPhaseColor() const override { return ColorGenerator::getColor(1); } + QString Name() const final { return "REQ"; } RelevantAttributes getRelevantAttributes() const override { return static_cast(0); } - std::vector getYVals(const TraceDrawingProperties &drawingProperties) const override; + std::vector getYVals(const TraceDrawingProperties& drawingProperties) const override; }; class RESP final : public Phase @@ -206,21 +221,15 @@ public: using Phase::Phase; protected: - QColor getPhaseColor() const override - { - return ColorGenerator::getColor(1); - } - QString Name() const override - { - return "RESP"; - } + QColor getPhaseColor() const override { return ColorGenerator::getColor(1); } + QString Name() const override { return "RESP"; } RelevantAttributes getRelevantAttributes() const override { return static_cast(0); } - std::vector getYVals(const TraceDrawingProperties &drawingProperties) const override; + std::vector getYVals(const TraceDrawingProperties& drawingProperties) const override; }; class PREPB final : public Phase @@ -229,14 +238,8 @@ public: using Phase::Phase; protected: - QColor getPhaseColor() const override - { - return ColorGenerator::getColor(1); - } - QString Name() const override - { - return "PREPB"; - } + QColor getPhaseColor() const override { return ColorGenerator::getColor(1); } + QString Name() const override { return "PREPB"; } RelevantAttributes getRelevantAttributes() const override { @@ -250,27 +253,15 @@ public: using Phase::Phase; protected: - QString Name() const override - { - return "PRESB"; - } - virtual std::vector getTimesOnCommandBus() const - { - return {span.Begin()}; - } - QColor getColor(const TraceDrawingProperties &drawingProperties) const override + QString Name() const override { return "PRESB"; } + virtual std::vector getTimesOnCommandBus() const { return {span.Begin()}; } + QColor getColor(const TraceDrawingProperties& drawingProperties) const override { Q_UNUSED(drawingProperties) return getPhaseColor(); } - QColor getPhaseColor() const override - { - return ColorGenerator::getColor(1); - } - Granularity getGranularity() const override - { - return Granularity::Groupwise; - } + QColor getPhaseColor() const override { return ColorGenerator::getColor(1); } + Granularity getGranularity() const override { return Granularity::Groupwise; } RelevantAttributes getRelevantAttributes() const override { @@ -284,32 +275,17 @@ public: using Phase::Phase; protected: - QString Name() const override - { - return "PREAB"; - } - virtual std::vector getTimesOnCommandBus() const - { - return {span.Begin()}; - } - QColor getColor(const TraceDrawingProperties &drawingProperties) const override + QString Name() const override { return "PREAB"; } + virtual std::vector getTimesOnCommandBus() const { return {span.Begin()}; } + QColor getColor(const TraceDrawingProperties& drawingProperties) const override { Q_UNUSED(drawingProperties) return getPhaseColor(); } - QColor getPhaseColor() const override - { - return ColorGenerator::getColor(10); - } - Granularity getGranularity() const override - { - return Granularity::Rankwise; - } + QColor getPhaseColor() const override { return ColorGenerator::getColor(10); } + Granularity getGranularity() const override { return Granularity::Rankwise; } - RelevantAttributes getRelevantAttributes() const override - { - return RelevantAttributes::Rank; - } + RelevantAttributes getRelevantAttributes() const override { return RelevantAttributes::Rank; } }; class ACT final : public Phase @@ -318,14 +294,8 @@ public: using Phase::Phase; protected: - QColor getPhaseColor() const override - { - return ColorGenerator::getColor(3); - } - QString Name() const override - { - return "ACT"; - } + QColor getPhaseColor() const override { return ColorGenerator::getColor(3); } + QString Name() const override { return "ACT"; } RelevantAttributes getRelevantAttributes() const override { @@ -340,14 +310,8 @@ public: using Phase::Phase; protected: - QColor getPhaseColor() const override - { - return ColorGenerator::getColor(4); - } - QString Name() const override - { - return "RD"; - } + QColor getPhaseColor() const override { return ColorGenerator::getColor(4); } + QString Name() const override { return "RD"; } RelevantAttributes getRelevantAttributes() const override { @@ -362,14 +326,8 @@ public: using Phase::Phase; protected: - QColor getPhaseColor() const override - { - return ColorGenerator::getColor(5); - } - QString Name() const override - { - return "RDA"; - } + QColor getPhaseColor() const override { return ColorGenerator::getColor(5); } + QString Name() const override { return "RDA"; } RelevantAttributes getRelevantAttributes() const override { @@ -384,14 +342,8 @@ public: using Phase::Phase; protected: - QColor getPhaseColor() const override - { - return ColorGenerator::getColor(6); - } - QString Name() const override - { - return "WR"; - } + QColor getPhaseColor() const override { return ColorGenerator::getColor(6); } + QString Name() const override { return "WR"; } RelevantAttributes getRelevantAttributes() const override { @@ -406,14 +358,8 @@ public: using Phase::Phase; protected: - QColor getPhaseColor() const override - { - return ColorGenerator::getColor(6); - } - QString Name() const override - { - return "MWR"; - } + QColor getPhaseColor() const override { return ColorGenerator::getColor(6); } + QString Name() const override { return "MWR"; } RelevantAttributes getRelevantAttributes() const override { @@ -428,14 +374,8 @@ public: using Phase::Phase; protected: - QColor getPhaseColor() const override - { - return ColorGenerator::getColor(7); - } - QString Name() const override - { - return "WRA"; - } + QColor getPhaseColor() const override { return ColorGenerator::getColor(7); } + QString Name() const override { return "WRA"; } RelevantAttributes getRelevantAttributes() const override { @@ -450,14 +390,8 @@ public: using Phase::Phase; protected: - QColor getPhaseColor() const override - { - return ColorGenerator::getColor(7); - } - QString Name() const override - { - return "MWRA"; - } + QColor getPhaseColor() const override { return ColorGenerator::getColor(7); } + QString Name() const override { return "MWRA"; } RelevantAttributes getRelevantAttributes() const override { @@ -472,15 +406,9 @@ public: using Phase::Phase; protected: - QString Name() const override - { - return "REF"; - } - virtual std::vector getTimesOnCommandBus() const - { - return {span.Begin()}; - } - QColor getColor(const TraceDrawingProperties &drawingProperties) const override + QString Name() const override { return "REF"; } + virtual std::vector getTimesOnCommandBus() const { return {span.Begin()}; } + QColor getColor(const TraceDrawingProperties& drawingProperties) const override { Q_UNUSED(drawingProperties) return getPhaseColor(); @@ -499,19 +427,10 @@ public: using AUTO_REFRESH::AUTO_REFRESH; protected: - QString Name() const override - { - return "REFAB"; - } - Granularity getGranularity() const override - { - return Granularity::Rankwise; - } + QString Name() const override { return "REFAB"; } + Granularity getGranularity() const override { return Granularity::Rankwise; } - RelevantAttributes getRelevantAttributes() const override - { - return RelevantAttributes::Rank; - } + RelevantAttributes getRelevantAttributes() const override { return RelevantAttributes::Rank; } }; class RFMAB final : public AUTO_REFRESH @@ -520,14 +439,8 @@ public: using AUTO_REFRESH::AUTO_REFRESH; protected: - QString Name() const override - { - return "RFMAB"; - } - Granularity getGranularity() const override - { - return Granularity::Rankwise; - } + QString Name() const override { return "RFMAB"; } + Granularity getGranularity() const override { return Granularity::Rankwise; } QColor getPhaseColor() const override { auto phaseColor = QColor(Qt::darkRed); @@ -535,10 +448,7 @@ protected: return phaseColor; } - RelevantAttributes getRelevantAttributes() const override - { - return RelevantAttributes::Rank; - } + RelevantAttributes getRelevantAttributes() const override { return RelevantAttributes::Rank; } }; class REFPB final : public AUTO_REFRESH @@ -547,10 +457,7 @@ public: using AUTO_REFRESH::AUTO_REFRESH; protected: - QString Name() const override - { - return "REFPB"; - } + QString Name() const override { return "REFPB"; } RelevantAttributes getRelevantAttributes() const override { @@ -564,10 +471,7 @@ public: using AUTO_REFRESH::AUTO_REFRESH; protected: - QString Name() const override - { - return "RFMPB"; - } + QString Name() const override { return "RFMPB"; } QColor getPhaseColor() const override { auto phaseColor = QColor(Qt::darkRed); @@ -587,14 +491,8 @@ public: using AUTO_REFRESH::AUTO_REFRESH; protected: - QString Name() const override - { - return "REFP2B"; - } - Granularity getGranularity() const override - { - return Granularity::TwoBankwise; - } + QString Name() const override { return "REFP2B"; } + Granularity getGranularity() const override { return Granularity::TwoBankwise; } RelevantAttributes getRelevantAttributes() const override { @@ -608,14 +506,8 @@ public: using AUTO_REFRESH::AUTO_REFRESH; protected: - QString Name() const override - { - return "RFMP2B"; - } - Granularity getGranularity() const override - { - return Granularity::TwoBankwise; - } + QString Name() const override { return "RFMP2B"; } + Granularity getGranularity() const override { return Granularity::TwoBankwise; } QColor getPhaseColor() const override { auto phaseColor = QColor(Qt::darkRed); @@ -635,14 +527,8 @@ public: using AUTO_REFRESH::AUTO_REFRESH; protected: - QString Name() const override - { - return "REFSB"; - } - Granularity getGranularity() const override - { - return Granularity::Groupwise; - } + QString Name() const override { return "REFSB"; } + Granularity getGranularity() const override { return Granularity::Groupwise; } RelevantAttributes getRelevantAttributes() const override { @@ -656,14 +542,8 @@ public: using AUTO_REFRESH::AUTO_REFRESH; protected: - QString Name() const override - { - return "RFMSB"; - } - Granularity getGranularity() const override - { - return Granularity::Groupwise; - } + QString Name() const override { return "RFMSB"; } + Granularity getGranularity() const override { return Granularity::Groupwise; } QColor getPhaseColor() const override { auto phaseColor = QColor(Qt::darkRed); @@ -684,27 +564,15 @@ public: virtual ~PDNAB() = default; protected: - QString Name() const override - { - return "PDNAB"; - } - Qt::BrushStyle getBrushStyle() const override - { - return Qt::Dense6Pattern; - } - QColor getColor(const TraceDrawingProperties &drawingProperties) const override + QString Name() const override { return "PDNAB"; } + Qt::BrushStyle getBrushStyle() const override { return Qt::Dense6Pattern; } + QColor getColor(const TraceDrawingProperties& drawingProperties) const override { Q_UNUSED(drawingProperties) return getPhaseColor(); } - QColor getPhaseColor() const override - { - return {Qt::black}; - } - Phase::PhaseSymbol getPhaseSymbol() const override - { - return PhaseSymbol::Rect; - } + QColor getPhaseColor() const override { return {Qt::black}; } + Phase::PhaseSymbol getPhaseSymbol() const override { return PhaseSymbol::Rect; } RelevantAttributes getRelevantAttributes() const override { @@ -718,19 +586,10 @@ public: using PDNAB::PDNAB; protected: - QString Name() const override - { - return "PDNA"; - } - Granularity getGranularity() const override - { - return Granularity::Rankwise; - } + QString Name() const override { return "PDNA"; } + Granularity getGranularity() const override { return Granularity::Rankwise; } - RelevantAttributes getRelevantAttributes() const override - { - return RelevantAttributes::Rank; - } + RelevantAttributes getRelevantAttributes() const override { return RelevantAttributes::Rank; } }; class PDNPB : public Phase @@ -740,27 +599,15 @@ public: virtual ~PDNPB() = default; protected: - QString Name() const override - { - return "PDNPB"; - } - Qt::BrushStyle getBrushStyle() const override - { - return Qt::Dense4Pattern; - } - QColor getColor(const TraceDrawingProperties &drawingProperties) const override + QString Name() const override { return "PDNPB"; } + Qt::BrushStyle getBrushStyle() const override { return Qt::Dense4Pattern; } + QColor getColor(const TraceDrawingProperties& drawingProperties) const override { Q_UNUSED(drawingProperties) return getPhaseColor(); } - QColor getPhaseColor() const override - { - return {Qt::black}; - } - Phase::PhaseSymbol getPhaseSymbol() const override - { - return PhaseSymbol::Rect; - } + QColor getPhaseColor() const override { return {Qt::black}; } + Phase::PhaseSymbol getPhaseSymbol() const override { return PhaseSymbol::Rect; } RelevantAttributes getRelevantAttributes() const override { @@ -774,18 +621,9 @@ public: using PDNPB::PDNPB; protected: - QString Name() const override - { - return "PDNP"; - } - Granularity getGranularity() const override - { - return Granularity::Rankwise; - } - RelevantAttributes getRelevantAttributes() const override - { - return RelevantAttributes::Rank; - } + QString Name() const override { return "PDNP"; } + Granularity getGranularity() const override { return Granularity::Rankwise; } + RelevantAttributes getRelevantAttributes() const override { return RelevantAttributes::Rank; } }; class SREFB : public Phase @@ -795,27 +633,15 @@ public: virtual ~SREFB() = default; protected: - QString Name() const override - { - return "SREFB"; - } - Qt::BrushStyle getBrushStyle() const override - { - return Qt::Dense1Pattern; - } - QColor getColor(const TraceDrawingProperties &drawingProperties) const override + QString Name() const override { return "SREFB"; } + Qt::BrushStyle getBrushStyle() const override { return Qt::Dense1Pattern; } + QColor getColor(const TraceDrawingProperties& drawingProperties) const override { Q_UNUSED(drawingProperties) return getPhaseColor(); } - QColor getPhaseColor() const override - { - return {Qt::black}; - } - Phase::PhaseSymbol getPhaseSymbol() const override - { - return PhaseSymbol::Rect; - } + QColor getPhaseColor() const override { return {Qt::black}; } + Phase::PhaseSymbol getPhaseSymbol() const override { return PhaseSymbol::Rect; } RelevantAttributes getRelevantAttributes() const override { @@ -829,18 +655,9 @@ public: using SREFB::SREFB; protected: - QString Name() const override - { - return "SREF"; - } - Granularity getGranularity() const override - { - return Granularity::Rankwise; - } - RelevantAttributes getRelevantAttributes() const override - { - return RelevantAttributes::Rank; - } + QString Name() const override { return "SREF"; } + Granularity getGranularity() const override { return Granularity::Rankwise; } + RelevantAttributes getRelevantAttributes() const override { return RelevantAttributes::Rank; } }; #endif // BANKPHASE_H diff --git a/extensions/apps/traceAnalyzer/businessObjects/phases/phasedependency.cpp b/extensions/apps/traceAnalyzer/businessObjects/phases/phasedependency.cpp index 5529d099..190cb3c2 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/phases/phasedependency.cpp +++ b/extensions/apps/traceAnalyzer/businessObjects/phases/phasedependency.cpp @@ -37,7 +37,9 @@ #include "phase.h" #include -PhaseDependency::PhaseDependency(DependencyType type, QString timeDependency, std::shared_ptr dependency) +PhaseDependency::PhaseDependency(DependencyType type, + QString timeDependency, + std::shared_ptr dependency) { mType = type; mTimeDependency = timeDependency; @@ -56,8 +58,11 @@ PhaseDependency::~PhaseDependency() { } -bool PhaseDependency::draw(QPoint &end, const TraceDrawingProperties &drawingProperties, QPainter *painter, - const QwtScaleMap &xMap, const QwtScaleMap &yMap) +bool PhaseDependency::draw(QPoint& end, + const TraceDrawingProperties& drawingProperties, + QPainter* painter, + const QwtScaleMap& xMap, + const QwtScaleMap& yMap) { if (mIsInvisible) return false; @@ -78,26 +83,33 @@ bool PhaseDependency::draw(QPoint &end, const TraceDrawingProperties &drawingPro return drawn; } -void PhaseDependency::mDraw(QPoint &end, double depY, const TraceDrawingProperties &drawingProperties, - QPainter *painter, const QwtScaleMap &xMap, const QwtScaleMap &yMap) +void PhaseDependency::mDraw(QPoint& end, + double depY, + const TraceDrawingProperties& drawingProperties, + QPainter* painter, + const QwtScaleMap& xMap, + const QwtScaleMap& yMap) { traceTime depBegin = mDependency->span.Begin(); traceTime depEnd = mDependency->span.End(); - traceTime depOffset = (depBegin == depEnd) ? static_cast(0.05 * mDependency->clk) : 0; + traceTime depOffset = + (depBegin == depEnd) ? static_cast(0.05 * mDependency->clk) : 0; double depYVal = yMap.transform(depY); double depSymbolHeight = yMap.transform(0) - yMap.transform(mDependency->hexagonHeight); - QPoint depLineFrom(static_cast(xMap.transform(depBegin /* + (depEnd + depOffset - depBegin)/4*/)), - static_cast(depYVal)); + QPoint depLineFrom( + static_cast(xMap.transform(depBegin /* + (depEnd + depOffset - depBegin)/4*/)), + static_cast(depYVal)); QLineF line(depLineFrom, end); double angle = std::atan2(-line.dy(), line.dx()); qreal arrowSize = 10; - QPointF arrowP1 = line.p2() - QPointF(sin(angle + M_PI / 3) * arrowSize, cos(angle + M_PI / 3) * arrowSize); - QPointF arrowP2 = - line.p2() - QPointF(sin(angle + M_PI - M_PI / 3) * arrowSize, cos(angle + M_PI - M_PI / 3) * arrowSize); + QPointF arrowP1 = + line.p2() - QPointF(sin(angle + M_PI / 3) * arrowSize, cos(angle + M_PI / 3) * arrowSize); + QPointF arrowP2 = line.p2() - QPointF(sin(angle + M_PI - M_PI / 3) * arrowSize, + cos(angle + M_PI - M_PI / 3) * arrowSize); QPolygonF arrowHead; arrowHead << line.p2() << arrowP1 << arrowP2; @@ -109,7 +121,8 @@ void PhaseDependency::mDraw(QPoint &end, double depY, const TraceDrawingProperti if (drawingProperties.drawDependenciesOption.text == DependencyTextOption::Enabled) { - QPoint textPosition(line.x1() + (line.x2() - line.x1()) / 2, line.y1() + (line.y2() - line.y1()) / 2); + QPoint textPosition(line.x1() + (line.x2() - line.x1()) / 2, + line.y1() + (line.y2() - line.y1()) / 2); auto alignment = TextPositioning::topRight; if (textPosition.y() == line.y1()) @@ -128,38 +141,39 @@ void PhaseDependency::mDraw(QPoint &end, double depY, const TraceDrawingProperti } } -QString PhaseDependency::dependencyTypeName(DependencyType dtype) { - switch(dtype) { - case IntraBank: - return "IntraBank"; +QString PhaseDependency::dependencyTypeName(DependencyType dtype) +{ + switch (dtype) + { + case IntraBank: + return "IntraBank"; - case IntraBankGroup: - return "IntraBankGroup"; - - case IntraBankInGroup: - return "IntraBankInGroup"; + case IntraBankGroup: + return "IntraBankGroup"; - case IntraRank: - return "IntraRank"; + case IntraBankInGroup: + return "IntraBankInGroup"; - case IntraLogicalRank: - return "IntraLogicalRank"; + case IntraRank: + return "IntraRank"; - case IntraPhysicalRank: - return "IntraPhysicalRank"; + case IntraLogicalRank: + return "IntraLogicalRank"; - case IntraDIMMRank: - return "IntraDIMMRank"; + case IntraPhysicalRank: + return "IntraPhysicalRank"; - case InterRank: - return "InterRank"; + case IntraDIMMRank: + return "IntraDIMMRank"; - case InterDIMMRank: - return "InterDIMMRank"; + case InterRank: + return "InterRank"; - default: - // TODO - maybe throw? - return ""; + case InterDIMMRank: + return "InterDIMMRank"; + default: + // TODO - maybe throw? + return ""; } } diff --git a/extensions/apps/traceAnalyzer/businessObjects/phases/phasedependency.h b/extensions/apps/traceAnalyzer/businessObjects/phases/phasedependency.h index 08317954..28d9c939 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/phases/phasedependency.h +++ b/extensions/apps/traceAnalyzer/businessObjects/phases/phasedependency.h @@ -66,13 +66,13 @@ public: PhaseDependency(DependencyType type, QString timeDependency); ~PhaseDependency(); - bool isVisible() - { - return !mIsInvisible; - } + bool isVisible() { return !mIsInvisible; } - bool draw(QPoint &end, const TraceDrawingProperties &drawingProperties, QPainter *painter, const QwtScaleMap &xMap, - const QwtScaleMap &yMap); + bool draw(QPoint& end, + const TraceDrawingProperties& drawingProperties, + QPainter* painter, + const QwtScaleMap& xMap, + const QwtScaleMap& yMap); static QString dependencyTypeName(DependencyType); @@ -83,6 +83,10 @@ protected: bool mIsInvisible = false; - void mDraw(QPoint &end, double depY, const TraceDrawingProperties &drawingProperties, QPainter *painter, - const QwtScaleMap &xMap, const QwtScaleMap &yMap); + void mDraw(QPoint& end, + double depY, + const TraceDrawingProperties& drawingProperties, + QPainter* painter, + const QwtScaleMap& xMap, + const QwtScaleMap& yMap); }; diff --git a/extensions/apps/traceAnalyzer/businessObjects/phases/phasefactory.cpp b/extensions/apps/traceAnalyzer/businessObjects/phases/phasefactory.cpp index 15597832..4327ab30 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/phases/phasefactory.cpp +++ b/extensions/apps/traceAnalyzer/businessObjects/phases/phasefactory.cpp @@ -36,116 +36,415 @@ */ #include "phasefactory.h" -#include -#include "phase.h" +#include "businessObjects/timespan.h" #include "businessObjects/transaction.h" #include "data/tracedb.h" -#include "businessObjects/timespan.h" +#include "phase.h" +#include -std::shared_ptr PhaseFactory::createPhase(ID id, const QString &dbPhaseName, - Timespan span, Timespan spanOnDataStrobe, - unsigned int rank, unsigned int bankGroup, unsigned int bank, unsigned int row, unsigned int column, - unsigned int burstLength, const std::shared_ptr &trans, TraceDB &database) +std::shared_ptr PhaseFactory::createPhase(ID id, + const QString& dbPhaseName, + Timespan span, + Timespan spanOnDataStrobe, + unsigned int rank, + unsigned int bankGroup, + unsigned int bank, + unsigned int row, + unsigned int column, + unsigned int burstLength, + const std::shared_ptr& trans, + TraceDB& database) { auto clk = static_cast(database.getGeneralInfo().clkPeriod); unsigned int groupsPerRank = database.getGeneralInfo().groupsPerRank; unsigned int banksPerGroup = database.getGeneralInfo().banksPerGroup; - const CommandLengths &cl = database.getCommandLengths(); + const CommandLengths& cl = database.getCommandLengths(); if (dbPhaseName == "REQ") - return std::shared_ptr(new REQ(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, - burstLength, clk, trans, {}, groupsPerRank, banksPerGroup)); + return std::shared_ptr(new REQ(id, + span, + spanOnDataStrobe, + rank, + bankGroup, + bank, + row, + column, + burstLength, + clk, + trans, + {}, + groupsPerRank, + banksPerGroup)); if (dbPhaseName == "RESP") - return std::shared_ptr(new RESP(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, - burstLength, clk, trans, {}, groupsPerRank, banksPerGroup)); + return std::shared_ptr(new RESP(id, + span, + spanOnDataStrobe, + rank, + bankGroup, + bank, + row, + column, + burstLength, + clk, + trans, + {}, + groupsPerRank, + banksPerGroup)); if (dbPhaseName == "PREPB") - return std::shared_ptr(new PREPB(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, - burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.PREPB)}, groupsPerRank, banksPerGroup)); + return std::shared_ptr( + new PREPB(id, + span, + spanOnDataStrobe, + rank, + bankGroup, + bank, + row, + column, + burstLength, + clk, + trans, + {Timespan(span.Begin(), span.Begin() + clk * cl.PREPB)}, + groupsPerRank, + banksPerGroup)); if (dbPhaseName == "ACT") - return std::shared_ptr(new ACT(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, - burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.ACT)}, groupsPerRank, banksPerGroup)); + return std::shared_ptr(new ACT(id, + span, + spanOnDataStrobe, + rank, + bankGroup, + bank, + row, + column, + burstLength, + clk, + trans, + {Timespan(span.Begin(), span.Begin() + clk * cl.ACT)}, + groupsPerRank, + banksPerGroup)); if (dbPhaseName == "PREAB") - return std::shared_ptr(new PREAB(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, - burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.PREAB)}, groupsPerRank, banksPerGroup)); + return std::shared_ptr( + new PREAB(id, + span, + spanOnDataStrobe, + rank, + bankGroup, + bank, + row, + column, + burstLength, + clk, + trans, + {Timespan(span.Begin(), span.Begin() + clk * cl.PREAB)}, + groupsPerRank, + banksPerGroup)); if (dbPhaseName == "REFAB") - return std::shared_ptr(new REFAB(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, - burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.REFAB)}, groupsPerRank, banksPerGroup)); + return std::shared_ptr( + new REFAB(id, + span, + spanOnDataStrobe, + rank, + bankGroup, + bank, + row, + column, + burstLength, + clk, + trans, + {Timespan(span.Begin(), span.Begin() + clk * cl.REFAB)}, + groupsPerRank, + banksPerGroup)); if (dbPhaseName == "RFMAB") - return std::shared_ptr(new RFMAB(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, - burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.RFMAB)}, groupsPerRank, banksPerGroup)); + return std::shared_ptr( + new RFMAB(id, + span, + spanOnDataStrobe, + rank, + bankGroup, + bank, + row, + column, + burstLength, + clk, + trans, + {Timespan(span.Begin(), span.Begin() + clk * cl.RFMAB)}, + groupsPerRank, + banksPerGroup)); if (dbPhaseName == "REFPB") - return std::shared_ptr(new REFPB(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, - burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.REFPB)}, groupsPerRank, banksPerGroup)); + return std::shared_ptr( + new REFPB(id, + span, + spanOnDataStrobe, + rank, + bankGroup, + bank, + row, + column, + burstLength, + clk, + trans, + {Timespan(span.Begin(), span.Begin() + clk * cl.REFPB)}, + groupsPerRank, + banksPerGroup)); if (dbPhaseName == "RFMPB") - return std::shared_ptr(new RFMPB(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, - burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.RFMPB)}, groupsPerRank, banksPerGroup)); + return std::shared_ptr( + new RFMPB(id, + span, + spanOnDataStrobe, + rank, + bankGroup, + bank, + row, + column, + burstLength, + clk, + trans, + {Timespan(span.Begin(), span.Begin() + clk * cl.RFMPB)}, + groupsPerRank, + banksPerGroup)); if (dbPhaseName == "REFP2B") - return std::shared_ptr(new REFP2B(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, - burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.REFP2B)}, groupsPerRank, banksPerGroup)); + return std::shared_ptr( + new REFP2B(id, + span, + spanOnDataStrobe, + rank, + bankGroup, + bank, + row, + column, + burstLength, + clk, + trans, + {Timespan(span.Begin(), span.Begin() + clk * cl.REFP2B)}, + groupsPerRank, + banksPerGroup)); if (dbPhaseName == "RFMP2B") - return std::shared_ptr(new RFMP2B(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, - burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.RFMP2B)}, groupsPerRank, banksPerGroup)); + return std::shared_ptr( + new RFMP2B(id, + span, + spanOnDataStrobe, + rank, + bankGroup, + bank, + row, + column, + burstLength, + clk, + trans, + {Timespan(span.Begin(), span.Begin() + clk * cl.RFMP2B)}, + groupsPerRank, + banksPerGroup)); if (dbPhaseName == "PRESB") - return std::shared_ptr(new PRESB(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, - burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.PRESB)}, groupsPerRank, banksPerGroup)); + return std::shared_ptr( + new PRESB(id, + span, + spanOnDataStrobe, + rank, + bankGroup, + bank, + row, + column, + burstLength, + clk, + trans, + {Timespan(span.Begin(), span.Begin() + clk * cl.PRESB)}, + groupsPerRank, + banksPerGroup)); if (dbPhaseName == "REFSB") - return std::shared_ptr(new REFSB(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, - burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.REFSB)}, groupsPerRank, banksPerGroup)); + return std::shared_ptr( + new REFSB(id, + span, + spanOnDataStrobe, + rank, + bankGroup, + bank, + row, + column, + burstLength, + clk, + trans, + {Timespan(span.Begin(), span.Begin() + clk * cl.REFSB)}, + groupsPerRank, + banksPerGroup)); if (dbPhaseName == "RFMSB") - return std::shared_ptr(new RFMSB(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, - burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.RFMSB)}, groupsPerRank, banksPerGroup)); + return std::shared_ptr( + new RFMSB(id, + span, + spanOnDataStrobe, + rank, + bankGroup, + bank, + row, + column, + burstLength, + clk, + trans, + {Timespan(span.Begin(), span.Begin() + clk * cl.RFMSB)}, + groupsPerRank, + banksPerGroup)); if (dbPhaseName == "RD") - return std::shared_ptr(new RD(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, - burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.RD)}, groupsPerRank, banksPerGroup)); + return std::shared_ptr(new RD(id, + span, + spanOnDataStrobe, + rank, + bankGroup, + bank, + row, + column, + burstLength, + clk, + trans, + {Timespan(span.Begin(), span.Begin() + clk * cl.RD)}, + groupsPerRank, + banksPerGroup)); if (dbPhaseName == "RDA") - return std::shared_ptr(new RDA(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, - burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.RDA)}, groupsPerRank, banksPerGroup)); + return std::shared_ptr(new RDA(id, + span, + spanOnDataStrobe, + rank, + bankGroup, + bank, + row, + column, + burstLength, + clk, + trans, + {Timespan(span.Begin(), span.Begin() + clk * cl.RDA)}, + groupsPerRank, + banksPerGroup)); if (dbPhaseName == "WR") - return std::shared_ptr(new WR(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, - burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.WR)}, groupsPerRank, banksPerGroup)); + return std::shared_ptr(new WR(id, + span, + spanOnDataStrobe, + rank, + bankGroup, + bank, + row, + column, + burstLength, + clk, + trans, + {Timespan(span.Begin(), span.Begin() + clk * cl.WR)}, + groupsPerRank, + banksPerGroup)); if (dbPhaseName == "MWR") - return std::shared_ptr(new MWR(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, - burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.WR)}, groupsPerRank, banksPerGroup)); + return std::shared_ptr(new MWR(id, + span, + spanOnDataStrobe, + rank, + bankGroup, + bank, + row, + column, + burstLength, + clk, + trans, + {Timespan(span.Begin(), span.Begin() + clk * cl.WR)}, + groupsPerRank, + banksPerGroup)); if (dbPhaseName == "WRA") - return std::shared_ptr(new WRA(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, - burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.WRA)}, groupsPerRank, banksPerGroup)); + return std::shared_ptr(new WRA(id, + span, + spanOnDataStrobe, + rank, + bankGroup, + bank, + row, + column, + burstLength, + clk, + trans, + {Timespan(span.Begin(), span.Begin() + clk * cl.WRA)}, + groupsPerRank, + banksPerGroup)); if (dbPhaseName == "MWRA") - return std::shared_ptr(new MWRA(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, - burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.WR)}, groupsPerRank, banksPerGroup)); + return std::shared_ptr(new MWRA(id, + span, + spanOnDataStrobe, + rank, + bankGroup, + bank, + row, + column, + burstLength, + clk, + trans, + {Timespan(span.Begin(), span.Begin() + clk * cl.WR)}, + groupsPerRank, + banksPerGroup)); if (dbPhaseName == "PDNA") - return std::shared_ptr(new PDNA(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, - burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.PDEA), - Timespan(span.End() - clk * cl.PDXA, span.End())}, groupsPerRank, banksPerGroup)); + return std::shared_ptr( + new PDNA(id, + span, + spanOnDataStrobe, + rank, + bankGroup, + bank, + row, + column, + burstLength, + clk, + trans, + {Timespan(span.Begin(), span.Begin() + clk * cl.PDEA), + Timespan(span.End() - clk * cl.PDXA, span.End())}, + groupsPerRank, + banksPerGroup)); if (dbPhaseName == "PDNP") - return std::shared_ptr(new PDNP(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, - burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.PDEP), - Timespan(span.End() - clk * cl.PDXP, span.End())}, groupsPerRank, banksPerGroup)); + return std::shared_ptr( + new PDNP(id, + span, + spanOnDataStrobe, + rank, + bankGroup, + bank, + row, + column, + burstLength, + clk, + trans, + {Timespan(span.Begin(), span.Begin() + clk * cl.PDEP), + Timespan(span.End() - clk * cl.PDXP, span.End())}, + groupsPerRank, + banksPerGroup)); if (dbPhaseName == "SREF") - return std::shared_ptr(new SREF(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, - burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.SREFEN), - Timespan(span.End() - clk * cl.SREFEX, span.End())}, groupsPerRank, banksPerGroup)); + return std::shared_ptr( + new SREF(id, + span, + spanOnDataStrobe, + rank, + bankGroup, + bank, + row, + column, + burstLength, + clk, + trans, + {Timespan(span.Begin(), span.Begin() + clk * cl.SREFEN), + Timespan(span.End() - clk * cl.SREFEX, span.End())}, + groupsPerRank, + banksPerGroup)); - throw std::runtime_error("DB phasename " + dbPhaseName.toStdString() + " unkown to phasefactory"); + throw std::runtime_error("DB phasename " + dbPhaseName.toStdString() + + " unkown to phasefactory"); } diff --git a/extensions/apps/traceAnalyzer/businessObjects/phases/phasefactory.h b/extensions/apps/traceAnalyzer/businessObjects/phases/phasefactory.h index 63130e2a..3a7630f9 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/phases/phasefactory.h +++ b/extensions/apps/traceAnalyzer/businessObjects/phases/phasefactory.h @@ -38,10 +38,10 @@ #ifndef PHASEFACTORY_H #define PHASEFACTORY_H +#include "businessObjects/transaction.h" #include "phase.h" #include #include -#include "businessObjects/transaction.h" class TraceDB; @@ -49,10 +49,18 @@ class PhaseFactory { public: PhaseFactory() = delete; - static std::shared_ptr createPhase(ID id, const QString &dbPhaseName, - Timespan span, Timespan spanOnDataStrobe, - unsigned int rank, unsigned int bankGroup, unsigned int bank, unsigned int row, unsigned int column, - unsigned int burstLength, const std::shared_ptr &trans, TraceDB &database); + static std::shared_ptr createPhase(ID id, + const QString& dbPhaseName, + Timespan span, + Timespan spanOnDataStrobe, + unsigned int rank, + unsigned int bankGroup, + unsigned int bank, + unsigned int row, + unsigned int column, + unsigned int burstLength, + const std::shared_ptr& trans, + TraceDB& database); }; #endif // PHASEFACTORY_H diff --git a/extensions/apps/traceAnalyzer/businessObjects/pythoncaller.cpp b/extensions/apps/traceAnalyzer/businessObjects/pythoncaller.cpp index f1aefa1e..f55effed 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/pythoncaller.cpp +++ b/extensions/apps/traceAnalyzer/businessObjects/pythoncaller.cpp @@ -39,10 +39,10 @@ #include "pythoncaller.h" #include -#include #include #include #include +#include std::string PythonCaller::generatePlots(std::string_view pathToTrace) { @@ -52,12 +52,12 @@ std::string PythonCaller::generatePlots(std::string_view pathToTrace) auto result = metricsModule.attr("generatePlots")(pathToTrace).cast(); return result; } - catch (std::exception const &err) + catch (std::exception const& err) { std::cout << err.what() << std::endl; } - return {}; + return {}; } std::vector PythonCaller::availableMetrics(std::string_view pathToTrace) @@ -68,7 +68,7 @@ std::vector PythonCaller::availableMetrics(std::string_view pathToT pybind11::list result = metricsModule.attr("getMetrics")(pathToTrace); return result.cast>(); } - catch (std::exception const &err) + catch (std::exception const& err) { std::cout << err.what() << std::endl; } @@ -76,14 +76,16 @@ std::vector PythonCaller::availableMetrics(std::string_view pathToT return {}; } -TraceCalculatedMetrics PythonCaller::evaluateMetrics(std::string_view pathToTrace, std::vector selectedMetrics) +TraceCalculatedMetrics PythonCaller::evaluateMetrics(std::string_view pathToTrace, + std::vector selectedMetrics) { TraceCalculatedMetrics metrics(pathToTrace.data()); try { pybind11::module_ metricsModule = pybind11::module_::import("metrics"); - pybind11::list result = metricsModule.attr("calculateMetrics")(pathToTrace, selectedMetrics); + pybind11::list result = + metricsModule.attr("calculateMetrics")(pathToTrace, selectedMetrics); auto metricList = result.cast>(); for (auto metricPair : metricList) @@ -93,7 +95,7 @@ TraceCalculatedMetrics PythonCaller::evaluateMetrics(std::string_view pathToTrac metrics.addCalculatedMetric({name, value}); } } - catch (std::exception const &err) + catch (std::exception const& err) { std::cout << err.what() << std::endl; } @@ -109,7 +111,7 @@ std::string PythonCaller::dumpVcd(std::string_view pathToTrace) pybind11::str result = vcdModule.attr("dumpVcd")(pathToTrace); return result.cast(); } - catch (std::exception const &err) + catch (std::exception const& err) { std::cout << err.what() << std::endl; } diff --git a/extensions/apps/traceAnalyzer/businessObjects/pythoncaller.h b/extensions/apps/traceAnalyzer/businessObjects/pythoncaller.h index 402674a7..06b0cf70 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/pythoncaller.h +++ b/extensions/apps/traceAnalyzer/businessObjects/pythoncaller.h @@ -45,18 +45,17 @@ #undef slots #endif -#include #include "businessObjects/tracecalculatedmetrics.h" +#include class PythonCaller { public: static std::vector availableMetrics(std::string_view pathToTrace); - static TraceCalculatedMetrics evaluateMetrics(std::string_view pathToTrace, std::vector selectedMetrics); + static TraceCalculatedMetrics evaluateMetrics(std::string_view pathToTrace, + std::vector selectedMetrics); static std::string generatePlots(std::string_view pathToTrace); static std::string dumpVcd(std::string_view pathToTrace); }; #endif // PYTHONCALLER_H - - diff --git a/extensions/apps/traceAnalyzer/businessObjects/testresult.h b/extensions/apps/traceAnalyzer/businessObjects/testresult.h index b4033f64..b3d6ffec 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/testresult.h +++ b/extensions/apps/traceAnalyzer/businessObjects/testresult.h @@ -42,27 +42,21 @@ class TestResult { public: - TestResult(const QString &testName, bool passed, QString &message) : - testName(testName), passed(passed), message(message) {} + TestResult(const QString& testName, bool passed, QString& message) : + testName(testName), + passed(passed), + message(message) + { + } - QString getTestName() const - { - return testName; - } - QString getMessage() const - { - return message; - } - bool hasPassed() const - { - return passed; - } + QString getTestName() const { return testName; } + QString getMessage() const { return message; } + bool hasPassed() const { return passed; } private: QString testName; bool passed; QString message; - }; #endif // TESTRESULT_H diff --git a/extensions/apps/traceAnalyzer/businessObjects/timespan.cpp b/extensions/apps/traceAnalyzer/businessObjects/timespan.cpp index 0c0aca7c..bfd5a4fc 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/timespan.cpp +++ b/extensions/apps/traceAnalyzer/businessObjects/timespan.cpp @@ -42,7 +42,7 @@ bool Timespan::contains(traceTime time) const return (begin <= time && time <= end); } -bool Timespan::overlaps(const Timespan &other) const +bool Timespan::overlaps(const Timespan& other) const { return other.Begin() < this->end && this->begin < other.End(); } @@ -50,5 +50,5 @@ bool Timespan::overlaps(const Timespan &other) const void Timespan::shift(traceTime offset) { begin += offset; - end += offset; + end += offset; } diff --git a/extensions/apps/traceAnalyzer/businessObjects/timespan.h b/extensions/apps/traceAnalyzer/businessObjects/timespan.h index 3bf1ed4e..c0a29358 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/timespan.h +++ b/extensions/apps/traceAnalyzer/businessObjects/timespan.h @@ -37,43 +37,25 @@ #ifndef TIMESPAN_H #define TIMESPAN_H +#include "tracetime.h" #include #include -#include "tracetime.h" class Timespan { traceTime begin; traceTime end; -public: +public: explicit Timespan(traceTime begin = 0, traceTime end = 0) : begin(begin), end(end) {} - traceTime timeCovered() const - { - return std::abs(End() - Begin()); - } - traceTime Begin() const - { - return begin; - } - void setBegin(traceTime time) - { - begin = time; - } - traceTime End() const - { - return end; - } - traceTime Middle() const - { - return (begin + end) / 2; - } - void setEnd(traceTime time) - { - end = time; - } + traceTime timeCovered() const { return std::abs(End() - Begin()); } + traceTime Begin() const { return begin; } + void setBegin(traceTime time) { begin = time; } + traceTime End() const { return end; } + traceTime Middle() const { return (begin + end) / 2; } + void setEnd(traceTime time) { end = time; } bool contains(traceTime time) const; - bool overlaps(const Timespan &other) const; + bool overlaps(const Timespan& other) const; void shift(traceTime offset); }; diff --git a/extensions/apps/traceAnalyzer/businessObjects/tracecalculatedmetrics.h b/extensions/apps/traceAnalyzer/businessObjects/tracecalculatedmetrics.h index 851ba68d..d2ce5521 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/tracecalculatedmetrics.h +++ b/extensions/apps/traceAnalyzer/businessObjects/tracecalculatedmetrics.h @@ -37,33 +37,28 @@ #ifndef TRACEMETRICRESULTS_H #define TRACEMETRICRESULTS_H +#include "calculatedMetric.h" #include #include -#include "calculatedMetric.h" class TraceCalculatedMetrics { public: - TraceCalculatedMetrics(const QString &traceName): traceName(traceName) {} + TraceCalculatedMetrics(const QString& traceName) : traceName(traceName) {} - void addCalculatedMetric(const CalculatedMetric &result) + void addCalculatedMetric(const CalculatedMetric& result) { calculatedMetrics.push_back(result); } - QString getTraceName() const - { - return traceName; - } - const std::vector &getCalculatedMetrics() const - { - return calculatedMetrics; - } + QString getTraceName() const { return traceName; } + const std::vector& getCalculatedMetrics() const { return calculatedMetrics; } QString toCSVHeader() { QString result = ""; result.append("Trace"); - for (CalculatedMetric calculatedMetric : calculatedMetrics) { + for (CalculatedMetric calculatedMetric : calculatedMetrics) + { result.append(","); result.append(calculatedMetric.name.c_str()); } @@ -74,7 +69,8 @@ public: { QString result = ""; result.append(traceName); - for (CalculatedMetric calculatedMetric : calculatedMetrics) { + for (CalculatedMetric calculatedMetric : calculatedMetrics) + { result.append(","); result.append(QString::number(calculatedMetric.value)); } @@ -86,5 +82,4 @@ private: std::vector calculatedMetrics; }; - #endif // TRACEMETRICRESULTS_H diff --git a/extensions/apps/traceAnalyzer/businessObjects/traceplotlinemodel.cpp b/extensions/apps/traceAnalyzer/businessObjects/traceplotlinemodel.cpp index 54e6f027..b53f5001 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/traceplotlinemodel.cpp +++ b/extensions/apps/traceAnalyzer/businessObjects/traceplotlinemodel.cpp @@ -41,72 +41,83 @@ #include #include -AbstractTracePlotLineModel::AbstractTracePlotLineModel(const GeneralInfo &generalInfo, QObject *parent) - : QAbstractItemModel(parent), internalSelectionModel(new QItemSelectionModel(this, this)), - rootNode(std::make_shared()), numberOfRanks(generalInfo.numberOfRanks), - groupsPerRank(generalInfo.groupsPerRank), banksPerGroup(generalInfo.banksPerGroup), - banksPerRank(generalInfo.banksPerRank), commandBusType(getCommandBusType(generalInfo)), - dataBusType(getDataBusType(generalInfo)) +AbstractTracePlotLineModel::AbstractTracePlotLineModel(const GeneralInfo& generalInfo, + QObject* parent) : + QAbstractItemModel(parent), + internalSelectionModel(new QItemSelectionModel(this, this)), + rootNode(std::make_shared()), + numberOfRanks(generalInfo.numberOfRanks), + groupsPerRank(generalInfo.groupsPerRank), + banksPerGroup(generalInfo.banksPerGroup), + banksPerRank(generalInfo.banksPerRank), + commandBusType(getCommandBusType(generalInfo)), + dataBusType(getDataBusType(generalInfo)) { createInitialNodes(); } -AvailableTracePlotLineModel::AvailableTracePlotLineModel(const GeneralInfo &generalInfo, QObject *parent) - : AbstractTracePlotLineModel(generalInfo, parent) +AvailableTracePlotLineModel::AvailableTracePlotLineModel(const GeneralInfo& generalInfo, + QObject* parent) : + AbstractTracePlotLineModel(generalInfo, parent) { } -SelectedTracePlotLineModel::SelectedTracePlotLineModel(const GeneralInfo &generalInfo, QObject *parent) - : AbstractTracePlotLineModel(generalInfo, parent) +SelectedTracePlotLineModel::SelectedTracePlotLineModel(const GeneralInfo& generalInfo, + QObject* parent) : + AbstractTracePlotLineModel(generalInfo, parent) { } -void AbstractTracePlotLineModel::addTopLevelNode(std::shared_ptr &&node) +void AbstractTracePlotLineModel::addTopLevelNode(std::shared_ptr&& node) { rootNode->children.push_back(std::move(node)); } void AbstractTracePlotLineModel::createInitialNodes() { - addTopLevelNode( - std::unique_ptr(new Node({LineType::RequestLine, getLabel(LineType::RequestLine)}, rootNode.get()))); - addTopLevelNode( - std::unique_ptr(new Node({LineType::ResponseLine, getLabel(LineType::ResponseLine)}, rootNode.get()))); + addTopLevelNode(std::unique_ptr( + new Node({LineType::RequestLine, getLabel(LineType::RequestLine)}, rootNode.get()))); + addTopLevelNode(std::unique_ptr( + new Node({LineType::ResponseLine, getLabel(LineType::ResponseLine)}, rootNode.get()))); for (unsigned int rank = 0; rank < numberOfRanks; rank++) addTopLevelNode(createRankGroupNode(rank)); if (commandBusType == CommandBusType::SingleCommandBus) { - addTopLevelNode(std::unique_ptr( - new Node({LineType::CommandBusLine, getLabel(LineType::CommandBusLine)}, rootNode.get()))); + addTopLevelNode(std::unique_ptr(new Node( + {LineType::CommandBusLine, getLabel(LineType::CommandBusLine)}, rootNode.get()))); } else // commandBusType == CommandBusType::RowColumnCommandBus { + addTopLevelNode(std::unique_ptr(new Node( + {LineType::RowCommandBusLine, getLabel(LineType::RowCommandBusLine)}, rootNode.get()))); addTopLevelNode(std::unique_ptr( - new Node({LineType::RowCommandBusLine, getLabel(LineType::RowCommandBusLine)}, rootNode.get()))); - addTopLevelNode(std::unique_ptr( - new Node({LineType::ColumnCommandBusLine, getLabel(LineType::ColumnCommandBusLine)}, rootNode.get()))); + new Node({LineType::ColumnCommandBusLine, getLabel(LineType::ColumnCommandBusLine)}, + rootNode.get()))); } if (dataBusType == DataBusType::LegacyMode) { - addTopLevelNode( - std::unique_ptr(new Node({LineType::DataBusLine, getLabel(LineType::DataBusLine)}, rootNode.get()))); + addTopLevelNode(std::unique_ptr( + new Node({LineType::DataBusLine, getLabel(LineType::DataBusLine)}, rootNode.get()))); } else // dataBusType == DataBusType::PseudoChannelMode { addTopLevelNode(std::unique_ptr( - new Node({LineType::PseudoChannel0Line, getLabel(LineType::PseudoChannel0Line)}, rootNode.get()))); + new Node({LineType::PseudoChannel0Line, getLabel(LineType::PseudoChannel0Line)}, + rootNode.get()))); addTopLevelNode(std::unique_ptr( - new Node({LineType::PseudoChannel1Line, getLabel(LineType::PseudoChannel1Line)}, rootNode.get()))); + new Node({LineType::PseudoChannel1Line, getLabel(LineType::PseudoChannel1Line)}, + rootNode.get()))); } } std::shared_ptr AbstractTracePlotLineModel::createRankGroupNode(unsigned int rank) const { - auto rankGroup = std::unique_ptr(new Node({LineType::RankGroup, getLabel(rank), rank}, rootNode.get())); + auto rankGroup = std::unique_ptr( + new Node({LineType::RankGroup, getLabel(rank), rank}, rootNode.get())); for (unsigned int group = 0; group < groupsPerRank; group++) { @@ -116,9 +127,12 @@ AbstractTracePlotLineModel::createRankGroupNode(unsigned int rank) const unsigned int absoluteGroup = group + rank * groupsPerRank; unsigned int absoluteBank = bank + rank * banksPerRank + group * banksPerGroup; - auto bankLine = std::unique_ptr( - new Node({LineType::BankLine, getLabel(rank, group, bank), absoluteRank, absoluteGroup, absoluteBank}, - rankGroup.get())); + auto bankLine = std::unique_ptr(new Node({LineType::BankLine, + getLabel(rank, group, bank), + absoluteRank, + absoluteGroup, + absoluteBank}, + rankGroup.get())); rankGroup->children.push_back(std::move(bankLine)); } @@ -127,34 +141,34 @@ AbstractTracePlotLineModel::createRankGroupNode(unsigned int rank) const return rankGroup; } -int AbstractTracePlotLineModel::rowCount(const QModelIndex &parent) const +int AbstractTracePlotLineModel::rowCount(const QModelIndex& parent) const { if (parent.column() > 0) return 0; - const Node *parentNode; + const Node* parentNode; if (!parent.isValid()) parentNode = rootNode.get(); else - parentNode = static_cast(parent.internalPointer()); + parentNode = static_cast(parent.internalPointer()); return parentNode->childCount(); } -int AbstractTracePlotLineModel::columnCount(const QModelIndex &parent) const +int AbstractTracePlotLineModel::columnCount(const QModelIndex& parent) const { Q_UNUSED(parent) return 1; } -QVariant AbstractTracePlotLineModel::data(const QModelIndex &index, int role) const +QVariant AbstractTracePlotLineModel::data(const QModelIndex& index, int role) const { if (!index.isValid()) return QVariant(); - auto *node = static_cast(index.internalPointer()); + auto* node = static_cast(index.internalPointer()); switch (role) { @@ -171,12 +185,12 @@ QVariant AbstractTracePlotLineModel::data(const QModelIndex &index, int role) co return QVariant(); } -bool SelectedTracePlotLineModel::setData(const QModelIndex &index, const QVariant &value, int role) +bool SelectedTracePlotLineModel::setData(const QModelIndex& index, const QVariant& value, int role) { if (!index.isValid()) return false; - auto *node = static_cast(index.internalPointer()); + auto* node = static_cast(index.internalPointer()); switch (role) { @@ -194,7 +208,8 @@ bool SelectedTracePlotLineModel::setData(const QModelIndex &index, const QVarian return false; } -QVariant AvailableTracePlotLineModel::headerData(int section, Qt::Orientation orientation, int role) const +QVariant +AvailableTracePlotLineModel::headerData(int section, Qt::Orientation orientation, int role) const { if (role != Qt::DisplayRole) return QVariant(); @@ -205,7 +220,8 @@ QVariant AvailableTracePlotLineModel::headerData(int section, Qt::Orientation or return QVariant(); } -QVariant SelectedTracePlotLineModel::headerData(int section, Qt::Orientation orientation, int role) const +QVariant +SelectedTracePlotLineModel::headerData(int section, Qt::Orientation orientation, int role) const { if (role != Qt::DisplayRole) return QVariant(); @@ -218,39 +234,39 @@ QVariant SelectedTracePlotLineModel::headerData(int section, Qt::Orientation ori return QVariant(); } -QModelIndex AbstractTracePlotLineModel::index(int row, int column, const QModelIndex &parent) const +QModelIndex AbstractTracePlotLineModel::index(int row, int column, const QModelIndex& parent) const { if (!hasIndex(row, column, parent)) return QModelIndex(); - const Node *parentNode; + const Node* parentNode; if (!parent.isValid()) parentNode = rootNode.get(); else - parentNode = static_cast(parent.internalPointer()); + parentNode = static_cast(parent.internalPointer()); - const Node *node = parentNode->children[row].get(); + const Node* node = parentNode->children[row].get(); - return createIndex(row, column, const_cast(node)); + return createIndex(row, column, const_cast(node)); } -QModelIndex AbstractTracePlotLineModel::parent(const QModelIndex &index) const +QModelIndex AbstractTracePlotLineModel::parent(const QModelIndex& index) const { if (!index.isValid()) return QModelIndex(); - const Node *childNode = static_cast(index.internalPointer()); - const Node *parentNode = childNode->parent; + const Node* childNode = static_cast(index.internalPointer()); + const Node* parentNode = childNode->parent; if (!parentNode || parentNode == rootNode.get()) return QModelIndex(); - return createIndex(parentNode->getRow(), 0, const_cast(parentNode)); + return createIndex(parentNode->getRow(), 0, const_cast(parentNode)); } -void SelectedTracePlotLineModel::recreateCollapseButtons(TracePlot *tracePlot, - CustomLabelScaleDraw *customLabelScaleDraw) +void SelectedTracePlotLineModel::recreateCollapseButtons(TracePlot* tracePlot, + CustomLabelScaleDraw* customLabelScaleDraw) { // Remove old buttons for (auto button : collapseButtons) @@ -261,12 +277,12 @@ void SelectedTracePlotLineModel::recreateCollapseButtons(TracePlot *tracePlot, collapseButtons.clear(); - for (const auto &node : rootNode->children) + for (const auto& node : rootNode->children) { if (node->data.type != LineType::RankGroup) continue; - QPushButton *collapseButton = new QPushButton(tracePlot); + QPushButton* collapseButton = new QPushButton(tracePlot); unsigned int yVal = [node]() { @@ -295,11 +311,15 @@ void SelectedTracePlotLineModel::recreateCollapseButtons(TracePlot *tracePlot, recreateCollapseButtons(tracePlot, customLabelScaleDraw); }; - // Important: The context of the connection is `collapseButton` as it should be disconnected when the button - // ceases to exist. - connect(customLabelScaleDraw, &CustomLabelScaleDraw::scaleRedraw, collapseButton, repositionButton); + // Important: The context of the connection is `collapseButton` as it should be disconnected + // when the button ceases to exist. + connect(customLabelScaleDraw, + &CustomLabelScaleDraw::scaleRedraw, + collapseButton, + repositionButton); connect(collapseButton, &QPushButton::pressed, this, toggleCollapsed); - connect(collapseButton, &QPushButton::pressed, tracePlot, &TracePlot::recreateCollapseButtons); + connect( + collapseButton, &QPushButton::pressed, tracePlot, &TracePlot::recreateCollapseButtons); collapseButton->show(); collapseButtons.push_back(collapseButton); @@ -311,21 +331,23 @@ int AbstractTracePlotLineModel::Node::getRow() const if (!parent) return 0; - const auto &siblings = parent->children; - const auto siblingsIt = std::find_if(siblings.begin(), siblings.end(), - [this](const std::shared_ptr &node) { return node.get() == this; }); + const auto& siblings = parent->children; + const auto siblingsIt = + std::find_if(siblings.begin(), + siblings.end(), + [this](const std::shared_ptr& node) { return node.get() == this; }); Q_ASSERT(siblingsIt != siblings.end()); return std::distance(siblings.begin(), siblingsIt); } -std::shared_ptr AbstractTracePlotLineModel::Node::cloneNode(const Node *node, - const Node *parent) +std::shared_ptr +AbstractTracePlotLineModel::Node::cloneNode(const Node* node, const Node* parent) { std::shared_ptr clonedNode = std::make_shared(node->data, parent); - for (const auto &child : node->children) + for (const auto& child : node->children) clonedNode->children.push_back(cloneNode(child.get(), clonedNode.get())); return clonedNode; @@ -362,13 +384,16 @@ QString AbstractTracePlotLineModel::getLabel(unsigned int rank) const return rankLabel.data() + QString::number(rank); } -QString AbstractTracePlotLineModel::getLabel(unsigned int rank, unsigned int group, unsigned int bank) const +QString +AbstractTracePlotLineModel::getLabel(unsigned int rank, unsigned int group, unsigned int bank) const { std::string_view rankLabel = dataBusType == DataBusType::LegacyMode ? "RA" : "PC"; - return rankLabel.data() + QString::number(rank) + " BG" + QString::number(group) + " BA" + QString::number(bank); + return rankLabel.data() + QString::number(rank) + " BG" + QString::number(group) + " BA" + + QString::number(bank); } -AbstractTracePlotLineModel::CommandBusType AbstractTracePlotLineModel::getCommandBusType(const GeneralInfo &generalInfo) +AbstractTracePlotLineModel::CommandBusType +AbstractTracePlotLineModel::getCommandBusType(const GeneralInfo& generalInfo) { if (generalInfo.rowColumnCommandBus) return CommandBusType::RowColumnCommandBus; @@ -376,7 +401,8 @@ AbstractTracePlotLineModel::CommandBusType AbstractTracePlotLineModel::getComman return CommandBusType::SingleCommandBus; } -AbstractTracePlotLineModel::DataBusType AbstractTracePlotLineModel::getDataBusType(const GeneralInfo &generalInfo) +AbstractTracePlotLineModel::DataBusType +AbstractTracePlotLineModel::getDataBusType(const GeneralInfo& generalInfo) { if (generalInfo.pseudoChannelMode) return DataBusType::PseudoChannelMode; @@ -384,27 +410,28 @@ AbstractTracePlotLineModel::DataBusType AbstractTracePlotLineModel::getDataBusTy return DataBusType::LegacyMode; } -bool SelectedTracePlotLineModel::removeRows(int row, int count, const QModelIndex &parent) +bool SelectedTracePlotLineModel::removeRows(int row, int count, const QModelIndex& parent) { if (parent != QModelIndex()) return false; // Note: beginRemoveRows requires [first, last], but erase requires [first, last) beginRemoveRows(QModelIndex(), row, row + count - 1); - rootNode->children.erase(rootNode->children.begin() + row, rootNode->children.begin() + row + count); + rootNode->children.erase(rootNode->children.begin() + row, + rootNode->children.begin() + row + count); endRemoveRows(); return true; } -void AvailableTracePlotLineModel::itemsDoubleClicked(const QModelIndex &index) +void AvailableTracePlotLineModel::itemsDoubleClicked(const QModelIndex& index) { QModelIndexList indexList({index}); emit returnPressed(indexList); } -void SelectedTracePlotLineModel::itemsDoubleClicked(const QModelIndex &index) +void SelectedTracePlotLineModel::itemsDoubleClicked(const QModelIndex& index) { if (index.parent() != QModelIndex()) return; @@ -412,13 +439,13 @@ void SelectedTracePlotLineModel::itemsDoubleClicked(const QModelIndex &index) removeRow(index.row(), QModelIndex()); } -bool AvailableTracePlotLineModel::eventFilter(QObject *object, QEvent *event) +bool AvailableTracePlotLineModel::eventFilter(QObject* object, QEvent* event) { Q_UNUSED(object) if (event->type() == QEvent::KeyPress) { - QKeyEvent *keyEvent = static_cast(event); + QKeyEvent* keyEvent = static_cast(event); if (keyEvent->key() == Qt::Key_Return) { @@ -435,13 +462,13 @@ bool AvailableTracePlotLineModel::eventFilter(QObject *object, QEvent *event) return false; } -bool SelectedTracePlotLineModel::eventFilter(QObject *object, QEvent *event) +bool SelectedTracePlotLineModel::eventFilter(QObject* object, QEvent* event) { Q_UNUSED(object) if (event->type() == QEvent::KeyPress) { - QKeyEvent *keyEvent = static_cast(event); + QKeyEvent* keyEvent = static_cast(event); if (keyEvent->key() == Qt::Key_Delete) { @@ -452,7 +479,7 @@ bool SelectedTracePlotLineModel::eventFilter(QObject *object, QEvent *event) if (indexes.count() == 0) return true; - for (const auto &index : indexes) + for (const auto& index : indexes) { // Only remove toplevel indexes if (index.parent() != QModelIndex()) @@ -471,11 +498,11 @@ bool SelectedTracePlotLineModel::eventFilter(QObject *object, QEvent *event) return false; } -void SelectedTracePlotLineModel::addIndexesFromAvailableModel(const QModelIndexList &indexes) +void SelectedTracePlotLineModel::addIndexesFromAvailableModel(const QModelIndexList& indexes) { - for (const auto &index : indexes) + for (const auto& index : indexes) { - auto node = static_cast(index.internalPointer()); + auto node = static_cast(index.internalPointer()); auto clonedNode = Node::cloneNode(node, rootNode.get()); beginInsertRows(QModelIndex(), rootNode->children.size(), rootNode->children.size()); @@ -484,7 +511,7 @@ void SelectedTracePlotLineModel::addIndexesFromAvailableModel(const QModelIndexL } } -QItemSelectionModel *AbstractTracePlotLineModel::selectionModel() const +QItemSelectionModel* AbstractTracePlotLineModel::selectionModel() const { return internalSelectionModel; } @@ -497,27 +524,30 @@ QStringList AbstractTracePlotLineModel::mimeTypes() const return types; } -QMimeData *AbstractTracePlotLineModel::mimeData(const QModelIndexList &indexes) const +QMimeData* AbstractTracePlotLineModel::mimeData(const QModelIndexList& indexes) const { QByteArray traceLineData; QDataStream dataStream(&traceLineData, QIODevice::WriteOnly); - for (const auto &index : indexes) + for (const auto& index : indexes) { - const Node *node = static_cast(index.internalPointer()); + const Node* node = static_cast(index.internalPointer()); - dataStream << node->data.type << node->data.label << node->data.rank << node->data.group << node->data.bank - << node->data.collapsed; + dataStream << node->data.type << node->data.label << node->data.rank << node->data.group + << node->data.bank << node->data.collapsed; } - QMimeData *mimeData = new QMimeData; + QMimeData* mimeData = new QMimeData; mimeData->setData(TRACELINE_MIMETYPE, traceLineData); return mimeData; } -bool AbstractTracePlotLineModel::canDropMimeData(const QMimeData *data, Qt::DropAction action, int row, int column, - const QModelIndex &parent) const +bool AbstractTracePlotLineModel::canDropMimeData(const QMimeData* data, + Qt::DropAction action, + int row, + int column, + const QModelIndex& parent) const { Q_UNUSED(action); Q_UNUSED(row); @@ -532,8 +562,8 @@ bool AbstractTracePlotLineModel::canDropMimeData(const QMimeData *data, Qt::Drop return true; } -bool AbstractTracePlotLineModel::dropMimeData(const QMimeData *data, Qt::DropAction action, int row, int column, - const QModelIndex &parent) +bool AbstractTracePlotLineModel::dropMimeData( + const QMimeData* data, Qt::DropAction action, int row, int column, const QModelIndex& parent) { if (!canDropMimeData(data, action, row, column, parent)) return false; @@ -571,7 +601,8 @@ bool AbstractTracePlotLineModel::dropMimeData(const QMimeData *data, Qt::DropAct std::shared_ptr node; if (type == LineType::BankLine) - node = std::make_shared(Node::NodeData{type, label, rank, group, bank}, rootNode.get()); + node = std::make_shared(Node::NodeData{type, label, rank, group, bank}, + rootNode.get()); else if (type == LineType::RankGroup) node = createRankGroupNode(rank); else @@ -585,7 +616,8 @@ bool AbstractTracePlotLineModel::dropMimeData(const QMimeData *data, Qt::DropAct // Note: beginRemoveRows requires [first, last] beginInsertRows(QModelIndex(), beginRow, beginRow + droppedNodes.size() - 1); - rootNode->children.insert(rootNode->children.begin() + beginRow, std::make_move_iterator(droppedNodes.begin()), + rootNode->children.insert(rootNode->children.begin() + beginRow, + std::make_move_iterator(droppedNodes.begin()), std::make_move_iterator(droppedNodes.end())); endInsertRows(); } @@ -602,7 +634,7 @@ Qt::DropActions AbstractTracePlotLineModel::supportedDropActions() const return (Qt::MoveAction | Qt::CopyAction); } -Qt::ItemFlags AbstractTracePlotLineModel::flags(const QModelIndex &index) const +Qt::ItemFlags AbstractTracePlotLineModel::flags(const QModelIndex& index) const { Qt::ItemFlags defaultFlags = QAbstractItemModel::flags(index); @@ -626,8 +658,9 @@ void SelectedTracePlotLineModel::setRootNode(std::shared_ptr & parent)> addNodes; - addNodes = [=, &addNodes](std::shared_ptr &parent) + addNodes = [=, &addNodes](std::shared_ptr& parent) { - for (auto &childNode : parent->children) + for (auto& childNode : parent->children) { - if (childNode->data.type == AbstractTracePlotLineModel::RankGroup && !childNode->data.collapsed) + if (childNode->data.type == AbstractTracePlotLineModel::RankGroup && + !childNode->data.collapsed) { addNodes(childNode); continue; // Don't add the parent node itself when not collapsed. diff --git a/extensions/apps/traceAnalyzer/businessObjects/traceplotlinemodel.h b/extensions/apps/traceAnalyzer/businessObjects/traceplotlinemodel.h index 2a58f471..55801a1c 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/traceplotlinemodel.h +++ b/extensions/apps/traceAnalyzer/businessObjects/traceplotlinemodel.h @@ -51,17 +51,18 @@ class AbstractTracePlotLineModel : public QAbstractItemModel Q_OBJECT public: - explicit AbstractTracePlotLineModel(const GeneralInfo &generalInfo, QObject *parent = nullptr); + explicit AbstractTracePlotLineModel(const GeneralInfo& generalInfo, QObject* parent = nullptr); - int rowCount(const QModelIndex &parent = QModelIndex()) const override; - int columnCount(const QModelIndex &parent = QModelIndex()) const override; + int rowCount(const QModelIndex& parent = QModelIndex()) const override; + int columnCount(const QModelIndex& parent = QModelIndex()) const override; - QVariant data(const QModelIndex &index, int role = Qt::DisplayRole) const override; + QVariant data(const QModelIndex& index, int role = Qt::DisplayRole) const override; - QModelIndex index(int row, int column, const QModelIndex &parent = QModelIndex()) const override; - QModelIndex parent(const QModelIndex &index) const override; + QModelIndex + index(int row, int column, const QModelIndex& parent = QModelIndex()) const override; + QModelIndex parent(const QModelIndex& index) const override; - QItemSelectionModel *selectionModel() const; + QItemSelectionModel* selectionModel() const; enum Role { @@ -91,16 +92,25 @@ public: { NodeData() = default; - NodeData(LineType type, const QString &label) : type(type), label(label) + NodeData(LineType type, const QString& label) : type(type), label(label) {} + + NodeData(LineType type, const QString& label, unsigned int rank) : + type(type), + label(label), + rank(rank) { } - NodeData(LineType type, const QString &label, unsigned int rank) : type(type), label(label), rank(rank) - { - } - - NodeData(LineType type, const QString &label, unsigned int rank, unsigned int group, unsigned int bank) - : type(type), label(label), rank(rank), group(group), bank(bank) + NodeData(LineType type, + const QString& label, + unsigned int rank, + unsigned int group, + unsigned int bank) : + type(type), + label(label), + rank(rank), + group(group), + bank(bank) { } @@ -126,24 +136,19 @@ public: */ Node() = default; - Node(NodeData data, const Node *parent) : data(data), parent(parent) - { - } + Node(NodeData data, const Node* parent) : data(data), parent(parent) {} /** * Gets the row relative to its parent. */ int getRow() const; - int childCount() const - { - return children.size(); - } + int childCount() const { return children.size(); } - static std::shared_ptr cloneNode(const Node *node, const Node *parent); + static std::shared_ptr cloneNode(const Node* node, const Node* parent); NodeData data; - const Node *parent = nullptr; + const Node* parent = nullptr; std::vector> children; }; @@ -161,15 +166,21 @@ protected: }; QStringList mimeTypes() const override; - QMimeData *mimeData(const QModelIndexList &indexes) const override; - bool dropMimeData(const QMimeData *data, Qt::DropAction action, int row, int column, - const QModelIndex &parent) override; - bool canDropMimeData(const QMimeData *data, Qt::DropAction action, int row, int column, - const QModelIndex &parent) const override; + QMimeData* mimeData(const QModelIndexList& indexes) const override; + bool dropMimeData(const QMimeData* data, + Qt::DropAction action, + int row, + int column, + const QModelIndex& parent) override; + bool canDropMimeData(const QMimeData* data, + Qt::DropAction action, + int row, + int column, + const QModelIndex& parent) const override; Qt::DropActions supportedDropActions() const override; - Qt::ItemFlags flags(const QModelIndex &index) const override; + Qt::ItemFlags flags(const QModelIndex& index) const override; - void addTopLevelNode(std::shared_ptr &&node); + void addTopLevelNode(std::shared_ptr&& node); void createInitialNodes(); std::shared_ptr createRankGroupNode(unsigned int rank) const; @@ -177,12 +188,12 @@ protected: QString getLabel(unsigned int rank) const; QString getLabel(unsigned int rank, unsigned int group, unsigned int bank) const; - static CommandBusType getCommandBusType(const GeneralInfo &generalInfo); - static DataBusType getDataBusType(const GeneralInfo &generalInfo); + static CommandBusType getCommandBusType(const GeneralInfo& generalInfo); + static DataBusType getDataBusType(const GeneralInfo& generalInfo); static constexpr auto TRACELINE_MIMETYPE = "application/x-tracelinedata"; - QItemSelectionModel *const internalSelectionModel; + QItemSelectionModel* const internalSelectionModel; std::shared_ptr rootNode; @@ -200,17 +211,18 @@ class AvailableTracePlotLineModel : public AbstractTracePlotLineModel Q_OBJECT public: - explicit AvailableTracePlotLineModel(const GeneralInfo &generalInfo, QObject *parent = nullptr); + explicit AvailableTracePlotLineModel(const GeneralInfo& generalInfo, QObject* parent = nullptr); public Q_SLOTS: - void itemsDoubleClicked(const QModelIndex &index); + void itemsDoubleClicked(const QModelIndex& index); Q_SIGNALS: - void returnPressed(const QModelIndexList &indexes); + void returnPressed(const QModelIndexList& indexes); protected: - QVariant headerData(int section, Qt::Orientation orientation, int role = Qt::DisplayRole) const override; - bool eventFilter(QObject *object, QEvent *event) override; + QVariant + headerData(int section, Qt::Orientation orientation, int role = Qt::DisplayRole) const override; + bool eventFilter(QObject* object, QEvent* event) override; }; class SelectedTracePlotLineModel : public AbstractTracePlotLineModel @@ -218,28 +230,29 @@ class SelectedTracePlotLineModel : public AbstractTracePlotLineModel Q_OBJECT public: - explicit SelectedTracePlotLineModel(const GeneralInfo &generalInfo, QObject *parent = nullptr); + explicit SelectedTracePlotLineModel(const GeneralInfo& generalInfo, QObject* parent = nullptr); - bool setData(const QModelIndex &index, const QVariant &value, int role) override; + bool setData(const QModelIndex& index, const QVariant& value, int role) override; - void recreateCollapseButtons(TracePlot *tracePlot, CustomLabelScaleDraw *customLabelScaleDraw); + void recreateCollapseButtons(TracePlot* tracePlot, CustomLabelScaleDraw* customLabelScaleDraw); std::shared_ptr getClonedRootNode(); void setRootNode(std::shared_ptr node); public Q_SLOTS: - void itemsDoubleClicked(const QModelIndex &index); + void itemsDoubleClicked(const QModelIndex& index); - void addIndexesFromAvailableModel(const QModelIndexList &indexes); + void addIndexesFromAvailableModel(const QModelIndexList& indexes); protected: - bool eventFilter(QObject *object, QEvent *event) override; + bool eventFilter(QObject* object, QEvent* event) override; - QVariant headerData(int section, Qt::Orientation orientation, int role = Qt::DisplayRole) const override; - bool removeRows(int row, int count, const QModelIndex &parent = QModelIndex()) override; + QVariant + headerData(int section, Qt::Orientation orientation, int role = Qt::DisplayRole) const override; + bool removeRows(int row, int count, const QModelIndex& parent = QModelIndex()) override; private: - std::vector collapseButtons; + std::vector collapseButtons; friend class TracePlotLineDataSource; }; @@ -254,16 +267,11 @@ class TracePlotLineDataSource : public QObject public: using TracePlotLine = AbstractTracePlotLineModel::Node; - explicit TracePlotLineDataSource(SelectedTracePlotLineModel *selectedModel, QObject *parent = nullptr); + explicit TracePlotLineDataSource(SelectedTracePlotLineModel* selectedModel, + QObject* parent = nullptr); - SelectedTracePlotLineModel *getSelectedModel() const - { - return selectedModel; - }; - std::vector> &getTracePlotLines() - { - return entries; - } + SelectedTracePlotLineModel* getSelectedModel() const { return selectedModel; }; + std::vector>& getTracePlotLines() { return entries; } public Q_SLOTS: void updateModel(); @@ -272,7 +280,7 @@ Q_SIGNALS: void modelChanged(); private: - SelectedTracePlotLineModel *selectedModel; + SelectedTracePlotLineModel* selectedModel; std::vector> entries; }; diff --git a/extensions/apps/traceAnalyzer/businessObjects/tracetime.h b/extensions/apps/traceAnalyzer/businessObjects/tracetime.h index b63009ab..7038a7e1 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/tracetime.h +++ b/extensions/apps/traceAnalyzer/businessObjects/tracetime.h @@ -51,8 +51,7 @@ inline QString prettyFormatTime(traceTime time) inline QString formatInClks(traceTime time, unsigned int clkPeriod) { long long numberOfClockCovered = time / clkPeriod; - QString suffix = (numberOfClockCovered != 1) ? QString(" clks") : - QString(" clk"); + QString suffix = (numberOfClockCovered != 1) ? QString(" clks") : QString(" clk"); return QString::number(numberOfClockCovered) + suffix; } @@ -61,5 +60,4 @@ inline traceTime alignToClk(traceTime time, unsigned int clkPeriod) return round(1.0 * time / clkPeriod) * clkPeriod; } - #endif // TRACETIME_H diff --git a/extensions/apps/traceAnalyzer/businessObjects/transaction.cpp b/extensions/apps/traceAnalyzer/businessObjects/transaction.cpp index 395d25d4..b04a7ae9 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/transaction.cpp +++ b/extensions/apps/traceAnalyzer/businessObjects/transaction.cpp @@ -44,25 +44,44 @@ using namespace std; unsigned int Transaction::mSNumTransactions = 0; -Transaction::Transaction(ID id, QString command, unsigned int address, unsigned int dataLength, - unsigned int thread, unsigned int channel, Timespan span, traceTime clk) - : clk(clk), command(std::move(command)), address(address), dataLength(dataLength), thread(thread), channel(channel), - span(span), id(id) {} +Transaction::Transaction(ID id, + QString command, + unsigned int address, + unsigned int dataLength, + unsigned int thread, + unsigned int channel, + Timespan span, + traceTime clk) : + clk(clk), + command(std::move(command)), + address(address), + dataLength(dataLength), + thread(thread), + channel(channel), + span(span), + id(id) +{ +} void Transaction::addPhase(const shared_ptr& phase) { phases.push_back(phase); } -void Transaction::draw(QPainter *painter, const QwtScaleMap &xMap, - const QwtScaleMap &yMap, const QRectF &canvasRect, bool highlight, - const TraceDrawingProperties &drawingProperties) const +void Transaction::draw(QPainter* painter, + const QwtScaleMap& xMap, + const QwtScaleMap& yMap, + const QRectF& canvasRect, + bool highlight, + const TraceDrawingProperties& drawingProperties) const { for (const shared_ptr& phase : phases) phase->draw(painter, xMap, yMap, canvasRect, highlight, drawingProperties); } -bool Transaction::isSelected(Timespan timespan, double yVal, const TraceDrawingProperties &drawingproperties) const +bool Transaction::isSelected(Timespan timespan, + double yVal, + const TraceDrawingProperties& drawingproperties) const { if (span.overlaps(timespan)) { diff --git a/extensions/apps/traceAnalyzer/businessObjects/transaction.h b/extensions/apps/traceAnalyzer/businessObjects/transaction.h index 29e62530..0c99c6f6 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/transaction.h +++ b/extensions/apps/traceAnalyzer/businessObjects/transaction.h @@ -38,11 +38,11 @@ #ifndef TRANSACTION_H #define TRANSACTION_H -#include -#include -#include "timespan.h" #include "phases/phase.h" #include "presentation/tracedrawingproperties.h" +#include "timespan.h" +#include +#include typedef unsigned int ID; @@ -59,20 +59,28 @@ public: const Timespan span; const ID id; - Transaction(ID id, QString command, unsigned int address, unsigned int dataLength, unsigned int thread, - unsigned int channel, Timespan span, traceTime clk); + Transaction(ID id, + QString command, + unsigned int address, + unsigned int dataLength, + unsigned int thread, + unsigned int channel, + Timespan span, + traceTime clk); - void draw(QPainter *painter, const QwtScaleMap &xMap, const QwtScaleMap &yMap, - const QRectF &canvasRect, bool highlight, - const TraceDrawingProperties &drawingProperties) const; + void draw(QPainter* painter, + const QwtScaleMap& xMap, + const QwtScaleMap& yMap, + const QRectF& canvasRect, + bool highlight, + const TraceDrawingProperties& drawingProperties) const; void addPhase(const std::shared_ptr& phase); - bool isSelected(Timespan timespan, double yVal, const TraceDrawingProperties &drawingproperties) const; + bool isSelected(Timespan timespan, + double yVal, + const TraceDrawingProperties& drawingproperties) const; - const std::vector> &Phases() const - { - return phases; - } + const std::vector>& Phases() const { return phases; } public: static void setNumTransactions(const unsigned int numTransactions) diff --git a/extensions/apps/traceAnalyzer/data/QueryTexts.h b/extensions/apps/traceAnalyzer/data/QueryTexts.h index deef0e8d..9c11eae8 100644 --- a/extensions/apps/traceAnalyzer/data/QueryTexts.h +++ b/extensions/apps/traceAnalyzer/data/QueryTexts.h @@ -40,28 +40,35 @@ #define QUERYTEXTS_H #include -struct TransactionQueryTexts { +struct TransactionQueryTexts +{ QString queryHead; QString selectTransactionsByTimespan, selectTransactionById; QString checkDependenciesExist, selectDependenciesByTimespan; - QString selectDependencyTypePercentages, selectTimeDependencyPercentages, selectDelayedPhasePercentages, - selectDependencyPhasePercentages; + QString selectDependencyTypePercentages, selectTimeDependencyPercentages, + selectDelayedPhasePercentages, selectDependencyPhasePercentages; TransactionQueryTexts() { - queryHead = - "SELECT Transactions.ID AS TransactionID, Ranges.begin, Ranges.end, Address, DataLength, Thread, Channel, Command, Phases.ID AS PhaseID, PhaseName, PhaseBegin, PhaseEnd, DataStrobeBegin, DataStrobeEnd, Rank, BankGroup, Bank, Row, Column, BurstLength " - " FROM Transactions INNER JOIN Phases ON Phases.Transact = Transactions.ID INNER JOIN Ranges ON Transactions.Range = Ranges.ID "; + queryHead = "SELECT Transactions.ID AS TransactionID, Ranges.begin, Ranges.end, Address, " + "DataLength, Thread, Channel, Command, Phases.ID AS PhaseID, PhaseName, " + "PhaseBegin, PhaseEnd, DataStrobeBegin, DataStrobeEnd, Rank, BankGroup, Bank, " + "Row, Column, BurstLength " + " FROM Transactions INNER JOIN Phases ON Phases.Transact = Transactions.ID " + "INNER JOIN Ranges ON Transactions.Range = Ranges.ID "; - selectTransactionsByTimespan = queryHead + " WHERE Ranges.end >= :begin AND Ranges.begin <= :end"; + selectTransactionsByTimespan = + queryHead + " WHERE Ranges.end >= :begin AND Ranges.begin <= :end"; selectTransactionById = queryHead + " WHERE Transactions.ID = :id"; - checkDependenciesExist = "SELECT CASE WHEN 0 < (SELECT count(*) FROM sqlite_master WHERE type = 'table' AND " - "name = 'DirectDependencies') THEN 1 ELSE 0 END AS result"; + checkDependenciesExist = + "SELECT CASE WHEN 0 < (SELECT count(*) FROM sqlite_master WHERE type = 'table' AND " + "name = 'DirectDependencies') THEN 1 ELSE 0 END AS result"; selectDependenciesByTimespan = "WITH timespanTransactions AS (" + selectTransactionsByTimespan + ") SELECT * from DirectDependencies WHERE DelayedPhaseID IN (" - " SELECT DirectDependencies.DelayedPhaseID FROM DirectDependencies JOIN timespanTransactions " + " SELECT DirectDependencies.DelayedPhaseID FROM DirectDependencies JOIN " + "timespanTransactions " " ON DirectDependencies.DelayedPhaseID = timespanTransactions.PhaseID ) "; // For some reason I could not use a parameter for these below @@ -125,7 +132,6 @@ struct TransactionQueryTexts { "FROM DependencyTypeDeps " "ORDER BY percentage DESC ;"; } - }; #endif // QUERYTEXTS_H diff --git a/extensions/apps/traceAnalyzer/data/tracedb.cpp b/extensions/apps/traceAnalyzer/data/tracedb.cpp index 712a51d9..48526f90 100644 --- a/extensions/apps/traceAnalyzer/data/tracedb.cpp +++ b/extensions/apps/traceAnalyzer/data/tracedb.cpp @@ -37,20 +37,19 @@ * Iron Prando da Silva */ -#include -#include -#include -#include -#include -#include -#include -#include #include "data/tracedb.h" #include "businessObjects/phases/phasefactory.h" +#include +#include +#include +#include +#include +#include +#include +#include - -//define symbol printqueries if all queries should be printed to the console -//#define printqueries +// define symbol printqueries if all queries should be printed to the console +// #define printqueries TraceDB::TraceDB(const QString& path, bool openExisting) { @@ -88,11 +87,14 @@ void TraceDB::prepareQueries() qDebug() << database.lastError().text(); selectDebugMessagesByTimespan = QSqlQuery(database); - if (!selectDebugMessagesByTimespan.prepare("SELECT time, Message FROM DebugMessages WHERE :begin <= time AND time <= :end ")) + if (!selectDebugMessagesByTimespan.prepare( + "SELECT time, Message FROM DebugMessages WHERE :begin <= time AND time <= :end ")) qDebug() << database.lastError().text(); selectDebugMessagesByTimespanWithLimit = QSqlQuery(database); - if (!selectDebugMessagesByTimespanWithLimit.prepare("SELECT time, Message FROM DebugMessages WHERE :begin <= time AND time <= :end LIMIT :limit")) + if (!selectDebugMessagesByTimespanWithLimit.prepare( + "SELECT time, Message FROM DebugMessages WHERE :begin <= time AND time <= :end LIMIT " + ":limit")) qDebug() << database.lastError().text(); checkDependenciesExist = QSqlQuery(database); @@ -102,17 +104,16 @@ void TraceDB::prepareQueries() selectDependenciesByTimespan = QSqlQuery(database); if (!selectDependenciesByTimespan.prepare(queryTexts.selectDependenciesByTimespan)) qDebug() << database.lastError().text(); - } -void TraceDB::updateComments(const std::vector &comments) +void TraceDB::updateComments(const std::vector& comments) { QSqlQuery query(database); query.prepare("DELETE FROM Comments"); executeQuery(query); query.prepare("insert into Comments values(:time,:text)"); - for (const auto &comment : comments) + for (const auto& comment : comments) { query.bindValue(":time", comment.time); query.bindValue(":text", comment.text); @@ -120,7 +121,7 @@ void TraceDB::updateComments(const std::vector &comments) } } -void TraceDB::updateFileDescription(const QString &description) +void TraceDB::updateFileDescription(const QString& description) { QSqlQuery query(database); query.prepare("UPDATE GeneralInfo SET Description=:description"); @@ -134,9 +135,11 @@ void TraceDB::refreshData() generalInfo = getGeneralInfoFromDB(); } -//QueryText must select the fields -//TransactionID, Ranges.begin, Ranges.end, Address, TThread, TChannel, TBank, TRow, TColumn, Phases.ID AS PhaseID, PhaseName, PhaseBegin, PhaseEnd -std::vector> TraceDB::getTransactionsWithCustomQuery(const QString& queryText) +// QueryText must select the fields +// TransactionID, Ranges.begin, Ranges.end, Address, TThread, TChannel, TBank, TRow, TColumn, +// Phases.ID AS PhaseID, PhaseName, PhaseBegin, PhaseEnd +std::vector> +TraceDB::getTransactionsWithCustomQuery(const QString& queryText) { QSqlQuery query(database); query.prepare(queryText); @@ -144,7 +147,8 @@ std::vector> TraceDB::getTransactionsWithCustomQuer return parseTransactionsFromQuery(query); } -std::vector> TraceDB::getTransactionsInTimespan(const Timespan &span, bool updateVisiblePhases) +std::vector> +TraceDB::getTransactionsInTimespan(const Timespan& span, bool updateVisiblePhases) { selectTransactionsByTimespan.bindValue(":begin", span.Begin()); selectTransactionsByTimespan.bindValue(":end", span.End()); @@ -163,7 +167,7 @@ bool TraceDB::checkDependencyTableExists() return exists; } -void TraceDB::updateDependenciesInTimespan(const Timespan &span) +void TraceDB::updateDependenciesInTimespan(const Timespan& span) { if (checkDependencyTableExists()) { @@ -174,7 +178,7 @@ void TraceDB::updateDependenciesInTimespan(const Timespan &span) } } -//TODO Remove exception +// TODO Remove exception std::shared_ptr TraceDB::getTransactionByID(ID id) { selectTransactionById.bindValue(":id", id); @@ -183,16 +187,17 @@ std::shared_ptr TraceDB::getTransactionByID(ID id) if (!result.empty()) return result[0]; else - throw sqlException(("Transaction with ID " + QString::number( - id) + " not in DB").toStdString(), this->pathToDB.toStdString()); + throw sqlException( + ("Transaction with ID " + QString::number(id) + " not in DB").toStdString(), + this->pathToDB.toStdString()); } - std::shared_ptr TraceDB::getNextActivate(traceTime time) { QSqlQuery query(database); - QString queryText = queryTexts.queryHead + - "WHERE PhaseBegin > :traceTime AND PhaseName = 'ACT' ORDER BY PhaseBegin ASC LIMIT 1"; + QString queryText = + queryTexts.queryHead + + "WHERE PhaseBegin > :traceTime AND PhaseName = 'ACT' ORDER BY PhaseBegin ASC LIMIT 1"; query.prepare(queryText); query.bindValue(":traceTime", time); @@ -242,7 +247,8 @@ std::shared_ptr TraceDB::getNextRefresh(traceTime time) QSqlQuery query(database); QString queryText = queryTexts.queryHead + "WHERE PhaseBegin > :traceTime AND PhaseName " - "IN ('REFAB','REFA','REFB','REFPB','REFP2B','REFSB','SREF','SREFB') ORDER BY PhaseBegin ASC LIMIT 1"; + "IN ('REFAB','REFA','REFB','REFPB','REFP2B','REFSB','SREF','SREFB') ORDER " + "BY PhaseBegin ASC LIMIT 1"; query.prepare(queryText); query.bindValue(":traceTime", time); executeQuery(query); @@ -252,8 +258,8 @@ std::shared_ptr TraceDB::getNextRefresh(traceTime time) std::shared_ptr TraceDB::getNextCommand(traceTime time) { QSqlQuery query(database); - QString queryText = queryTexts.queryHead + - "WHERE PhaseBegin > :traceTime ORDER BY PhaseBegin ASC LIMIT 1"; + QString queryText = + queryTexts.queryHead + "WHERE PhaseBegin > :traceTime ORDER BY PhaseBegin ASC LIMIT 1"; query.prepare(queryText); query.bindValue(":traceTime", time); executeQuery(query); @@ -279,9 +285,12 @@ ID TraceDB::getTransactionIDFromPhaseID(ID phaseID) query.bindValue(":id", phaseID); executeQuery(query); - if (query.next()) { + if (query.next()) + { return query.value(0).toInt(); - } else { + } + else + { throw sqlException("Phase with ID " + std::to_string(phaseID) + " not in db", this->pathToDB.toStdString()); } @@ -300,11 +309,12 @@ GeneralInfo TraceDB::getGeneralInfoFromDB() parameter = getParameterFromTable("UnitOfTime", "GeneralInfo"); QString unitOfTime = parameter.isValid() ? parameter.toString() : "PS"; parameter = getParameterFromTable("Traces", "GeneralInfo"); - QString traces = parameter.isValid() ? "Traces: " + parameter.toString() : "Traces: empty"; + QString traces = parameter.isValid() ? "Traces: " + parameter.toString() : "Traces: empty"; parameter = getParameterFromTable("Memspec", "GeneralInfo"); - QString memspec = parameter.isValid() ? "Memspec: " + parameter.toString() : "Memspec: empty"; + QString memspec = parameter.isValid() ? "Memspec: " + parameter.toString() : "Memspec: empty"; parameter = getParameterFromTable("MCconfig", "GeneralInfo"); - QString mcconfig = parameter.isValid() ? "MCconfig: " + parameter.toString() : "MCconfig: empty"; + QString mcconfig = + parameter.isValid() ? "MCconfig: " + parameter.toString() : "MCconfig: empty"; parameter = getParameterFromTable("WindowSize", "GeneralInfo"); uint64_t windowSize = parameter.isValid() ? parameter.toULongLong() : 0; parameter = getParameterFromTable("RefreshMaxPostponed", "GeneralInfo"); @@ -334,21 +344,34 @@ GeneralInfo TraceDB::getGeneralInfoFromDB() description += "Length of trace: " + prettyFormatTime(traceEnd) + "\n"; description += "Window size: " + QString::number(windowSize) + "\n"; - return {numberOfTransactions, numberOfPhases, Timespan(0, traceEnd), - numberOfRanks, numberOfBankGroups, numberOfBanks, - description, unitOfTime, clkPeriod, - windowSize, refreshMaxPostponed, refreshMaxPulledin, - controllerThread, maxBufferDepth, per2BankOffset, - rowColumnCommandBus, pseudoChannelMode}; + return {numberOfTransactions, + numberOfPhases, + Timespan(0, traceEnd), + numberOfRanks, + numberOfBankGroups, + numberOfBanks, + description, + unitOfTime, + clkPeriod, + windowSize, + refreshMaxPostponed, + refreshMaxPulledin, + controllerThread, + maxBufferDepth, + per2BankOffset, + rowColumnCommandBus, + pseudoChannelMode}; } CommandLengths TraceDB::getCommandLengthsFromDB() { const std::string table = "CommandLengths"; - auto getLengthFromDb = [=, &table](const std::string &command) -> QVariant + auto getLengthFromDb = [=, &table](const std::string& command) -> QVariant { - QSqlQuery query(("SELECT Length FROM " + table + " WHERE Command = \"" + command + "\"").c_str(), database); + QSqlQuery query( + ("SELECT Length FROM " + table + " WHERE Command = \"" + command + "\"").c_str(), + database); if (query.first()) return query.value(0); @@ -356,7 +379,7 @@ CommandLengths TraceDB::getCommandLengthsFromDB() return {}; }; - auto getCommandLength = [=, &table](const std::string &command) -> double + auto getCommandLength = [=, &table](const std::string& command) -> double { QVariant length = getLengthFromDb(command); @@ -364,8 +387,8 @@ CommandLengths TraceDB::getCommandLengthsFromDB() return length.toDouble(); else { - qDebug() << "CommandLength for" << command.c_str() << "not present in table" << table.c_str() - << ". Defaulting to 1."; + qDebug() << "CommandLength for" << command.c_str() << "not present in table" + << table.c_str() << ". Defaulting to 1."; return 1; } }; @@ -455,8 +478,7 @@ std::vector TraceDB::getComments() return parseCommentsFromQuery(query); } - -std::vector TraceDB::getDebugMessagesInTimespan(const Timespan &span) +std::vector TraceDB::getDebugMessagesInTimespan(const Timespan& span) { selectDebugMessagesByTimespan.bindValue(":begin", span.Begin()); selectDebugMessagesByTimespan.bindValue(":end", span.End()); @@ -465,8 +487,8 @@ std::vector TraceDB::getDebugMessagesInTimespan(const Tim return parseCommentsFromQuery(selectDebugMessagesByTimespan); } -std::vector TraceDB::getDebugMessagesInTimespan(const Timespan &span, - unsigned int limit = 50) +std::vector TraceDB::getDebugMessagesInTimespan(const Timespan& span, + unsigned int limit = 50) { selectDebugMessagesByTimespanWithLimit.bindValue(":begin", span.Begin()); selectDebugMessagesByTimespanWithLimit.bindValue(":end", span.End()); @@ -485,46 +507,45 @@ DependencyInfos TraceDB::getDependencyInfos(DependencyInfos::Type infoType) switch (infoType) { - case DependencyInfos::Type::DependencyType: - { - selectDependencyTypePercentages = QSqlQuery(database); - if (!selectDependencyTypePercentages.prepare(queryTexts.selectDependencyTypePercentages)) - qDebug() << database.lastError().text(); + case DependencyInfos::Type::DependencyType: + { + selectDependencyTypePercentages = QSqlQuery(database); + if (!selectDependencyTypePercentages.prepare(queryTexts.selectDependencyTypePercentages)) + qDebug() << database.lastError().text(); - executeQuery(selectDependencyTypePercentages); - return parseDependencyInfos(selectDependencyTypePercentages, infoType); - } + executeQuery(selectDependencyTypePercentages); + return parseDependencyInfos(selectDependencyTypePercentages, infoType); + } - case DependencyInfos::Type::TimeDependency: - { - selectTimeDependencyPercentages = QSqlQuery(database); - if (!selectTimeDependencyPercentages.prepare(queryTexts.selectTimeDependencyPercentages)) - qDebug() << database.lastError().text(); + case DependencyInfos::Type::TimeDependency: + { + selectTimeDependencyPercentages = QSqlQuery(database); + if (!selectTimeDependencyPercentages.prepare(queryTexts.selectTimeDependencyPercentages)) + qDebug() << database.lastError().text(); - executeQuery(selectTimeDependencyPercentages); - return parseDependencyInfos(selectTimeDependencyPercentages, infoType); - } + executeQuery(selectTimeDependencyPercentages); + return parseDependencyInfos(selectTimeDependencyPercentages, infoType); + } - case DependencyInfos::Type::DelayedPhase: - { - selectDelayedPhasePercentages = QSqlQuery(database); - if (!selectDelayedPhasePercentages.prepare(queryTexts.selectDelayedPhasePercentages)) - qDebug() << database.lastError().text(); + case DependencyInfos::Type::DelayedPhase: + { + selectDelayedPhasePercentages = QSqlQuery(database); + if (!selectDelayedPhasePercentages.prepare(queryTexts.selectDelayedPhasePercentages)) + qDebug() << database.lastError().text(); - executeQuery(selectDelayedPhasePercentages); - return parseDependencyInfos(selectDelayedPhasePercentages, infoType); - } + executeQuery(selectDelayedPhasePercentages); + return parseDependencyInfos(selectDelayedPhasePercentages, infoType); + } - case DependencyInfos::Type::DependencyPhase: - { - selectDependencyPhasePercentages = QSqlQuery(database); - if (!selectDependencyPhasePercentages.prepare(queryTexts.selectDependencyPhasePercentages)) - qDebug() << database.lastError().text(); - - executeQuery(selectDependencyPhasePercentages); - return parseDependencyInfos(selectDependencyPhasePercentages, infoType); - } + case DependencyInfos::Type::DependencyPhase: + { + selectDependencyPhasePercentages = QSqlQuery(database); + if (!selectDependencyPhasePercentages.prepare(queryTexts.selectDependencyPhasePercentages)) + qDebug() << database.lastError().text(); + executeQuery(selectDependencyPhasePercentages); + return parseDependencyInfos(selectDependencyPhasePercentages, infoType); + } } return dummy; @@ -541,8 +562,7 @@ QSqlDatabase TraceDB::getDatabase() const * */ - -std::shared_ptr TraceDB::parseTransactionFromQuery(QSqlQuery &query) +std::shared_ptr TraceDB::parseTransactionFromQuery(QSqlQuery& query) { auto result = parseTransactionsFromQuery(query); if (!result.empty()) @@ -551,7 +571,8 @@ std::shared_ptr TraceDB::parseTransactionFromQuery(QSqlQuery &query return {}; } -std::vector> TraceDB::parseTransactionsFromQuery(QSqlQuery &query, bool updateVisiblePhases) +std::vector> +TraceDB::parseTransactionsFromQuery(QSqlQuery& query, bool updateVisiblePhases) { if (updateVisiblePhases) { @@ -579,8 +600,14 @@ std::vector> TraceDB::parseTransactionsFromQuery(QS unsigned int thread = query.value(5).toUInt(); unsigned int channel = query.value(6).toUInt(); QString command = query.value(7).toString(); - result.push_back(std::make_shared(id, std::move(command), address, dataLength, thread, channel, - span, generalInfo.clkPeriod)); + result.push_back(std::make_shared(id, + std::move(command), + address, + dataLength, + thread, + channel, + span, + generalInfo.clkPeriod)); } unsigned int phaseID = query.value(8).toInt(); @@ -593,8 +620,18 @@ std::vector> TraceDB::parseTransactionsFromQuery(QS unsigned int row = query.value(17).toUInt(); unsigned int column = query.value(18).toUInt(); unsigned int burstLength = query.value(19).toUInt(); - auto phase = PhaseFactory::createPhase(phaseID, phaseName, span, spanOnDataStrobe, rank, bankGroup, bank, - row, column, burstLength, result.at(result.size() - 1), *this); + auto phase = PhaseFactory::createPhase(phaseID, + phaseName, + span, + spanOnDataStrobe, + rank, + bankGroup, + bank, + row, + column, + burstLength, + result.at(result.size() - 1), + *this); result.at(result.size() - 1)->addPhase(phase); if (updateVisiblePhases) @@ -605,7 +642,7 @@ std::vector> TraceDB::parseTransactionsFromQuery(QS return result; } -void TraceDB::mUpdateDependenciesFromQuery(QSqlQuery &query) +void TraceDB::mUpdateDependenciesFromQuery(QSqlQuery& query) { DependencyType type; while (query.next()) @@ -636,13 +673,13 @@ void TraceDB::mUpdateDependenciesFromQuery(QSqlQuery &query) { _visiblePhases[delayedID]->addDependency(std::make_shared( - PhaseDependency(type, timeDependencyStr, _visiblePhases[dependencyID]))); + PhaseDependency(type, timeDependencyStr, _visiblePhases[dependencyID]))); } else { _visiblePhases[delayedID]->addDependency( - std::make_shared(PhaseDependency(type, timeDependencyStr))); + std::make_shared(PhaseDependency(type, timeDependencyStr))); } } else @@ -652,18 +689,19 @@ void TraceDB::mUpdateDependenciesFromQuery(QSqlQuery &query) } } -std::vector TraceDB::parseCommentsFromQuery(QSqlQuery &query) +std::vector TraceDB::parseCommentsFromQuery(QSqlQuery& query) { std::vector result; while (query.next()) { - result.push_back(CommentModel::Comment{query.value(0).toLongLong(), - query.value(1).toString()}); + result.push_back( + CommentModel::Comment{query.value(0).toLongLong(), query.value(1).toString()}); } return result; } -DependencyInfos TraceDB::parseDependencyInfos(QSqlQuery &query, const DependencyInfos::Type infoType) +DependencyInfos TraceDB::parseDependencyInfos(QSqlQuery& query, + const DependencyInfos::Type infoType) { DependencyInfos infos(infoType); @@ -680,18 +718,21 @@ DependencyInfos TraceDB::parseDependencyInfos(QSqlQuery &query, const Dependency void TraceDB::executeQuery(QSqlQuery query) { - //query.exec returns bool indicating if the query was sucessfull - if (query.exec()) { + // query.exec returns bool indicating if the query was sucessfull + if (query.exec()) + { #ifdef printqueries cout << queryToString(query).toStdString() << endl; #endif } - else { + else + { query.finish(); - throw sqlException( ("Query:\n " + queryToString(query) + "\n failed. Error: \n" - + - query.lastError().text()).toStdString(), this->pathToDB.toStdString()); + throw sqlException( + ("Query:\n " + queryToString(query) + "\n failed. Error: \n" + query.lastError().text()) + .toStdString(), + this->pathToDB.toStdString()); } } @@ -699,14 +740,14 @@ QString TraceDB::queryToString(const QSqlQuery& query) { QString str = query.lastQuery(); QMapIterator it(query.boundValues()); - while (it.hasNext()) { + while (it.hasNext()) + { it.next(); str.replace(it.key(), it.value().toString()); } return str; } - void TraceDB::dropAndCreateTables() { executeScriptFile("common/static/createTraceDB.sql"); @@ -717,16 +758,20 @@ void TraceDB::executeScriptFile(const QString& fileName) QSqlQuery query(database); QFile scriptFile(fileName); - if (scriptFile.open(QIODevice::ReadOnly)) { + if (scriptFile.open(QIODevice::ReadOnly)) + { // The SQLite driver executes only a single (the first) query in the QSqlQuery // if the script contains more queries, it needs to be splitted. QStringList scriptQueries = QTextStream(&scriptFile).readAll().split(';'); - for (QString &queryTxt : scriptQueries) { - if (queryTxt.trimmed().isEmpty()) { + for (QString& queryTxt : scriptQueries) + { + if (queryTxt.trimmed().isEmpty()) + { continue; } - if (!query.exec(queryTxt)) { + if (!query.exec(queryTxt)) + { throw sqlException("Querry failed:" + query.lastError().text().toStdString(), this->pathToDB.toStdString()); } diff --git a/extensions/apps/traceAnalyzer/data/tracedb.h b/extensions/apps/traceAnalyzer/data/tracedb.h index c4e38be6..af871ed5 100644 --- a/extensions/apps/traceAnalyzer/data/tracedb.h +++ b/extensions/apps/traceAnalyzer/data/tracedb.h @@ -65,46 +65,36 @@ class TraceDB : public QObject public: TraceDB(const QString& path, bool openExisting); - const QString &getPathToDB() const - { - return pathToDB; - } + const QString& getPathToDB() const { return pathToDB; } - void updateComments(const std::vector &comments); - void updateFileDescription(const QString &description); - void updateDependenciesInTimespan(const Timespan &span); + void updateComments(const std::vector& comments); + void updateFileDescription(const QString& description); + void updateDependenciesInTimespan(const Timespan& span); void refreshData(); - const GeneralInfo &getGeneralInfo() const - { - return generalInfo; - } + const GeneralInfo& getGeneralInfo() const { return generalInfo; } - const CommandLengths &getCommandLengths() const - { - return commandLengths; - } + const CommandLengths& getCommandLengths() const { return commandLengths; } - std::vector> getTransactionsWithCustomQuery( - const QString& queryText); - std::vector> getTransactionsInTimespan(const Timespan &span, - bool updateVisiblePhases = false); + std::vector> + getTransactionsWithCustomQuery(const QString& queryText); + std::vector> + getTransactionsInTimespan(const Timespan& span, bool updateVisiblePhases = false); std::shared_ptr getNextPrecharge(traceTime time); std::shared_ptr getNextActivate(traceTime time); std::shared_ptr getNextRefresh(traceTime time); std::shared_ptr getNextCommand(traceTime time); -// std::shared_ptr getNextPreb(ID currentTransactionId); -// std::shared_ptr getNextActb(ID currentTransactionId); -// std::shared_ptr getNextRefb(ID currentTransactionId); - + // std::shared_ptr getNextPreb(ID currentTransactionId); + // std::shared_ptr getNextActb(ID currentTransactionId); + // std::shared_ptr getNextRefb(ID currentTransactionId); std::shared_ptr getTransactionByID(ID id); ID getTransactionIDFromPhaseID(ID phaseID); std::vector getComments(); - std::vector getDebugMessagesInTimespan(const Timespan &span); - std::vector getDebugMessagesInTimespan(const Timespan &span, - unsigned int limit); + std::vector getDebugMessagesInTimespan(const Timespan& span); + std::vector getDebugMessagesInTimespan(const Timespan& span, + unsigned int limit); bool checkDependencyTableExists(); DependencyInfos getDependencyInfos(DependencyInfos::Type infoType); @@ -134,13 +124,14 @@ private: void prepareQueries(); void executeQuery(QSqlQuery query); static QString queryToString(const QSqlQuery& query); - std::shared_ptr parseTransactionFromQuery(QSqlQuery &query); - std::vector> parseTransactionsFromQuery(QSqlQuery &query, - bool updateVisiblePhases = false); - static std::vector parseCommentsFromQuery(QSqlQuery &query); + std::shared_ptr parseTransactionFromQuery(QSqlQuery& query); + std::vector> + parseTransactionsFromQuery(QSqlQuery& query, bool updateVisiblePhases = false); + static std::vector parseCommentsFromQuery(QSqlQuery& query); - void mUpdateDependenciesFromQuery(QSqlQuery &query); - static DependencyInfos parseDependencyInfos(QSqlQuery &query, const DependencyInfos::Type infoType); + void mUpdateDependenciesFromQuery(QSqlQuery& query); + static DependencyInfos parseDependencyInfos(QSqlQuery& query, + const DependencyInfos::Type infoType); void executeScriptFile(const QString& fileName); void dropAndCreateTables(); @@ -152,27 +143,23 @@ private: CommandLengths getCommandLengthsFromDB(); QVariant getParameterFromTable(const std::string& parameter, const std::string& table); - std::map> _visiblePhases; // Updated at parseTransactionsFromQuery + std::map> + _visiblePhases; // Updated at parseTransactionsFromQuery // At businessObjects/phasedependenciestracker.h friend class PhaseDependenciesTracker; }; - - class sqlException : public std::exception { private: std::string message; + public: sqlException(std::string message, std::string filename) { - this->message = std::string("Error in file ") + filename + std::string(" ") + - message; - } - const char *what() const noexcept override - { - return message.c_str(); + this->message = std::string("Error in file ") + filename + std::string(" ") + message; } + const char* what() const noexcept override { return message.c_str(); } }; #endif // TRACEDB_H diff --git a/extensions/apps/traceAnalyzer/evaluationtool.cpp b/extensions/apps/traceAnalyzer/evaluationtool.cpp index cf419492..cc865e57 100644 --- a/extensions/apps/traceAnalyzer/evaluationtool.cpp +++ b/extensions/apps/traceAnalyzer/evaluationtool.cpp @@ -38,29 +38,29 @@ * Derek Christ */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include #include "evaluationtool.h" #include "ui_evaluationtool.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include -EvaluationTool::EvaluationTool(PythonCaller &pythonCaller, QWidget *parent) : +EvaluationTool::EvaluationTool(PythonCaller& pythonCaller, QWidget* parent) : QWidget(parent), - ui(new Ui::EvaluationTool), pythonCaller(pythonCaller) + ui(new Ui::EvaluationTool), + pythonCaller(pythonCaller) { ui->setupUi(this); traceFilesModel = new QStandardItemModel(this); ui->listView->setModel(traceFilesModel); selectMetrics = new SelectMetrics(this); - QObject::connect(selectMetrics, SIGNAL(getSelectedMetrics()), this, - SLOT(getSelectedMetrics())); + QObject::connect(selectMetrics, SIGNAL(getSelectedMetrics()), this, SLOT(getSelectedMetrics())); } EvaluationTool::~EvaluationTool() @@ -88,9 +88,11 @@ void EvaluationTool::showAndEvaluateMetrics(QList paths) std::vector EvaluationTool::getMetrics() { std::vector metrics; - for (int row = 0; row < traceFilesModel->rowCount(); ++row) { - TraceFileItem *item = static_cast(traceFilesModel->item(row)); - std::vector result = PythonCaller::availableMetrics(item->getPath().toStdString()); + for (int row = 0; row < traceFilesModel->rowCount(); ++row) + { + TraceFileItem* item = static_cast(traceFilesModel->item(row)); + std::vector result = + PythonCaller::availableMetrics(item->getPath().toStdString()); if (result.size() > metrics.size()) // TODO use std::set metrics = result; } @@ -106,11 +108,12 @@ void EvaluationTool::cleanUpUI() void EvaluationTool::fillFileList(QList paths) { - std::sort(paths.begin(), paths.end(), [] (const QString & path1, - const QString & path2) { - return QFileInfo(path1).baseName() < QFileInfo(path2).baseName(); - }); - for (const QString &path : paths) { + std::sort(paths.begin(), + paths.end(), + [](const QString& path1, const QString& path2) + { return QFileInfo(path1).baseName() < QFileInfo(path2).baseName(); }); + for (const QString& path : paths) + { traceFilesModel->appendRow(new TraceFileItem(path)); } } @@ -125,7 +128,8 @@ void EvaluationTool::on_btn_calculateMetrics_clicked() void EvaluationTool::getSelectedMetrics() { std::vector selectedMetrics; - for (QCheckBox *metric : selectMetrics->metrics) { + for (QCheckBox* metric : selectMetrics->metrics) + { selectedMetrics.push_back(metric->isChecked()); } calculateMetrics(selectedMetrics); @@ -134,11 +138,13 @@ void EvaluationTool::getSelectedMetrics() void EvaluationTool::calculateMetrics(std::vector selectedMetrics) { ui->traceMetricTreeWidget->clear(); - for (int row = 0; row < traceFilesModel->rowCount(); ++row) { - TraceFileItem *item = static_cast(traceFilesModel->item(row)); + for (int row = 0; row < traceFilesModel->rowCount(); ++row) + { + TraceFileItem* item = static_cast(traceFilesModel->item(row)); if (item->checkState() == Qt::Checked) { - TraceCalculatedMetrics result = pythonCaller.evaluateMetrics(item->getPath().toStdString(), selectedMetrics); + TraceCalculatedMetrics result = + pythonCaller.evaluateMetrics(item->getPath().toStdString(), selectedMetrics); calculatedMetrics.push_back(result); ui->traceMetricTreeWidget->addTraceMetricResults(result); } @@ -146,7 +152,7 @@ void EvaluationTool::calculateMetrics(std::vector selectedMetrics) ui->traceMetricTreeWidget->expandAll(); } -EvaluationTool::TraceFileItem::TraceFileItem(const QString &path) +EvaluationTool::TraceFileItem::TraceFileItem(const QString& path) { this->path = path; setText(QFileInfo(this->path).baseName()); @@ -157,15 +163,18 @@ EvaluationTool::TraceFileItem::TraceFileItem(const QString &path) void EvaluationTool::on_btn_exportCSV_clicked() { - if (calculatedMetrics.size() > 0) { - QString filename = QFileDialog::getSaveFileName(this, "Export to CSV", "", - "Comma separated Values(*.csv)"); - if (filename != "") { + if (calculatedMetrics.size() > 0) + { + QString filename = QFileDialog::getSaveFileName( + this, "Export to CSV", "", "Comma separated Values(*.csv)"); + if (filename != "") + { QFile file(filename); file.open(QIODevice::WriteOnly | QIODevice::Text); QTextStream out(&file); out << calculatedMetrics[0].toCSVHeader() << "\n"; - for (TraceCalculatedMetrics &metrics : calculatedMetrics) { + for (TraceCalculatedMetrics& metrics : calculatedMetrics) + { out << metrics.toCSVLine() << "\n"; } file.close(); @@ -187,7 +196,7 @@ void EvaluationTool::genPlots() for (int row = 0; row < traceFilesModel->rowCount(); ++row) { - TraceFileItem *item = static_cast(traceFilesModel->item(row)); + TraceFileItem* item = static_cast(traceFilesModel->item(row)); if (item->checkState() == Qt::Checked) { ui->traceMetricTreeWidget->addTracePlotResults( diff --git a/extensions/apps/traceAnalyzer/evaluationtool.h b/extensions/apps/traceAnalyzer/evaluationtool.h index 406ea9ed..d768d11f 100644 --- a/extensions/apps/traceAnalyzer/evaluationtool.h +++ b/extensions/apps/traceAnalyzer/evaluationtool.h @@ -43,16 +43,17 @@ #include "selectmetrics.h" -#include -#include -#include -#include -#include -#include #include "businessObjects/pythoncaller.h" #include "businessObjects/tracecalculatedmetrics.h" +#include +#include +#include +#include +#include +#include -namespace Ui { +namespace Ui +{ class EvaluationTool; } @@ -61,7 +62,7 @@ class EvaluationTool : public QWidget Q_OBJECT public: - explicit EvaluationTool(PythonCaller &pythonCaller, QWidget *parent = nullptr); + explicit EvaluationTool(PythonCaller& pythonCaller, QWidget* parent = nullptr); ~EvaluationTool(); void showForFiles(QList paths); @@ -80,27 +81,22 @@ private: void calculateMetrics(std::vector selectedMetrics); std::vector getMetrics(); - - Ui::EvaluationTool *ui; - QStandardItemModel *traceFilesModel; + Ui::EvaluationTool* ui; + QStandardItemModel* traceFilesModel; std::vector calculatedMetrics; - SelectMetrics *selectMetrics; + SelectMetrics* selectMetrics; - PythonCaller &pythonCaller; + PythonCaller& pythonCaller; class TraceFileItem : public QStandardItem { public: - TraceFileItem(const QString &path); - QString getPath() - { - return path; - } + TraceFileItem(const QString& path); + QString getPath() { return path; } private: QString path; }; - }; #endif // EVALUATIONTOOL_H diff --git a/extensions/apps/traceAnalyzer/gototimedialog.cpp b/extensions/apps/traceAnalyzer/gototimedialog.cpp index 751d554f..53b4e99c 100644 --- a/extensions/apps/traceAnalyzer/gototimedialog.cpp +++ b/extensions/apps/traceAnalyzer/gototimedialog.cpp @@ -39,7 +39,7 @@ #include "ui_gototimedialog.h" #include -GoToTimeDialog::GoToTimeDialog(double *goToSecond, QWidget *parent) : +GoToTimeDialog::GoToTimeDialog(double* goToSecond, QWidget* parent) : QDialog(parent), goToSecond(goToSecond), ui(new Ui::GoToTimeDialog) @@ -59,8 +59,8 @@ void GoToTimeDialog::on_pushButton_clicked() *goToSecond = c.toDouble(ui->timeEdit->text(), &validNumber); if (validNumber) accept(); - else { - QMessageBox::warning(this, "Invalid number", - "Please enter a valid floating point number"); + else + { + QMessageBox::warning(this, "Invalid number", "Please enter a valid floating point number"); } } diff --git a/extensions/apps/traceAnalyzer/gototimedialog.h b/extensions/apps/traceAnalyzer/gototimedialog.h index 4077f0d6..0140957b 100644 --- a/extensions/apps/traceAnalyzer/gototimedialog.h +++ b/extensions/apps/traceAnalyzer/gototimedialog.h @@ -39,9 +39,8 @@ #define GOTOTIMEDIALOG_H #include - - -namespace Ui { +namespace Ui +{ class GoToTimeDialog; } @@ -50,18 +49,17 @@ class GoToTimeDialog : public QDialog Q_OBJECT public: - explicit GoToTimeDialog(double *goToSecond, QWidget *parent = 0); + explicit GoToTimeDialog(double* goToSecond, QWidget* parent = 0); ~GoToTimeDialog(); - private: - double *goToSecond; + double* goToSecond; private Q_SLOTS: void on_pushButton_clicked(); private: - Ui::GoToTimeDialog *ui; + Ui::GoToTimeDialog* ui; }; #endif // GOTOTIMEDIALOG_H diff --git a/extensions/apps/traceAnalyzer/main.cpp b/extensions/apps/traceAnalyzer/main.cpp index 71efabeb..8b9627f2 100644 --- a/extensions/apps/traceAnalyzer/main.cpp +++ b/extensions/apps/traceAnalyzer/main.cpp @@ -46,7 +46,7 @@ #include #include -int main(int argc, char *argv[]) +int main(int argc, char* argv[]) { std::cout << argv[0] << std::endl; QApplication a(argc, argv); @@ -66,28 +66,33 @@ int main(int argc, char *argv[]) pybind11::list path = sys.attr("path"); path.append(modulesDir.c_str()); - if (argc > 1) { + if (argc > 1) + { QSet arguments; for (int i = 1; i < argc; ++i) arguments.insert(QString(argv[i])); StartupOption startupOption = StartupOption::showPlots; QString testflag("-t"); - if (arguments.contains(testflag)) { + if (arguments.contains(testflag)) + { startupOption = StartupOption::runTests; arguments.remove(testflag); } QString openFolderFlag("-f"); - if (arguments.contains(openFolderFlag)) { + if (arguments.contains(openFolderFlag)) + { arguments.remove(openFolderFlag); QStringList nameFilter("*.tdb"); QSet paths = arguments; arguments.clear(); - for (QString path : paths) { + for (QString path : paths) + { QDir directory(path); QStringList files = directory.entryList(nameFilter); - for (QString &file : files) { + for (QString& file : files) + { arguments.insert(path.append("/") + file); } } @@ -96,12 +101,11 @@ int main(int argc, char *argv[]) TraceAnalyzer analyzer(arguments, startupOption); analyzer.show(); return a.exec(); - } else { + } + else + { TraceAnalyzer analyzer; analyzer.show(); return a.exec(); } - } - - diff --git a/extensions/apps/traceAnalyzer/markerplotitem.h b/extensions/apps/traceAnalyzer/markerplotitem.h index d59b75a7..85d01288 100644 --- a/extensions/apps/traceAnalyzer/markerplotitem.h +++ b/extensions/apps/traceAnalyzer/markerplotitem.h @@ -52,12 +52,17 @@ private: QColor color; public: - MarkerPlotItem(traceTime time, int width = 4, - QColor color = QColor(Qt::black)): time(time), width(width), color(color) {} + MarkerPlotItem(traceTime time, int width = 4, QColor color = QColor(Qt::black)) : + time(time), + width(width), + color(color) + { + } virtual int rtti() const; - virtual void draw(QPainter *painter, const QwtScaleMap &xMap, - const QwtScaleMap &yMap, const QRectF &canvasRect) const; - + virtual void draw(QPainter* painter, + const QwtScaleMap& xMap, + const QwtScaleMap& yMap, + const QRectF& canvasRect) const; }; #endif // MARKERPLOTITEM_H diff --git a/extensions/apps/traceAnalyzer/presentation/debugmessagetreewidget.cpp b/extensions/apps/traceAnalyzer/presentation/debugmessagetreewidget.cpp index b52fd4b0..9495cbd4 100644 --- a/extensions/apps/traceAnalyzer/presentation/debugmessagetreewidget.cpp +++ b/extensions/apps/traceAnalyzer/presentation/debugmessagetreewidget.cpp @@ -39,18 +39,16 @@ #include #include -using namespace std; +using namespace std; -void DebugMessageTreeWidget::init(TraceNavigator *navigator, - TracePlot *traceplot) +void DebugMessageTreeWidget::init(TraceNavigator* navigator, TracePlot* traceplot) { Q_ASSERT(isInitialized == false); isInitialized = true; arrangeUiSettings(); - connect(navigator, SIGNAL(currentTraceTimeChanged()), this, - SLOT(currentTraceTimeChanged())); - connect(navigator, SIGNAL(selectedTransactionsChanged()), this, - SLOT(selectedTransactionChanged())); + connect(navigator, SIGNAL(currentTraceTimeChanged()), this, SLOT(currentTraceTimeChanged())); + connect( + navigator, SIGNAL(selectedTransactionsChanged()), this, SLOT(selectedTransactionChanged())); this->traceplot = traceplot; this->navigator = navigator; currentTraceTimeChanged(); @@ -67,35 +65,42 @@ void DebugMessageTreeWidget::arrangeUiSettings() void DebugMessageTreeWidget::selectedTransactionChanged() { - if (navigator->hasSelectedTransactions()) { + if (navigator->hasSelectedTransactions()) + { Timespan span = navigator->getSpanCoveredBySelectedTransaction(); showDebugMessages(navigator->TraceFile().getDebugMessagesInTimespan(span)); - } else { - showDebugMessages(navigator->TraceFile().getDebugMessagesInTimespan( - traceplot->GetCurrentTimespan())); + } + else + { + showDebugMessages( + navigator->TraceFile().getDebugMessagesInTimespan(traceplot->GetCurrentTimespan())); } } - void DebugMessageTreeWidget::currentTraceTimeChanged() { if (!navigator->hasSelectedTransactions()) - showDebugMessages(navigator->TraceFile().getDebugMessagesInTimespan( - traceplot->GetCurrentTimespan())); + showDebugMessages( + navigator->TraceFile().getDebugMessagesInTimespan(traceplot->GetCurrentTimespan())); } -void DebugMessageTreeWidget::showDebugMessages(const vector &comments) +void DebugMessageTreeWidget::showDebugMessages(const vector& comments) { clear(); if (comments.empty()) return; traceTime currentTime = -1; - for (const auto &comment : comments) { - if (currentTime != comment.time) { - addTopLevelItem(new QTreeWidgetItem({prettyFormatTime(comment.time), formatDebugMessage(comment.text)})); + for (const auto& comment : comments) + { + if (currentTime != comment.time) + { + addTopLevelItem(new QTreeWidgetItem( + {prettyFormatTime(comment.time), formatDebugMessage(comment.text)})); currentTime = comment.time; - } else { + } + else + { addTopLevelItem(new QTreeWidgetItem({"", formatDebugMessage(comment.text)})); } } @@ -104,7 +109,7 @@ void DebugMessageTreeWidget::showDebugMessages(const vectorscrollToTop(); } -QString DebugMessageTreeWidget::formatDebugMessage(const QString &message) +QString DebugMessageTreeWidget::formatDebugMessage(const QString& message) { QString formattedMessage = message; formattedMessage.replace(hexAdressMatcher, ""); @@ -113,12 +118,11 @@ QString DebugMessageTreeWidget::formatDebugMessage(const QString &message) return formattedMessage; } -void DebugMessageTreeWidget::mousePressEvent(QMouseEvent *event) +void DebugMessageTreeWidget::mousePressEvent(QMouseEvent* event) { - QTreeWidgetItem *itemUnderCursor = itemAt(event->pos()); - if (itemUnderCursor != NULL) { + QTreeWidgetItem* itemUnderCursor = itemAt(event->pos()); + if (itemUnderCursor != NULL) + { QToolTip::showText(this->mapToGlobal(event->pos()), itemUnderCursor->text(1)); } } - - diff --git a/extensions/apps/traceAnalyzer/presentation/debugmessagetreewidget.h b/extensions/apps/traceAnalyzer/presentation/debugmessagetreewidget.h index 4b918019..500c301d 100644 --- a/extensions/apps/traceAnalyzer/presentation/debugmessagetreewidget.h +++ b/extensions/apps/traceAnalyzer/presentation/debugmessagetreewidget.h @@ -37,26 +37,30 @@ #ifndef DEBUGMESSAGELISTWIDGET_H #define DEBUGMESSAGELISTWIDGET_H -#include -#include -#include -#include -#include #include "businessObjects/commentmodel.h" #include "tracenavigator.h" #include "traceplot.h" +#include +#include +#include +#include +#include class DebugMessageTreeWidget : public QTreeWidget { Q_OBJECT public: - DebugMessageTreeWidget(QWidget *parent = 0) : QTreeWidget(parent), - isInitialized(false), timeAnnotationMatcher(QString("@[0-9]+ n?s")), - hexAdressMatcher(QString("0x[0-9,a-f]+")) {} - void init(TraceNavigator *navigator, TracePlot *traceplot); + DebugMessageTreeWidget(QWidget* parent = 0) : + QTreeWidget(parent), + isInitialized(false), + timeAnnotationMatcher(QString("@[0-9]+ n?s")), + hexAdressMatcher(QString("0x[0-9,a-f]+")) + { + } + void init(TraceNavigator* navigator, TracePlot* traceplot); - void showDebugMessages(const std::vector &comments); + void showDebugMessages(const std::vector& comments); void arrangeUiSettings(); public Q_SLOTS: @@ -65,12 +69,12 @@ public Q_SLOTS: private: bool isInitialized; - TracePlot *traceplot; - TraceNavigator *navigator; + TracePlot* traceplot; + TraceNavigator* navigator; QRegularExpression timeAnnotationMatcher; QRegularExpression hexAdressMatcher; - QString formatDebugMessage(const QString &message); - void mousePressEvent(QMouseEvent *event); + QString formatDebugMessage(const QString& message); + void mousePressEvent(QMouseEvent* event); }; #endif // DEBUGMESSAGELISTWIDGET_H diff --git a/extensions/apps/traceAnalyzer/presentation/selectedtransactiontreewidget.cpp b/extensions/apps/traceAnalyzer/presentation/selectedtransactiontreewidget.cpp index 94b06c1f..d1e53edd 100644 --- a/extensions/apps/traceAnalyzer/presentation/selectedtransactiontreewidget.cpp +++ b/extensions/apps/traceAnalyzer/presentation/selectedtransactiontreewidget.cpp @@ -37,12 +37,11 @@ #include "selectedtransactiontreewidget.h" - - void SelectedTransactionTreeWidget::selectedTransactionsChanged() { this->clear(); - for (const auto &transaction : navigator->SelectedTransactions()) { + for (const auto& transaction : navigator->SelectedTransactions()) + { AppendTransaction(transaction); } expandAll(); @@ -65,9 +64,11 @@ void SelectedTransactionTreeWidget::selectedTransactionsChanged() resizeColumnToContents(0); } -void SelectedTransactionTreeWidget::init(TraceNavigator *navigator) +void SelectedTransactionTreeWidget::init(TraceNavigator* navigator) { TransactionTreeWidget::init(navigator); - QObject::connect(navigator, SIGNAL(selectedTransactionsChanged()), this, + QObject::connect(navigator, + SIGNAL(selectedTransactionsChanged()), + this, SLOT(selectedTransactionsChanged())); } diff --git a/extensions/apps/traceAnalyzer/presentation/selectedtransactiontreewidget.h b/extensions/apps/traceAnalyzer/presentation/selectedtransactiontreewidget.h index d8cfb1ad..4970ef11 100644 --- a/extensions/apps/traceAnalyzer/presentation/selectedtransactiontreewidget.h +++ b/extensions/apps/traceAnalyzer/presentation/selectedtransactiontreewidget.h @@ -44,14 +44,17 @@ class SelectedTransactionTreeWidget : public TransactionTreeWidget Q_OBJECT bool isInitialized; + public: - SelectedTransactionTreeWidget(QWidget *parent = 0) : TransactionTreeWidget( - parent), isInitialized(false) {} - virtual void init(TraceNavigator *navigator); + SelectedTransactionTreeWidget(QWidget* parent = 0) : + TransactionTreeWidget(parent), + isInitialized(false) + { + } + virtual void init(TraceNavigator* navigator); public Q_SLOTS: void selectedTransactionsChanged(); - }; #endif // SELECTEDTRANSACTIONTREEWIDGET_H diff --git a/extensions/apps/traceAnalyzer/presentation/tracePlotMouseLabel.cpp b/extensions/apps/traceAnalyzer/presentation/tracePlotMouseLabel.cpp index 11665fd1..1ca51c70 100644 --- a/extensions/apps/traceAnalyzer/presentation/tracePlotMouseLabel.cpp +++ b/extensions/apps/traceAnalyzer/presentation/tracePlotMouseLabel.cpp @@ -44,18 +44,23 @@ void TracePlotMouseLabel::setMode(MouseLabelMode mode) this->mode = mode; } -QwtText TracePlotMouseLabel::trackerText(const QPoint &point) const +QwtText TracePlotMouseLabel::trackerText(const QPoint& point) const { - if (mode == MouseLabelMode::AbsoluteTime) { - traceTime mouseTime = static_cast(traceplot->invTransform( - traceplot->xBottom, point.x())); - return QwtText(prettyFormatTime(alignToClk(mouseTime, - clkPeriod)) + "(" + formatInClks(mouseTime, clkPeriod) + ")"); - } else if (mode == MouseLabelMode::Timedifference) { + if (mode == MouseLabelMode::AbsoluteTime) + { + traceTime mouseTime = + static_cast(traceplot->invTransform(traceplot->xBottom, point.x())); + return QwtText(prettyFormatTime(alignToClk(mouseTime, clkPeriod)) + "(" + + formatInClks(mouseTime, clkPeriod) + ")"); + } + else if (mode == MouseLabelMode::Timedifference) + { traceTime mouseTime = timeDifferenceSpan.timeCovered(); - return QwtText(prettyFormatTime(alignToClk(mouseTime, - clkPeriod)) + "(" + formatInClks(mouseTime, clkPeriod) + ")"); - } else { + return QwtText(prettyFormatTime(alignToClk(mouseTime, clkPeriod)) + "(" + + formatInClks(mouseTime, clkPeriod) + ")"); + } + else + { Q_ASSERT(false); } return QwtText(QString("")); diff --git a/extensions/apps/traceAnalyzer/presentation/tracePlotMouseLabel.h b/extensions/apps/traceAnalyzer/presentation/tracePlotMouseLabel.h index 22b3d770..46ce45ad 100644 --- a/extensions/apps/traceAnalyzer/presentation/tracePlotMouseLabel.h +++ b/extensions/apps/traceAnalyzer/presentation/tracePlotMouseLabel.h @@ -38,30 +38,43 @@ #ifndef TRACEPLOTPICKER_H #define TRACEPLOTPICKER_H -#include #include "traceplot.h" +#include -enum class MouseLabelMode {AbsoluteTime, Timedifference}; +enum class MouseLabelMode +{ + AbsoluteTime, + Timedifference +}; class TracePlotMouseLabel : public QwtPlotPicker { public: - TracePlotMouseLabel(TracePlot *traceplot, unsigned int clkPeriod, - Timespan &timeDifferenceSpan): - QwtPlotPicker(QwtPlot::xBottom, QwtPlot::yLeft, QwtPlotPicker::VLineRubberBand, - QwtPicker::AlwaysOn, traceplot->canvas()), - mode(MouseLabelMode::AbsoluteTime), traceplot(traceplot), clkPeriod(clkPeriod), - timeDifferenceSpan(timeDifferenceSpan) {} + TracePlotMouseLabel(TracePlot* traceplot, + unsigned int clkPeriod, + Timespan& timeDifferenceSpan) : + QwtPlotPicker(QwtPlot::xBottom, + QwtPlot::yLeft, + QwtPlotPicker::VLineRubberBand, + QwtPicker::AlwaysOn, + traceplot->canvas()), + mode(MouseLabelMode::AbsoluteTime), + traceplot(traceplot), + clkPeriod(clkPeriod), + timeDifferenceSpan(timeDifferenceSpan) + { + } void setMode(MouseLabelMode mode); + protected: - virtual QwtText trackerText(const QPoint &point) const; + virtual QwtText trackerText(const QPoint& point) const; private: MouseLabelMode mode; - TracePlot *traceplot; + TracePlot* traceplot; unsigned int clkPeriod; - Timespan &timeDifferenceSpan; + Timespan& timeDifferenceSpan; }; #endif // TRACEPLOTPICKER_H diff --git a/extensions/apps/traceAnalyzer/presentation/tracedrawing.cpp b/extensions/apps/traceAnalyzer/presentation/tracedrawing.cpp index 7f0b42d5..12ec49c2 100644 --- a/extensions/apps/traceAnalyzer/presentation/tracedrawing.cpp +++ b/extensions/apps/traceAnalyzer/presentation/tracedrawing.cpp @@ -37,7 +37,7 @@ #include "tracedrawing.h" -void drawVerticalLine(QPainter *painter, int xPos, const QRectF &canvasRect) +void drawVerticalLine(QPainter* painter, int xPos, const QRectF& canvasRect) { /* P1 (xPos,lowerCanvasYBorder) * | @@ -47,14 +47,12 @@ void drawVerticalLine(QPainter *painter, int xPos, const QRectF &canvasRect) * P2 (xPos,upperCanvasYBorder) */ - - QPoint P1(xPos, static_cast(canvasRect.top())); QPoint P2(xPos, static_cast(canvasRect.bottom())); painter->drawLine(QLine(P1, P2)); } -void drawDoubleArrow(QPainter *painter, int xFrom, int xTo, int y) +void drawDoubleArrow(QPainter* painter, int xFrom, int xTo, int y) { /* P1 P3 @@ -78,57 +76,53 @@ void drawDoubleArrow(QPainter *painter, int xFrom, int xTo, int y) painter->drawLine(P2, from); painter->drawLine(P3, to); painter->drawLine(P4, to); - - - } -void drawDoubleArrow(QPainter *painter, int xFrom, int xTo, int y, - const QString &text, const QColor &textColor) +void drawDoubleArrow( + QPainter* painter, int xFrom, int xTo, int y, const QString& text, const QColor& textColor) { drawDoubleArrow(painter, xFrom, xTo, y); - drawText(painter, text, QPoint((xTo + xFrom) / 2, y), - TextPositioning::topCenter, textColor); + drawText(painter, text, QPoint((xTo + xFrom) / 2, y), TextPositioning::topCenter, textColor); } -void drawHexagon(QPainter *painter, const QPoint &from, const QPoint &to, - double height) +void drawHexagon(QPainter* painter, const QPoint& from, const QPoint& to, double height) { -// {text} -// P1------------------------P2 -// From / \ To -// \ / -// P4-------------------------P3 + // {text} + // P1------------------------P2 + // From / \ To + // \ / + // P4-------------------------P3 int offset = 10; - if ( (to.x() - from.x()) <= 20) { + if ((to.x() - from.x()) <= 20) + { offset = 5; } - if ( (to.x() - from.x()) <= 10) { + if ((to.x() - from.x()) <= 10) + { offset = 2; } - if ( (to.x() - from.x()) <= 4) { + if ((to.x() - from.x()) <= 4) + { offset = 0; } - QPointF P1(from.x() + offset , from.y() - height / 2); - QPointF P2(to.x() - offset , to.y() - height / 2); - QPointF P3(to.x() - offset , to.y() + height / 2); - QPointF P4(from.x() + offset , from.y() + height / 2); + QPointF P1(from.x() + offset, from.y() - height / 2); + QPointF P2(to.x() - offset, to.y() - height / 2); + QPointF P3(to.x() - offset, to.y() + height / 2); + QPointF P4(from.x() + offset, from.y() + height / 2); QPolygonF polygon; - polygon << from - << P1 - << P2 - << to - << P3 - << P4; + polygon << from << P1 << P2 << to << P3 << P4; painter->drawPolygon(polygon); } -void drawText(QPainter *painter, const QString &text, const QPoint &position, - const TextPositioning &positioning, const QColor &textColor) +void drawText(QPainter* painter, + const QString& text, + const QPoint& position, + const TextPositioning& positioning, + const QColor& textColor) { //*--------------* //| | | @@ -143,7 +137,8 @@ void drawText(QPainter *painter, const QString &text, const QPoint &position, QRect rect(position - offset, position + offset); int flags; - switch (positioning) { + switch (positioning) + { case TextPositioning::topRight: flags = Qt::AlignRight | Qt::AlignTop; break; diff --git a/extensions/apps/traceAnalyzer/presentation/tracedrawing.h b/extensions/apps/traceAnalyzer/presentation/tracedrawing.h index c437183f..673346fa 100644 --- a/extensions/apps/traceAnalyzer/presentation/tracedrawing.h +++ b/extensions/apps/traceAnalyzer/presentation/tracedrawing.h @@ -38,21 +38,35 @@ #ifndef TRACEDRAWING_H #define TRACEDRAWING_H +#include #include #include -#include #include -enum class TextPositioning {topRight, topLeft, bottomRight, bottomLeft, topCenter, bottomCenter, centerCenter}; +enum class TextPositioning +{ + topRight, + topLeft, + bottomRight, + bottomLeft, + topCenter, + bottomCenter, + centerCenter +}; -void drawVerticalLine(QPainter *painter, int xPos, const QRectF &canvasRect); -void drawDoubleArrow(QPainter *painter, int xFrom, int xTo, int y); -void drawDoubleArrow(QPainter *painter, int xFrom, int xTo, int y, - const QString &text, const QColor &textColor = QColor(Qt::black)); -void drawHexagon(QPainter *painter, const QPoint &from, const QPoint &to, - double height); -void drawText(QPainter *painter, const QString &text, const QPoint &position, - const TextPositioning &positioning, - const QColor &textColor = QColor(Qt::black)); +void drawVerticalLine(QPainter* painter, int xPos, const QRectF& canvasRect); +void drawDoubleArrow(QPainter* painter, int xFrom, int xTo, int y); +void drawDoubleArrow(QPainter* painter, + int xFrom, + int xTo, + int y, + const QString& text, + const QColor& textColor = QColor(Qt::black)); +void drawHexagon(QPainter* painter, const QPoint& from, const QPoint& to, double height); +void drawText(QPainter* painter, + const QString& text, + const QPoint& position, + const TextPositioning& positioning, + const QColor& textColor = QColor(Qt::black)); #endif // TRACEDRAWING_H diff --git a/extensions/apps/traceAnalyzer/presentation/tracedrawingproperties.cpp b/extensions/apps/traceAnalyzer/presentation/tracedrawingproperties.cpp index 3cf2b32d..04588d82 100644 --- a/extensions/apps/traceAnalyzer/presentation/tracedrawingproperties.cpp +++ b/extensions/apps/traceAnalyzer/presentation/tracedrawingproperties.cpp @@ -38,14 +38,18 @@ #include "../businessObjects/traceplotlinemodel.h" #include "util/customlabelscaledraw.h" -TraceDrawingProperties::TraceDrawingProperties(bool drawText, bool drawBorder, DependencyOptions drawDependenciesOption, - ColorGrouping colorGrouping) - : drawText(drawText), drawBorder(drawBorder), drawDependenciesOption(drawDependenciesOption), - colorGrouping(colorGrouping) +TraceDrawingProperties::TraceDrawingProperties(bool drawText, + bool drawBorder, + DependencyOptions drawDependenciesOption, + ColorGrouping colorGrouping) : + drawText(drawText), + drawBorder(drawBorder), + drawDependenciesOption(drawDependenciesOption), + colorGrouping(colorGrouping) { } -void TraceDrawingProperties::init(TracePlotLineDataSource *tracePlotLineDataSource) +void TraceDrawingProperties::init(TracePlotLineDataSource* tracePlotLineDataSource) { this->tracePlotLineDataSource = tracePlotLineDataSource; @@ -63,7 +67,8 @@ void TraceDrawingProperties::updateLabels() auto selectedModel = tracePlotLineDataSource->getSelectedModel(); for (auto it = tracePlotLineDataSource->getTracePlotLines().rbegin(); - it != tracePlotLineDataSource->getTracePlotLines().rend(); ++it) + it != tracePlotLineDataSource->getTracePlotLines().rend(); + ++it) { auto line = *it; diff --git a/extensions/apps/traceAnalyzer/presentation/tracedrawingproperties.h b/extensions/apps/traceAnalyzer/presentation/tracedrawingproperties.h index a0b800f2..9af84122 100644 --- a/extensions/apps/traceAnalyzer/presentation/tracedrawingproperties.h +++ b/extensions/apps/traceAnalyzer/presentation/tracedrawingproperties.h @@ -96,17 +96,19 @@ public: unsigned int banksPerGroup = 1; unsigned int per2BankOffset = 0; - TraceDrawingProperties(bool drawText = true, bool drawBorder = true, - DependencyOptions drawDependenciesOption = {DependencyOption::Disabled, - DependencyTextOption::Enabled}, + TraceDrawingProperties(bool drawText = true, + bool drawBorder = true, + DependencyOptions drawDependenciesOption = + {DependencyOption::Disabled, DependencyTextOption::Enabled}, ColorGrouping colorGrouping = ColorGrouping::PhaseType); - void init(TracePlotLineDataSource *tracePlotLineDataSource); + void init(TracePlotLineDataSource* tracePlotLineDataSource); void updateLabels(); unsigned int getNumberOfDisplayedLines() const; - const std::vector> &getTracePlotLines() const + const std::vector>& + getTracePlotLines() const { return tracePlotLineDataSource->getTracePlotLines(); } @@ -119,7 +121,7 @@ Q_SIGNALS: private: std::shared_ptr> labels = std::make_shared>(); - TracePlotLineDataSource *tracePlotLineDataSource; + TracePlotLineDataSource* tracePlotLineDataSource; }; #endif // TRACECOLLECTIONDRAWINGPROPERTIES_H diff --git a/extensions/apps/traceAnalyzer/presentation/tracemetrictreewidget.cpp b/extensions/apps/traceAnalyzer/presentation/tracemetrictreewidget.cpp index a72f49d9..9a72e9fa 100644 --- a/extensions/apps/traceAnalyzer/presentation/tracemetrictreewidget.cpp +++ b/extensions/apps/traceAnalyzer/presentation/tracemetrictreewidget.cpp @@ -38,32 +38,34 @@ #include "tracemetrictreewidget.h" -TraceMetricTreeWidget::TraceMetricTreeWidget(QWidget *parent) : QTreeWidget( - parent) +TraceMetricTreeWidget::TraceMetricTreeWidget(QWidget* parent) : QTreeWidget(parent) { setHeaderHidden(true); - } -void TraceMetricTreeWidget::addTraceMetricResults(const TraceCalculatedMetrics - &result) +void TraceMetricTreeWidget::addTraceMetricResults(const TraceCalculatedMetrics& result) { - QTreeWidgetItem *top = new QTreeWidgetItem({result.getTraceName()}); + QTreeWidgetItem* top = new QTreeWidgetItem({result.getTraceName()}); addTopLevelItem(top); - if (result.getCalculatedMetrics().empty()) { + if (result.getCalculatedMetrics().empty()) + { new QTreeWidgetItem(top, {QString("Number of threads: 1")}); - } else { - for (CalculatedMetric calculatedMetric : result.getCalculatedMetrics()) { - new QTreeWidgetItem(top, {calculatedMetric.name.c_str() + QString(": ") + QString::number(calculatedMetric.value, 'f')}); + } + else + { + for (CalculatedMetric calculatedMetric : result.getCalculatedMetrics()) + { + new QTreeWidgetItem(top, + {calculatedMetric.name.c_str() + QString(": ") + + QString::number(calculatedMetric.value, 'f')}); } } } -void TraceMetricTreeWidget::addTracePlotResults(QString traceName, - QString outputFiles) +void TraceMetricTreeWidget::addTracePlotResults(QString traceName, QString outputFiles) { - QTreeWidgetItem *top = new QTreeWidgetItem({traceName}); + QTreeWidgetItem* top = new QTreeWidgetItem({traceName}); addTopLevelItem(top); new QTreeWidgetItem(top, {outputFiles}); diff --git a/extensions/apps/traceAnalyzer/presentation/tracemetrictreewidget.h b/extensions/apps/traceAnalyzer/presentation/tracemetrictreewidget.h index 10f3037d..4543a901 100644 --- a/extensions/apps/traceAnalyzer/presentation/tracemetrictreewidget.h +++ b/extensions/apps/traceAnalyzer/presentation/tracemetrictreewidget.h @@ -38,18 +38,16 @@ #ifndef TRACEMETRICTREEWIDGET_H #define TRACEMETRICTREEWIDGET_H -#include #include "businessObjects/tracecalculatedmetrics.h" - +#include class TraceMetricTreeWidget : public QTreeWidget { Q_OBJECT public: - explicit TraceMetricTreeWidget(QWidget *parent = nullptr); - void addTraceMetricResults(const TraceCalculatedMetrics &result); + explicit TraceMetricTreeWidget(QWidget* parent = nullptr); + void addTraceMetricResults(const TraceCalculatedMetrics& result); void addTracePlotResults(QString traceName, QString outputFiles); - }; #endif // TRACEMETRICTREEWIDGET_H diff --git a/extensions/apps/traceAnalyzer/presentation/tracenavigator.cpp b/extensions/apps/traceAnalyzer/presentation/tracenavigator.cpp index c80442bb..a4394de2 100644 --- a/extensions/apps/traceAnalyzer/presentation/tracenavigator.cpp +++ b/extensions/apps/traceAnalyzer/presentation/tracenavigator.cpp @@ -38,29 +38,35 @@ */ #include "tracenavigator.h" -#include "vector" #include "businessObjects/commentmodel.h" +#include "vector" #include #include using namespace std; -TraceNavigator::TraceNavigator(QString path, CommentModel *commentModel, QObject *parent) - : QObject(parent), traceFile(path, true), commentModel(commentModel), changesToCommitExist(false) +TraceNavigator::TraceNavigator(QString path, CommentModel* commentModel, QObject* parent) : + QObject(parent), + traceFile(path, true), + commentModel(commentModel), + changesToCommitExist(false) { getCommentsFromDB(); - QObject::connect(commentModel, &CommentModel::gotoCommentTriggered, this, [=](const QModelIndex &index){ - navigateToTime(commentModel->getTimeFromIndex(index)); - }); + QObject::connect(commentModel, + &CommentModel::gotoCommentTriggered, + this, + [=](const QModelIndex& index) + { navigateToTime(commentModel->getTimeFromIndex(index)); }); - QObject::connect(commentModel, &CommentModel::dataChanged, this, &TraceNavigator::traceFileModified); - QObject::connect(commentModel, &CommentModel::rowsRemoved, this, &TraceNavigator::traceFileModified); + QObject::connect( + commentModel, &CommentModel::dataChanged, this, &TraceNavigator::traceFileModified); + QObject::connect( + commentModel, &CommentModel::rowsRemoved, this, &TraceNavigator::traceFileModified); Transaction::setNumTransactions(GeneralTraceInfo().numberOfTransactions); } - /* Navigation * * @@ -72,7 +78,8 @@ void TraceNavigator::navigateToTime(traceTime time) time = 0; else if (time > traceFile.getGeneralInfo().span.End()) time = traceFile.getGeneralInfo().span.End(); - else { + else + { currentTraceTime = time; Q_EMIT currentTraceTimeChanged(); } @@ -95,7 +102,7 @@ void TraceNavigator::commitChangesToDB() void TraceNavigator::getCommentsFromDB() { - for (const auto &comment : traceFile.getComments()) + for (const auto& comment : traceFile.getComments()) commentModel->addComment(comment.time, comment.text); } @@ -111,17 +118,16 @@ void TraceNavigator::refreshData() * */ -void TraceNavigator::addSelectedTransactions(const - vector> &transactions) +void TraceNavigator::addSelectedTransactions(const vector>& transactions) { - for (const auto transaction : transactions) { + for (const auto transaction : transactions) + { selectedTransactions.push_back(transaction); } Q_EMIT selectedTransactionsChanged(); } -void TraceNavigator::addSelectedTransaction(const shared_ptr - &transaction) +void TraceNavigator::addSelectedTransaction(const shared_ptr& transaction) { selectedTransactions.push_back(transaction); Q_EMIT selectedTransactionsChanged(); @@ -141,17 +147,15 @@ void TraceNavigator::selectTransaction(ID id) navigateToTransaction(id); } -void TraceNavigator::selectTransaction(const shared_ptr - &transaction) +void TraceNavigator::selectTransaction(const shared_ptr& transaction) { selectTransaction(transaction->id); } void TraceNavigator::selectNextTransaction() { - if (selectedTransactions.empty() - || selectedTransactions.front()->id == - traceFile.getGeneralInfo().numberOfTransactions) + if (selectedTransactions.empty() || + selectedTransactions.front()->id == traceFile.getGeneralInfo().numberOfTransactions) selectFirstTransaction(); else selectTransaction(selectedTransactions.front()->id + 1); @@ -175,7 +179,6 @@ void TraceNavigator::selectLastTransaction() selectTransaction(traceFile.getGeneralInfo().numberOfTransactions); } - void TraceNavigator::selectNextRefresh(traceTime time) { shared_ptr nextRefresh; @@ -256,15 +259,15 @@ void TraceNavigator::selectNextCommand(traceTime time) // selectTransaction(n); // } -bool TraceNavigator::transactionIsSelected(const shared_ptr - &transaction) const +bool TraceNavigator::transactionIsSelected(const shared_ptr& transaction) const { return transactionIsSelected(transaction->id); } bool TraceNavigator::transactionIsSelected(ID id) const { - for (const auto &transaction : selectedTransactions) { + for (const auto& transaction : selectedTransactions) + { if (transaction->id == id) return true; } @@ -273,7 +276,8 @@ bool TraceNavigator::transactionIsSelected(ID id) const void TraceNavigator::clearSelectedTransactions() { - if (hasSelectedTransactions()) { + if (hasSelectedTransactions()) + { selectedTransactions.clear(); Q_EMIT selectedTransactionsChanged(); } @@ -292,7 +296,8 @@ Timespan TraceNavigator::getSpanCoveredBySelectedTransaction() traceTime begin = SelectedTransactions().at(0)->span.Begin(); traceTime end = SelectedTransactions().at(0)->span.End(); - for (const auto &transaction : selectedTransactions) { + for (const auto& transaction : selectedTransactions) + { if (transaction->span.End() > end) end = transaction->span.End(); } @@ -300,7 +305,7 @@ Timespan TraceNavigator::getSpanCoveredBySelectedTransaction() return Timespan(begin, end); } -const CommentModel *TraceNavigator::getCommentModel() const +const CommentModel* TraceNavigator::getCommentModel() const { return commentModel; } diff --git a/extensions/apps/traceAnalyzer/presentation/tracenavigator.h b/extensions/apps/traceAnalyzer/presentation/tracenavigator.h index 95b9ffb2..dddf3964 100644 --- a/extensions/apps/traceAnalyzer/presentation/tracenavigator.h +++ b/extensions/apps/traceAnalyzer/presentation/tracenavigator.h @@ -38,12 +38,12 @@ #ifndef TRACENAVIGATOR_H #define TRACENAVIGATOR_H -#include -#include -#include "data/tracedb.h" #include "businessObjects/generalinfo.h" #include "businessObjects/transaction.h" +#include "data/tracedb.h" #include "memory" +#include +#include class CommentModel; @@ -57,20 +57,11 @@ class TraceNavigator : public QObject Q_OBJECT public: - TraceNavigator(QString path, CommentModel *commentModel, QObject *parent = 0); + TraceNavigator(QString path, CommentModel* commentModel, QObject* parent = 0); - traceTime CurrentTraceTime() const - { - return currentTraceTime; - } - TraceDB &TraceFile() - { - return traceFile; - } - const GeneralInfo &GeneralTraceInfo() - { - return traceFile.getGeneralInfo(); - } + traceTime CurrentTraceTime() const { return currentTraceTime; } + TraceDB& TraceFile() { return traceFile; } + const GeneralInfo& GeneralTraceInfo() { return traceFile.getGeneralInfo(); } void navigateToTime(traceTime time); void navigateToTransaction(ID id); @@ -79,7 +70,7 @@ public: * (selecting a single transactions also navigates to that transaction) */ void selectTransaction(ID id); - void selectTransaction(const std::shared_ptr &transaction); + void selectTransaction(const std::shared_ptr& transaction); void selectNextTransaction(); void selectPreviousTransaction(); void selectLastTransaction(); @@ -88,30 +79,28 @@ public: void selectNextActivate(traceTime time); void selectNextPrecharge(traceTime time); void selectNextCommand(traceTime time); -// void selectNextActb(); -// void selectNextPreb(); -// void selectNextRefb(); + // void selectNextActb(); + // void selectNextPreb(); + // void selectNextRefb(); - void addSelectedTransactions(const std::vector> - &transactions); - const std::vector> &SelectedTransactions() + void addSelectedTransactions(const std::vector>& transactions); + const std::vector>& SelectedTransactions() { return selectedTransactions; } - void addSelectedTransaction(const std::shared_ptr &Transaction); + void addSelectedTransaction(const std::shared_ptr& Transaction); void addSelectedTransaction(ID id); void clearSelectedTransactions(); bool hasSelectedTransactions(); Timespan getSpanCoveredBySelectedTransaction(); bool transactionIsSelected(ID id) const; - bool transactionIsSelected(const std::shared_ptr &Transaction) - const; + bool transactionIsSelected(const std::shared_ptr& Transaction) const; void commitChangesToDB(); void refreshData(); - const CommentModel *getCommentModel() const; + const CommentModel* getCommentModel() const; bool existChangesToCommit() const; @@ -125,12 +114,12 @@ public Q_SLOTS: private: TraceDB traceFile; - //represents the current position in the tracefile - //components drawing the tracefile center around that time + // represents the current position in the tracefile + // components drawing the tracefile center around that time traceTime currentTraceTime = 0; std::vector> selectedTransactions; - CommentModel *commentModel; + CommentModel* commentModel; void getCommentsFromDB(); bool changesToCommitExist; diff --git a/extensions/apps/traceAnalyzer/presentation/traceplot.cpp b/extensions/apps/traceAnalyzer/presentation/traceplot.cpp index c2f0f9d9..bc70ca8b 100644 --- a/extensions/apps/traceAnalyzer/presentation/traceplot.cpp +++ b/extensions/apps/traceAnalyzer/presentation/traceplot.cpp @@ -62,16 +62,19 @@ #include #include -TracePlot::TracePlot(QWidget *parent): - QwtPlot(parent), isInitialized(false), +TracePlot::TracePlot(QWidget* parent) : + QwtPlot(parent), + isInitialized(false), customLabelScaleDraw(new CustomLabelScaleDraw(drawingProperties.getLabels())) { canvas()->setCursor(Qt::ArrowCursor); setUpActions(); } -void TracePlot::init(TraceNavigator *navigator, QScrollBar *scrollBar, TracePlotLineDataSource *tracePlotLineDataSource, - CommentModel *commentModel) +void TracePlot::init(TraceNavigator* navigator, + QScrollBar* scrollBar, + TracePlotLineDataSource* tracePlotLineDataSource, + CommentModel* commentModel) { Q_ASSERT(isInitialized == false); isInitialized = true; @@ -87,13 +90,19 @@ void TracePlot::init(TraceNavigator *navigator, QScrollBar *scrollBar, TracePlot QObject::connect(commentModel, &CommentModel::rowsRemoved, this, &TracePlot::commentsChanged); - QObject::connect(commentModel->selectionModel(), &QItemSelectionModel::selectionChanged, this, + QObject::connect(commentModel->selectionModel(), + &QItemSelectionModel::selectionChanged, + this, &TracePlot::commentsChanged); auto selectedTracePlotLineModel = tracePlotLineDataSource->getSelectedModel(); - QObject::connect(selectedTracePlotLineModel, &QAbstractItemModel::rowsInserted, this, + QObject::connect(selectedTracePlotLineModel, + &QAbstractItemModel::rowsInserted, + this, &TracePlot::recreateCollapseButtons); - QObject::connect(selectedTracePlotLineModel, &QAbstractItemModel::rowsRemoved, this, + QObject::connect(selectedTracePlotLineModel, + &QAbstractItemModel::rowsRemoved, + this, &TracePlot::recreateCollapseButtons); connectNavigatorQ_SIGNALS(); @@ -103,7 +112,8 @@ void TracePlot::init(TraceNavigator *navigator, QScrollBar *scrollBar, TracePlot setUpTracePlotItem(); setUpZoom(); setUpQueryEditor(); - mouseLabel = new TracePlotMouseLabel(this, navigator->GeneralTraceInfo().clkPeriod, this->mouseDownData.zoomSpan); + mouseLabel = new TracePlotMouseLabel( + this, navigator->GeneralTraceInfo().clkPeriod, this->mouseDownData.zoomSpan); getAndDrawComments(); setZoomLevel(1000); @@ -116,19 +126,16 @@ void TracePlot::init(TraceNavigator *navigator, QScrollBar *scrollBar, TracePlot void TracePlot::setUpActions() { insertComment = new QAction("Insert comment", this); - QObject::connect(insertComment, SIGNAL(triggered()), this, - SLOT(on_insertComment())); + QObject::connect(insertComment, SIGNAL(triggered()), this, SLOT(on_insertComment())); goToTime = new QAction("Go to time", this); QObject::connect(goToTime, SIGNAL(triggered()), this, SLOT(on_goToTime())); goToTransaction = new QAction("Go to transaction", this); - QObject::connect(goToTransaction, SIGNAL(triggered()), this, - SLOT(on_goToTransaction())); + QObject::connect(goToTransaction, SIGNAL(triggered()), this, SLOT(on_goToTransaction())); deselectAll = new QAction("Deselect all", this); - QObject::connect(deselectAll, SIGNAL(triggered()), this, - SLOT(on_deselectAll())); + QObject::connect(deselectAll, SIGNAL(triggered()), this, SLOT(on_deselectAll())); goToPhase = new QAction("Go to phase", this); QObject::connect(goToPhase, SIGNAL(triggered()), this, SLOT(on_goToPhase())); @@ -136,73 +143,74 @@ void TracePlot::setUpActions() showQueryEditor = new QAction("Execute query", this); showQueryEditor->setShortcut(QKeySequence("ctrl+e")); addAction(showQueryEditor); - QObject::connect(showQueryEditor, SIGNAL(triggered()), this, - SLOT(on_executeQuery())); + QObject::connect(showQueryEditor, SIGNAL(triggered()), this, SLOT(on_executeQuery())); selectNextRefresh = new QAction("Select next refresh", this); addAction(selectNextRefresh); - QObject::connect(selectNextRefresh, SIGNAL(triggered()), this, - SLOT(on_selectNextRefresh())); + QObject::connect(selectNextRefresh, SIGNAL(triggered()), this, SLOT(on_selectNextRefresh())); selectNextActivate = new QAction("Select next activate", this); addAction(selectNextActivate); - QObject::connect(selectNextActivate, SIGNAL(triggered()), this, - SLOT(on_selectNextActivate())); + QObject::connect(selectNextActivate, SIGNAL(triggered()), this, SLOT(on_selectNextActivate())); selectNextPrecharge = new QAction("Select next precharge", this); addAction(selectNextPrecharge); - QObject::connect(selectNextPrecharge, SIGNAL(triggered()), this, - SLOT(on_selectNextPrecharge())); + QObject::connect( + selectNextPrecharge, SIGNAL(triggered()), this, SLOT(on_selectNextPrecharge())); selectNextCommand = new QAction("Select next command", this); addAction(selectNextCommand); - QObject::connect(selectNextCommand, SIGNAL(triggered()), this, - SLOT(on_selectNextCommand())); + QObject::connect(selectNextCommand, SIGNAL(triggered()), this, SLOT(on_selectNextCommand())); -// selectNextActb = new QAction("Select next atcb", this); -// selectNextActb->setShortcut(QKeySequence("alt+b")); -// addAction(selectNextActb); -// QObject::connect(selectNextActb, SIGNAL(triggered()), this, -// SLOT(on_selectNextActb())); -// -// selectNextPreb = new QAction("Select next preb", this); -// selectNextPreb->setShortcut(QKeySequence("alt+q")); -// addAction(selectNextPreb); -// QObject::connect(selectNextPreb, SIGNAL(triggered()), this, -// SLOT(on_selectNextPreb())); -// -// selectNextRefb = new QAction("Select next refb", this); -// selectNextRefb->setShortcut(QKeySequence("alt+s")); -// addAction(selectNextRefb); -// QObject::connect(selectNextRefb, SIGNAL(triggered()), this, -// SLOT(on_selectNextRefb())); + // selectNextActb = new QAction("Select next atcb", this); + // selectNextActb->setShortcut(QKeySequence("alt+b")); + // addAction(selectNextActb); + // QObject::connect(selectNextActb, SIGNAL(triggered()), this, + // SLOT(on_selectNextActb())); + // + // selectNextPreb = new QAction("Select next preb", this); + // selectNextPreb->setShortcut(QKeySequence("alt+q")); + // addAction(selectNextPreb); + // QObject::connect(selectNextPreb, SIGNAL(triggered()), this, + // SLOT(on_selectNextPreb())); + // + // selectNextRefb = new QAction("Select next refb", this); + // selectNextRefb->setShortcut(QKeySequence("alt+s")); + // addAction(selectNextRefb); + // QObject::connect(selectNextRefb, SIGNAL(triggered()), this, + // SLOT(on_selectNextRefb())); setColorGroupingPhase = new QAction("Group by Phase", this); setColorGroupingPhase->setCheckable(true); setColorGroupingPhase->setChecked(true); addAction(setColorGroupingPhase); - QObject::connect(setColorGroupingPhase, SIGNAL(triggered()), this, - SLOT(on_colorGroupingPhase())); + QObject::connect( + setColorGroupingPhase, SIGNAL(triggered()), this, SLOT(on_colorGroupingPhase())); setColorGroupingTransaction = new QAction("Group by Transaction", this); setColorGroupingTransaction->setCheckable(true); addAction(setColorGroupingTransaction); - QObject::connect(setColorGroupingTransaction, SIGNAL(triggered()), this, + QObject::connect(setColorGroupingTransaction, + SIGNAL(triggered()), + this, SLOT(on_colorGroupingTransaction())); - setColorGroupingRainbowTransaction = new QAction("Group by Transaction - Rainbow Colored", this); + setColorGroupingRainbowTransaction = + new QAction("Group by Transaction - Rainbow Colored", this); setColorGroupingRainbowTransaction->setCheckable(true); addAction(setColorGroupingRainbowTransaction); - QObject::connect(setColorGroupingRainbowTransaction, SIGNAL(triggered()), this, + QObject::connect(setColorGroupingRainbowTransaction, + SIGNAL(triggered()), + this, SLOT(on_colorGroupingRainbowTransaction())); setColorGroupingThread = new QAction("Group by Thread", this); setColorGroupingThread->setCheckable(true); addAction(setColorGroupingThread); - QObject::connect(setColorGroupingThread, SIGNAL(triggered()), this, - SLOT(on_colorGroupingThread())); + QObject::connect( + setColorGroupingThread, SIGNAL(triggered()), this, SLOT(on_colorGroupingThread())); - QActionGroup *colorGroupingGroup = new QActionGroup(this); + QActionGroup* colorGroupingGroup = new QActionGroup(this); colorGroupingGroup->addAction(setColorGroupingPhase); colorGroupingGroup->addAction(setColorGroupingTransaction); colorGroupingGroup->addAction(setColorGroupingRainbowTransaction); @@ -210,13 +218,12 @@ void TracePlot::setUpActions() exportToPdf = new QAction("Export to SVG", this); addAction(exportToPdf); - QObject::connect(exportToPdf, SIGNAL(triggered()), this, - SLOT(on_exportToPDF())); + QObject::connect(exportToPdf, SIGNAL(triggered()), this, SLOT(on_exportToPDF())); toggleCollapsedState = new ToggleCollapsedAction(this); addAction(toggleCollapsedState); - QObject::connect(toggleCollapsedState, SIGNAL(triggered()), this, - SLOT(on_toggleCollapsedState())); + QObject::connect( + toggleCollapsedState, SIGNAL(triggered()), this, SLOT(on_toggleCollapsedState())); toggleCollapsedState->setShortcut(Qt::CTRL + Qt::Key_X); disabledDependencies = new QAction("Disabled", this); @@ -232,33 +239,50 @@ void TracePlot::setUpActions() switchDrawDependencyTextsOption->setChecked(true); disabledDependencies->setChecked(true); - QObject::connect(disabledDependencies, &QAction::triggered, this, [&]() { - drawingProperties.drawDependenciesOption.draw = DependencyOption::Disabled; - currentTraceTimeChanged(); - }); - QObject::connect(selectedDependencies, &QAction::triggered, this, [&]() { - drawingProperties.drawDependenciesOption.draw = DependencyOption::Selected; - currentTraceTimeChanged(); - }); - QObject::connect(allDependencies, &QAction::triggered, this, [&]() { - drawingProperties.drawDependenciesOption.draw = DependencyOption::All; - currentTraceTimeChanged(); - }); - QObject::connect(switchDrawDependencyTextsOption, &QAction::triggered, this, [&]() { - if (drawingProperties.drawDependenciesOption.text == DependencyTextOption::Disabled) + QObject::connect(disabledDependencies, + &QAction::triggered, + this, + [&]() + { + drawingProperties.drawDependenciesOption.draw = DependencyOption::Disabled; + currentTraceTimeChanged(); + }); + QObject::connect(selectedDependencies, + &QAction::triggered, + this, + [&]() + { + drawingProperties.drawDependenciesOption.draw = DependencyOption::Selected; + currentTraceTimeChanged(); + }); + QObject::connect(allDependencies, + &QAction::triggered, + this, + [&]() + { + drawingProperties.drawDependenciesOption.draw = DependencyOption::All; + currentTraceTimeChanged(); + }); + QObject::connect( + switchDrawDependencyTextsOption, + &QAction::triggered, + this, + [&]() { - drawingProperties.drawDependenciesOption.text = DependencyTextOption::Enabled; - switchDrawDependencyTextsOption->setChecked(true); - } - else - { - drawingProperties.drawDependenciesOption.text = DependencyTextOption::Disabled; - switchDrawDependencyTextsOption->setChecked(false); - } - currentTraceTimeChanged(); - }); + if (drawingProperties.drawDependenciesOption.text == DependencyTextOption::Disabled) + { + drawingProperties.drawDependenciesOption.text = DependencyTextOption::Enabled; + switchDrawDependencyTextsOption->setChecked(true); + } + else + { + drawingProperties.drawDependenciesOption.text = DependencyTextOption::Disabled; + switchDrawDependencyTextsOption->setChecked(false); + } + currentTraceTimeChanged(); + }); - QActionGroup *dependenciesGroup = new QActionGroup(this); + QActionGroup* dependenciesGroup = new QActionGroup(this); dependenciesGroup->addAction(disabledDependencies); dependenciesGroup->addAction(selectedDependencies); dependenciesGroup->addAction(allDependencies); @@ -271,22 +295,30 @@ void TracePlot::setUpContextMenu() contextMenu = new QMenu(this); contextMenu->addActions({deselectAll}); - QMenu *colorGroupingSubMenu = new QMenu("Group by", contextMenu); - colorGroupingSubMenu->addActions( - {setColorGroupingPhase, setColorGroupingTransaction, setColorGroupingRainbowTransaction, setColorGroupingThread}); + QMenu* colorGroupingSubMenu = new QMenu("Group by", contextMenu); + colorGroupingSubMenu->addActions({setColorGroupingPhase, + setColorGroupingTransaction, + setColorGroupingRainbowTransaction, + setColorGroupingThread}); contextMenu->addMenu(colorGroupingSubMenu); dependenciesSubMenu = new QMenu("Show dependencies", contextMenu); - dependenciesSubMenu->addActions( - {disabledDependencies, selectedDependencies, allDependencies, switchDrawDependencyTextsOption}); + dependenciesSubMenu->addActions({disabledDependencies, + selectedDependencies, + allDependencies, + switchDrawDependencyTextsOption}); contextMenu->addMenu(dependenciesSubMenu); - QMenu *goToSubMenu = new QMenu("Go to", contextMenu); + QMenu* goToSubMenu = new QMenu("Go to", contextMenu); goToSubMenu->addActions({goToPhase, goToTransaction, goToTime}); contextMenu->addMenu(goToSubMenu); - QMenu *selectSubMenu = new QMenu("Select", contextMenu); - selectSubMenu->addActions({selectNextRefresh, selectNextActivate, selectNextPrecharge, selectNextCommand /*, selectNextActb, selectNextPreb, selectNextRefb */}); + QMenu* selectSubMenu = new QMenu("Select", contextMenu); + selectSubMenu->addActions( + {selectNextRefresh, + selectNextActivate, + selectNextPrecharge, + selectNextCommand /*, selectNextActb, selectNextPreb, selectNextRefb */}); contextMenu->addMenu(selectSubMenu); contextMenu->addActions({showQueryEditor, insertComment, exportToPdf, toggleCollapsedState}); @@ -294,23 +326,31 @@ void TracePlot::setUpContextMenu() void TracePlot::connectNavigatorQ_SIGNALS() { - QObject::connect(navigator, SIGNAL(currentTraceTimeChanged()), this, - SLOT(currentTraceTimeChanged())); - QObject::connect(navigator, SIGNAL(selectedTransactionsChanged()), this, + QObject::connect( + navigator, SIGNAL(currentTraceTimeChanged()), this, SLOT(currentTraceTimeChanged())); + QObject::connect(navigator, + SIGNAL(selectedTransactionsChanged()), + this, SLOT(selectedTransactionsChanged())); } void TracePlot::setUpDrawingProperties() { - connect(this, &TracePlot::tracePlotLinesChanged, &drawingProperties, &TraceDrawingProperties::updateLabels); - connect(&drawingProperties, &TraceDrawingProperties::labelsUpdated, this, &TracePlot::updateScrollbar); + connect(this, + &TracePlot::tracePlotLinesChanged, + &drawingProperties, + &TraceDrawingProperties::updateLabels); + connect(&drawingProperties, + &TraceDrawingProperties::labelsUpdated, + this, + &TracePlot::updateScrollbar); drawingProperties.init(tracePlotLineDataSource); drawingProperties.textColor = palette().text().color(); drawingProperties.numberOfRanks = navigator->GeneralTraceInfo().numberOfRanks; drawingProperties.numberOfBankGroups = navigator->GeneralTraceInfo().numberOfBankGroups; - drawingProperties.numberOfBanks = navigator->GeneralTraceInfo().numberOfBanks; + drawingProperties.numberOfBanks = navigator->GeneralTraceInfo().numberOfBanks; drawingProperties.banksPerRank = navigator->GeneralTraceInfo().banksPerRank; drawingProperties.groupsPerRank = navigator->GeneralTraceInfo().groupsPerRank; drawingProperties.banksPerGroup = navigator->GeneralTraceInfo().banksPerGroup; @@ -321,8 +361,8 @@ void TracePlot::setUpQueryEditor() { queryEditor = new QueryEditor(this); queryEditor->setWindowFlags(Qt::Window); - queryEditor->setWindowTitle("Query " + QFileInfo( - navigator->TraceFile().getPathToDB()).baseName()); + queryEditor->setWindowTitle("Query " + + QFileInfo(navigator->TraceFile().getPathToDB()).baseName()); queryEditor->init(navigator); } @@ -336,7 +376,7 @@ void TracePlot::setUpTracePlotItem() void TracePlot::setUpGrid() { unsigned int clk = navigator->GeneralTraceInfo().clkPeriod; - QwtPlotGrid *grid = new ClkGrid(clk, GridVisiblityClks * clk); + QwtPlotGrid* grid = new ClkGrid(clk, GridVisiblityClks * clk); grid->setZ(0); grid->attach(this); } @@ -345,8 +385,7 @@ void TracePlot::setUpZoom() { minZoomLevel = minZoomClks * navigator->GeneralTraceInfo().clkPeriod; maxZoomLevel = maxZoomClks * navigator->GeneralTraceInfo().clkPeriod; - textVisibilityZoomLevel = textVisibilityClks * - navigator->GeneralTraceInfo().clkPeriod; + textVisibilityZoomLevel = textVisibilityClks * navigator->GeneralTraceInfo().clkPeriod; zoomZone = new QwtPlotZoneItem(); zoomZone->setZ(2); zoomZone->attach(this); @@ -435,7 +474,8 @@ ToggleCollapsedAction::CollapsedState TracePlot::getCollapsedState() const if (type != AbstractTracePlotLineModel::RankGroup) continue; - bool isCollapsed = selectedModel->data(index, AbstractTracePlotLineModel::CollapsedRole).toBool(); + bool isCollapsed = + selectedModel->data(index, AbstractTracePlotLineModel::CollapsedRole).toBool(); if (!isCollapsed) { notCollapsedCount++; @@ -486,12 +526,16 @@ void TracePlot::getAndDrawComments() for (int row = 0; row < commentModel->rowCount(); row++) { - QModelIndex timeIndex = commentModel->index(row, static_cast(CommentModel::Column::Time)); - QModelIndex textIndex = commentModel->index(row, static_cast(CommentModel::Column::Comment)); + QModelIndex timeIndex = + commentModel->index(row, static_cast(CommentModel::Column::Time)); + QModelIndex textIndex = + commentModel->index(row, static_cast(CommentModel::Column::Comment)); - bool selected = std::find(selectedRows.begin(), selectedRows.end(), commentModel->index(row, 0)) != selectedRows.end(); + bool selected = + std::find(selectedRows.begin(), selectedRows.end(), commentModel->index(row, 0)) != + selectedRows.end(); - QwtPlotMarker *marker = new QwtPlotMarker(); + QwtPlotMarker* marker = new QwtPlotMarker(); marker->setLabel(textIndex.data().toString()); marker->setLabelOrientation(Qt::Vertical); marker->setLabelAlignment(Qt::AlignLeft | Qt::AlignBottom); @@ -502,12 +546,12 @@ void TracePlot::getAndDrawComments() } } -CustomLabelScaleDraw *TracePlot::getCustomLabelScaleDraw() const +CustomLabelScaleDraw* TracePlot::getCustomLabelScaleDraw() const { return customLabelScaleDraw; } -const TraceDrawingProperties &TracePlot::getDrawingProperties() const +const TraceDrawingProperties& TracePlot::getDrawingProperties() const { return drawingProperties; } @@ -517,8 +561,7 @@ void TracePlot::enterZoomMode() mouseDownData.mouseIsDownForZooming = true; mouseLabel->setMode(MouseLabelMode::Timedifference); zoomZone->setVisible(true); - zoomZone->setInterval(mouseDownData.zoomSpan.Begin(), - mouseDownData.zoomSpan.End()); + zoomZone->setInterval(mouseDownData.zoomSpan.Begin(), mouseDownData.zoomSpan.End()); } void TracePlot::exitZoomMode() @@ -530,8 +573,7 @@ void TracePlot::exitZoomMode() void TracePlot::zoomIn(traceTime zoomCenter) { setZoomLevel(zoomLevel * zoomFactor); - traceTime time = zoomCenter + (GetCurrentTimespan().Middle() - zoomCenter) * - zoomFactor; + traceTime time = zoomCenter + (GetCurrentTimespan().Middle() - zoomCenter) * zoomFactor; Q_EMIT tracePlotZoomChanged(); navigator->navigateToTime(time); } @@ -540,8 +582,8 @@ void TracePlot::zoomOut(traceTime zoomCenter) { setZoomLevel(zoomLevel / zoomFactor); Q_EMIT tracePlotZoomChanged(); - navigator->navigateToTime(static_cast(zoomCenter + - (GetCurrentTimespan().Middle() - zoomCenter) / zoomFactor)); + navigator->navigateToTime(static_cast( + zoomCenter + (GetCurrentTimespan().Middle() - zoomCenter) / zoomFactor)); } traceTime TracePlot::ZoomLevel() const @@ -581,16 +623,18 @@ void TracePlot::recreateCollapseButtons() void TracePlot::currentTraceTimeChanged() { - bool drawDependencies = getDrawingProperties().drawDependenciesOption.draw != DependencyOption::Disabled; + bool drawDependencies = + getDrawingProperties().drawDependenciesOption.draw != DependencyOption::Disabled; - transactions = navigator->TraceFile().getTransactionsInTimespan(GetCurrentTimespan(), drawDependencies); + transactions = + navigator->TraceFile().getTransactionsInTimespan(GetCurrentTimespan(), drawDependencies); if (drawDependencies) { navigator->TraceFile().updateDependenciesInTimespan(GetCurrentTimespan()); } setAxisScale(xBottom, GetCurrentTimespan().Begin(), GetCurrentTimespan().End()); - + dependenciesSubMenu->setEnabled(navigator->TraceFile().checkDependencyTableExists()); replot(); @@ -684,10 +728,17 @@ void TracePlot::on_goToTransaction() { bool ok; int maxID = navigator->GeneralTraceInfo().numberOfTransactions; - int transactionID = QInputDialog::getInt(this, "Go to transaction", - "Enter transaction ID (1 - " + QString::number(maxID) + ")", 0, 1, maxID, 1, - &ok); - if (ok) { + int transactionID = + QInputDialog::getInt(this, + "Go to transaction", + "Enter transaction ID (1 - " + QString::number(maxID) + ")", + 0, + 1, + maxID, + 1, + &ok); + if (ok) + { navigator->clearSelectedTransactions(); navigator->selectTransaction(transactionID); } @@ -697,13 +748,19 @@ void TracePlot::on_goToPhase() { bool ok; int maxID = navigator->GeneralTraceInfo().numberOfPhases; - int phaseID = QInputDialog::getInt(this, "Go to phase", - "Enter phase ID (1 - " + QString::number(maxID) + ")", 0, 1, maxID, 1, &ok); + int phaseID = QInputDialog::getInt(this, + "Go to phase", + "Enter phase ID (1 - " + QString::number(maxID) + ")", + 0, + 1, + maxID, + 1, + &ok); - if (ok) { + if (ok) + { navigator->clearSelectedTransactions(); - navigator->selectTransaction(navigator->TraceFile().getTransactionIDFromPhaseID( - phaseID)); + navigator->selectTransaction(navigator->TraceFile().getTransactionIDFromPhaseID(phaseID)); } } @@ -723,7 +780,8 @@ void TracePlot::on_goToTime() double goToTime; GoToTimeDialog dialog(&goToTime, this); int dialogCode = dialog.exec(); - if (dialogCode == QDialog::Accepted) { + if (dialogCode == QDialog::Accepted) + { traceTime time = static_cast(goToTime) * 1000; navigator->navigateToTime(time); } @@ -732,13 +790,13 @@ void TracePlot::on_goToTime() void TracePlot::on_exportToPDF() { QwtPlotRenderer renderer; - QString filename = QFileDialog::getSaveFileName(this, "Export to SVG", "", - "Portable Document Format(*.svg)"); - if (filename != "") { + QString filename = + QFileDialog::getSaveFileName(this, "Export to SVG", "", "Portable Document Format(*.svg)"); + if (filename != "") + { QBrush saved = this->canvasBackground(); this->setCanvasBackground(QBrush(Qt::white)); - renderer.renderDocument(this, filename, "svg", QSizeF(this->widthMM(), - this->heightMM())); + renderer.renderDocument(this, filename, "svg", QSizeF(this->widthMM(), this->heightMM())); this->setCanvasBackground(QBrush(saved)); } } @@ -754,7 +812,7 @@ void TracePlot::on_toggleCollapsedState() * */ -void TracePlot::keyPressEvent(QKeyEvent *keyPressedEvent) +void TracePlot::keyPressEvent(QKeyEvent* keyPressedEvent) { int key = keyPressedEvent->key(); if (Qt::Key_Control == key) @@ -765,51 +823,64 @@ void TracePlot::keyPressEvent(QKeyEvent *keyPressedEvent) navigator->selectNextTransaction(); else if (Qt::Key_Left == key) navigator->selectPreviousTransaction(); - else if (Qt::Key_Minus == key) { + else if (Qt::Key_Minus == key) + { zoomOut(GetCurrentTimespan().Middle()); - } else if (Qt::Key_Plus == key) { + } + else if (Qt::Key_Plus == key) + { zoomIn(GetCurrentTimespan().Middle()); } } -void TracePlot::keyReleaseEvent(QKeyEvent *keyReleasedEvent) +void TracePlot::keyReleaseEvent(QKeyEvent* keyReleasedEvent) { int key = keyReleasedEvent->key(); if (Qt::Key_Control == key) keyPressData.ctrlPressed = false; - else if (Qt::Key_Shift == key) { + else if (Qt::Key_Shift == key) + { keyPressData.shiftPressed = false; exitZoomMode(); replot(); } } - -bool TracePlot::eventFilter(QObject *object, QEvent *event) +bool TracePlot::eventFilter(QObject* object, QEvent* event) { - if (object == canvas()) { - switch (event->type()) { - case QEvent::Wheel : { - QWheelEvent *wheelEvent = static_cast(event); - traceTime zoomCenter = static_cast(this->invTransform(xBottom, - wheelEvent->position().x())); + if (object == canvas()) + { + switch (event->type()) + { + case QEvent::Wheel: + { + QWheelEvent* wheelEvent = static_cast(event); + traceTime zoomCenter = + static_cast(this->invTransform(xBottom, wheelEvent->position().x())); (wheelEvent->angleDelta().y() > 0) ? zoomIn(zoomCenter) : zoomOut(zoomCenter); return true; } - case QEvent::MouseButtonPress: { - QMouseEvent *mouseEvent = static_cast(event); + case QEvent::MouseButtonPress: + { + QMouseEvent* mouseEvent = static_cast(event); - if (mouseEvent->button() == Qt::LeftButton) { - if (keyPressData.shiftPressed) { - mouseDownData.zoomSpan.setBegin(alignToClk(invTransform(xBottom, - mouseEvent->x()), navigator->GeneralTraceInfo().clkPeriod)); - mouseDownData.zoomSpan.setEnd(alignToClk(invTransform(xBottom, mouseEvent->x()), - navigator->GeneralTraceInfo().clkPeriod)); + if (mouseEvent->button() == Qt::LeftButton) + { + if (keyPressData.shiftPressed) + { + mouseDownData.zoomSpan.setBegin( + alignToClk(invTransform(xBottom, mouseEvent->x()), + navigator->GeneralTraceInfo().clkPeriod)); + mouseDownData.zoomSpan.setEnd( + alignToClk(invTransform(xBottom, mouseEvent->x()), + navigator->GeneralTraceInfo().clkPeriod)); enterZoomMode(); - } else { + } + else + { mouseDownData.mouseDownX = mouseEvent->x(); mouseDownData.mouseDownTime = GetCurrentTimespan().Middle(); mouseDownData.mouseIsDownForDragging = true; @@ -818,25 +889,31 @@ bool TracePlot::eventFilter(QObject *object, QEvent *event) SelectComment(mouseEvent->x()); } return true; - } else if (mouseEvent->button() == Qt::RightButton) { + } + else if (mouseEvent->button() == Qt::RightButton) + { // Also select comments to make it more obvious. SelectComment(mouseEvent->x()); - openContextMenu(this->canvas()->mapToGlobal(mouseEvent->pos()), - mouseEvent->pos()); + openContextMenu(this->canvas()->mapToGlobal(mouseEvent->pos()), mouseEvent->pos()); return true; } break; } - case QEvent::MouseButtonRelease: { - QMouseEvent *mouseEvent = static_cast(event); + case QEvent::MouseButtonRelease: + { + QMouseEvent* mouseEvent = static_cast(event); - if (mouseEvent->button() == Qt::LeftButton) { - if (mouseDownData.mouseIsDownForDragging) { + if (mouseEvent->button() == Qt::LeftButton) + { + if (mouseDownData.mouseIsDownForDragging) + { mouseDownData.mouseIsDownForDragging = false; canvas()->setCursor(Qt::ArrowCursor); return true; - } else if (mouseDownData.mouseIsDownForZooming) { + } + else if (mouseDownData.mouseIsDownForZooming) + { exitZoomMode(); traceTime newCenter = mouseDownData.zoomSpan.Middle(); setZoomLevel(mouseDownData.zoomSpan.timeCovered()); @@ -847,15 +924,19 @@ bool TracePlot::eventFilter(QObject *object, QEvent *event) } break; } - case QEvent::MouseMove: { - QMouseEvent *mouseEvent = static_cast(event); + case QEvent::MouseMove: + { + QMouseEvent* mouseEvent = static_cast(event); - if (mouseDownData.mouseIsDownForDragging) { - traceTime deltaTime = invTransform(xBottom, - mouseDownData.mouseDownX) - invTransform(xBottom, mouseEvent->x()); + if (mouseDownData.mouseIsDownForDragging) + { + traceTime deltaTime = invTransform(xBottom, mouseDownData.mouseDownX) - + invTransform(xBottom, mouseEvent->x()); navigator->navigateToTime(mouseDownData.mouseDownTime + deltaTime); return true; - } else if (mouseDownData.mouseIsDownForZooming) { + } + else if (mouseDownData.mouseIsDownForZooming) + { mouseDownData.zoomSpan.setEnd(alignToClk(invTransform(xBottom, mouseEvent->x()), navigator->GeneralTraceInfo().clkPeriod)); if (mouseDownData.zoomSpan.Begin() < mouseDownData.zoomSpan.End()) @@ -868,7 +949,6 @@ bool TracePlot::eventFilter(QObject *object, QEvent *event) replot(); } break; - } default: break; @@ -902,9 +982,11 @@ void TracePlot::SelectComment(int x) const return; if (keyPressData.ctrlPressed) - commentModel->selectionModel()->setCurrentIndex(index, QItemSelectionModel::Toggle | QItemSelectionModel::Rows); + commentModel->selectionModel()->setCurrentIndex( + index, QItemSelectionModel::Toggle | QItemSelectionModel::Rows); else - commentModel->selectionModel()->setCurrentIndex(index, QItemSelectionModel::ClearAndSelect | QItemSelectionModel::Rows); + commentModel->selectionModel()->setCurrentIndex( + index, QItemSelectionModel::ClearAndSelect | QItemSelectionModel::Rows); } Timespan TracePlot::hoveredTimespan(int x) const @@ -915,7 +997,7 @@ Timespan TracePlot::hoveredTimespan(int x) const return Timespan(time - offset, time + offset); } -void TracePlot::openContextMenu(const QPoint &pos, const QPoint &mouseDown) +void TracePlot::openContextMenu(const QPoint& pos, const QPoint& mouseDown) { contextMenuMouseDown = mouseDown; Timespan timespan = hoveredTimespan(mouseDown.x()); diff --git a/extensions/apps/traceAnalyzer/presentation/traceplot.h b/extensions/apps/traceAnalyzer/presentation/traceplot.h index d9561667..597e11be 100644 --- a/extensions/apps/traceAnalyzer/presentation/traceplot.h +++ b/extensions/apps/traceAnalyzer/presentation/traceplot.h @@ -46,16 +46,16 @@ #include "traceplotitem.h" #include "util/togglecollapsedaction.h" -#include -#include +#include #include +#include +#include +#include +#include +#include +#include #include #include -#include -#include -#include -#include -#include class TracePlotMouseLabel; class CustomLabelScaleDraw; @@ -72,16 +72,18 @@ class TracePlot : public QwtPlot Q_OBJECT public: - TracePlot(QWidget *parent = NULL); - void init(TraceNavigator *navigator, QScrollBar *scrollBar, TracePlotLineDataSource *tracePlotLineDataSource, - CommentModel *commentModel); + TracePlot(QWidget* parent = NULL); + void init(TraceNavigator* navigator, + QScrollBar* scrollBar, + TracePlotLineDataSource* tracePlotLineDataSource, + CommentModel* commentModel); Timespan GetCurrentTimespan(); traceTime ZoomLevel() const; void setZoomLevel(traceTime newZoomLevel); - CustomLabelScaleDraw *getCustomLabelScaleDraw() const; - const TraceDrawingProperties &getDrawingProperties() const; + CustomLabelScaleDraw* getCustomLabelScaleDraw() const; + const TraceDrawingProperties& getDrawingProperties() const; public Q_SLOTS: void currentTraceTimeChanged(); @@ -103,9 +105,9 @@ private Q_SLOTS: void on_selectNextActivate(); void on_selectNextPrecharge(); void on_selectNextCommand(); -// void on_selectNextActb(); -// void on_selectNextPreb(); -// void on_selectNextRefb(); + // void on_selectNextActb(); + // void on_selectNextPreb(); + // void on_selectNextRefb(); void on_colorGroupingPhase(); void on_colorGroupingTransaction(); void on_colorGroupingThread(); @@ -120,19 +122,19 @@ private Q_SLOTS: private: bool isInitialized; - TraceNavigator *navigator; + TraceNavigator* navigator; TraceDrawingProperties drawingProperties; - TracePlotItem *tracePlotItem; - QwtPlotZoneItem *zoomZone; + TracePlotItem* tracePlotItem; + QwtPlotZoneItem* zoomZone; std::vector> transactions; - QueryEditor *queryEditor; - QMenu *contextMenu; - QScrollBar *scrollBar; - CustomLabelScaleDraw *customLabelScaleDraw; + QueryEditor* queryEditor; + QMenu* contextMenu; + QScrollBar* scrollBar; + CustomLabelScaleDraw* customLabelScaleDraw; - CommentModel *commentModel; + CommentModel* commentModel; - TracePlotLineDataSource *tracePlotLineDataSource; + TracePlotLineDataSource* tracePlotLineDataSource; void setUpTracePlotItem(); void setUpDrawingProperties(); @@ -165,67 +167,72 @@ private: void exitZoomMode(); void enterZoomMode(); - /* keyboard an mouse events * */ - bool eventFilter( QObject *object, QEvent *event ); + bool eventFilter(QObject* object, QEvent* event); - QAction *goToTime; - QAction *goToTransaction; - QAction *goToPhase; - QAction *showQueryEditor; - QAction *insertComment; - QAction *deselectAll; - QAction *selectNextRefresh; - QAction *selectNextActivate; - QAction *selectNextPrecharge; - QAction *selectNextCommand; -// QAction *selectNextActb; -// QAction *selectNextPreb; -// QAction *selectNextRefb; - QAction *setColorGroupingPhase; - QAction *setColorGroupingTransaction; - QAction *setColorGroupingThread; - QAction *setColorGroupingRainbowTransaction; - QAction *exportToPdf; - ToggleCollapsedAction *toggleCollapsedState; + QAction* goToTime; + QAction* goToTransaction; + QAction* goToPhase; + QAction* showQueryEditor; + QAction* insertComment; + QAction* deselectAll; + QAction* selectNextRefresh; + QAction* selectNextActivate; + QAction* selectNextPrecharge; + QAction* selectNextCommand; + // QAction *selectNextActb; + // QAction *selectNextPreb; + // QAction *selectNextRefb; + QAction* setColorGroupingPhase; + QAction* setColorGroupingTransaction; + QAction* setColorGroupingThread; + QAction* setColorGroupingRainbowTransaction; + QAction* exportToPdf; + ToggleCollapsedAction* toggleCollapsedState; - QMenu *dependenciesSubMenu; - QAction *disabledDependencies; - QAction *selectedDependencies; - QAction *allDependencies; - QAction *switchDrawDependencyTextsOption; + QMenu* dependenciesSubMenu; + QAction* disabledDependencies; + QAction* selectedDependencies; + QAction* allDependencies; + QAction* switchDrawDependencyTextsOption; - TracePlotMouseLabel *mouseLabel; + TracePlotMouseLabel* mouseLabel; - void openContextMenu(const QPoint &pos, const QPoint &mouseDown); + void openContextMenu(const QPoint& pos, const QPoint& mouseDown); QPoint contextMenuMouseDown; void SelectTransaction(int x, int y) const; void SelectComment(int x) const; - //const std::vector> hoveredComments(traceTime time) const; + // const std::vector> hoveredComments(traceTime time) const; Timespan hoveredTimespan(int x) const; - void keyPressEvent(QKeyEvent *keyPressedEvent); - void keyReleaseEvent(QKeyEvent *keyReleasedEvent); + void keyPressEvent(QKeyEvent* keyPressedEvent); + void keyReleaseEvent(QKeyEvent* keyReleasedEvent); - struct KeyPressData { + struct KeyPressData + { bool ctrlPressed, shiftPressed; - KeyPressData(): ctrlPressed(false), shiftPressed(false) {} + KeyPressData() : ctrlPressed(false), shiftPressed(false) {} }; - struct MouseDownData { + struct MouseDownData + { traceTime mouseDownTime; Timespan zoomSpan; int mouseDownX; bool mouseIsDownForDragging; bool mouseIsDownForZooming; - MouseDownData(): mouseDownTime(0), mouseDownX(0), mouseIsDownForDragging(false), - mouseIsDownForZooming(false) {} + MouseDownData() : + mouseDownTime(0), + mouseDownX(0), + mouseIsDownForDragging(false), + mouseIsDownForZooming(false) + { + } }; MouseDownData mouseDownData; KeyPressData keyPressData; }; - #endif // TRACEPLOT_H diff --git a/extensions/apps/traceAnalyzer/presentation/traceplotitem.cpp b/extensions/apps/traceAnalyzer/presentation/traceplotitem.cpp index ee6512cb..dca69ff4 100644 --- a/extensions/apps/traceAnalyzer/presentation/traceplotitem.cpp +++ b/extensions/apps/traceAnalyzer/presentation/traceplotitem.cpp @@ -38,11 +38,11 @@ #include "traceplotitem.h" #include "tracedrawing.h" #include "util/colorgenerator.h" -#include #include +#include +#include #include #include -#include using namespace std; int TracePlotItem::rtti() const @@ -50,21 +50,24 @@ int TracePlotItem::rtti() const return QwtPlotItem::Rtti_PlotUserItem; } -void TracePlotItem::draw(QPainter *painter, const QwtScaleMap &xMap, - const QwtScaleMap &yMap, const QRectF &canvasRect) const +void TracePlotItem::draw(QPainter* painter, + const QwtScaleMap& xMap, + const QwtScaleMap& yMap, + const QRectF& canvasRect) const { - for (const auto &transaction : transactions) { + for (const auto& transaction : transactions) + { bool highlight = navigator.transactionIsSelected(transaction); - transaction->draw(painter, xMap, yMap, canvasRect, highlight, - drawingProperties); + transaction->draw(painter, xMap, yMap, canvasRect, highlight, drawingProperties); } } -vector> TracePlotItem::getSelectedTransactions(Timespan timespan, double yVal) +vector> TracePlotItem::getSelectedTransactions(Timespan timespan, + double yVal) { vector> result; - for (const auto &transaction : transactions) + for (const auto& transaction : transactions) { if (transaction->isSelected(timespan, yVal, drawingProperties)) result.push_back(transaction); diff --git a/extensions/apps/traceAnalyzer/presentation/traceplotitem.h b/extensions/apps/traceAnalyzer/presentation/traceplotitem.h index fe723def..72ff2067 100644 --- a/extensions/apps/traceAnalyzer/presentation/traceplotitem.h +++ b/extensions/apps/traceAnalyzer/presentation/traceplotitem.h @@ -38,35 +38,40 @@ #ifndef TRACEPLOTITEM_H #define TRACEPLOTITEM_H -#include -#include -#include -#include #include "businessObjects/tracetime.h" #include "businessObjects/transaction.h" #include "presentation/tracedrawingproperties.h" -#include "util/colorgenerator.h" #include "presentation/tracenavigator.h" +#include "util/colorgenerator.h" +#include +#include +#include +#include class TracePlotItem : public QwtPlotItem { private: - const std::vector> &transactions; - const TraceNavigator &navigator; - const TraceDrawingProperties &drawingProperties; + const std::vector>& transactions; + const TraceNavigator& navigator; + const TraceDrawingProperties& drawingProperties; public: - TracePlotItem(const std::vector> &transactions, - const TraceNavigator &navigator, - const TraceDrawingProperties &drawingProperties): - transactions(transactions), navigator(navigator), - drawingProperties(drawingProperties) {} + TracePlotItem(const std::vector>& transactions, + const TraceNavigator& navigator, + const TraceDrawingProperties& drawingProperties) : + transactions(transactions), + navigator(navigator), + drawingProperties(drawingProperties) + { + } virtual int rtti() const; - virtual void draw(QPainter *painter, const QwtScaleMap &xMap, - const QwtScaleMap &yMap, const QRectF &canvasRect) const; - std::vector> getSelectedTransactions(Timespan timespan, double yVal); + virtual void draw(QPainter* painter, + const QwtScaleMap& xMap, + const QwtScaleMap& yMap, + const QRectF& canvasRect) const; + std::vector> getSelectedTransactions(Timespan timespan, + double yVal); }; #endif // TRACEPLOTITEM_H - diff --git a/extensions/apps/traceAnalyzer/presentation/tracescroller.cpp b/extensions/apps/traceAnalyzer/presentation/tracescroller.cpp index 4b6a2db1..5bed584e 100644 --- a/extensions/apps/traceAnalyzer/presentation/tracescroller.cpp +++ b/extensions/apps/traceAnalyzer/presentation/tracescroller.cpp @@ -44,10 +44,13 @@ #include #include -TraceScroller::TraceScroller(QWidget *parent) - : QwtPlot(parent), isInitialized(false), - drawingProperties(false, false, {DependencyOption::Disabled, DependencyTextOption::Disabled}, - ColorGrouping::PhaseType) +TraceScroller::TraceScroller(QWidget* parent) : + QwtPlot(parent), + isInitialized(false), + drawingProperties(false, + false, + {DependencyOption::Disabled, DependencyTextOption::Disabled}, + ColorGrouping::PhaseType) { setAxisScaleDraw(xBottom, new EngineeringScaleDraw); canvas()->setCursor(Qt::ArrowCursor); @@ -56,29 +59,35 @@ TraceScroller::TraceScroller(QWidget *parent) canvasClip->attach(this); } -void TraceScroller::init(TraceNavigator *navigator, TracePlot *tracePlot, - TracePlotLineDataSource *tracePlotLineDataSource) +void TraceScroller::init(TraceNavigator* navigator, + TracePlot* tracePlot, + TracePlotLineDataSource* tracePlotLineDataSource) { Q_ASSERT(isInitialized == false); isInitialized = true; this->tracePlotLineDataSource = tracePlotLineDataSource; - this -> navigator = navigator; + this->navigator = navigator; connectNavigatorQ_SIGNALS(); - const CommentModel *commentModel = navigator->getCommentModel(); + const CommentModel* commentModel = navigator->getCommentModel(); - QObject::connect(commentModel, &CommentModel::dataChanged, - this, &TraceScroller::commentsChanged); + QObject::connect( + commentModel, &CommentModel::dataChanged, this, &TraceScroller::commentsChanged); - QObject::connect(commentModel, &CommentModel::rowsRemoved, - this, &TraceScroller::commentsChanged); + QObject::connect( + commentModel, &CommentModel::rowsRemoved, this, &TraceScroller::commentsChanged); - QObject::connect(commentModel->selectionModel(), &QItemSelectionModel::selectionChanged, - this, &TraceScroller::commentsChanged); + QObject::connect(commentModel->selectionModel(), + &QItemSelectionModel::selectionChanged, + this, + &TraceScroller::commentsChanged); - QObject::connect(tracePlotLineDataSource, &TracePlotLineDataSource::modelChanged, this, &TraceScroller::updateAxis); + QObject::connect(tracePlotLineDataSource, + &TracePlotLineDataSource::modelChanged, + this, + &TraceScroller::updateAxis); setUpDrawingProperties(); setUpAxis(); @@ -89,21 +98,20 @@ void TraceScroller::init(TraceNavigator *navigator, TracePlot *tracePlot, getAndDrawComments(); this->tracePlot = tracePlot; - QObject::connect(tracePlot, SIGNAL(tracePlotZoomChanged()), this, - SLOT(tracePlotZoomChanged())); + QObject::connect(tracePlot, SIGNAL(tracePlotZoomChanged()), this, SLOT(tracePlotZoomChanged())); tracePlotZoomChanged(); - QObject::connect(tracePlot, SIGNAL(colorGroupingChanged(ColorGrouping)), this, + QObject::connect(tracePlot, + SIGNAL(colorGroupingChanged(ColorGrouping)), + this, SLOT(colorGroupingChanged(ColorGrouping))); QObject::connect(tracePlot, SIGNAL(tracePlotLinesChanged()), this, SLOT(updateAxis())); } - void TraceScroller::setUpTracePlotItem() { - TracePlotItem *tracePlotItem = new TracePlotItem(transactions, *navigator, - drawingProperties); + TracePlotItem* tracePlotItem = new TracePlotItem(transactions, *navigator, drawingProperties); tracePlotItem->setZ(1); tracePlotItem->attach(this); } @@ -115,18 +123,20 @@ void TraceScroller::setUpDrawingProperties() drawingProperties.textColor = palette().text().color(); drawingProperties.numberOfRanks = navigator->GeneralTraceInfo().numberOfRanks; drawingProperties.numberOfBankGroups = navigator->GeneralTraceInfo().numberOfBankGroups; - drawingProperties.numberOfBanks = navigator->GeneralTraceInfo().numberOfBanks; - drawingProperties.banksPerRank = drawingProperties.numberOfBanks / drawingProperties.numberOfRanks; - drawingProperties.groupsPerRank = drawingProperties.numberOfBankGroups / drawingProperties.numberOfRanks; - drawingProperties.banksPerGroup = drawingProperties.numberOfBanks / drawingProperties.numberOfBankGroups; + drawingProperties.numberOfBanks = navigator->GeneralTraceInfo().numberOfBanks; + drawingProperties.banksPerRank = + drawingProperties.numberOfBanks / drawingProperties.numberOfRanks; + drawingProperties.groupsPerRank = + drawingProperties.numberOfBankGroups / drawingProperties.numberOfRanks; + drawingProperties.banksPerGroup = + drawingProperties.numberOfBanks / drawingProperties.numberOfBankGroups; drawingProperties.per2BankOffset = navigator->GeneralTraceInfo().per2BankOffset; } - void TraceScroller::setUpAxis() { - axisScaleDraw(yLeft)->enableComponent(QwtAbstractScaleDraw::Labels, false ); - axisScaleDraw(yLeft)->enableComponent(QwtAbstractScaleDraw::Ticks, false ); + axisScaleDraw(yLeft)->enableComponent(QwtAbstractScaleDraw::Labels, false); + axisScaleDraw(yLeft)->enableComponent(QwtAbstractScaleDraw::Ticks, false); } void TraceScroller::updateAxis() @@ -137,23 +147,22 @@ void TraceScroller::updateAxis() void TraceScroller::connectNavigatorQ_SIGNALS() { - QObject::connect(navigator, SIGNAL(currentTraceTimeChanged()), this, - SLOT(currentTraceTimeChanged())); + QObject::connect( + navigator, SIGNAL(currentTraceTimeChanged()), this, SLOT(currentTraceTimeChanged())); - QObject::connect(navigator, SIGNAL(selectedTransactionsChanged()), this, + QObject::connect(navigator, + SIGNAL(selectedTransactionsChanged()), + this, SLOT(selectedTransactionsChanged())); } Timespan TraceScroller::GetCurrentTimespan() { - traceTime deltaOnTracePlot = navigator->GeneralTraceInfo().span.End() - - tracePlot->ZoomLevel(); - traceTime deltaOnTraceScroller = navigator->GeneralTraceInfo().span.End() - - zoomLevel; + traceTime deltaOnTracePlot = navigator->GeneralTraceInfo().span.End() - tracePlot->ZoomLevel(); + traceTime deltaOnTraceScroller = navigator->GeneralTraceInfo().span.End() - zoomLevel; - traceTime newBegin = static_cast - (tracePlot->GetCurrentTimespan().Begin() * (1.0 * deltaOnTraceScroller) / - deltaOnTracePlot); + traceTime newBegin = static_cast(tracePlot->GetCurrentTimespan().Begin() * + (1.0 * deltaOnTraceScroller) / deltaOnTracePlot); Timespan span(newBegin, newBegin + zoomLevel); if (span.Begin() < 0) @@ -163,19 +172,21 @@ Timespan TraceScroller::GetCurrentTimespan() return span; } - void TraceScroller::getAndDrawComments() { - const CommentModel *commentModel = navigator->getCommentModel(); + const CommentModel* commentModel = navigator->getCommentModel(); QList selectedRows = commentModel->selectionModel()->selectedRows(); for (int row = 0; row < commentModel->rowCount(); row++) { - QModelIndex timeIndex = commentModel->index(row, static_cast(CommentModel::Column::Time)); + QModelIndex timeIndex = + commentModel->index(row, static_cast(CommentModel::Column::Time)); - bool selected = std::find(selectedRows.begin(), selectedRows.end(), commentModel->index(row, 0)) != selectedRows.end(); + bool selected = + std::find(selectedRows.begin(), selectedRows.end(), commentModel->index(row, 0)) != + selectedRows.end(); - QwtPlotMarker *maker = new QwtPlotMarker(); + QwtPlotMarker* maker = new QwtPlotMarker(); maker->setXValue(static_cast(timeIndex.data(Qt::UserRole).toLongLong())); maker->setLineStyle(QwtPlotMarker::LineStyle::VLine); maker->setLinePen(QColor(selected ? Qt::red : Qt::blue), 2); @@ -201,7 +212,8 @@ void TraceScroller::colorGroupingChanged(ColorGrouping colorGrouping) void TraceScroller::currentTraceTimeChanged() { - bool drawDependencies = drawingProperties.drawDependenciesOption.draw != DependencyOption::Disabled; + bool drawDependencies = + drawingProperties.drawDependenciesOption.draw != DependencyOption::Disabled; Timespan spanOnTracePlot = tracePlot->GetCurrentTimespan(); canvasClip->setInterval(spanOnTracePlot.Begin(), spanOnTracePlot.End()); @@ -231,79 +243,99 @@ void TraceScroller::tracePlotZoomChanged() zoomLevel = navigator->GeneralTraceInfo().span.timeCovered(); } -bool TraceScroller::eventFilter( QObject *object, QEvent *event ) +bool TraceScroller::eventFilter(QObject* object, QEvent* event) { - if (object == canvas()) { + if (object == canvas()) + { static bool clipDragged = false; static bool leftMousePressed = false; static int mouseDownX = 0; static traceTime mouseDownTracePlotTime = 0; - switch (event->type()) { - case QEvent::Wheel : { - QWheelEvent *wheelEvent = static_cast(event); + switch (event->type()) + { + case QEvent::Wheel: + { + QWheelEvent* wheelEvent = static_cast(event); traceTime offset; int speed = 4; - (wheelEvent->angleDelta().y() > 0) ? offset = -zoomLevel * speed : offset = zoomLevel * - speed; + (wheelEvent->angleDelta().y() > 0) ? offset = -zoomLevel* speed + : offset = zoomLevel * speed; navigator->navigateToTime(navigator->CurrentTraceTime() + offset); return true; } - case QEvent::MouseButtonDblClick: { - QMouseEvent *mouseEvent = static_cast(event); + case QEvent::MouseButtonDblClick: + { + QMouseEvent* mouseEvent = static_cast(event); traceTime time = invTransform(xBottom, mouseEvent->x()); navigator->navigateToTime(time); return true; } - case QEvent::MouseButtonPress: { - QMouseEvent *mouseEvent = static_cast(event); + case QEvent::MouseButtonPress: + { + QMouseEvent* mouseEvent = static_cast(event); - if (mouseEvent->button() == Qt::LeftButton) { + if (mouseEvent->button() == Qt::LeftButton) + { canvas()->setCursor(Qt::ClosedHandCursor); leftMousePressed = true; mouseDownTracePlotTime = tracePlot->GetCurrentTimespan().Middle(); mouseDownX = mouseEvent->x(); - if (tracePlot->GetCurrentTimespan().contains(invTransform(xBottom, - mouseEvent->x()))) + if (tracePlot->GetCurrentTimespan().contains( + invTransform(xBottom, mouseEvent->x()))) clipDragged = true; else clipDragged = false; return true; - } else if (mouseEvent->button() == Qt::RightButton) { - navigator->navigateToTime(static_cast(invTransform(xBottom, - mouseEvent->x()))); + } + else if (mouseEvent->button() == Qt::RightButton) + { + navigator->navigateToTime( + static_cast(invTransform(xBottom, mouseEvent->x()))); return true; } } - case QEvent::MouseButtonRelease: { - QMouseEvent *mouseEvent = static_cast(event); - if (mouseEvent->button() == Qt::LeftButton) { + case QEvent::MouseButtonRelease: + { + QMouseEvent* mouseEvent = static_cast(event); + if (mouseEvent->button() == Qt::LeftButton) + { clipDragged = false; leftMousePressed = false; canvas()->setCursor(Qt::ArrowCursor); return true; } } - case QEvent::MouseMove: { - QMouseEvent *mouseEvent = static_cast(event); - if (leftMousePressed) { - if (clipDragged) { - double clipWidth = transform(xBottom, - tracePlot->ZoomLevel()) - transform(xBottom, 0); + case QEvent::MouseMove: + { + QMouseEvent* mouseEvent = static_cast(event); + if (leftMousePressed) + { + if (clipDragged) + { + double clipWidth = + transform(xBottom, tracePlot->ZoomLevel()) - transform(xBottom, 0); - if (mouseEvent->x() < clipWidth / 2) { + if (mouseEvent->x() < clipWidth / 2) + { navigator->navigateToTime(0); - } else if (mouseEvent->x() > canvas()->width() - clipWidth / 2) { + } + else if (mouseEvent->x() > canvas()->width() - clipWidth / 2) + { navigator->navigateToTime(navigator->GeneralTraceInfo().span.End()); - } else { - traceTime time = static_cast((mouseEvent->x() - clipWidth / 2) / - (canvas()->width() - clipWidth) * (navigator->GeneralTraceInfo().span.End() - - tracePlot->ZoomLevel())); + } + else + { + traceTime time = static_cast( + (mouseEvent->x() - clipWidth / 2) / (canvas()->width() - clipWidth) * + (navigator->GeneralTraceInfo().span.End() - tracePlot->ZoomLevel())); navigator->navigateToTime(time); } - } else { - traceTime deltaTime = invTransform(xBottom, mouseDownX) - invTransform(xBottom, - mouseEvent->x()); + } + else + { + traceTime deltaTime = + invTransform(xBottom, mouseDownX) - invTransform(xBottom, mouseEvent->x()); navigator->navigateToTime(mouseDownTracePlotTime + deltaTime); } return true; diff --git a/extensions/apps/traceAnalyzer/presentation/tracescroller.h b/extensions/apps/traceAnalyzer/presentation/tracescroller.h index 3fac8ec9..a738a520 100644 --- a/extensions/apps/traceAnalyzer/presentation/tracescroller.h +++ b/extensions/apps/traceAnalyzer/presentation/tracescroller.h @@ -40,11 +40,11 @@ #ifndef TRACESCROLLER_H #define TRACESCROLLER_H +#include "presentation/tracenavigator.h" +#include "traceplot.h" #include #include #include -#include "presentation/tracenavigator.h" -#include "traceplot.h" class TracePlotLineDataSource; @@ -54,9 +54,9 @@ class TraceScroller : public QwtPlot private: std::vector> transactions; bool isInitialized; - TraceNavigator *navigator; - TracePlot *tracePlot; - TracePlotLineDataSource *tracePlotLineDataSource; + TraceNavigator* navigator; + TracePlot* tracePlot; + TracePlotLineDataSource* tracePlotLineDataSource; constexpr static int tracePlotEnlargementFactor = 4; void setUpTracePlotItem(); void setUpDrawingProperties(); @@ -64,14 +64,16 @@ private: void connectNavigatorQ_SIGNALS(); void getAndDrawComments(); - QwtPlotZoneItem *canvasClip; + QwtPlotZoneItem* canvasClip; traceTime zoomLevel; - bool eventFilter( QObject *object, QEvent *event ); + bool eventFilter(QObject* object, QEvent* event); TraceDrawingProperties drawingProperties; public: - TraceScroller(QWidget *parent = NULL); - void init(TraceNavigator *navigator, TracePlot *tracePlot, TracePlotLineDataSource *tracePlotLineDataSource); + TraceScroller(QWidget* parent = NULL); + void init(TraceNavigator* navigator, + TracePlot* tracePlot, + TracePlotLineDataSource* tracePlotLineDataSource); Timespan GetCurrentTimespan(); public Q_SLOTS: @@ -83,7 +85,6 @@ public Q_SLOTS: private Q_SLOTS: void updateAxis(); - }; #endif // TraceScroller_H diff --git a/extensions/apps/traceAnalyzer/presentation/transactiontreewidget.cpp b/extensions/apps/traceAnalyzer/presentation/transactiontreewidget.cpp index 410fb8ce..6efc9394 100644 --- a/extensions/apps/traceAnalyzer/presentation/transactiontreewidget.cpp +++ b/extensions/apps/traceAnalyzer/presentation/transactiontreewidget.cpp @@ -43,14 +43,17 @@ using namespace std; -TransactionTreeWidget::TransactionTreeWidget(QWidget *parent) : QTreeWidget(parent), isInitialized(false) +TransactionTreeWidget::TransactionTreeWidget(QWidget* parent) : + QTreeWidget(parent), + isInitialized(false) { - QObject::connect(this, SIGNAL(customContextMenuRequested(QPoint)), this, SLOT(ContextMenuRequested(QPoint))); + QObject::connect( + this, SIGNAL(customContextMenuRequested(QPoint)), this, SLOT(ContextMenuRequested(QPoint))); setContextMenuPolicy(Qt::CustomContextMenu); goToTransaction = new QAction("Move to", this); } -void TransactionTreeWidget::init(TraceNavigator *_navigator) +void TransactionTreeWidget::init(TraceNavigator* _navigator) { Q_ASSERT(isInitialized == false); isInitialized = true; @@ -60,40 +63,43 @@ void TransactionTreeWidget::init(TraceNavigator *_navigator) setHeaderLabels(QStringList({"Transaction", "Value", "Value"})); } -void TransactionTreeWidget::AppendTransaction(const shared_ptr &transaction) +void TransactionTreeWidget::AppendTransaction(const shared_ptr& transaction) { - QTreeWidgetItem *node = new TransactionTreeItem(this, transaction, navigator->GeneralTraceInfo()); + QTreeWidgetItem* node = + new TransactionTreeItem(this, transaction, navigator->GeneralTraceInfo()); addTopLevelItem(node); } void TransactionTreeWidget::ContextMenuRequested(QPoint point) { if (selectedItems().count() > 0 && - selectedItems().at(0)->type() == TransactionTreeWidget::TransactionTreeItem::transactionTreeItemType) + selectedItems().at(0)->type() == + TransactionTreeWidget::TransactionTreeItem::transactionTreeItemType) { QMenu contextMenu; contextMenu.addActions({goToTransaction}); - QAction *selectedContextMenuItems = contextMenu.exec(mapToGlobal(point)); + QAction* selectedContextMenuItems = contextMenu.exec(mapToGlobal(point)); if (selectedContextMenuItems) { - TransactionTreeItem *item = dynamic_cast(selectedItems().at(0)); + TransactionTreeItem* item = dynamic_cast(selectedItems().at(0)); navigator->selectTransaction(item->Id()); } } } -TransactionTreeWidget::TransactionTreeItem::TransactionTreeItem(QTreeWidget *parent, - const shared_ptr &transaction, - const GeneralInfo &generalInfo) - : QTreeWidgetItem(parent, transactionTreeItemType) +TransactionTreeWidget::TransactionTreeItem::TransactionTreeItem( + QTreeWidget* parent, + const shared_ptr& transaction, + const GeneralInfo& generalInfo) : + QTreeWidgetItem(parent, transactionTreeItemType) { this->setText(0, QString::number(transaction->id)); this->id = transaction->id; bool isControllerTransaction = (transaction->thread == generalInfo.controllerThread); - auto *time = new QTreeWidgetItem({"Timespan"}); + auto* time = new QTreeWidgetItem({"Timespan"}); AppendTimespan(time, transaction->span); this->addChild(time); if (!isControllerTransaction) @@ -103,33 +109,37 @@ TransactionTreeWidget::TransactionTreeItem::TransactionTreeItem(QTreeWidget *par else // if (transaction->command == "W") this->addChild(new QTreeWidgetItem({"Command", "Write"})); } - this->addChild(new QTreeWidgetItem({"Length", prettyFormatTime(transaction->span.timeCovered())})); + this->addChild( + new QTreeWidgetItem({"Length", prettyFormatTime(transaction->span.timeCovered())})); if (!isControllerTransaction) - this->addChild(new QTreeWidgetItem({"Address", QString("0x") + QString::number(transaction->address, 16)})); + this->addChild(new QTreeWidgetItem( + {"Address", QString("0x") + QString::number(transaction->address, 16)})); if (!isControllerTransaction) - this->addChild(new QTreeWidgetItem({"Data Length", QString::number(transaction->dataLength)})); + this->addChild( + new QTreeWidgetItem({"Data Length", QString::number(transaction->dataLength)})); this->addChild(new QTreeWidgetItem({"Channel", QString::number(transaction->channel)})); if (!isControllerTransaction) this->addChild(new QTreeWidgetItem({"Thread", QString::number(transaction->thread)})); - auto *phasesNode = new QTreeWidgetItem(this); + auto* phasesNode = new QTreeWidgetItem(this); phasesNode->setText(0, "Phases"); phasesNode->addChild(new QTreeWidgetItem({"", "Begin", "End"})); - for (const std::shared_ptr &phase : transaction->Phases()) + for (const std::shared_ptr& phase : transaction->Phases()) AppendPhase(phasesNode, *phase); } -void TransactionTreeWidget::TransactionTreeItem::AppendPhase(QTreeWidgetItem *parent, const Phase &phase) +void TransactionTreeWidget::TransactionTreeItem::AppendPhase(QTreeWidgetItem* parent, + const Phase& phase) { - auto *node = new QTreeWidgetItem(parent); + auto* node = new QTreeWidgetItem(parent); node->setText(0, phase.Name() + QString(" [") + QString::number(phase.Id()) + QString("]")); AppendTimespan(node, phase.Span()); auto addMapping = [node](std::string_view label, unsigned value) { - auto *mappingNode = new QTreeWidgetItem(node); + auto* mappingNode = new QTreeWidgetItem(node); mappingNode->setText(0, label.data()); mappingNode->setText(1, QString::number(value)); }; @@ -155,7 +165,8 @@ void TransactionTreeWidget::TransactionTreeItem::AppendPhase(QTreeWidgetItem *pa } } -void TransactionTreeWidget::TransactionTreeItem::AppendTimespan(QTreeWidgetItem *parent, const Timespan ×pan) +void TransactionTreeWidget::TransactionTreeItem::AppendTimespan(QTreeWidgetItem* parent, + const Timespan& timespan) { parent->setText(1, prettyFormatTime(timespan.Begin())); parent->setText(2, prettyFormatTime(timespan.End())); diff --git a/extensions/apps/traceAnalyzer/presentation/transactiontreewidget.h b/extensions/apps/traceAnalyzer/presentation/transactiontreewidget.h index 8a5a6c2d..3ba3b322 100644 --- a/extensions/apps/traceAnalyzer/presentation/transactiontreewidget.h +++ b/extensions/apps/traceAnalyzer/presentation/transactiontreewidget.h @@ -38,10 +38,10 @@ #ifndef TRANSACTIONTREEWIDGET_H #define TRANSACTIONTREEWIDGET_H -#include #include "tracenavigator.h" -#include #include +#include +#include class TransactionTreeWidget : public QTreeWidget { @@ -49,35 +49,34 @@ class TransactionTreeWidget : public QTreeWidget Q_OBJECT public: - explicit TransactionTreeWidget(QWidget *parent); + explicit TransactionTreeWidget(QWidget* parent); - void AppendTransaction(const std::shared_ptr &transaction); - virtual void init(TraceNavigator *_navigator); + void AppendTransaction(const std::shared_ptr& transaction); + virtual void init(TraceNavigator* _navigator); public Q_SLOTS: void ContextMenuRequested(QPoint point); protected: - TraceNavigator *navigator; + TraceNavigator* navigator; private: bool isInitialized; - QAction *goToTransaction; + QAction* goToTransaction; class TransactionTreeItem : public QTreeWidgetItem { public: static constexpr int transactionTreeItemType = 1001; - TransactionTreeItem(QTreeWidget *parent, - const std::shared_ptr &trans, const GeneralInfo &generalInfo); - ID Id() const - { - return id; - } + TransactionTreeItem(QTreeWidget* parent, + const std::shared_ptr& trans, + const GeneralInfo& generalInfo); + ID Id() const { return id; } + private: ID id; - static void AppendTimespan(QTreeWidgetItem *parent, const Timespan ×pan); - static void AppendPhase(QTreeWidgetItem *parent, const Phase &phase); + static void AppendTimespan(QTreeWidgetItem* parent, const Timespan& timespan); + static void AppendPhase(QTreeWidgetItem* parent, const Phase& phase); }; }; diff --git a/extensions/apps/traceAnalyzer/presentation/util/clkgrid.cpp b/extensions/apps/traceAnalyzer/presentation/util/clkgrid.cpp index 479d2d4d..2894ef33 100644 --- a/extensions/apps/traceAnalyzer/presentation/util/clkgrid.cpp +++ b/extensions/apps/traceAnalyzer/presentation/util/clkgrid.cpp @@ -36,32 +36,32 @@ */ #include "clkgrid.h" -#include -#include #include +#include +#include using namespace std; -void ClkGrid::updateScaleDiv(const QwtScaleDiv &xMap, const QwtScaleDiv &yMap) +void ClkGrid::updateScaleDiv(const QwtScaleDiv& xMap, const QwtScaleDiv& yMap) { QwtScaleDiv scaleDiv; - scaleDiv.setInterval( xMap.interval() ); + scaleDiv.setInterval(xMap.interval()); double min = xMap.interval().minValue(); double max = xMap.interval().maxValue(); - if ( min > max ) - qSwap( min, max ); + if (min > max) + qSwap(min, max); - if ((max - min) < maxVisibility) { - min = static_cast( min / clkPeriod ) * clkPeriod; - QList ticks; - for ( double tick = min; tick <= max; tick += clkPeriod ) + if ((max - min) < maxVisibility) + { + min = static_cast(min / clkPeriod) * clkPeriod; + QList ticks; + for (double tick = min; tick <= max; tick += clkPeriod) ticks += tick; - scaleDiv.setTicks( QwtScaleDiv::MajorTick, ticks ); - + scaleDiv.setTicks(QwtScaleDiv::MajorTick, ticks); } - QwtPlotGrid::updateScaleDiv( scaleDiv, yMap ); + QwtPlotGrid::updateScaleDiv(scaleDiv, yMap); } diff --git a/extensions/apps/traceAnalyzer/presentation/util/clkgrid.h b/extensions/apps/traceAnalyzer/presentation/util/clkgrid.h index 33bccad3..1ff1ea4c 100644 --- a/extensions/apps/traceAnalyzer/presentation/util/clkgrid.h +++ b/extensions/apps/traceAnalyzer/presentation/util/clkgrid.h @@ -38,15 +38,18 @@ #ifndef CLKGRID_H #define CLKGRID_H -#include #include "businessObjects/tracetime.h" +#include class ClkGrid : public QwtPlotGrid { public: - virtual void updateScaleDiv(const QwtScaleDiv &xMap, const QwtScaleDiv &yMap); - ClkGrid(unsigned int clkPeriod, traceTime maxVisibility) : clkPeriod(clkPeriod), - maxVisibility(maxVisibility) {} + virtual void updateScaleDiv(const QwtScaleDiv& xMap, const QwtScaleDiv& yMap); + ClkGrid(unsigned int clkPeriod, traceTime maxVisibility) : + clkPeriod(clkPeriod), + maxVisibility(maxVisibility) + { + } private: unsigned int clkPeriod; diff --git a/extensions/apps/traceAnalyzer/presentation/util/colorgenerator.cpp b/extensions/apps/traceAnalyzer/presentation/util/colorgenerator.cpp index acb87f59..8ad253b3 100644 --- a/extensions/apps/traceAnalyzer/presentation/util/colorgenerator.cpp +++ b/extensions/apps/traceAnalyzer/presentation/util/colorgenerator.cpp @@ -41,11 +41,12 @@ QColor ColorGenerator::getColor(unsigned int i, ColorName color) { - switch(color) { - case ColorName::Default: - return cDefault.getColor(i); - case ColorName::HSV15: - return cHSV15.getColor(i); + switch (color) + { + case ColorName::Default: + return cDefault.getColor(i); + case ColorName::HSV15: + return cHSV15.getColor(i); } return {0, 0, 0}; @@ -53,11 +54,12 @@ QColor ColorGenerator::getColor(unsigned int i, ColorName color) QColor ColorGenerator::getRainbowColored(unsigned int i, ColorName color) { - switch(color) { - case ColorName::Default: - return cDefault.getRainbowColored(i); - case ColorName::HSV15: - return cHSV15.getRainbowColored(i); + switch (color) + { + case ColorName::Default: + return cDefault.getRainbowColored(i); + case ColorName::HSV15: + return cHSV15.getRainbowColored(i); } return {0, 0, 0}; diff --git a/extensions/apps/traceAnalyzer/presentation/util/colorgenerator.h b/extensions/apps/traceAnalyzer/presentation/util/colorgenerator.h index 12b9d58f..43e76721 100644 --- a/extensions/apps/traceAnalyzer/presentation/util/colorgenerator.h +++ b/extensions/apps/traceAnalyzer/presentation/util/colorgenerator.h @@ -41,8 +41,8 @@ #include "colorobject.h" -#include #include +#include enum ColorName { @@ -63,5 +63,4 @@ public: static QColor getRainbowColored(unsigned int i, ColorName color = ColorName::Default); }; - #endif // RANDOMCOLORGENERATOR_H diff --git a/extensions/apps/traceAnalyzer/presentation/util/colorobject.cpp b/extensions/apps/traceAnalyzer/presentation/util/colorobject.cpp index 03ecf4c4..5528c782 100644 --- a/extensions/apps/traceAnalyzer/presentation/util/colorobject.cpp +++ b/extensions/apps/traceAnalyzer/presentation/util/colorobject.cpp @@ -38,7 +38,6 @@ #include "colorobject.h" - QColor ColorObject::getColor(unsigned int i) { i = i % numberOfColors; @@ -61,7 +60,7 @@ QColor ColorObject::getRainbowColored(unsigned int i) return result; } -ColorDefault::ColorDefault() +ColorDefault::ColorDefault() { numberOfColors = 16; diff --git a/extensions/apps/traceAnalyzer/presentation/util/colorobject.h b/extensions/apps/traceAnalyzer/presentation/util/colorobject.h index d488343f..3875f361 100644 --- a/extensions/apps/traceAnalyzer/presentation/util/colorobject.h +++ b/extensions/apps/traceAnalyzer/presentation/util/colorobject.h @@ -50,10 +50,9 @@ protected: std::vector b; // std::vector a; - ColorObject() {}; - -public: + ColorObject(){}; +public: virtual QColor getColor(unsigned int i); virtual QColor getRainbowColored(unsigned int i); }; diff --git a/extensions/apps/traceAnalyzer/presentation/util/customlabelscaledraw.cpp b/extensions/apps/traceAnalyzer/presentation/util/customlabelscaledraw.cpp index 6c9e1516..27557492 100644 --- a/extensions/apps/traceAnalyzer/presentation/util/customlabelscaledraw.cpp +++ b/extensions/apps/traceAnalyzer/presentation/util/customlabelscaledraw.cpp @@ -35,14 +35,18 @@ #include "customlabelscaledraw.h" -CustomLabelScaleDraw::CustomLabelScaleDraw(std::shared_ptr> labels) : labels(labels), QObject(nullptr) {} +CustomLabelScaleDraw::CustomLabelScaleDraw(std::shared_ptr> labels) : + labels(labels), + QObject(nullptr) +{ +} QwtText CustomLabelScaleDraw::label(double v) const { return QwtText((*labels)[static_cast(v)]); } -void CustomLabelScaleDraw::draw(QPainter *painter, const QPalette &palette) const +void CustomLabelScaleDraw::draw(QPainter* painter, const QPalette& palette) const { emit scaleRedraw(); QwtScaleDraw::draw(painter, palette); diff --git a/extensions/apps/traceAnalyzer/presentation/util/customlabelscaledraw.h b/extensions/apps/traceAnalyzer/presentation/util/customlabelscaledraw.h index 1cfa8871..cb0a7197 100644 --- a/extensions/apps/traceAnalyzer/presentation/util/customlabelscaledraw.h +++ b/extensions/apps/traceAnalyzer/presentation/util/customlabelscaledraw.h @@ -38,11 +38,11 @@ #ifndef CUSTOMLABELSCALEDRAW_H #define CUSTOMLABELSCALEDRAW_H -#include -#include -#include #include +#include #include +#include +#include class CustomLabelScaleDraw : public QObject, public QwtScaleDraw { @@ -57,7 +57,7 @@ public: virtual QwtText label(double v) const override; - void draw(QPainter *painter, const QPalette &palette) const override; + void draw(QPainter* painter, const QPalette& palette) const override; void clearCache(); Q_SIGNALS: diff --git a/extensions/apps/traceAnalyzer/presentation/util/engineeringScaleDraw.h b/extensions/apps/traceAnalyzer/presentation/util/engineeringScaleDraw.h index 74c12fe9..32844242 100644 --- a/extensions/apps/traceAnalyzer/presentation/util/engineeringScaleDraw.h +++ b/extensions/apps/traceAnalyzer/presentation/util/engineeringScaleDraw.h @@ -37,10 +37,10 @@ #ifndef ENGINEERINGSCALEDRAW_H #define ENGINEERINGSCALEDRAW_H +#include "businessObjects/tracetime.h" +#include #include #include -#include -#include "businessObjects/tracetime.h" class EngineeringScaleDraw : public QwtScaleDraw { diff --git a/extensions/apps/traceAnalyzer/presentation/util/testlight.cpp b/extensions/apps/traceAnalyzer/presentation/util/testlight.cpp index 85f9b38b..278d0f2f 100644 --- a/extensions/apps/traceAnalyzer/presentation/util/testlight.cpp +++ b/extensions/apps/traceAnalyzer/presentation/util/testlight.cpp @@ -38,7 +38,7 @@ #include "testlight.h" #include -TestLight::TestLight(QWidget *parent) : QWidget(parent) +TestLight::TestLight(QWidget* parent) : QWidget(parent) { setGray(); } @@ -61,10 +61,9 @@ void TestLight::setRed() update(); } -void TestLight::paintEvent(QPaintEvent * /*paintEvent*/) +void TestLight::paintEvent(QPaintEvent* /*paintEvent*/) { QPainter painter(this); painter.fillRect(this->rect(), lightColor); painter.drawRect(this->rect()); } - diff --git a/extensions/apps/traceAnalyzer/presentation/util/testlight.h b/extensions/apps/traceAnalyzer/presentation/util/testlight.h index c41049f9..81e86b04 100644 --- a/extensions/apps/traceAnalyzer/presentation/util/testlight.h +++ b/extensions/apps/traceAnalyzer/presentation/util/testlight.h @@ -37,21 +37,22 @@ #ifndef TESTLIGHT_H #define TESTLIGHT_H -#include #include #include +#include class TestLight : public QWidget { Q_OBJECT public: - TestLight(QWidget *parent = 0); + TestLight(QWidget* parent = 0); void setGreen(); void setRed(); void setGray(); + protected: - void paintEvent(QPaintEvent *paintEvent); + void paintEvent(QPaintEvent* paintEvent); private: QColor lightColor; diff --git a/extensions/apps/traceAnalyzer/presentation/util/togglecollapsedaction.cpp b/extensions/apps/traceAnalyzer/presentation/util/togglecollapsedaction.cpp index 2cc165f1..5e24be47 100644 --- a/extensions/apps/traceAnalyzer/presentation/util/togglecollapsedaction.cpp +++ b/extensions/apps/traceAnalyzer/presentation/util/togglecollapsedaction.cpp @@ -35,24 +35,26 @@ #include "togglecollapsedaction.h" -ToggleCollapsedAction::ToggleCollapsedAction(QObject *parent) : QAction(parent) +ToggleCollapsedAction::ToggleCollapsedAction(QObject* parent) : QAction(parent) { updateCollapsedState(currentCollapsedState); } -void ToggleCollapsedAction::updateCollapsedState(ToggleCollapsedAction::CollapsedState collapsedState) +void ToggleCollapsedAction::updateCollapsedState( + ToggleCollapsedAction::CollapsedState collapsedState) { - switch(collapsedState) { - case CollapsedState::Expanded: - case CollapsedState::Mixed: - actionText = "Collapse all ranks"; - collapseAction = CollapseAction::CollapseAllRanks; - break; + switch (collapsedState) + { + case CollapsedState::Expanded: + case CollapsedState::Mixed: + actionText = "Collapse all ranks"; + collapseAction = CollapseAction::CollapseAllRanks; + break; - case CollapsedState::Collapsed: - actionText = "Expand all ranks"; - collapseAction = CollapseAction::ExpandAllRanks; - break; + case CollapsedState::Collapsed: + actionText = "Expand all ranks"; + collapseAction = CollapseAction::ExpandAllRanks; + break; } this->setText(actionText); diff --git a/extensions/apps/traceAnalyzer/presentation/util/togglecollapsedaction.h b/extensions/apps/traceAnalyzer/presentation/util/togglecollapsedaction.h index 7fbf3455..4f358a9c 100644 --- a/extensions/apps/traceAnalyzer/presentation/util/togglecollapsedaction.h +++ b/extensions/apps/traceAnalyzer/presentation/util/togglecollapsedaction.h @@ -41,15 +41,17 @@ class ToggleCollapsedAction : public QAction { public: - explicit ToggleCollapsedAction(QObject *parent = nullptr); + explicit ToggleCollapsedAction(QObject* parent = nullptr); - enum class CollapsedState { + enum class CollapsedState + { Mixed, Collapsed, Expanded }; - enum class CollapseAction { + enum class CollapseAction + { ExpandAllRanks, CollapseAllRanks }; diff --git a/extensions/apps/traceAnalyzer/queryeditor.cpp b/extensions/apps/traceAnalyzer/queryeditor.cpp index 1759587f..948274f0 100644 --- a/extensions/apps/traceAnalyzer/queryeditor.cpp +++ b/extensions/apps/traceAnalyzer/queryeditor.cpp @@ -40,9 +40,7 @@ #include #include -QueryEditor::QueryEditor(QWidget *parent) : - QWidget(parent), - ui(new Ui::QueryEditor) +QueryEditor::QueryEditor(QWidget* parent) : QWidget(parent), ui(new Ui::QueryEditor) { ui->setupUi(this); ui->queryHead->setText(queryTexts.queryHead); @@ -63,8 +61,9 @@ void QueryEditor::on_executeQuery_clicked() { try { - std::vector> result = navigator->TraceFile().getTransactionsWithCustomQuery( - queryTexts.queryHead + " " + ui->queryEdit->toPlainText()); + std::vector> result = + navigator->TraceFile().getTransactionsWithCustomQuery(queryTexts.queryHead + " " + + ui->queryEdit->toPlainText()); ui->transactiontreeWidget->clear(); for (const auto& trans : result) { diff --git a/extensions/apps/traceAnalyzer/queryeditor.h b/extensions/apps/traceAnalyzer/queryeditor.h index 7c476d80..8c5e7ac3 100644 --- a/extensions/apps/traceAnalyzer/queryeditor.h +++ b/extensions/apps/traceAnalyzer/queryeditor.h @@ -38,11 +38,12 @@ #ifndef QUERYEDITOR_H #define QUERYEDITOR_H -#include #include "data/QueryTexts.h" #include "presentation/tracenavigator.h" +#include -namespace Ui { +namespace Ui +{ class QueryEditor; } @@ -51,16 +52,16 @@ class QueryEditor : public QWidget Q_OBJECT public: - explicit QueryEditor(QWidget *parent = 0); + explicit QueryEditor(QWidget* parent = 0); ~QueryEditor(); - void init(TraceNavigator *_navigator); + void init(TraceNavigator* _navigator); private Q_SLOTS: void on_executeQuery_clicked(); private: - Ui::QueryEditor *ui; - TraceNavigator *navigator; + Ui::QueryEditor* ui; + TraceNavigator* navigator; TransactionQueryTexts queryTexts; }; diff --git a/extensions/apps/traceAnalyzer/selectmetrics.cpp b/extensions/apps/traceAnalyzer/selectmetrics.cpp index 4b44c2ce..bfa2c943 100644 --- a/extensions/apps/traceAnalyzer/selectmetrics.cpp +++ b/extensions/apps/traceAnalyzer/selectmetrics.cpp @@ -36,11 +36,9 @@ #include "selectmetrics.h" #include "ui_selectmetrics.h" -#include +#include -SelectMetrics::SelectMetrics(QWidget *parent) : - QDialog(parent), - ui(new Ui::SelectMetrics) +SelectMetrics::SelectMetrics(QWidget* parent) : QDialog(parent), ui(new Ui::SelectMetrics) { ui->setupUi(this); @@ -54,32 +52,37 @@ SelectMetrics::SelectMetrics(QWidget *parent) : void SelectMetrics::on_okButton_clicked() { - if (isThereAnyMetricSelected()) { + if (isThereAnyMetricSelected()) + { close(); Q_EMIT getSelectedMetrics(); - } else { + } + else + { QMessageBox::warning(this, "Warning", "Please select at least one metric"); } } void SelectMetrics::on_clearAllButton_clicked() { - for (QCheckBox *checkBox : metrics) { + for (QCheckBox* checkBox : metrics) + { checkBox->setChecked(false); } - } void SelectMetrics::on_selectAllButton_clicked() { - for (QCheckBox *checkBox : metrics) { + for (QCheckBox* checkBox : metrics) + { checkBox->setChecked(true); } } bool SelectMetrics::isThereAnyMetricSelected() { - for (QCheckBox *checkBox : metrics) { + for (QCheckBox* checkBox : metrics) + { if (checkBox->isChecked()) return true; } @@ -88,21 +91,24 @@ bool SelectMetrics::isThereAnyMetricSelected() void SelectMetrics::setMetrics(std::vector metrics) { - if (this->metrics.size() != metrics.size()) { - for (QCheckBox *checkBox : this->metrics) { + if (this->metrics.size() != metrics.size()) + { + for (QCheckBox* checkBox : this->metrics) + { layout->removeWidget(checkBox); } this->metrics.clear(); - for (std::string metric : metrics) { - QCheckBox *checkBox = new QCheckBox(); - checkBox->setObjectName (QString::fromStdString(metric)); - checkBox->setCheckable (true); - checkBox->setChecked (true); + for (std::string metric : metrics) + { + QCheckBox* checkBox = new QCheckBox(); + checkBox->setObjectName(QString::fromStdString(metric)); + checkBox->setCheckable(true); + checkBox->setChecked(true); - checkBox->setGeometry (10, 25, 100, 17); - checkBox->setText (QString::fromStdString(metric)); + checkBox->setGeometry(10, 25, 100, 17); + checkBox->setText(QString::fromStdString(metric)); this->metrics.push_back(checkBox); layout->addWidget(checkBox, Qt::AlignLeft); } @@ -113,7 +119,3 @@ SelectMetrics::~SelectMetrics() { delete ui; } - - - - diff --git a/extensions/apps/traceAnalyzer/selectmetrics.h b/extensions/apps/traceAnalyzer/selectmetrics.h index 7f90d125..10b7ce34 100644 --- a/extensions/apps/traceAnalyzer/selectmetrics.h +++ b/extensions/apps/traceAnalyzer/selectmetrics.h @@ -37,13 +37,13 @@ #ifndef SELECTMETRICS_H #define SELECTMETRICS_H +#include #include #include -#include #include - -namespace Ui { +namespace Ui +{ class SelectMetrics; } @@ -52,14 +52,13 @@ class SelectMetrics : public QDialog Q_OBJECT public: - explicit SelectMetrics(QWidget *parent = 0); + explicit SelectMetrics(QWidget* parent = 0); ~SelectMetrics(); - std::vector metrics; + std::vector metrics; void setMetrics(std::vector metrics); - Q_SIGNALS: void getSelectedMetrics(); @@ -68,10 +67,9 @@ private Q_SLOTS: void on_selectAllButton_clicked(); void on_clearAllButton_clicked(); - private: - Ui::SelectMetrics *ui; - QVBoxLayout *layout; + Ui::SelectMetrics* ui; + QVBoxLayout* layout; bool isThereAnyMetricSelected(); }; diff --git a/extensions/apps/traceAnalyzer/simulationdialog.cpp b/extensions/apps/traceAnalyzer/simulationdialog.cpp index a50e474b..4462cb4f 100644 --- a/extensions/apps/traceAnalyzer/simulationdialog.cpp +++ b/extensions/apps/traceAnalyzer/simulationdialog.cpp @@ -44,7 +44,7 @@ #include #include -SimulationDialog::SimulationDialog(QWidget *parent) : QWidget(parent), ui(new Ui::SimulationDialog) +SimulationDialog::SimulationDialog(QWidget* parent) : QWidget(parent), ui(new Ui::SimulationDialog) { ui->setupUi(this); @@ -76,15 +76,15 @@ SimulationDialog::SimulationDialog(QWidget *parent) : QWidget(parent), ui(new Ui void SimulationDialog::on_browseDramSysButton_clicked() { - QString fileName = - QFileDialog::getOpenFileName(this, ui->browseDramSysButton->text(), {}, "DRAMSys executable (*)"); + QString fileName = QFileDialog::getOpenFileName( + this, ui->browseDramSysButton->text(), {}, "DRAMSys executable (*)"); ui->dramSysPath->setText(fileName); } void SimulationDialog::on_browseConfigButton_clicked() { - QString fileName = - QFileDialog::getOpenFileName(this, ui->browseConfigButton->text(), {}, "Configuration file (*.json)"); + QString fileName = QFileDialog::getOpenFileName( + this, ui->browseConfigButton->text(), {}, "Configuration file (*.json)"); ui->jsonPath->setText(fileName); loadConfigurationFromPath(); @@ -100,7 +100,8 @@ void SimulationDialog::on_browseOutputButton_clicked() void SimulationDialog::on_browseResourceDirButton_clicked() { - QString fileName = QFileDialog::getExistingDirectory(this, ui->browseResourceDirButton->text(), {}); + QString fileName = + QFileDialog::getExistingDirectory(this, ui->browseResourceDirButton->text(), {}); ui->resourceDirLineEdit->setText(fileName); loadConfigurationFromPath(); @@ -119,7 +120,9 @@ void SimulationDialog::on_simulateButton_clicked() // Spawn the DRAMSys process simulatorProcess = new QProcess(this); - QObject::connect(simulatorProcess, &QIODevice::readyRead, this, + QObject::connect(simulatorProcess, + &QIODevice::readyRead, + this, [=] { QByteArray msg = simulatorProcess->read(4096); @@ -127,7 +130,9 @@ void SimulationDialog::on_simulateButton_clicked() processMessage(msg.toStdString()); }); - QObject::connect(simulatorProcess, QOverload::of(&QProcess::finished), this, + QObject::connect(simulatorProcess, + QOverload::of(&QProcess::finished), + this, [=](int exitCode, QProcess::ExitStatus exitStatus) { Q_UNUSED(exitStatus) @@ -192,7 +197,7 @@ void SimulationDialog::showStopButton(bool val) ui->stopButton->setVisible(val); } -void SimulationDialog::saveConfiguration(QFile &file) +void SimulationDialog::saveConfiguration(QFile& file) { if (!file.open(QIODevice::ReadWrite | QIODevice::Text)) return; @@ -221,7 +226,7 @@ void SimulationDialog::saveConfiguration(QFile &file) out << dump.c_str(); } -void SimulationDialog::processMessage(const std::string &msg) +void SimulationDialog::processMessage(const std::string& msg) { // Get percentages QRegularExpression re("(\\d+(\\.\\d+)?|\\.\\d+) ?%"); @@ -252,15 +257,17 @@ void SimulationDialog::loadConfigurationFromTextFields() try { - nlohmann::json::parse(ui->addressMappingTextEdit->toPlainText().toStdString()).get_to(addressMapping); + nlohmann::json::parse(ui->addressMappingTextEdit->toPlainText().toStdString()) + .get_to(addressMapping); nlohmann::json::parse(ui->mcConfigTextEdit->toPlainText().toStdString()).get_to(mcConfig); nlohmann::json::parse(ui->memSpecTextEdit->toPlainText().toStdString()).get_to(memSpec); nlohmann::json::parse(ui->simConfigTextEdit->toPlainText().toStdString()).get_to(simConfig); if (!ui->traceSetupTextEdit->toPlainText().toStdString().empty()) - nlohmann::json::parse(ui->traceSetupTextEdit->toPlainText().toStdString()).get_to(traceSetup); + nlohmann::json::parse(ui->traceSetupTextEdit->toPlainText().toStdString()) + .get_to(traceSetup); } - catch (const std::exception &e) + catch (const std::exception& e) { qWarning() << "Error while parsing json:" << e.what(); return; @@ -272,8 +279,7 @@ void SimulationDialog::loadConfigurationFromTextFields() memSpec, simConfig, simulationId, - std::make_optional>(std::move(traceSetup)) - }; + std::make_optional>(std::move(traceSetup))}; loadConfiguration(); } @@ -289,7 +295,7 @@ void SimulationDialog::loadConfigurationFromPath() { configuration = DRAMSys::Config::from_path(ui->jsonPath->text().toStdString()); } - catch (const std::exception &e) + catch (const std::exception& e) { qWarning() << "Error while parsing json:" << e.what(); return; @@ -350,7 +356,7 @@ void SimulationDialog::loadTraceSetup() { ui->traceSetupTextEdit->clear(); - if (const auto &traceSetup = configuration.tracesetup) + if (const auto& traceSetup = configuration.tracesetup) { std::string dump = nlohmann::json(*traceSetup).dump(4); ui->traceSetupTextEdit->setText(dump.c_str()); @@ -372,7 +378,7 @@ QFileInfoList SimulationDialog::getSimulationResults() // Get the path where the tracefiles are located QDir baseDir(ui->outputDirLineEdit->text()); - for (const auto &fileInfo : baseDir.entryInfoList()) + for (const auto& fileInfo : baseDir.entryInfoList()) { if (fileInfo.baseName().startsWith(configuration.simulationid.c_str())) { @@ -387,8 +393,8 @@ QFileInfoList SimulationDialog::getSimulationResults() return list; } -void SimulationDialog::openSimulationResults(const QFileInfoList &fileInfos) +void SimulationDialog::openSimulationResults(const QFileInfoList& fileInfos) { - for (const auto &fileInfo : fileInfos) + for (const auto& fileInfo : fileInfos) openFileRequested(fileInfo.absoluteFilePath()); } diff --git a/extensions/apps/traceAnalyzer/simulationdialog.h b/extensions/apps/traceAnalyzer/simulationdialog.h index b4c43108..eaa5c7d2 100644 --- a/extensions/apps/traceAnalyzer/simulationdialog.h +++ b/extensions/apps/traceAnalyzer/simulationdialog.h @@ -57,10 +57,10 @@ class SimulationDialog : public QWidget Q_OBJECT public: - explicit SimulationDialog(QWidget *parent = nullptr); + explicit SimulationDialog(QWidget* parent = nullptr); signals: - void openFileRequested(const QString &path); + void openFileRequested(const QString& path); private Q_SLOTS: void on_browseDramSysButton_clicked(); @@ -85,18 +85,18 @@ private: void loadPreview(); void showStopButton(bool val); - void saveConfiguration(QFile &file); - void processMessage(const std::string &msg); + void saveConfiguration(QFile& file); + void processMessage(const std::string& msg); QFileInfoList getSimulationResults(); - void openSimulationResults(const QFileInfoList &fileInfos); + void openSimulationResults(const QFileInfoList& fileInfos); QTemporaryFile temporaryConfigurationFile; DRAMSys::Config::Configuration configuration; QPointer simulatorProcess; - Ui::SimulationDialog *ui; + Ui::SimulationDialog* ui; }; #endif diff --git a/extensions/apps/traceAnalyzer/traceanalyzer.cpp b/extensions/apps/traceAnalyzer/traceanalyzer.cpp index cdf52de7..835ee0ca 100644 --- a/extensions/apps/traceAnalyzer/traceanalyzer.cpp +++ b/extensions/apps/traceAnalyzer/traceanalyzer.cpp @@ -60,8 +60,7 @@ void TraceAnalyzer::setUpGui() ui->traceFileTabs->clear(); } - -TraceAnalyzer::TraceAnalyzer(QWidget *parent) : +TraceAnalyzer::TraceAnalyzer(QWidget* parent) : QMainWindow(parent), ui(new Ui::TraceAnalyzer), evaluationTool(pythonCaller) @@ -69,15 +68,14 @@ TraceAnalyzer::TraceAnalyzer(QWidget *parent) : setUpGui(); } -TraceAnalyzer::TraceAnalyzer(QSet paths, StartupOption option, - QWidget *parent): +TraceAnalyzer::TraceAnalyzer(QSet paths, StartupOption option, QWidget* parent) : QMainWindow(parent), ui(new Ui::TraceAnalyzer), evaluationTool(pythonCaller) { setUpGui(); - for (const QString &path : paths) + for (const QString& path : paths) openTracefileTab(path); } @@ -88,32 +86,30 @@ TraceAnalyzer::~TraceAnalyzer() void TraceAnalyzer::on_actionOpen_triggered() { - QStringList paths = QFileDialog::getOpenFileNames(this, - tr("Open Tracefile"), - "../simulator/", - tr("Tracefile (*.tdb)")); + QStringList paths = QFileDialog::getOpenFileNames( + this, tr("Open Tracefile"), "../simulator/", tr("Tracefile (*.tdb)")); if (paths.isEmpty()) return; - for (const QString &path : paths) + for (const QString& path : paths) openTracefileTab(path); } -TraceFileTab *TraceAnalyzer::createTraceFileTab(const QString &path) +TraceFileTab* TraceAnalyzer::createTraceFileTab(const QString& path) { - TraceFileTab *traceFileTab = new TraceFileTab(path.toStdString(), pythonCaller, this); + TraceFileTab* traceFileTab = new TraceFileTab(path.toStdString(), pythonCaller, this); connect(traceFileTab, &TraceFileTab::statusChanged, this, &TraceAnalyzer::statusChanged); return traceFileTab; } -void TraceAnalyzer::openTracefileTab(const QString &path) +void TraceAnalyzer::openTracefileTab(const QString& path) { if (openedTraceFiles.contains(path)) return; - TraceFileTab *traceFileTab = createTraceFileTab(path); + TraceFileTab* traceFileTab = createTraceFileTab(path); ui->traceFileTabs->addTab(traceFileTab, QFileInfo(path).baseName()); openedTraceFiles.insert(path); @@ -141,8 +137,7 @@ void TraceAnalyzer::on_menuFile_aboutToShow() void TraceAnalyzer::closeTab(int index) { - TraceFileTab *traceFileTab = static_cast - (ui->traceFileTabs->widget(index)); + TraceFileTab* traceFileTab = static_cast(ui->traceFileTabs->widget(index)); if (traceFileTab->close()) { @@ -172,7 +167,7 @@ void TraceAnalyzer::on_actionClose_all_triggered() void TraceAnalyzer::reloadTab(int index) { - auto traceFileTab = static_cast(ui->traceFileTabs->widget(index)); + auto traceFileTab = static_cast(ui->traceFileTabs->widget(index)); QString traceFile = traceFileTab->getPathToTraceFile(); traceTime time = traceFileTab->getCurrentTraceTime(); @@ -215,30 +210,32 @@ void TraceAnalyzer::on_actionReload_all_triggered() void TraceAnalyzer::on_actionSave_triggered() { - auto traceFileTab = static_cast(ui->traceFileTabs->currentWidget()); + auto traceFileTab = static_cast(ui->traceFileTabs->currentWidget()); traceFileTab->commitChangesToDB(); - this->statusChanged(QString("Saved database ") + QFileInfo(traceFileTab->getPathToTraceFile()).baseName() + " "); + this->statusChanged(QString("Saved database ") + + QFileInfo(traceFileTab->getPathToTraceFile()).baseName() + " "); } void TraceAnalyzer::on_actionSave_all_triggered() { - for (int index = 0; index < ui->traceFileTabs->count(); index++) { + for (int index = 0; index < ui->traceFileTabs->count(); index++) + { // Changes in the database files will trigger the file watchers from - // the TraceFileTab class. They generate signals connected to TraceAnalyzer::statusChanged(). - TraceFileTab *traceFileTab = static_cast - (ui->traceFileTabs->widget(index)); + // the TraceFileTab class. They generate signals connected to + // TraceAnalyzer::statusChanged(). + TraceFileTab* traceFileTab = static_cast(ui->traceFileTabs->widget(index)); traceFileTab->commitChangesToDB(); } } void TraceAnalyzer::on_actionExportAsVCD_triggered() { - TraceFileTab *traceFileTab = static_cast(ui->traceFileTabs->currentWidget()); + TraceFileTab* traceFileTab = static_cast(ui->traceFileTabs->currentWidget()); traceFileTab->exportAsVCD(); } -void TraceAnalyzer::statusChanged(const QString &message) +void TraceAnalyzer::statusChanged(const QString& message) { statusLabel->setText(message + QTime::currentTime().toString()); } @@ -253,18 +250,21 @@ void TraceAnalyzer::on_actionMetrics_triggered() void TraceAnalyzer::on_actionAbout_triggered() { QMessageBox::about( - this, QStringLiteral("DRAMSys"), - QStringLiteral( - "DRAMSys4.0 is a flexible DRAM subsystem design space exploration framework based on SystemC " - "TLM-2.0. It was developed at the Microelectronic Systems " - "Design Research Group and Fraunhofer IESE.")); + this, + QStringLiteral("DRAMSys"), + QStringLiteral("DRAMSys4.0 is a flexible DRAM subsystem design space exploration " + "framework based on SystemC " + "TLM-2.0. It was developed at the Microelectronic Systems " + "Design Research Group and Fraunhofer IESE.")); } -void TraceAnalyzer::closeEvent(QCloseEvent *event) +void TraceAnalyzer::closeEvent(QCloseEvent* event) { for (unsigned int i = 0; i < ui->traceFileTabs->count(); i++) { - QWidget *tab = ui->traceFileTabs->widget(i); + QWidget* tab = ui->traceFileTabs->widget(i); if (!tab->close()) { event->ignore(); @@ -277,10 +277,13 @@ void TraceAnalyzer::closeEvent(QCloseEvent *event) void TraceAnalyzer::on_actionSimulate_triggered() { - SimulationDialog *simulationDialog = new SimulationDialog(this); + SimulationDialog* simulationDialog = new SimulationDialog(this); simulationDialog->setWindowFlag(Qt::Window); - QObject::connect(simulationDialog, &SimulationDialog::openFileRequested, this, &TraceAnalyzer::openTracefileTab); + QObject::connect(simulationDialog, + &SimulationDialog::openFileRequested, + this, + &TraceAnalyzer::openTracefileTab); simulationDialog->show(); } diff --git a/extensions/apps/traceAnalyzer/traceanalyzer.h b/extensions/apps/traceAnalyzer/traceanalyzer.h index 5a41185b..91c8797d 100644 --- a/extensions/apps/traceAnalyzer/traceanalyzer.h +++ b/extensions/apps/traceAnalyzer/traceanalyzer.h @@ -39,19 +39,28 @@ #ifndef TRACEANALYZER_H #define TRACEANALYZER_H -#include -#include -#include -#include -#include #include "evaluationtool.h" +#include +#include +#include +#include +#include -namespace Ui { +namespace Ui +{ class TraceAnalyzer; } -enum class StartupOption {showPlots, runTests}; -enum class OpenOptions {files, folders}; +enum class StartupOption +{ + showPlots, + runTests +}; +enum class OpenOptions +{ + files, + folders +}; class TraceFileTab; @@ -60,24 +69,23 @@ class TraceAnalyzer : public QMainWindow Q_OBJECT public: - explicit TraceAnalyzer(QWidget *parent = nullptr); - explicit TraceAnalyzer(QSet paths, StartupOption option, - QWidget *parent = nullptr); + explicit TraceAnalyzer(QWidget* parent = nullptr); + explicit TraceAnalyzer(QSet paths, StartupOption option, QWidget* parent = nullptr); ~TraceAnalyzer(); void setUpStatusBar(); void setUpGui(); protected: - void closeEvent(QCloseEvent *event) override; + void closeEvent(QCloseEvent* event) override; private: - TraceFileTab *createTraceFileTab(const QString &path); - void openTracefileTab(const QString &path); + TraceFileTab* createTraceFileTab(const QString& path); + void openTracefileTab(const QString& path); void reloadTab(int index); void closeTab(int index); - QLabel *statusLabel; + QLabel* statusLabel; QSet openedTraceFiles; EvaluationTool evaluationTool; PythonCaller pythonCaller; @@ -99,11 +107,10 @@ private Q_SLOTS: void on_actionSimulate_triggered(); public Q_SLOTS: - void statusChanged(const QString &message); + void statusChanged(const QString& message); private: - Ui::TraceAnalyzer *ui; + Ui::TraceAnalyzer* ui; }; #endif // TRACEANALYZER_H - diff --git a/extensions/apps/traceAnalyzer/tracefiletab.cpp b/extensions/apps/traceAnalyzer/tracefiletab.cpp index 4ca86e62..acb8488d 100644 --- a/extensions/apps/traceAnalyzer/tracefiletab.cpp +++ b/extensions/apps/traceAnalyzer/tracefiletab.cpp @@ -70,21 +70,26 @@ #include #include -TraceFileTab::TraceFileTab(std::string_view traceFilePath, PythonCaller &pythonCaller, QWidget *parent) - : QWidget(parent), ui(new Ui::TraceFileTab), commentModel(new CommentModel(this)), - navigator(new TraceNavigator(traceFilePath.data(), commentModel, this)), - mcConfigModel(new McConfigModel(navigator->TraceFile(), this)), - memSpecModel(new MemSpecModel(navigator->TraceFile(), this)), - availableRowsModel(new AvailableTracePlotLineModel(navigator->GeneralTraceInfo(), this)), - selectedRowsModel(new SelectedTracePlotLineModel(navigator->GeneralTraceInfo(), this)), - tracePlotLineDataSource(new TracePlotLineDataSource(selectedRowsModel, this)), - depInfosView(new DependencyInfosModel(navigator->TraceFile(), this)), savingChangesToDB(false), - pythonCaller(pythonCaller), traceFilePath(traceFilePath) +TraceFileTab::TraceFileTab(std::string_view traceFilePath, + PythonCaller& pythonCaller, + QWidget* parent) : + QWidget(parent), + ui(new Ui::TraceFileTab), + commentModel(new CommentModel(this)), + navigator(new TraceNavigator(traceFilePath.data(), commentModel, this)), + mcConfigModel(new McConfigModel(navigator->TraceFile(), this)), + memSpecModel(new MemSpecModel(navigator->TraceFile(), this)), + availableRowsModel(new AvailableTracePlotLineModel(navigator->GeneralTraceInfo(), this)), + selectedRowsModel(new SelectedTracePlotLineModel(navigator->GeneralTraceInfo(), this)), + tracePlotLineDataSource(new TracePlotLineDataSource(selectedRowsModel, this)), + depInfosView(new DependencyInfosModel(navigator->TraceFile(), this)), + savingChangesToDB(false), + pythonCaller(pythonCaller), + traceFilePath(traceFilePath) { ui->setupUi(this); - std::cout << "Opening new tab for \"" << traceFilePath << "\"" << - std::endl; + std::cout << "Opening new tab for \"" << traceFilePath << "\"" << std::endl; ui->mcConfigView->setModel(mcConfigModel); ui->mcConfigView->horizontalHeader()->setSectionResizeMode(QHeaderView::ResizeToContents); @@ -119,10 +124,11 @@ void TraceFileTab::commitChangesToDB() void TraceFileTab::exportAsVCD() { - std::string filename = QFileDialog::getSaveFileName(this, "Export to VCD", "", "VCD files (*.vcd)").toStdString(); + std::string filename = + QFileDialog::getSaveFileName(this, "Export to VCD", "", "VCD files (*.vcd)").toStdString(); auto dump = PythonCaller::dumpVcd(traceFilePath); - + std::ofstream file(filename); file << dump; @@ -139,26 +145,40 @@ void TraceFileTab::setUpTraceSelector() ui->selectedTreeView->setSelectionModel(selectedRowsModel->selectionModel()); ui->selectedTreeView->installEventFilter(selectedRowsModel); - connect(availableRowsModel, &AvailableTracePlotLineModel::returnPressed, selectedRowsModel, + connect(availableRowsModel, + &AvailableTracePlotLineModel::returnPressed, + selectedRowsModel, &SelectedTracePlotLineModel::addIndexesFromAvailableModel); - connect(ui->availableTreeView, &QAbstractItemView::doubleClicked, availableRowsModel, + connect(ui->availableTreeView, + &QAbstractItemView::doubleClicked, + availableRowsModel, &AvailableTracePlotLineModel::itemsDoubleClicked); - connect(ui->selectedTreeView, &QAbstractItemView::doubleClicked, selectedRowsModel, + connect(ui->selectedTreeView, + &QAbstractItemView::doubleClicked, + selectedRowsModel, &SelectedTracePlotLineModel::itemsDoubleClicked); - connect(selectedRowsModel, &QAbstractItemModel::dataChanged, tracePlotLineDataSource, + connect(selectedRowsModel, + &QAbstractItemModel::dataChanged, + tracePlotLineDataSource, &TracePlotLineDataSource::updateModel); - connect(selectedRowsModel, &QAbstractItemModel::rowsInserted, tracePlotLineDataSource, + connect(selectedRowsModel, + &QAbstractItemModel::rowsInserted, + tracePlotLineDataSource, &TracePlotLineDataSource::updateModel); - connect(selectedRowsModel, &QAbstractItemModel::rowsRemoved, tracePlotLineDataSource, + connect(selectedRowsModel, + &QAbstractItemModel::rowsRemoved, + tracePlotLineDataSource, &TracePlotLineDataSource::updateModel); } void TraceFileTab::setUpTraceplotScrollbar() { - QObject::connect(ui->traceplotScrollbar, SIGNAL(valueChanged(int)), - ui->traceplot, SLOT(verticalScrollbarChanged(int))); + QObject::connect(ui->traceplotScrollbar, + SIGNAL(valueChanged(int)), + ui->traceplot, + SLOT(verticalScrollbarChanged(int))); } void TraceFileTab::initNavigatorAndItsDependentWidgets(QString path) @@ -166,11 +186,13 @@ void TraceFileTab::initNavigatorAndItsDependentWidgets(QString path) ui->traceplot->init(navigator, ui->traceplotScrollbar, tracePlotLineDataSource, commentModel); ui->traceScroller->init(navigator, ui->traceplot, tracePlotLineDataSource); - connect(this, SIGNAL(colorGroupingChanged(ColorGrouping)), - ui->traceScroller, SLOT(colorGroupingChanged(ColorGrouping))); + connect(this, + SIGNAL(colorGroupingChanged(ColorGrouping)), + ui->traceScroller, + SLOT(colorGroupingChanged(ColorGrouping))); ui->selectedTransactionTree->init(navigator); - //ui->debugMessages->init(navigator,ui->traceplot); + // ui->debugMessages->init(navigator,ui->traceplot); ui->bandwidthPlot->canvas()->installEventFilter(this); ui->powerPlot->canvas()->installEventFilter(this); @@ -180,8 +202,7 @@ void TraceFileTab::initNavigatorAndItsDependentWidgets(QString path) void TraceFileTab::setUpFileWatcher(QString path) { fileWatcher = new QFileSystemWatcher(QStringList(path), this); - QObject::connect(fileWatcher, SIGNAL(fileChanged(QString)), this, - SLOT(tracefileChanged())); + QObject::connect(fileWatcher, SIGNAL(fileChanged(QString)), this, SLOT(tracefileChanged())); } void TraceFileTab::setUpCommentView() @@ -191,41 +212,50 @@ void TraceFileTab::setUpCommentView() ui->commentView->installEventFilter(commentModel); ui->commentView->setContextMenuPolicy(Qt::CustomContextMenu); - QObject::connect(ui->commentView, &QTableView::customContextMenuRequested, - commentModel, &CommentModel::openContextMenu); + QObject::connect(ui->commentView, + &QTableView::customContextMenuRequested, + commentModel, + &CommentModel::openContextMenu); - QObject::connect(commentModel, &CommentModel::editTriggered, ui->commentView, - [=](const QModelIndex &index) + QObject::connect(commentModel, + &CommentModel::editTriggered, + ui->commentView, + [=](const QModelIndex& index) { ui->tabWidget->setCurrentWidget(ui->tabComments); ui->commentView->edit(index); ui->commentView->scrollTo(index); }); - QObject::connect(ui->commentView, &QTableView::doubleClicked, - commentModel, &CommentModel::rowDoubleClicked); + QObject::connect( + ui->commentView, &QTableView::doubleClicked, commentModel, &CommentModel::rowDoubleClicked); } -void TraceFileTab::setUpPossiblePhases() { +void TraceFileTab::setUpPossiblePhases() +{ const auto possiblePhases = ConfigurationFactory::possiblePhases(navigator->TraceFile()); - for (auto p : possiblePhases) { + for (auto p : possiblePhases) + { auto item = new QListWidgetItem(p, ui->depTabPossiblePhases); item->setFlags(item->flags() | Qt::ItemIsUserCheckable); // set checkable flag - item->setCheckState(Qt::Unchecked); // AND initialize check state - + item->setCheckState(Qt::Unchecked); // AND initialize check state } - ui->calculateDependencies->setEnabled(ConfigurationFactory::deviceSupported(navigator->TraceFile())); + ui->calculateDependencies->setEnabled( + ConfigurationFactory::deviceSupported(navigator->TraceFile())); } void TraceFileTab::tracefileChanged() { - if (savingChangesToDB == true) { + if (savingChangesToDB == true) + { // Database has changed due to user action (e.g., saving comments). // No need to disable the "Save changes to DB" menu. savingChangesToDB = false; Q_EMIT statusChanged(QString("Changes saved ")); - } else { + } + else + { // External event changed the database file (e.g., the database file // was overwritten when running a new test). // The "Save changes to DB" menu must be disabled to avoid saving @@ -235,15 +265,17 @@ void TraceFileTab::tracefileChanged() navigator->refreshData(); } -void TraceFileTab::closeEvent(QCloseEvent *event) +void TraceFileTab::closeEvent(QCloseEvent* event) { if (navigator->existChangesToCommit()) { QMessageBox saveDialog; saveDialog.setWindowTitle(QFileInfo(traceFilePath.data()).baseName()); saveDialog.setText("The trace file has been modified."); - saveDialog.setInformativeText("Do you want to save your changes?
Unsaved changes will be lost."); - saveDialog.setStandardButtons(QMessageBox::Save | QMessageBox::Discard | QMessageBox::Cancel); + saveDialog.setInformativeText( + "Do you want to save your changes?
Unsaved changes will be lost."); + saveDialog.setStandardButtons(QMessageBox::Save | QMessageBox::Discard | + QMessageBox::Cancel); saveDialog.setDefaultButton(QMessageBox::Save); saveDialog.setIcon(QMessageBox::Warning); int returnCode = saveDialog.exec(); @@ -278,14 +310,14 @@ void TraceFileTab::navigateToTime(traceTime time) traceTime TraceFileTab::getZoomLevel() const { - TracePlot *traceplot = static_cast(ui->traceplot); + TracePlot* traceplot = static_cast(ui->traceplot); return traceplot->ZoomLevel(); } void TraceFileTab::setZoomLevel(traceTime zoomLevel) { - TracePlot *traceplot = static_cast(ui->traceplot); - TraceScroller *tracescroller = static_cast(ui->traceScroller); + TracePlot* traceplot = static_cast(ui->traceplot); + TraceScroller* tracescroller = static_cast(ui->traceScroller); traceplot->setZoomLevel(zoomLevel); tracescroller->tracePlotZoomChanged(); } @@ -295,59 +327,64 @@ std::shared_ptr TraceFileTab::saveTraceSelecto return selectedRowsModel->getClonedRootNode(); } -void TraceFileTab::restoreTraceSelectorState(std::shared_ptr rootNode) +void TraceFileTab::restoreTraceSelectorState( + std::shared_ptr rootNode) { selectedRowsModel->setRootNode(std::move(rootNode)); } -class ItemDelegate: public QItemDelegate +class ItemDelegate : public QItemDelegate { public: - ItemDelegate(QObject* parent = nullptr): QItemDelegate(parent) - { - } + ItemDelegate(QObject* parent = nullptr) : QItemDelegate(parent) {} - void paint(QPainter* painter, const QStyleOptionViewItem& option, const QModelIndex& index) const + void + paint(QPainter* painter, const QStyleOptionViewItem& option, const QModelIndex& index) const { - if (index.column() == 1) { + if (index.column() == 1) + { double progress = index.data().toDouble(); QStyleOptionProgressBar opt; opt.rect = option.rect; opt.minimum = 0; opt.maximum = 100; opt.progress = static_cast(floor(progress)); - opt.text = QString::number(progress, 'f', 2)+" %"; + opt.text = QString::number(progress, 'f', 2) + " %"; opt.textVisible = true; QApplication::style()->drawControl(QStyle::CE_ProgressBar, &opt, painter, nullptr); - } else { + } + else + { QItemDelegate::paint(painter, option, index); } } }; -void TraceFileTab::on_latencyTreeView_doubleClicked(const QModelIndex &index) +void TraceFileTab::on_latencyTreeView_doubleClicked(const QModelIndex& index) { // Get onlye the leaf: - if(index.column() == 0 && index.model()->hasChildren(index) == false) { + if (index.column() == 0 && index.model()->hasChildren(index) == false) + { unsigned int id = index.data().toUInt(); - if(id!=0) { + if (id != 0) + { navigator->selectTransaction(id); } } } -bool TraceFileTab::eventFilter(QObject *object, QEvent *event) +bool TraceFileTab::eventFilter(QObject* object, QEvent* event) { - if (auto canvas = qobject_cast(object)) + if (auto canvas = qobject_cast(object)) { if (event->type() == QEvent::MouseButtonDblClick) { - QMouseEvent *mouseEvent = static_cast(event); + QMouseEvent* mouseEvent = static_cast(event); if (mouseEvent->button() != Qt::LeftButton) return false; - QwtPlot *plot = canvas->plot(); + QwtPlot* plot = canvas->plot(); double realTime = plot->invTransform(QwtPlot::xBottom, mouseEvent->x()); @@ -362,20 +399,21 @@ bool TraceFileTab::eventFilter(QObject *object, QEvent *event) return QWidget::eventFilter(object, event); } -void TraceFileTab::on_calculateDependencies_clicked() { +void TraceFileTab::on_calculateDependencies_clicked() +{ std::vector dependencyFilter; - for (int row = 0; row < ui->depTabPossiblePhases->count(); row++) { + for (int row = 0; row < ui->depTabPossiblePhases->count(); row++) + { auto item = ui->depTabPossiblePhases->item(row); if (item->checkState() == Qt::Checked) dependencyFilter.push_back(item->text()); } - + savingChangesToDB = true; PhaseDependenciesTracker::calculateDependencies(navigator->TraceFile(), dependencyFilter); depInfosView = new DependencyInfosModel(navigator->TraceFile(), this); ui->depInfosView->setModel(depInfosView); ui->depInfosView->header()->setSectionResizeMode(QHeaderView::ResizeToContents); - } void TraceFileTab::on_startLatencyAnalysis_clicked() @@ -406,45 +444,48 @@ void TraceFileTab::on_startLatencyAnalysis_clicked() int currentLatency = 0; QStandardItem* currentLatencyItem = nullptr; int counter = 0; - while (query.next()) { - if(query.value(0) != currentLatency) { - currentLatencyItem = new QStandardItem(QString::number(query.value(0).toInt())+" ns"); + while (query.next()) + { + if (query.value(0) != currentLatency) + { + currentLatencyItem = new QStandardItem(QString::number(query.value(0).toInt()) + " ns"); currentLatency = query.value(0).toInt(); - QList row; + QList row; row.append(currentLatencyItem); row.append(new QStandardItem()); model->appendRow(row); } - QStandardItem * id = new QStandardItem(query.value(1).toString()); + QStandardItem* id = new QStandardItem(query.value(1).toString()); currentLatencyItem->appendRow(id); counter++; - int percentage = int(ceil((double(counter))/(double(maxTransactions))*100.0)); + int percentage = int(ceil((double(counter)) / (double(maxTransactions)) * 100.0)); ui->latencyAnalysisProgressBar->setValue(percentage); } - QStringList header = {"Latency","Occurences"}; + QStringList header = {"Latency", "Occurences"}; model->setHorizontalHeaderLabels(header); // Generate Histrogram and Tree: - QwtPlotHistogram *hist = new QwtPlotHistogram; - QVector *intervals = new QVector; - for(int i = 0; i < model->rowCount(); i++) { - double latency = model->item(i,0)->text().replace(" ns","").toDouble(); + QwtPlotHistogram* hist = new QwtPlotHistogram; + QVector* intervals = new QVector; + for (int i = 0; i < model->rowCount(); i++) + { + double latency = model->item(i, 0)->text().replace(" ns", "").toDouble(); int numberOfChilds = model->item(i)->rowCount(); - double percentage = 100*((double(numberOfChilds))/(double(counter))); - model->item(i,1)->setText(QString::number(percentage)); - intervals->append(QwtIntervalSample(percentage, latency, latency+1)); + double percentage = 100 * ((double(numberOfChilds)) / (double(counter))); + model->item(i, 1)->setText(QString::number(percentage)); + intervals->append(QwtIntervalSample(percentage, latency, latency + 1)); } ui->latencyTreeView->setItemDelegate(new ItemDelegate(ui->latencyTreeView)); ui->latencyTreeView->setModel(model); hist->setSamples(*intervals); hist->attach(ui->latencyPlot); - hist->setPen(QPen(QColor(255,0,0,100))); - hist->setBrush(QBrush(QColor(255,0,0,255))); - ui->latencyPlot->setAxisTitle(0,"Occurences [%]"); - QwtText axisTitle( "Latency [ns]" ); - axisTitle.setFont( ui->latencyPlot->axisTitle( QwtPlot::xBottom ).font() ); - ui->latencyPlot->setAxisTitle( QwtPlot::xBottom, axisTitle ); + hist->setPen(QPen(QColor(255, 0, 0, 100))); + hist->setBrush(QBrush(QColor(255, 0, 0, 255))); + ui->latencyPlot->setAxisTitle(0, "Occurences [%]"); + QwtText axisTitle("Latency [ns]"); + axisTitle.setFont(ui->latencyPlot->axisTitle(QwtPlot::xBottom).font()); + ui->latencyPlot->setAxisTitle(QwtPlot::xBottom, axisTitle); ui->latencyPlot->replot(); } @@ -458,31 +499,32 @@ void TraceFileTab::on_startPowerAnalysis_clicked() query.exec(sql); - QwtPointSeriesData * data = new QwtPointSeriesData; - QwtPlotCurve * cur = new QwtPlotCurve("Speed"); - QVector* samples=new QVector; + QwtPointSeriesData* data = new QwtPointSeriesData; + QwtPlotCurve* cur = new QwtPlotCurve("Speed"); + QVector* samples = new QVector; - while (query.next()) { + while (query.next()) + { double time = query.value(0).toDouble(); double power = query.value(1).toDouble(); - samples->push_back(QPointF(time,power)); + samples->push_back(QPointF(time, power)); } - //ui->powerPlot->setAxisTitle(QwtPlot::xBottom,"Time"); - //ui->powerPlot->setAxisLabelRotation(QwtPlot::xBottom,-50.0); - //ui->powerPlot->setAxisLabelAlignment(QwtPlot::xBottom,Qt::AlignLeft|Qt::AlignBottom); - //ui->powerPlot->setAxisTitle(QwtPlot::yLeft,"Power"); + // ui->powerPlot->setAxisTitle(QwtPlot::xBottom,"Time"); + // ui->powerPlot->setAxisLabelRotation(QwtPlot::xBottom,-50.0); + // ui->powerPlot->setAxisLabelAlignment(QwtPlot::xBottom,Qt::AlignLeft|Qt::AlignBottom); + // ui->powerPlot->setAxisTitle(QwtPlot::yLeft,"Power"); data->setSamples(*samples); cur->setData(data); cur->attach(ui->powerPlot); - cur->setPen(QPen(QColor(255,0,0))); + cur->setPen(QPen(QColor(255, 0, 0))); - QwtPlotMagnifier *mag1 = new QwtPlotMagnifier(ui->powerPlot->canvas()); + QwtPlotMagnifier* mag1 = new QwtPlotMagnifier(ui->powerPlot->canvas()); mag1->setAxisEnabled(QwtPlot::xBottom, true); mag1->setAxisEnabled(QwtPlot::yLeft, false); mag1->setWheelFactor(5); - QwtPlotPanner *pan1 = new QwtPlotPanner(ui->powerPlot->canvas()); + QwtPlotPanner* pan1 = new QwtPlotPanner(ui->powerPlot->canvas()); pan1->setAxisEnabled(QwtPlot::xBottom, true); pan1->setAxisEnabled(QwtPlot::yLeft, false); @@ -492,11 +534,12 @@ void TraceFileTab::on_startPowerAnalysis_clicked() sql = "SELECT time, AverageBandwidth FROM Bandwidth;"; query.exec(sql); - QwtPointSeriesData * data2 = new QwtPointSeriesData; - QwtPlotCurve * cur2 = new QwtPlotCurve("Speed"); - QVector* samples2=new QVector; + QwtPointSeriesData* data2 = new QwtPointSeriesData; + QwtPlotCurve* cur2 = new QwtPlotCurve("Speed"); + QVector* samples2 = new QVector; - while (query.next()) { + while (query.next()) + { double time = query.value(0).toDouble(); double percentage = query.value(1).toDouble() * 100.0; samples2->push_back(QPointF(time, percentage)); @@ -505,19 +548,19 @@ void TraceFileTab::on_startPowerAnalysis_clicked() data2->setSamples(*samples2); cur2->setData(data2); cur2->attach(ui->bandwidthPlot); - cur2->setPen(QPen(QColor(255,0,0))); + cur2->setPen(QPen(QColor(255, 0, 0))); - ui->bandwidthPlot->setAxisTitle(0,"Bandwidth [%]"); - ui->bandwidthPlot->setAxisScale(0,0.0,100.0); - QwtText axisTitle2( "Time [s]" ); - axisTitle2.setFont( ui->bandwidthPlot->axisTitle( QwtPlot::xBottom ).font() ); - ui->bandwidthPlot->setAxisTitle( QwtPlot::xBottom, axisTitle2 ); + ui->bandwidthPlot->setAxisTitle(0, "Bandwidth [%]"); + ui->bandwidthPlot->setAxisScale(0, 0.0, 100.0); + QwtText axisTitle2("Time [s]"); + axisTitle2.setFont(ui->bandwidthPlot->axisTitle(QwtPlot::xBottom).font()); + ui->bandwidthPlot->setAxisTitle(QwtPlot::xBottom, axisTitle2); - QwtPlotMagnifier *mag2 = new QwtPlotMagnifier(ui->bandwidthPlot->canvas()); + QwtPlotMagnifier* mag2 = new QwtPlotMagnifier(ui->bandwidthPlot->canvas()); mag2->setAxisEnabled(QwtPlot::xBottom, true); mag2->setAxisEnabled(QwtPlot::yLeft, false); mag2->setWheelFactor(5); - QwtPlotPanner *pan2 = new QwtPlotPanner(ui->bandwidthPlot->canvas()); + QwtPlotPanner* pan2 = new QwtPlotPanner(ui->bandwidthPlot->canvas()); pan2->setAxisEnabled(QwtPlot::xBottom, true); pan2->setAxisEnabled(QwtPlot::yLeft, false); @@ -537,11 +580,12 @@ void TraceFileTab::on_startPowerAnalysis_clicked() sql = "select Time, AverageBufferDepth from BufferDepth where BufferNumber = 0"; // TODO query.exec(sql); - QwtPointSeriesData * data3 = new QwtPointSeriesData; - QwtPlotCurve * cur3 = new QwtPlotCurve("Speed"); + QwtPointSeriesData* data3 = new QwtPointSeriesData; + QwtPlotCurve* cur3 = new QwtPlotCurve("Speed"); QVector* samples3 = new QVector; - while (query.next()) { + while (query.next()) + { double time = query.value(0).toDouble(); double queue = query.value(1).toDouble(); samples3->push_back(QPointF(time, queue)); @@ -550,19 +594,19 @@ void TraceFileTab::on_startPowerAnalysis_clicked() data3->setSamples(*samples3); cur3->setData(data3); cur3->attach(ui->bufferPlot); - cur3->setPen(QPen(QColor(255,0,0))); + cur3->setPen(QPen(QColor(255, 0, 0))); - ui->bufferPlot->setAxisTitle(0,"Buffer Utilization"); - ui->bufferPlot->setAxisScale(0,0.0, maxBufferDepth); - QwtText axisTitle3( "Time [s]" ); - axisTitle3.setFont( ui->bufferPlot->axisTitle( QwtPlot::xBottom ).font() ); - ui->bufferPlot->setAxisTitle( QwtPlot::xBottom, axisTitle3 ); + ui->bufferPlot->setAxisTitle(0, "Buffer Utilization"); + ui->bufferPlot->setAxisScale(0, 0.0, maxBufferDepth); + QwtText axisTitle3("Time [s]"); + axisTitle3.setFont(ui->bufferPlot->axisTitle(QwtPlot::xBottom).font()); + ui->bufferPlot->setAxisTitle(QwtPlot::xBottom, axisTitle3); - QwtPlotMagnifier *mag3 = new QwtPlotMagnifier(ui->bufferPlot->canvas()); + QwtPlotMagnifier* mag3 = new QwtPlotMagnifier(ui->bufferPlot->canvas()); mag3->setAxisEnabled(QwtPlot::xBottom, true); mag3->setAxisEnabled(QwtPlot::yLeft, false); mag3->setWheelFactor(5); - QwtPlotPanner *pan3 = new QwtPlotPanner(ui->bufferPlot->canvas()); + QwtPlotPanner* pan3 = new QwtPlotPanner(ui->bufferPlot->canvas()); pan3->setAxisEnabled(QwtPlot::xBottom, true); pan3->setAxisEnabled(QwtPlot::yLeft, false); diff --git a/extensions/apps/traceAnalyzer/tracefiletab.h b/extensions/apps/traceAnalyzer/tracefiletab.h index 1f3d0485..ff8e390e 100644 --- a/extensions/apps/traceAnalyzer/tracefiletab.h +++ b/extensions/apps/traceAnalyzer/tracefiletab.h @@ -45,19 +45,20 @@ #include "presentation/traceplot.h" #include "presentation/tracescroller.h" +#include "businessObjects/configmodels.h" +#include "businessObjects/dependencymodels.h" #include #include #include #include -#include "businessObjects/configmodels.h" -#include "businessObjects/dependencymodels.h" class CommentModel; class McConfigModel; class MemSpecModel; class PythonCaller; -namespace Ui { +namespace Ui +{ class TraceFileTab; } @@ -66,7 +67,9 @@ class TraceFileTab : public QWidget Q_OBJECT public: - explicit TraceFileTab(std::string_view traceFilePath, PythonCaller &pythonCaller, QWidget *parent); + explicit TraceFileTab(std::string_view traceFilePath, + PythonCaller& pythonCaller, + QWidget* parent); ~TraceFileTab(); void setUpFileWatcher(QString filename); @@ -89,33 +92,33 @@ public: void restoreTraceSelectorState(std::shared_ptr rootNode); protected: - void closeEvent(QCloseEvent *event) override; + void closeEvent(QCloseEvent* event) override; /** * Used to respond to double click events in the analysis * plots to navigate quickly to the corresponding tracetime. * May be moved into a seperate class at a later point in time. */ - bool eventFilter(QObject *object, QEvent *event) override; + bool eventFilter(QObject* object, QEvent* event) override; private: std::string traceFilePath; - Ui::TraceFileTab *ui; - QFileSystemWatcher *fileWatcher; + Ui::TraceFileTab* ui; + QFileSystemWatcher* fileWatcher; - CommentModel *commentModel; - TraceNavigator *navigator; + CommentModel* commentModel; + TraceNavigator* navigator; - McConfigModel *mcConfigModel; - MemSpecModel *memSpecModel; + McConfigModel* mcConfigModel; + MemSpecModel* memSpecModel; - AvailableTracePlotLineModel *availableRowsModel; - SelectedTracePlotLineModel *selectedRowsModel; - TracePlotLineDataSource *tracePlotLineDataSource; + AvailableTracePlotLineModel* availableRowsModel; + SelectedTracePlotLineModel* selectedRowsModel; + TracePlotLineDataSource* tracePlotLineDataSource; - QAbstractItemModel *depInfosView; + QAbstractItemModel* depInfosView; - PythonCaller &pythonCaller; + PythonCaller& pythonCaller; void setUpQueryEditor(QString path); bool savingChangesToDB; @@ -124,15 +127,14 @@ public Q_SLOTS: void tracefileChanged(); Q_SIGNALS: - void statusChanged(const QString &message); + void statusChanged(const QString& message); void colorGroupingChanged(ColorGrouping colorgrouping); private Q_SLOTS: - void on_latencyTreeView_doubleClicked(const QModelIndex &index); + void on_latencyTreeView_doubleClicked(const QModelIndex& index); void on_calculateDependencies_clicked(); void on_startLatencyAnalysis_clicked(); void on_startPowerAnalysis_clicked(); }; #endif // TRACEFILETAB_H - diff --git a/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp b/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp index 76b1b02c..8dbb787d 100644 --- a/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp +++ b/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp @@ -46,86 +46,87 @@ using namespace tlm; namespace DRAMSys { -MemSpecDDR5::MemSpecDDR5(const DRAMSys::Config::MemSpec &memSpec) - : MemSpec(memSpec, MemoryType::DDR5, - memSpec.memarchitecturespec.entries.at("nbrOfChannels"), - 1, - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks") - / memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks") - * memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBankGroups") - * memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfDevices")), - dimmRanksPerChannel(memSpec.memarchitecturespec.entries.at("nbrOfDIMMRanks")), - physicalRanksPerDimmRank(memSpec.memarchitecturespec.entries.at("nbrOfPhysicalRanks")), - physicalRanksPerChannel(physicalRanksPerDimmRank * dimmRanksPerChannel), - logicalRanksPerPhysicalRank(memSpec.memarchitecturespec.entries.at("nbrOfLogicalRanks")), - logicalRanksPerChannel(logicalRanksPerPhysicalRank * physicalRanksPerChannel), - cmdMode(memSpec.memarchitecturespec.entries.at("cmdMode")), - refMode(memSpec.memarchitecturespec.entries.at("refMode")), - RAAIMT(memSpec.memarchitecturespec.entries.at("RAAIMT")), - RAAMMT(memSpec.memarchitecturespec.entries.at("RAAMMT")), - RAADEC(memSpec.memarchitecturespec.entries.at("RAADEC")), - tRCD (tCK * memSpec.memtimingspec.entries.at("RCD")), - tPPD (tCK * memSpec.memtimingspec.entries.at("PPD")), - tRP (tCK * memSpec.memtimingspec.entries.at("RP")), - tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")), - tRC (tRAS + tRP), - tRL (tCK * memSpec.memtimingspec.entries.at("RL")), - tRTP (tCK * memSpec.memtimingspec.entries.at("RTP")), - tRPRE (tCK * memSpec.memtimingspec.entries.at("RPRE")), - tRPST (tCK * memSpec.memtimingspec.entries.at("RPST")), - tRDDQS (tCK * memSpec.memtimingspec.entries.at("RDDQS")), - tWL (tCK * memSpec.memtimingspec.entries.at("WL")), - tWPRE (tCK * memSpec.memtimingspec.entries.at("WPRE")), - tWPST (tCK * memSpec.memtimingspec.entries.at("WPST")), - tWR (tCK * memSpec.memtimingspec.entries.at("WR")), - tCCD_L_slr (tCK * memSpec.memtimingspec.entries.at("CCD_L_slr")), - tCCD_L_WR_slr (tCK * memSpec.memtimingspec.entries.at("CCD_L_WR_slr")), - tCCD_L_WR2_slr (tCK * memSpec.memtimingspec.entries.at("CCD_L_WR2_slr")), - tCCD_M_slr (tCK * memSpec.memtimingspec.entries.at("CCD_M_slr")), - tCCD_M_WR_slr (tCK * memSpec.memtimingspec.entries.at("CCD_M_WR_slr")), - tCCD_S_slr (tCK * memSpec.memtimingspec.entries.at("CCD_S_slr")), - tCCD_S_WR_slr (tCK * memSpec.memtimingspec.entries.at("CCD_S_WR_slr")), - tCCD_dlr (tCK * memSpec.memtimingspec.entries.at("CCD_dlr")), - tCCD_WR_dlr (tCK * memSpec.memtimingspec.entries.at("CCD_WR_dlr")), - tCCD_WR_dpr (tCK * memSpec.memtimingspec.entries.at("CCD_WR_dpr")), - tRRD_L_slr (tCK * memSpec.memtimingspec.entries.at("RRD_L_slr")), - tRRD_S_slr (tCK * memSpec.memtimingspec.entries.at("RRD_S_slr")), - tRRD_dlr (tCK * memSpec.memtimingspec.entries.at("RRD_dlr")), - tFAW_slr (tCK * memSpec.memtimingspec.entries.at("FAW_slr")), - tFAW_dlr (tCK * memSpec.memtimingspec.entries.at("FAW_dlr")), - tWTR_L (tCK * memSpec.memtimingspec.entries.at("WTR_L")), - tWTR_M (tCK * memSpec.memtimingspec.entries.at("WTR_M")), - tWTR_S (tCK * memSpec.memtimingspec.entries.at("WTR_S")), - tRFC_slr ((refMode == 1) ? tCK * memSpec.memtimingspec.entries.at("RFC1_slr") - : tCK * memSpec.memtimingspec.entries.at("RFC2_slr")), - tRFC_dlr ((refMode == 1) ? tCK * memSpec.memtimingspec.entries.at("RFC1_dlr") - : tCK * memSpec.memtimingspec.entries.at("RFC2_dlr")), - tRFC_dpr ((refMode == 1) ? tCK * memSpec.memtimingspec.entries.at("RFC1_dpr") - : tCK * memSpec.memtimingspec.entries.at("RFC2_dpr")), - tRFCsb_slr (tCK * memSpec.memtimingspec.entries.at("RFCsb_slr")), - tRFCsb_dlr (tCK * memSpec.memtimingspec.entries.at("RFCsb_dlr")), - tREFI ((refMode == 1) ? tCK * memSpec.memtimingspec.entries.at("REFI1") - : tCK * memSpec.memtimingspec.entries.at("REFI2")), - tREFIsb (tCK * memSpec.memtimingspec.entries.at("REFISB")), - tREFSBRD_slr (tCK * memSpec.memtimingspec.entries.at("REFSBRD_slr")), - tREFSBRD_dlr (tCK * memSpec.memtimingspec.entries.at("REFSBRD_dlr")), - tRTRS (tCK * memSpec.memtimingspec.entries.at("RTRS")), - tCPDED (tCK * memSpec.memtimingspec.entries.at("CPDED")), - tPD (tCK * memSpec.memtimingspec.entries.at("PD")), - tXP (tCK * memSpec.memtimingspec.entries.at("XP")), - tACTPDEN (tCK * memSpec.memtimingspec.entries.at("ACTPDEN")), - tPRPDEN (tCK * memSpec.memtimingspec.entries.at("PRPDEN")), - tREFPDEN (tCK * memSpec.memtimingspec.entries.at("REFPDEN")), - shortCmdOffset (cmdMode == 2 ? 1 * tCK : 0 * tCK), - longCmdOffset (cmdMode == 2 ? 3 * tCK : 1 * tCK), - tBURST16 (tCK * 8), - tBURST32 (tCK * 16) +MemSpecDDR5::MemSpecDDR5(const DRAMSys::Config::MemSpec& memSpec) : + MemSpec(memSpec, + MemoryType::DDR5, + memSpec.memarchitecturespec.entries.at("nbrOfChannels"), + 1, + memSpec.memarchitecturespec.entries.at("nbrOfRanks"), + memSpec.memarchitecturespec.entries.at("nbrOfBanks"), + memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"), + memSpec.memarchitecturespec.entries.at("nbrOfBanks") / + memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"), + memSpec.memarchitecturespec.entries.at("nbrOfBanks") * + memSpec.memarchitecturespec.entries.at("nbrOfRanks"), + memSpec.memarchitecturespec.entries.at("nbrOfBankGroups") * + memSpec.memarchitecturespec.entries.at("nbrOfRanks"), + memSpec.memarchitecturespec.entries.at("nbrOfDevices")), + dimmRanksPerChannel(memSpec.memarchitecturespec.entries.at("nbrOfDIMMRanks")), + physicalRanksPerDimmRank(memSpec.memarchitecturespec.entries.at("nbrOfPhysicalRanks")), + physicalRanksPerChannel(physicalRanksPerDimmRank * dimmRanksPerChannel), + logicalRanksPerPhysicalRank(memSpec.memarchitecturespec.entries.at("nbrOfLogicalRanks")), + logicalRanksPerChannel(logicalRanksPerPhysicalRank * physicalRanksPerChannel), + cmdMode(memSpec.memarchitecturespec.entries.at("cmdMode")), + refMode(memSpec.memarchitecturespec.entries.at("refMode")), + RAAIMT(memSpec.memarchitecturespec.entries.at("RAAIMT")), + RAAMMT(memSpec.memarchitecturespec.entries.at("RAAMMT")), + RAADEC(memSpec.memarchitecturespec.entries.at("RAADEC")), + tRCD(tCK * memSpec.memtimingspec.entries.at("RCD")), + tPPD(tCK * memSpec.memtimingspec.entries.at("PPD")), + tRP(tCK * memSpec.memtimingspec.entries.at("RP")), + tRAS(tCK * memSpec.memtimingspec.entries.at("RAS")), + tRC(tRAS + tRP), + tRL(tCK * memSpec.memtimingspec.entries.at("RL")), + tRTP(tCK * memSpec.memtimingspec.entries.at("RTP")), + tRPRE(tCK * memSpec.memtimingspec.entries.at("RPRE")), + tRPST(tCK * memSpec.memtimingspec.entries.at("RPST")), + tRDDQS(tCK * memSpec.memtimingspec.entries.at("RDDQS")), + tWL(tCK * memSpec.memtimingspec.entries.at("WL")), + tWPRE(tCK * memSpec.memtimingspec.entries.at("WPRE")), + tWPST(tCK * memSpec.memtimingspec.entries.at("WPST")), + tWR(tCK * memSpec.memtimingspec.entries.at("WR")), + tCCD_L_slr(tCK * memSpec.memtimingspec.entries.at("CCD_L_slr")), + tCCD_L_WR_slr(tCK * memSpec.memtimingspec.entries.at("CCD_L_WR_slr")), + tCCD_L_WR2_slr(tCK * memSpec.memtimingspec.entries.at("CCD_L_WR2_slr")), + tCCD_M_slr(tCK * memSpec.memtimingspec.entries.at("CCD_M_slr")), + tCCD_M_WR_slr(tCK * memSpec.memtimingspec.entries.at("CCD_M_WR_slr")), + tCCD_S_slr(tCK * memSpec.memtimingspec.entries.at("CCD_S_slr")), + tCCD_S_WR_slr(tCK * memSpec.memtimingspec.entries.at("CCD_S_WR_slr")), + tCCD_dlr(tCK * memSpec.memtimingspec.entries.at("CCD_dlr")), + tCCD_WR_dlr(tCK * memSpec.memtimingspec.entries.at("CCD_WR_dlr")), + tCCD_WR_dpr(tCK * memSpec.memtimingspec.entries.at("CCD_WR_dpr")), + tRRD_L_slr(tCK * memSpec.memtimingspec.entries.at("RRD_L_slr")), + tRRD_S_slr(tCK * memSpec.memtimingspec.entries.at("RRD_S_slr")), + tRRD_dlr(tCK * memSpec.memtimingspec.entries.at("RRD_dlr")), + tFAW_slr(tCK * memSpec.memtimingspec.entries.at("FAW_slr")), + tFAW_dlr(tCK * memSpec.memtimingspec.entries.at("FAW_dlr")), + tWTR_L(tCK * memSpec.memtimingspec.entries.at("WTR_L")), + tWTR_M(tCK * memSpec.memtimingspec.entries.at("WTR_M")), + tWTR_S(tCK * memSpec.memtimingspec.entries.at("WTR_S")), + tRFC_slr((refMode == 1) ? tCK * memSpec.memtimingspec.entries.at("RFC1_slr") + : tCK * memSpec.memtimingspec.entries.at("RFC2_slr")), + tRFC_dlr((refMode == 1) ? tCK * memSpec.memtimingspec.entries.at("RFC1_dlr") + : tCK * memSpec.memtimingspec.entries.at("RFC2_dlr")), + tRFC_dpr((refMode == 1) ? tCK * memSpec.memtimingspec.entries.at("RFC1_dpr") + : tCK * memSpec.memtimingspec.entries.at("RFC2_dpr")), + tRFCsb_slr(tCK * memSpec.memtimingspec.entries.at("RFCsb_slr")), + tRFCsb_dlr(tCK * memSpec.memtimingspec.entries.at("RFCsb_dlr")), + tREFI((refMode == 1) ? tCK * memSpec.memtimingspec.entries.at("REFI1") + : tCK * memSpec.memtimingspec.entries.at("REFI2")), + tREFIsb(tCK * memSpec.memtimingspec.entries.at("REFISB")), + tREFSBRD_slr(tCK * memSpec.memtimingspec.entries.at("REFSBRD_slr")), + tREFSBRD_dlr(tCK * memSpec.memtimingspec.entries.at("REFSBRD_dlr")), + tRTRS(tCK * memSpec.memtimingspec.entries.at("RTRS")), + tCPDED(tCK * memSpec.memtimingspec.entries.at("CPDED")), + tPD(tCK * memSpec.memtimingspec.entries.at("PD")), + tXP(tCK * memSpec.memtimingspec.entries.at("XP")), + tACTPDEN(tCK * memSpec.memtimingspec.entries.at("ACTPDEN")), + tPRPDEN(tCK * memSpec.memtimingspec.entries.at("PRPDEN")), + tREFPDEN(tCK * memSpec.memtimingspec.entries.at("REFPDEN")), + shortCmdOffset(cmdMode == 2 ? 1 * tCK : 0 * tCK), + longCmdOffset(cmdMode == 2 ? 3 * tCK : 1 * tCK), + tBURST16(tCK * 8), + tBURST32(tCK * 16) { if (cmdMode == 1) { @@ -164,31 +165,33 @@ MemSpecDDR5::MemSpecDDR5(const DRAMSys::Config::MemSpec &memSpec) SC_REPORT_FATAL("MemSpecDDR5", "Invalid command mode!"); if (!(refMode == 1 || refMode == 2)) - SC_REPORT_FATAL("MemSpecDDR5", "Invalid refresh mode! " - "Set 1 for normal or 2 for fine granularity refresh mode."); + SC_REPORT_FATAL("MemSpecDDR5", + "Invalid refresh mode! " + "Set 1 for normal or 2 for fine granularity refresh mode."); - uint64_t deviceSizeBits = static_cast(banksPerRank) * rowsPerBank - * columnsPerRow * bitWidth * logicalRanksPerChannel; + uint64_t deviceSizeBits = static_cast(banksPerRank) * rowsPerBank * columnsPerRow * + bitWidth * logicalRanksPerChannel; uint64_t deviceSizeBytes = deviceSizeBits / 8; - memorySizeBytes = deviceSizeBytes * devicesPerRank - * ranksPerChannel / logicalRanksPerChannel * numberOfChannels; + memorySizeBytes = deviceSizeBytes * devicesPerRank * ranksPerChannel / logicalRanksPerChannel * + numberOfChannels; std::cout << headline << std::endl; std::cout << "Memory Configuration: " << std::endl << std::endl; - std::cout << " Memory type: " << "DDR5" << std::endl; - std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl; - std::cout << " Channels: " << numberOfChannels << std::endl; + std::cout << " Memory type: " + << "DDR5" << std::endl; + std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl; + std::cout << " Channels: " << numberOfChannels << std::endl; std::cout << " DIMMs per channel: " << dimmRanksPerChannel << std::endl; std::cout << " Physical ranks per DIMM: " << physicalRanksPerDimmRank << std::endl; std::cout << " Logical ranks per device: " << logicalRanksPerPhysicalRank << std::endl; std::cout << " Total ranks: " << ranksPerChannel << std::endl; - std::cout << " Bank groups per rank: " << groupsPerRank << std::endl; - std::cout << " Banks per rank: " << banksPerRank << std::endl; + std::cout << " Bank groups per rank: " << groupsPerRank << std::endl; + std::cout << " Banks per rank: " << banksPerRank << std::endl; std::cout << " Rows per bank: " << rowsPerBank << std::endl; std::cout << " Columns per row: " << columnsPerRow << std::endl; - std::cout << " Device width in bits: " << bitWidth << std::endl; - std::cout << " Device size in bits: " << deviceSizeBits << std::endl; - std::cout << " Device size in bytes: " << deviceSizeBytes << std::endl; + std::cout << " Device width in bits: " << bitWidth << std::endl; + std::cout << " Device size in bits: " << deviceSizeBits << std::endl; + std::cout << " Device size in bytes: " << deviceSizeBytes << std::endl; std::cout << " Devices per rank: " << devicesPerRank << std::endl; std::cout << std::endl; } @@ -219,7 +222,7 @@ unsigned MemSpecDDR5::getRAAMMT() const } // Returns the execution time for commands that have a fixed execution time -sc_time MemSpecDDR5::getExecutionTime(Command command, const tlm_generic_payload &payload) const +sc_time MemSpecDDR5::getExecutionTime(Command command, const tlm_generic_payload& payload) const { if (command == Command::PREPB || command == Command::PREAB || command == Command::PRESB) return tRP + shortCmdOffset; @@ -260,7 +263,8 @@ sc_time MemSpecDDR5::getExecutionTime(Command command, const tlm_generic_payload } } -TimeInterval MemSpecDDR5::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &payload) const +TimeInterval MemSpecDDR5::getIntervalOnDataStrobe(Command command, + const tlm_generic_payload& payload) const { if (command == Command::RD || command == Command::RDA) { @@ -269,7 +273,8 @@ TimeInterval MemSpecDDR5::getIntervalOnDataStrobe(Command command, const tlm_gen else return {tRL + longCmdOffset, tRL + tBURST16 + longCmdOffset}; } - else if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA) + else if (command == Command::WR || command == Command::WRA || command == Command::MWR || + command == Command::MWRA) { if (ControllerExtension::getBurstLength(payload) == 32) return {tWL + longCmdOffset, tWL + tBURST32 + longCmdOffset}; diff --git a/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.h b/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.h index d696d3d7..438beca6 100644 --- a/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.h +++ b/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.h @@ -37,8 +37,8 @@ #ifndef MEMSPECDDR5_H #define MEMSPECDDR5_H -#include #include +#include namespace DRAMSys { @@ -46,7 +46,7 @@ namespace DRAMSys class MemSpecDDR5 final : public MemSpec { public: - explicit MemSpecDDR5(const DRAMSys::Config::MemSpec &memSpec); + explicit MemSpecDDR5(const DRAMSys::Config::MemSpec& memSpec); const unsigned dimmRanksPerChannel; const unsigned physicalRanksPerDimmRank; @@ -126,8 +126,11 @@ public: [[nodiscard]] unsigned getRAAIMT() const override; [[nodiscard]] unsigned getRAAMMT() const override; - [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] sc_core::sc_time + getExecutionTime(Command command, const tlm::tlm_generic_payload& payload) const override; + [[nodiscard]] TimeInterval + getIntervalOnDataStrobe(Command command, + const tlm::tlm_generic_payload& payload) const override; [[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override; }; diff --git a/extensions/standards/DDR5/DRAMSys/simulation/dram/DramDDR5.cpp b/extensions/standards/DDR5/DRAMSys/simulation/dram/DramDDR5.cpp index 5ea79d0e..3be855a2 100644 --- a/extensions/standards/DDR5/DRAMSys/simulation/dram/DramDDR5.cpp +++ b/extensions/standards/DDR5/DRAMSys/simulation/dram/DramDDR5.cpp @@ -40,8 +40,7 @@ using namespace sc_core; namespace DRAMSys { -DramDDR5::DramDDR5(const sc_module_name& name, const Configuration& config) - : Dram(name, config) +DramDDR5::DramDDR5(const sc_module_name& name, const Configuration& config) : Dram(name, config) { #ifdef DRAMPOWER if (powerAnalysis) diff --git a/extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.cpp b/extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.cpp index b251ee72..21237812 100644 --- a/extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.cpp +++ b/extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.cpp @@ -36,8 +36,8 @@ #include -#include #include "MemSpecHBM3.h" +#include using namespace sc_core; using namespace tlm; @@ -45,53 +45,54 @@ using namespace tlm; namespace DRAMSys { -MemSpecHBM3::MemSpecHBM3(const DRAMSys::Config::MemSpec &memSpec) - : MemSpec(memSpec, MemoryType::HBM3, - memSpec.memarchitecturespec.entries.at("nbrOfChannels"), - memSpec.memarchitecturespec.entries.at("nbrOfPseudoChannels"), - memSpec.memarchitecturespec.entries.at("nbrOfPseudoChannels"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks") - / memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks") - * memSpec.memarchitecturespec.entries.at("nbrOfPseudoChannels"), - memSpec.memarchitecturespec.entries.at("nbrOfBankGroups") - * memSpec.memarchitecturespec.entries.at("nbrOfPseudoChannels"), - memSpec.memarchitecturespec.entries.at("nbrOfDevices")), - RAAIMT(memSpec.memarchitecturespec.entries.at("RAAIMT")), - RAAMMT(memSpec.memarchitecturespec.entries.at("RAAMMT")), - RAADEC(memSpec.memarchitecturespec.entries.at("RAADEC")), - tDQSCK (tCK * memSpec.memtimingspec.entries.at("DQSCK")), - tRC (tCK * memSpec.memtimingspec.entries.at("RC")), - tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")), - tRCDRD (tCK * memSpec.memtimingspec.entries.at("RCDRD")), - tRCDWR (tCK * memSpec.memtimingspec.entries.at("RCDWR")), - tRRDL (tCK * memSpec.memtimingspec.entries.at("RRDL")), - tRRDS (tCK * memSpec.memtimingspec.entries.at("RRDS")), - tFAW (tCK * memSpec.memtimingspec.entries.at("FAW")), - tRTP (tCK * memSpec.memtimingspec.entries.at("RTP")), - tRP (tCK * memSpec.memtimingspec.entries.at("RP")), - tRL (tCK * memSpec.memtimingspec.entries.at("RL")), - tWL (tCK * memSpec.memtimingspec.entries.at("WL")), - tPL (tCK * memSpec.memtimingspec.entries.at("PL")), - tWR (tCK * memSpec.memtimingspec.entries.at("WR")), - tCCDL (tCK * memSpec.memtimingspec.entries.at("CCDL")), - tCCDS (tCK * memSpec.memtimingspec.entries.at("CCDS")), - tWTRL (tCK * memSpec.memtimingspec.entries.at("WTRL")), - tWTRS (tCK * memSpec.memtimingspec.entries.at("WTRS")), - tRTW (tCK * memSpec.memtimingspec.entries.at("RTW")), - tXP (tCK * memSpec.memtimingspec.entries.at("XP")), - tCKE (tCK * memSpec.memtimingspec.entries.at("CKE")), - tPD (tCKE), - tCKESR (tCKE + tCK), - tXS (tCK * memSpec.memtimingspec.entries.at("XS")), - tRFC (tCK * memSpec.memtimingspec.entries.at("RFC")), - tRFCPB (tCK * memSpec.memtimingspec.entries.at("RFCPB")), - tRREFD (tCK * memSpec.memtimingspec.entries.at("RREFD")), - tREFI (tCK * memSpec.memtimingspec.entries.at("REFI")), - tREFIPB (tCK * memSpec.memtimingspec.entries.at("REFIPB")), - tPPD (tCK * memSpec.memtimingspec.entries.at("PPD")) +MemSpecHBM3::MemSpecHBM3(const DRAMSys::Config::MemSpec& memSpec) : + MemSpec(memSpec, + MemoryType::HBM3, + memSpec.memarchitecturespec.entries.at("nbrOfChannels"), + memSpec.memarchitecturespec.entries.at("nbrOfPseudoChannels"), + memSpec.memarchitecturespec.entries.at("nbrOfPseudoChannels"), + memSpec.memarchitecturespec.entries.at("nbrOfBanks"), + memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"), + memSpec.memarchitecturespec.entries.at("nbrOfBanks") / + memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"), + memSpec.memarchitecturespec.entries.at("nbrOfBanks") * + memSpec.memarchitecturespec.entries.at("nbrOfPseudoChannels"), + memSpec.memarchitecturespec.entries.at("nbrOfBankGroups") * + memSpec.memarchitecturespec.entries.at("nbrOfPseudoChannels"), + memSpec.memarchitecturespec.entries.at("nbrOfDevices")), + RAAIMT(memSpec.memarchitecturespec.entries.at("RAAIMT")), + RAAMMT(memSpec.memarchitecturespec.entries.at("RAAMMT")), + RAADEC(memSpec.memarchitecturespec.entries.at("RAADEC")), + tDQSCK(tCK * memSpec.memtimingspec.entries.at("DQSCK")), + tRC(tCK * memSpec.memtimingspec.entries.at("RC")), + tRAS(tCK * memSpec.memtimingspec.entries.at("RAS")), + tRCDRD(tCK * memSpec.memtimingspec.entries.at("RCDRD")), + tRCDWR(tCK * memSpec.memtimingspec.entries.at("RCDWR")), + tRRDL(tCK * memSpec.memtimingspec.entries.at("RRDL")), + tRRDS(tCK * memSpec.memtimingspec.entries.at("RRDS")), + tFAW(tCK * memSpec.memtimingspec.entries.at("FAW")), + tRTP(tCK * memSpec.memtimingspec.entries.at("RTP")), + tRP(tCK * memSpec.memtimingspec.entries.at("RP")), + tRL(tCK * memSpec.memtimingspec.entries.at("RL")), + tWL(tCK * memSpec.memtimingspec.entries.at("WL")), + tPL(tCK * memSpec.memtimingspec.entries.at("PL")), + tWR(tCK * memSpec.memtimingspec.entries.at("WR")), + tCCDL(tCK * memSpec.memtimingspec.entries.at("CCDL")), + tCCDS(tCK * memSpec.memtimingspec.entries.at("CCDS")), + tWTRL(tCK * memSpec.memtimingspec.entries.at("WTRL")), + tWTRS(tCK * memSpec.memtimingspec.entries.at("WTRS")), + tRTW(tCK * memSpec.memtimingspec.entries.at("RTW")), + tXP(tCK * memSpec.memtimingspec.entries.at("XP")), + tCKE(tCK * memSpec.memtimingspec.entries.at("CKE")), + tPD(tCKE), + tCKESR(tCKE + tCK), + tXS(tCK * memSpec.memtimingspec.entries.at("XS")), + tRFC(tCK * memSpec.memtimingspec.entries.at("RFC")), + tRFCPB(tCK * memSpec.memtimingspec.entries.at("RFCPB")), + tRREFD(tCK * memSpec.memtimingspec.entries.at("RREFD")), + tREFI(tCK * memSpec.memtimingspec.entries.at("REFI")), + tREFIPB(tCK * memSpec.memtimingspec.entries.at("REFIPB")), + tPPD(tCK * memSpec.memtimingspec.entries.at("PPD")) { commandLengthInCycles[Command::ACT] = 1.5; commandLengthInCycles[Command::PREPB] = 0.5; @@ -103,23 +104,25 @@ MemSpecHBM3::MemSpecHBM3(const DRAMSys::Config::MemSpec &memSpec) commandLengthInCycles[Command::PDXA] = 0.5; commandLengthInCycles[Command::SREFEX] = 0.5; - uint64_t deviceSizeBits = static_cast(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth; + uint64_t deviceSizeBits = + static_cast(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth; uint64_t deviceSizeBytes = deviceSizeBits / 8; memorySizeBytes = deviceSizeBytes * ranksPerChannel * numberOfChannels; std::cout << headline << std::endl; std::cout << "Memory Configuration:" << std::endl << std::endl; - std::cout << " Memory type: " << "HBM3" << std::endl; - std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl; + std::cout << " Memory type: " + << "HBM3" << std::endl; + std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl; std::cout << " Channels: " << numberOfChannels << std::endl; - std::cout << " Pseudo channels per channel: " << ranksPerChannel << std::endl; - std::cout << " Bank groups per pseudo channel: " << groupsPerRank << std::endl; - std::cout << " Banks per pseudo channel: " << banksPerRank << std::endl; - std::cout << " Rows per bank: " << rowsPerBank << std::endl; - std::cout << " Columns per row: " << columnsPerRow << std::endl; - std::cout << " Pseudo channel width in bits: " << bitWidth << std::endl; - std::cout << " Pseudo channel size in bits: " << deviceSizeBits << std::endl; - std::cout << " Pseudo channel size in bytes: " << deviceSizeBytes << std::endl; + std::cout << " Pseudo channels per channel: " << ranksPerChannel << std::endl; + std::cout << " Bank groups per pseudo channel: " << groupsPerRank << std::endl; + std::cout << " Banks per pseudo channel: " << banksPerRank << std::endl; + std::cout << " Rows per bank: " << rowsPerBank << std::endl; + std::cout << " Columns per row: " << columnsPerRow << std::endl; + std::cout << " Pseudo channel width in bits: " << bitWidth << std::endl; + std::cout << " Pseudo channel size in bits: " << deviceSizeBits << std::endl; + std::cout << " Pseudo channel size in bytes: " << deviceSizeBytes << std::endl; std::cout << std::endl; } @@ -138,7 +141,7 @@ bool MemSpecHBM3::hasRasAndCasBus() const return true; } -sc_time MemSpecHBM3::getExecutionTime(Command command, const tlm_generic_payload &payload) const +sc_time MemSpecHBM3::getExecutionTime(Command command, const tlm_generic_payload& payload) const { if (command == Command::PREPB || command == Command::PREAB) return tRP; @@ -169,7 +172,7 @@ sc_time MemSpecHBM3::getExecutionTime(Command command, const tlm_generic_payload } } -TimeInterval MemSpecHBM3::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const +TimeInterval MemSpecHBM3::getIntervalOnDataStrobe(Command command, const tlm_generic_payload&) const { if (command == Command::RD || command == Command::RDA) return {tRL + tDQSCK, tRL + tDQSCK + burstDuration}; diff --git a/extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.h b/extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.h index c5c65042..9c35964a 100644 --- a/extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.h +++ b/extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.h @@ -37,8 +37,8 @@ #ifndef MemSpecHBM3_H #define MemSpecHBM3_H -#include #include +#include namespace DRAMSys { @@ -54,7 +54,7 @@ public: // Memspec Variables: const sc_core::sc_time tDQSCK; -// sc_time tDQSQ; // TODO: check actual value of this parameter + // sc_time tDQSQ; // TODO: check actual value of this parameter const sc_core::sc_time tRC; const sc_core::sc_time tRAS; const sc_core::sc_time tRCDRD; @@ -70,13 +70,13 @@ public: const sc_core::sc_time tWR; const sc_core::sc_time tCCDL; const sc_core::sc_time tCCDS; -// sc_time tCCDR; // TODO: consecutive reads to different stack IDs + // sc_time tCCDR; // TODO: consecutive reads to different stack IDs const sc_core::sc_time tWTRL; const sc_core::sc_time tWTRS; const sc_core::sc_time tRTW; const sc_core::sc_time tXP; const sc_core::sc_time tCKE; - const sc_core::sc_time tPD; // = tCKE; + const sc_core::sc_time tPD; // = tCKE; const sc_core::sc_time tCKESR; // = tCKE + tCK; const sc_core::sc_time tXS; const sc_core::sc_time tRFC; @@ -98,8 +98,11 @@ public: [[nodiscard]] bool hasRasAndCasBus() const override; - [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] sc_core::sc_time + getExecutionTime(Command command, const tlm::tlm_generic_payload& payload) const override; + [[nodiscard]] TimeInterval + getIntervalOnDataStrobe(Command command, + const tlm::tlm_generic_payload& payload) const override; }; } // namespace DRAMSys diff --git a/extensions/standards/HBM3/DRAMSys/simulation/dram/DramHBM3.cpp b/extensions/standards/HBM3/DRAMSys/simulation/dram/DramHBM3.cpp index 0cf84011..c3f0e6a1 100644 --- a/extensions/standards/HBM3/DRAMSys/simulation/dram/DramHBM3.cpp +++ b/extensions/standards/HBM3/DRAMSys/simulation/dram/DramHBM3.cpp @@ -43,8 +43,7 @@ using namespace sc_core; namespace DRAMSys { -DramHBM3::DramHBM3(const sc_module_name& name, const Configuration& config) - : Dram(name, config) +DramHBM3::DramHBM3(const sc_module_name& name, const Configuration& config) : Dram(name, config) { #ifdef DRAMPOWER if (powerAnalysis) diff --git a/extensions/standards/HBM3/DRAMSys/simulation/dram/DramHBM3.h b/extensions/standards/HBM3/DRAMSys/simulation/dram/DramHBM3.h index 66a7f243..a1e90908 100644 --- a/extensions/standards/HBM3/DRAMSys/simulation/dram/DramHBM3.h +++ b/extensions/standards/HBM3/DRAMSys/simulation/dram/DramHBM3.h @@ -46,7 +46,7 @@ namespace DRAMSys class DramHBM3 : public Dram { public: - DramHBM3(const sc_core::sc_module_name &name, const Configuration& config); + DramHBM3(const sc_core::sc_module_name& name, const Configuration& config); SC_HAS_PROCESS(DramHBM3); }; diff --git a/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp b/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp index 67ff9f18..6506ab5e 100644 --- a/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp +++ b/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp @@ -45,88 +45,92 @@ using namespace tlm; namespace DRAMSys { -MemSpecLPDDR5::MemSpecLPDDR5(const DRAMSys::Config::MemSpec &memSpec) - : MemSpec(memSpec, MemoryType::LPDDR5, - memSpec.memarchitecturespec.entries.at("nbrOfChannels"), - 1, - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks") - / memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks") - * memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBankGroups") - * memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfDevices")), - tREFI (tCK * memSpec.memtimingspec.entries.at("REFI")), - tREFIpb (tCK * memSpec.memtimingspec.entries.at("REFIpb")), - tRFCab (tCK * memSpec.memtimingspec.entries.at("RFCab")), - tRFCpb (tCK * memSpec.memtimingspec.entries.at("RFCpb")), - tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")), - tRPab (tCK * memSpec.memtimingspec.entries.at("RPab")), - tRPpb (tCK * memSpec.memtimingspec.entries.at("RPpb")), - tRCpb (tCK * memSpec.memtimingspec.entries.at("RCpb")), - tRCab (tCK * memSpec.memtimingspec.entries.at("RCab")), - tPPD (tCK * memSpec.memtimingspec.entries.at("PPD")), - tRCD_L (tCK * memSpec.memtimingspec.entries.at("RCD_L")), - tRCD_S (tCK * memSpec.memtimingspec.entries.at("RCD_S")), - tFAW (tCK * memSpec.memtimingspec.entries.at("FAW")), - tRRD (tCK * memSpec.memtimingspec.entries.at("RRD")), - tRL (tCK * memSpec.memtimingspec.entries.at("RL")), - //tCCD (tCK * parseUint(memspec["memtimingspec"], "CCD")), - tRBTP (tCK * memSpec.memtimingspec.entries.at("RBTP")), - //tRPST (tCK * parseUint(memspec["memtimingspec"], "RPST")), - //tDQSCK (tCK * parseUint(memspec["memtimingspec"], "DQSCK")), - tWL (tCK * memSpec.memtimingspec.entries.at("WL")), - tWR (tCK * memSpec.memtimingspec.entries.at("WR")), - //tDQSS (tCK * parseUint(memspec["memtimingspec"], "DQSS")), - //tDQS2DQ (tCK * parseUint(memspec["memtimingspec"], "DQS2DQ")), - tRTRS (tCK * memSpec.memtimingspec.entries.at("RTRS")), - //tWPRE (tCK * parseUint(memspec["memtimingspec"], "WPRE")), - //tWTR (tCK * parseUint(memspec["memtimingspec"], "WTR")), - //tXP (tCK * parseUint(memspec["memtimingspec"] "XP")), - //tSR (tCK * parseUint(memspec["memtimingspec"], "SR")), - //tXSR (tCK * parseUint(memspec["memtimingspec"], "XSR")), - //tESCKE (tCK * parseUint(memspec["memtimingspec"], "ESCKE")), - //tCKE (tCK * parseUint(memspec["memtimingspec"], "CKE")), - //tCMDCKE (tCK * parseUint(memspec["memtimingspec"], "CMDCKE")), - BL_n_min_16(tCK * memSpec.memtimingspec.entries.at("BL_n_min_16")), - BL_n_max_16(tCK * memSpec.memtimingspec.entries.at("BL_n_max_16")), - BL_n_L_16(tCK * memSpec.memtimingspec.entries.at("BL_n_L_16")), - BL_n_S_16(tCK * memSpec.memtimingspec.entries.at("BL_n_S_16")), - BL_n_min_32(tCK * memSpec.memtimingspec.entries.at("BL_n_min_32")), - BL_n_max_32(tCK * memSpec.memtimingspec.entries.at("BL_n_max_32")), - BL_n_L_32(tCK * memSpec.memtimingspec.entries.at("BL_n_L_32")), - BL_n_S_32(tCK * memSpec.memtimingspec.entries.at("BL_n_S_32")), - tWTR_L (tCK * memSpec.memtimingspec.entries.at("WTR_L")), - tWTR_S (tCK * memSpec.memtimingspec.entries.at("WTR_S")), - tWCK2DQO(tCK * memSpec.memtimingspec.entries.at("WCK2DQO")), - tpbR2act(tCK * memSpec.memtimingspec.entries.at("pbR2act")), - tpbR2pbR(tCK * memSpec.memtimingspec.entries.at("pbR2pbR")), - tBURST16(tCK * 16 / dataRate), - tBURST32(tCK * 32 / dataRate), - bankMode(groupsPerRank != 1 ? BankMode::MBG : (banksPerRank == 16 ? BankMode::M16B : BankMode::M8B)), - per2BankOffset(memSpec.memarchitecturespec.entries.at("per2BankOffset")) +MemSpecLPDDR5::MemSpecLPDDR5(const DRAMSys::Config::MemSpec& memSpec) : + MemSpec(memSpec, + MemoryType::LPDDR5, + memSpec.memarchitecturespec.entries.at("nbrOfChannels"), + 1, + memSpec.memarchitecturespec.entries.at("nbrOfRanks"), + memSpec.memarchitecturespec.entries.at("nbrOfBanks"), + memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"), + memSpec.memarchitecturespec.entries.at("nbrOfBanks") / + memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"), + memSpec.memarchitecturespec.entries.at("nbrOfBanks") * + memSpec.memarchitecturespec.entries.at("nbrOfRanks"), + memSpec.memarchitecturespec.entries.at("nbrOfBankGroups") * + memSpec.memarchitecturespec.entries.at("nbrOfRanks"), + memSpec.memarchitecturespec.entries.at("nbrOfDevices")), + tREFI(tCK * memSpec.memtimingspec.entries.at("REFI")), + tREFIpb(tCK * memSpec.memtimingspec.entries.at("REFIpb")), + tRFCab(tCK * memSpec.memtimingspec.entries.at("RFCab")), + tRFCpb(tCK * memSpec.memtimingspec.entries.at("RFCpb")), + tRAS(tCK * memSpec.memtimingspec.entries.at("RAS")), + tRPab(tCK * memSpec.memtimingspec.entries.at("RPab")), + tRPpb(tCK * memSpec.memtimingspec.entries.at("RPpb")), + tRCpb(tCK * memSpec.memtimingspec.entries.at("RCpb")), + tRCab(tCK * memSpec.memtimingspec.entries.at("RCab")), + tPPD(tCK * memSpec.memtimingspec.entries.at("PPD")), + tRCD_L(tCK * memSpec.memtimingspec.entries.at("RCD_L")), + tRCD_S(tCK * memSpec.memtimingspec.entries.at("RCD_S")), + tFAW(tCK * memSpec.memtimingspec.entries.at("FAW")), + tRRD(tCK * memSpec.memtimingspec.entries.at("RRD")), + tRL(tCK * memSpec.memtimingspec.entries.at("RL")), + // tCCD (tCK * parseUint(memspec["memtimingspec"], "CCD")), + tRBTP(tCK * memSpec.memtimingspec.entries.at("RBTP")), + // tRPST (tCK * parseUint(memspec["memtimingspec"], "RPST")), + // tDQSCK (tCK * parseUint(memspec["memtimingspec"], "DQSCK")), + tWL(tCK * memSpec.memtimingspec.entries.at("WL")), + tWR(tCK * memSpec.memtimingspec.entries.at("WR")), + // tDQSS (tCK * parseUint(memspec["memtimingspec"], "DQSS")), + // tDQS2DQ (tCK * parseUint(memspec["memtimingspec"], "DQS2DQ")), + tRTRS(tCK * memSpec.memtimingspec.entries.at("RTRS")), + // tWPRE (tCK * parseUint(memspec["memtimingspec"], "WPRE")), + // tWTR (tCK * parseUint(memspec["memtimingspec"], "WTR")), + // tXP (tCK * parseUint(memspec["memtimingspec"] "XP")), + // tSR (tCK * parseUint(memspec["memtimingspec"], "SR")), + // tXSR (tCK * parseUint(memspec["memtimingspec"], "XSR")), + // tESCKE (tCK * parseUint(memspec["memtimingspec"], "ESCKE")), + // tCKE (tCK * parseUint(memspec["memtimingspec"], "CKE")), + // tCMDCKE (tCK * parseUint(memspec["memtimingspec"], "CMDCKE")), + BL_n_min_16(tCK * memSpec.memtimingspec.entries.at("BL_n_min_16")), + BL_n_max_16(tCK * memSpec.memtimingspec.entries.at("BL_n_max_16")), + BL_n_L_16(tCK * memSpec.memtimingspec.entries.at("BL_n_L_16")), + BL_n_S_16(tCK * memSpec.memtimingspec.entries.at("BL_n_S_16")), + BL_n_min_32(tCK * memSpec.memtimingspec.entries.at("BL_n_min_32")), + BL_n_max_32(tCK * memSpec.memtimingspec.entries.at("BL_n_max_32")), + BL_n_L_32(tCK * memSpec.memtimingspec.entries.at("BL_n_L_32")), + BL_n_S_32(tCK * memSpec.memtimingspec.entries.at("BL_n_S_32")), + tWTR_L(tCK * memSpec.memtimingspec.entries.at("WTR_L")), + tWTR_S(tCK * memSpec.memtimingspec.entries.at("WTR_S")), + tWCK2DQO(tCK * memSpec.memtimingspec.entries.at("WCK2DQO")), + tpbR2act(tCK * memSpec.memtimingspec.entries.at("pbR2act")), + tpbR2pbR(tCK * memSpec.memtimingspec.entries.at("pbR2pbR")), + tBURST16(tCK * 16 / dataRate), + tBURST32(tCK * 32 / dataRate), + bankMode(groupsPerRank != 1 ? BankMode::MBG + : (banksPerRank == 16 ? BankMode::M16B : BankMode::M8B)), + per2BankOffset(memSpec.memarchitecturespec.entries.at("per2BankOffset")) { commandLengthInCycles[Command::ACT] = 2; - uint64_t deviceSizeBits = static_cast(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth; + uint64_t deviceSizeBits = + static_cast(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth; uint64_t deviceSizeBytes = deviceSizeBits / 8; memorySizeBytes = deviceSizeBytes * ranksPerChannel * numberOfChannels; std::cout << headline << std::endl; std::cout << "Memory Configuration:" << std::endl << std::endl; - std::cout << " Memory type: " << "LPDDR5" << std::endl; - std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl; - std::cout << " Channels: " << numberOfChannels << std::endl; + std::cout << " Memory type: " + << "LPDDR5" << std::endl; + std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl; + std::cout << " Channels: " << numberOfChannels << std::endl; std::cout << " Ranks per channel: " << ranksPerChannel << std::endl; - std::cout << " Banks per rank: " << banksPerRank << std::endl; + std::cout << " Banks per rank: " << banksPerRank << std::endl; std::cout << " Rows per bank: " << rowsPerBank << std::endl; std::cout << " Columns per row: " << columnsPerRow << std::endl; - std::cout << " Device width in bits: " << bitWidth << std::endl; - std::cout << " Device size in bits: " << deviceSizeBits << std::endl; - std::cout << " Device size in bytes: " << deviceSizeBytes << std::endl; + std::cout << " Device width in bits: " << bitWidth << std::endl; + std::cout << " Device size in bits: " << deviceSizeBits << std::endl; + std::cout << " Device size in bytes: " << deviceSizeBytes << std::endl; std::cout << " Devices per rank: " << devicesPerRank << std::endl; std::cout << std::endl; } @@ -215,7 +219,8 @@ sc_time MemSpecLPDDR5::getExecutionTime(Command command, const tlm_generic_paylo } } -TimeInterval MemSpecLPDDR5::getIntervalOnDataStrobe(Command command, const tlm_generic_payload& trans) const +TimeInterval MemSpecLPDDR5::getIntervalOnDataStrobe(Command command, + const tlm_generic_payload& trans) const { if (command == Command::RD || command == Command::RDA) { @@ -229,7 +234,8 @@ TimeInterval MemSpecLPDDR5::getIntervalOnDataStrobe(Command command, const tlm_g else return {tRL, tRL + tBURST16}; } - else if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA) + else if (command == Command::WR || command == Command::WRA || command == Command::MWR || + command == Command::MWRA) { if (ControllerExtension::getBurstLength(trans) == 32) { diff --git a/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.h b/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.h index a66278d1..e0503b9d 100644 --- a/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.h +++ b/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.h @@ -36,19 +36,18 @@ #ifndef MEMSPECLPDDR5_H #define MEMSPECLPDDR5_H -#include #include +#include #include namespace DRAMSys { - class MemSpecLPDDR5 final : public MemSpec { public: - explicit MemSpecLPDDR5(const DRAMSys::Config::MemSpec &memSpec); + explicit MemSpecLPDDR5(const DRAMSys::Config::MemSpec& memSpec); // Memspec Variables: const sc_core::sc_time tREFI; @@ -65,25 +64,25 @@ public: const sc_core::sc_time tRCD_S; const sc_core::sc_time tFAW; const sc_core::sc_time tRRD; - //const sc_core::sc_time tCCD; + // const sc_core::sc_time tCCD; const sc_core::sc_time tRL; const sc_core::sc_time tRPRE; const sc_core::sc_time tRPST; - //const sc_core::sc_time tDQSCK; + // const sc_core::sc_time tDQSCK; const sc_core::sc_time tRBTP; const sc_core::sc_time tWL; - //const sc_core::sc_time tDQSS; - //const sc_core::sc_time tDQS2DQ; + // const sc_core::sc_time tDQSS; + // const sc_core::sc_time tDQS2DQ; const sc_core::sc_time tWR; const sc_core::sc_time tWPRE; const sc_core::sc_time tWPST; - //const sc_core::sc_time tWTR; - //const sc_core::sc_time tXP; - //const sc_core::sc_time tSR; - //const sc_core::sc_time tXSR; - //const sc_core::sc_time tESCKE; - //const sc_core::sc_time tCKE; - //const sc_core::sc_time tCMDCKE; + // const sc_core::sc_time tWTR; + // const sc_core::sc_time tXP; + // const sc_core::sc_time tSR; + // const sc_core::sc_time tXSR; + // const sc_core::sc_time tESCKE; + // const sc_core::sc_time tCKE; + // const sc_core::sc_time tCMDCKE; const sc_core::sc_time tRTRS; const sc_core::sc_time BL_n_min_16; @@ -106,7 +105,7 @@ public: const sc_core::sc_time tBURST16; const sc_core::sc_time tBURST32; - const enum class BankMode {M16B, MBG, M8B} bankMode; + const enum class BankMode { M16B, MBG, M8B } bankMode; // Currents and Voltages: // TODO: to be completed @@ -117,8 +116,11 @@ public: [[nodiscard]] unsigned getPer2BankOffset() const override; - [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] sc_core::sc_time + getExecutionTime(Command command, const tlm::tlm_generic_payload& payload) const override; + [[nodiscard]] TimeInterval + getIntervalOnDataStrobe(Command command, + const tlm::tlm_generic_payload& payload) const override; [[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override; diff --git a/extensions/standards/LPDDR5/DRAMSys/simulation/dram/DramLPDDR5.cpp b/extensions/standards/LPDDR5/DRAMSys/simulation/dram/DramLPDDR5.cpp index df749c85..4aed1610 100644 --- a/extensions/standards/LPDDR5/DRAMSys/simulation/dram/DramLPDDR5.cpp +++ b/extensions/standards/LPDDR5/DRAMSys/simulation/dram/DramLPDDR5.cpp @@ -43,8 +43,7 @@ using namespace sc_core; namespace DRAMSys { -DramLPDDR5::DramLPDDR5(const sc_module_name& name, const Configuration& config) - : Dram(name, config) +DramLPDDR5::DramLPDDR5(const sc_module_name& name, const Configuration& config) : Dram(name, config) { #ifdef DRAMPOWER if (powerAnalysis) diff --git a/src/configuration/DRAMSys/config/AddressMapping.h b/src/configuration/DRAMSys/config/AddressMapping.h index 8c45b241..d3127201 100644 --- a/src/configuration/DRAMSys/config/AddressMapping.h +++ b/src/configuration/DRAMSys/config/AddressMapping.h @@ -78,6 +78,6 @@ NLOHMANN_JSONIFY_ALL_THINGS(AddressMapping, CHANNEL_BIT, XOR) -} // namespace Configuration +} // namespace DRAMSys::Config #endif // DRAMSYSCONFIGURATION_ADDRESSMAPPING_H diff --git a/src/configuration/DRAMSys/config/DRAMSysConfiguration.cpp b/src/configuration/DRAMSys/config/DRAMSysConfiguration.cpp index 7909bf61..0a8ca1f9 100644 --- a/src/configuration/DRAMSys/config/DRAMSysConfiguration.cpp +++ b/src/configuration/DRAMSys/config/DRAMSysConfiguration.cpp @@ -57,17 +57,18 @@ Configuration from_path(std::string_view path, std::string_view resourceDirector // This custom parser callback is responsible to swap out the paths to the sub-config json files // with the actual json data. - std::function + std::function parser_callback; - parser_callback = - [&parser_callback, ¤t_sub_config, resourceDirectory]( - int depth, nlohmann::detail::parse_event_t event, json_t &parsed) -> bool { + parser_callback = [&parser_callback, ¤t_sub_config, resourceDirectory]( + int depth, nlohmann::detail::parse_event_t event, json_t& parsed) -> bool + { using nlohmann::detail::parse_event_t; if (depth != 2) return true; - if (event == parse_event_t::key) { + if (event == parse_event_t::key) + { assert(parsed.is_string()); if (parsed == MemSpec::KEY) @@ -86,12 +87,14 @@ Configuration from_path(std::string_view path, std::string_view resourceDirector // In case we have an value (string) instead of an object, replace the value with the loaded // json object. - if (event == parse_event_t::value && current_sub_config != SubConfig::Unkown) { + if (event == parse_event_t::value && current_sub_config != SubConfig::Unkown) + { // Replace name of json file with actual json data auto parse_json = [&parser_callback, resourceDirectory](std::string_view base_dir, std::string_view sub_config_key, - const std::string &filename) -> json_t { + const std::string& filename) -> json_t + { std::filesystem::path path(resourceDirectory); path /= base_dir; path /= filename; @@ -121,7 +124,8 @@ Configuration from_path(std::string_view path, std::string_view resourceDirector return true; }; - if (file.is_open()) { + if (file.is_open()) + { json_t simulation = json_t::parse(file, parser_callback, true, true).at(Configuration::KEY); return simulation.get(); } diff --git a/src/configuration/DRAMSys/config/DRAMSysConfiguration.h b/src/configuration/DRAMSys/config/DRAMSysConfiguration.h index dce71332..7b27df53 100644 --- a/src/configuration/DRAMSys/config/DRAMSysConfiguration.h +++ b/src/configuration/DRAMSys/config/DRAMSysConfiguration.h @@ -57,7 +57,8 @@ * with the actual json object that is stored at this path. */ -namespace DRAMSys::Config { +namespace DRAMSys::Config +{ struct Configuration { @@ -71,15 +72,11 @@ struct Configuration std::optional> tracesetup; }; -NLOHMANN_JSONIFY_ALL_THINGS(Configuration, - addressmapping, - mcconfig, - memspec, - simconfig, - simulationid, - tracesetup) +NLOHMANN_JSONIFY_ALL_THINGS( + Configuration, addressmapping, mcconfig, memspec, simconfig, simulationid, tracesetup) -Configuration from_path(std::string_view path, std::string_view resourceDirectory = DRAMSYS_RESOURCE_DIR); +Configuration from_path(std::string_view path, + std::string_view resourceDirectory = DRAMSYS_RESOURCE_DIR); } // namespace DRAMSys::Config diff --git a/src/configuration/DRAMSys/config/McConfig.h b/src/configuration/DRAMSys/config/McConfig.h index 1a89c056..2c536db6 100644 --- a/src/configuration/DRAMSys/config/McConfig.h +++ b/src/configuration/DRAMSys/config/McConfig.h @@ -39,8 +39,8 @@ #include "DRAMSys/util/json.h" #include -#include #include +#include namespace DRAMSys::Config { @@ -54,13 +54,14 @@ enum class PagePolicyType Invalid = -1 }; -NLOHMANN_JSON_SERIALIZE_ENUM(PagePolicyType, { - {PagePolicyType::Invalid, nullptr}, - {PagePolicyType::Open, "Open"}, - {PagePolicyType::OpenAdaptive, "OpenAdaptive"}, - {PagePolicyType::Closed, "Closed"}, - {PagePolicyType::ClosedAdaptive, "ClosedAdaptive"}, - }) +NLOHMANN_JSON_SERIALIZE_ENUM(PagePolicyType, + { + {PagePolicyType::Invalid, nullptr}, + {PagePolicyType::Open, "Open"}, + {PagePolicyType::OpenAdaptive, "OpenAdaptive"}, + {PagePolicyType::Closed, "Closed"}, + {PagePolicyType::ClosedAdaptive, "ClosedAdaptive"}, + }) enum class SchedulerType { @@ -72,12 +73,13 @@ enum class SchedulerType Invalid = -1 }; -NLOHMANN_JSON_SERIALIZE_ENUM(SchedulerType, {{SchedulerType::Invalid, nullptr}, - {SchedulerType::Fifo, "Fifo"}, - {SchedulerType::FrFcfs, "FrFcfs"}, - {SchedulerType::FrFcfsGrp, "FrFcfsGrp"}, - {SchedulerType::GrpFrFcfs, "GrpFrFcfs"}, - {SchedulerType::GrpFrFcfsWm, "GrpFrFcfsWm"}}) +NLOHMANN_JSON_SERIALIZE_ENUM(SchedulerType, + {{SchedulerType::Invalid, nullptr}, + {SchedulerType::Fifo, "Fifo"}, + {SchedulerType::FrFcfs, "FrFcfs"}, + {SchedulerType::FrFcfsGrp, "FrFcfsGrp"}, + {SchedulerType::GrpFrFcfs, "GrpFrFcfs"}, + {SchedulerType::GrpFrFcfsWm, "GrpFrFcfsWm"}}) enum class SchedulerBufferType { @@ -87,10 +89,11 @@ enum class SchedulerBufferType Invalid = -1 }; -NLOHMANN_JSON_SERIALIZE_ENUM(SchedulerBufferType, {{SchedulerBufferType::Invalid, nullptr}, - {SchedulerBufferType::Bankwise, "Bankwise"}, - {SchedulerBufferType::ReadWrite, "ReadWrite"}, - {SchedulerBufferType::Shared, "Shared"}}) +NLOHMANN_JSON_SERIALIZE_ENUM(SchedulerBufferType, + {{SchedulerBufferType::Invalid, nullptr}, + {SchedulerBufferType::Bankwise, "Bankwise"}, + {SchedulerBufferType::ReadWrite, "ReadWrite"}, + {SchedulerBufferType::Shared, "Shared"}}) enum class CmdMuxType { @@ -100,7 +103,9 @@ enum class CmdMuxType }; NLOHMANN_JSON_SERIALIZE_ENUM(CmdMuxType, - {{CmdMuxType::Invalid, nullptr}, {CmdMuxType::Oldest, "Oldest"}, {CmdMuxType::Strict, "Strict"}}) + {{CmdMuxType::Invalid, nullptr}, + {CmdMuxType::Oldest, "Oldest"}, + {CmdMuxType::Strict, "Strict"}}) enum class RespQueueType { @@ -109,9 +114,10 @@ enum class RespQueueType Invalid = -1 }; -NLOHMANN_JSON_SERIALIZE_ENUM(RespQueueType, {{RespQueueType::Invalid, nullptr}, - {RespQueueType::Fifo, "Fifo"}, - {RespQueueType::Reorder, "Reorder"}}) +NLOHMANN_JSON_SERIALIZE_ENUM(RespQueueType, + {{RespQueueType::Invalid, nullptr}, + {RespQueueType::Fifo, "Fifo"}, + {RespQueueType::Reorder, "Reorder"}}) enum class RefreshPolicyType { @@ -123,18 +129,19 @@ enum class RefreshPolicyType Invalid = -1 }; -NLOHMANN_JSON_SERIALIZE_ENUM(RefreshPolicyType, {{RefreshPolicyType::Invalid, nullptr}, - {RefreshPolicyType::NoRefresh, "NoRefresh"}, - {RefreshPolicyType::AllBank, "AllBank"}, - {RefreshPolicyType::PerBank, "PerBank"}, - {RefreshPolicyType::Per2Bank, "Per2Bank"}, - {RefreshPolicyType::SameBank, "SameBank"}, +NLOHMANN_JSON_SERIALIZE_ENUM(RefreshPolicyType, + {{RefreshPolicyType::Invalid, nullptr}, + {RefreshPolicyType::NoRefresh, "NoRefresh"}, + {RefreshPolicyType::AllBank, "AllBank"}, + {RefreshPolicyType::PerBank, "PerBank"}, + {RefreshPolicyType::Per2Bank, "Per2Bank"}, + {RefreshPolicyType::SameBank, "SameBank"}, - // Alternative conversions to provide backwards-compatibility - // when deserializing. Will not be used for serializing. - {RefreshPolicyType::AllBank, "Rankwise"}, - {RefreshPolicyType::PerBank, "Bankwise"}, - {RefreshPolicyType::SameBank, "Groupwise"}}) + // Alternative conversions to provide backwards-compatibility + // when deserializing. Will not be used for serializing. + {RefreshPolicyType::AllBank, "Rankwise"}, + {RefreshPolicyType::PerBank, "Bankwise"}, + {RefreshPolicyType::SameBank, "Groupwise"}}) enum class PowerDownPolicyType { @@ -143,9 +150,10 @@ enum class PowerDownPolicyType Invalid = -1 }; -NLOHMANN_JSON_SERIALIZE_ENUM(PowerDownPolicyType, {{PowerDownPolicyType::Invalid, nullptr}, - {PowerDownPolicyType::NoPowerDown, "NoPowerDown"}, - {PowerDownPolicyType::Staggered, "Staggered"}}) +NLOHMANN_JSON_SERIALIZE_ENUM(PowerDownPolicyType, + {{PowerDownPolicyType::Invalid, nullptr}, + {PowerDownPolicyType::NoPowerDown, "NoPowerDown"}, + {PowerDownPolicyType::Staggered, "Staggered"}}) enum class ArbiterType { @@ -155,10 +163,11 @@ enum class ArbiterType Invalid = -1 }; -NLOHMANN_JSON_SERIALIZE_ENUM(ArbiterType, {{ArbiterType::Invalid, nullptr}, - {ArbiterType::Simple, "Simple"}, - {ArbiterType::Fifo, "Fifo"}, - {ArbiterType::Reorder, "Reorder"}}) +NLOHMANN_JSON_SERIALIZE_ENUM(ArbiterType, + {{ArbiterType::Invalid, nullptr}, + {ArbiterType::Simple, "Simple"}, + {ArbiterType::Fifo, "Fifo"}, + {ArbiterType::Reorder, "Reorder"}}) struct McConfig { @@ -215,6 +224,6 @@ NLOHMANN_JSONIFY_ALL_THINGS(McConfig, BlockingReadDelay, BlockingWriteDelay) -} // namespace Configuration +} // namespace DRAMSys::Config #endif // DRAMSYSCONFIGURATION_MCCONFIG_H diff --git a/src/configuration/DRAMSys/config/SimConfig.h b/src/configuration/DRAMSys/config/SimConfig.h index 7f188d29..ea05ced5 100644 --- a/src/configuration/DRAMSys/config/SimConfig.h +++ b/src/configuration/DRAMSys/config/SimConfig.h @@ -51,10 +51,11 @@ enum class StoreModeType Invalid = -1 }; -NLOHMANN_JSON_SERIALIZE_ENUM(StoreModeType, {{StoreModeType::Invalid, nullptr}, - {StoreModeType::NoStorage, "NoStorage"}, - {StoreModeType::Store, "Store"}, - {StoreModeType::ErrorModel, "ErrorModel"}}) +NLOHMANN_JSON_SERIALIZE_ENUM(StoreModeType, + {{StoreModeType::Invalid, nullptr}, + {StoreModeType::NoStorage, "NoStorage"}, + {StoreModeType::Store, "Store"}, + {StoreModeType::ErrorModel, "ErrorModel"}}) struct SimConfig { @@ -93,6 +94,6 @@ NLOHMANN_JSONIFY_ALL_THINGS(SimConfig, UseMalloc, WindowSize) -} // namespace Configuration +} // namespace DRAMSys::Config #endif // DRAMSYSCONFIGURATION_SIMCONFIG_H diff --git a/src/configuration/DRAMSys/config/TraceSetup.h b/src/configuration/DRAMSys/config/TraceSetup.h index f59629d1..71003dbf 100644 --- a/src/configuration/DRAMSys/config/TraceSetup.h +++ b/src/configuration/DRAMSys/config/TraceSetup.h @@ -52,10 +52,11 @@ enum class TrafficInitiatorType Invalid = -1 }; -NLOHMANN_JSON_SERIALIZE_ENUM(TrafficInitiatorType, {{TrafficInitiatorType::Invalid, nullptr}, - {TrafficInitiatorType::Player, "player"}, - {TrafficInitiatorType::Hammer, "hammer"}, - {TrafficInitiatorType::Generator, "generator"}}) +NLOHMANN_JSON_SERIALIZE_ENUM(TrafficInitiatorType, + {{TrafficInitiatorType::Invalid, nullptr}, + {TrafficInitiatorType::Player, "player"}, + {TrafficInitiatorType::Hammer, "hammer"}, + {TrafficInitiatorType::Generator, "generator"}}) enum class AddressDistribution { @@ -64,9 +65,10 @@ enum class AddressDistribution Invalid = -1 }; -NLOHMANN_JSON_SERIALIZE_ENUM(AddressDistribution, {{AddressDistribution::Invalid, nullptr}, - {AddressDistribution::Random, "random"}, - {AddressDistribution::Sequential, "sequential"}}) +NLOHMANN_JSON_SERIALIZE_ENUM(AddressDistribution, + {{AddressDistribution::Invalid, nullptr}, + {AddressDistribution::Random, "random"}, + {AddressDistribution::Sequential, "sequential"}}) struct TracePlayer { @@ -192,8 +194,13 @@ struct RowHammer uint64_t rowIncrement{}; }; -NLOHMANN_JSONIFY_ALL_THINGS( - RowHammer, clkMhz, name, maxPendingReadRequests, maxPendingWriteRequests, numRequests, rowIncrement) +NLOHMANN_JSONIFY_ALL_THINGS(RowHammer, + clkMhz, + name, + maxPendingReadRequests, + maxPendingWriteRequests, + numRequests, + rowIncrement) struct TraceSetupConstants { @@ -201,8 +208,9 @@ struct TraceSetupConstants static constexpr std::string_view SUB_DIR = "tracesetup"; }; -using Initiator = std::variant; +using Initiator = + std::variant; -} // namespace Configuration +} // namespace DRAMSys::Config #endif // DRAMSYSCONFIGURATION_TRACESETUP_H diff --git a/src/configuration/DRAMSys/config/memspec/MemArchitectureSpec.cpp b/src/configuration/DRAMSys/config/memspec/MemArchitectureSpec.cpp index dceaeee4..72206564 100644 --- a/src/configuration/DRAMSys/config/memspec/MemArchitectureSpec.cpp +++ b/src/configuration/DRAMSys/config/memspec/MemArchitectureSpec.cpp @@ -38,22 +38,22 @@ namespace DRAMSys::Config { -void to_json(json_t &j, const MemArchitectureSpecType &c) +void to_json(json_t& j, const MemArchitectureSpecType& c) { j = json_t{}; - for (const auto &entry : c.entries) + for (const auto& entry : c.entries) { j[entry.first] = entry.second; } } -void from_json(const json_t &j, MemArchitectureSpecType &c) +void from_json(const json_t& j, MemArchitectureSpecType& c) { - for (const auto &entry : j.items()) + for (const auto& entry : j.items()) { c.entries[entry.key()] = entry.value(); } } -} // namespace Configuration +} // namespace DRAMSys::Config diff --git a/src/configuration/DRAMSys/config/memspec/MemArchitectureSpec.h b/src/configuration/DRAMSys/config/memspec/MemArchitectureSpec.h index caa3e92f..cd83f48d 100644 --- a/src/configuration/DRAMSys/config/memspec/MemArchitectureSpec.h +++ b/src/configuration/DRAMSys/config/memspec/MemArchitectureSpec.h @@ -48,9 +48,9 @@ struct MemArchitectureSpecType std::unordered_map entries; }; -void to_json(json_t &j, const MemArchitectureSpecType &c); -void from_json(const json_t &j, MemArchitectureSpecType &c); +void to_json(json_t& j, const MemArchitectureSpecType& c); +void from_json(const json_t& j, MemArchitectureSpecType& c); -} // namespace Configuration +} // namespace DRAMSys::Config #endif // DRAMSYSCONFIGURATION_MEMARCHITECTURESPEC_H diff --git a/src/configuration/DRAMSys/config/memspec/MemPowerSpec.cpp b/src/configuration/DRAMSys/config/memspec/MemPowerSpec.cpp index 2ea1a550..3d4049a5 100644 --- a/src/configuration/DRAMSys/config/memspec/MemPowerSpec.cpp +++ b/src/configuration/DRAMSys/config/memspec/MemPowerSpec.cpp @@ -38,22 +38,22 @@ namespace DRAMSys::Config { -void to_json(json_t &j, const MemPowerSpec &c) +void to_json(json_t& j, const MemPowerSpec& c) { j = json_t{}; - for (const auto &entry : c.entries) + for (const auto& entry : c.entries) { j[entry.first] = entry.second; } } -void from_json(const json_t &j, MemPowerSpec &c) +void from_json(const json_t& j, MemPowerSpec& c) { - for (const auto &entry : j.items()) + for (const auto& entry : j.items()) { c.entries[entry.key()] = entry.value(); } } -} // namespace Configuration +} // namespace DRAMSys::Config diff --git a/src/configuration/DRAMSys/config/memspec/MemPowerSpec.h b/src/configuration/DRAMSys/config/memspec/MemPowerSpec.h index 40ee1539..3c7d9f6e 100644 --- a/src/configuration/DRAMSys/config/memspec/MemPowerSpec.h +++ b/src/configuration/DRAMSys/config/memspec/MemPowerSpec.h @@ -48,9 +48,9 @@ struct MemPowerSpec std::unordered_map entries; }; -void to_json(json_t &j, const MemPowerSpec &c); -void from_json(const json_t &j, MemPowerSpec &c); +void to_json(json_t& j, const MemPowerSpec& c); +void from_json(const json_t& j, MemPowerSpec& c); -} // namespace Configuration +} // namespace DRAMSys::Config #endif // DRAMSYSCONFIGURATION_MEMPOWERSPEC_H diff --git a/src/configuration/DRAMSys/config/memspec/MemSpec.h b/src/configuration/DRAMSys/config/memspec/MemSpec.h index f002fa9f..fe6d14bf 100644 --- a/src/configuration/DRAMSys/config/memspec/MemSpec.h +++ b/src/configuration/DRAMSys/config/memspec/MemSpec.h @@ -36,14 +36,15 @@ #ifndef DRAMSYSCONFIGURATION_MEMSPEC_H #define DRAMSYSCONFIGURATION_MEMSPEC_H -#include "DRAMSys/util/json.h" #include "DRAMSys/config/memspec/MemArchitectureSpec.h" #include "DRAMSys/config/memspec/MemPowerSpec.h" #include "DRAMSys/config/memspec/MemTimingSpec.h" +#include "DRAMSys/util/json.h" #include -namespace DRAMSys::Config { +namespace DRAMSys::Config +{ struct MemSpec { @@ -60,6 +61,6 @@ struct MemSpec NLOHMANN_JSONIFY_ALL_THINGS( MemSpec, memarchitecturespec, memoryId, memoryType, memtimingspec, mempowerspec) -} // namespace Configuration +} // namespace DRAMSys::Config #endif // DRAMSYSCONFIGURATION_MEMSPEC_H diff --git a/src/configuration/DRAMSys/config/memspec/MemTimingSpec.cpp b/src/configuration/DRAMSys/config/memspec/MemTimingSpec.cpp index 6acf8d27..c44f7cb5 100644 --- a/src/configuration/DRAMSys/config/memspec/MemTimingSpec.cpp +++ b/src/configuration/DRAMSys/config/memspec/MemTimingSpec.cpp @@ -38,22 +38,22 @@ namespace DRAMSys::Config { -void to_json(json_t &j, const MemTimingSpecType &c) +void to_json(json_t& j, const MemTimingSpecType& c) { j = json_t{}; - for (const auto &entry : c.entries) + for (const auto& entry : c.entries) { j[entry.first] = entry.second; } } -void from_json(const json_t &j, MemTimingSpecType &c) +void from_json(const json_t& j, MemTimingSpecType& c) { - for (const auto &entry : j.items()) + for (const auto& entry : j.items()) { c.entries[entry.key()] = entry.value(); } } -} // namespace Configuration +} // namespace DRAMSys::Config diff --git a/src/configuration/DRAMSys/config/memspec/MemTimingSpec.h b/src/configuration/DRAMSys/config/memspec/MemTimingSpec.h index 24a7c02f..096fbd29 100644 --- a/src/configuration/DRAMSys/config/memspec/MemTimingSpec.h +++ b/src/configuration/DRAMSys/config/memspec/MemTimingSpec.h @@ -49,9 +49,9 @@ struct MemTimingSpecType std::unordered_map entries; }; -void to_json(json &j, const MemTimingSpecType &c); -void from_json(const json &j, MemTimingSpecType &c); +void to_json(json& j, const MemTimingSpecType& c); +void from_json(const json& j, MemTimingSpecType& c); -} // namespace Configuration +} // namespace DRAMSys::Config #endif // DRAMSYSCONFIGURATION_MEMTIMINGSPEC_H diff --git a/src/libdramsys/DRAMSys/common/DebugManager.cpp b/src/libdramsys/DRAMSys/common/DebugManager.cpp index 0bd0de25..a425da7c 100644 --- a/src/libdramsys/DRAMSys/common/DebugManager.cpp +++ b/src/libdramsys/DRAMSys/common/DebugManager.cpp @@ -43,15 +43,17 @@ namespace DRAMSys { -void DebugManager::printDebugMessage(const std::string &sender, const std::string &message) +void DebugManager::printDebugMessage(const std::string& sender, const std::string& message) { if (debugEnabled) { if (writeToConsole) - std::cout << " at " << sc_core::sc_time_stamp() << "\t in " << sender << "\t: " << message << std::endl; + std::cout << " at " << sc_core::sc_time_stamp() << "\t in " << sender + << "\t: " << message << std::endl; if (writeToFile && debugFile) - debugFile << " at " << sc_core::sc_time_stamp() << "\t in " << sender << "\t: " << message << std::endl; + debugFile << " at " << sc_core::sc_time_stamp() << "\t in " << sender + << "\t: " << message << std::endl; } } @@ -62,12 +64,13 @@ void DebugManager::setup(bool _debugEnabled, bool _writeToConsole, bool _writeTo writeToFile = _writeToFile; } -void DebugManager::printMessage(const std::string &sender, const std::string &message) +void DebugManager::printMessage(const std::string& sender, const std::string& message) { - std::cout << " at " << sc_core::sc_time_stamp() << "\t in " << sender << "\t: " << message << std::endl; + std::cout << " at " << sc_core::sc_time_stamp() << "\t in " << sender << "\t: " << message + << std::endl; } -void DebugManager::openDebugFile(const std::string &filename) +void DebugManager::openDebugFile(const std::string& filename) { if (debugFile) debugFile.close(); diff --git a/src/libdramsys/DRAMSys/common/DebugManager.h b/src/libdramsys/DRAMSys/common/DebugManager.h index 0c93e050..0a343485 100644 --- a/src/libdramsys/DRAMSys/common/DebugManager.h +++ b/src/libdramsys/DRAMSys/common/DebugManager.h @@ -38,12 +38,15 @@ #define DEBUGMANAGER_H #ifdef NDEBUG -#define PRINTDEBUGMESSAGE(sender, message) {} +#define PRINTDEBUGMESSAGE(sender, message) \ + { \ + } #else -#define PRINTDEBUGMESSAGE(sender, message) DebugManager::getInstance().printDebugMessage(sender, message) +#define PRINTDEBUGMESSAGE(sender, message) \ + DebugManager::getInstance().printDebugMessage(sender, message) -#include #include +#include namespace DRAMSys { @@ -51,7 +54,7 @@ namespace DRAMSys class DebugManager { public: - static DebugManager &getInstance() + static DebugManager& getInstance() { static DebugManager _instance; return _instance; @@ -69,9 +72,9 @@ public: void setup(bool _debugEnabled, bool _writeToConsole, bool _writeToFile); - void printDebugMessage(const std::string &sender, const std::string &message); - static void printMessage(const std::string &sender, const std::string &message); - void openDebugFile(const std::string &filename); + void printDebugMessage(const std::string& sender, const std::string& message); + static void printMessage(const std::string& sender, const std::string& message); + void openDebugFile(const std::string& filename); private: bool debugEnabled = false; diff --git a/src/libdramsys/DRAMSys/common/TlmRecorder.cpp b/src/libdramsys/DRAMSys/common/TlmRecorder.cpp index a0b6410d..6c2c02f5 100644 --- a/src/libdramsys/DRAMSys/common/TlmRecorder.cpp +++ b/src/libdramsys/DRAMSys/common/TlmRecorder.cpp @@ -52,9 +52,9 @@ using namespace tlm; namespace DRAMSys { -TlmRecorder::TlmRecorder(const std::string &name, - const Configuration &config, - const std::string &dbName) : +TlmRecorder::TlmRecorder(const std::string& name, + const Configuration& config, + const std::string& dbName) : name(name), config(config), memSpec(*config.memSpec), @@ -66,7 +66,7 @@ TlmRecorder::TlmRecorder(const std::string &name, storageDataBuffer->reserve(transactionCommitRate); openDB(dbName); - char *sErrMsg = nullptr; + char* sErrMsg = nullptr; sqlite3_exec(db, "PRAGMA main.page_size = 4096", nullptr, nullptr, &sErrMsg); sqlite3_exec(db, "PRAGMA main.cache_size=10000", nullptr, nullptr, &sErrMsg); sqlite3_exec(db, "PRAGMA main.locking_mode=EXCLUSIVE", nullptr, nullptr, &sErrMsg); @@ -106,7 +106,8 @@ void TlmRecorder::recordPower(double timeInSeconds, double averagePower) executeSqlStatement(insertPowerStatement); } -void TlmRecorder::recordBufferDepth(double timeInSeconds, const std::vector &averageBufferDepth) +void TlmRecorder::recordBufferDepth(double timeInSeconds, + const std::vector& averageBufferDepth) { for (size_t index = 0; index < averageBufferDepth.size(); index++) { @@ -124,7 +125,9 @@ void TlmRecorder::recordBandwidth(double timeInSeconds, double averageBandwidth) executeSqlStatement(insertBandwidthStatement); } -void TlmRecorder::recordPhase(tlm_generic_payload& trans, const tlm_phase& phase, const sc_time& delay) +void TlmRecorder::recordPhase(tlm_generic_payload& trans, + const tlm_phase& phase, + const sc_time& delay) { const sc_time& currentTime = sc_time_stamp(); @@ -132,22 +135,26 @@ void TlmRecorder::recordPhase(tlm_generic_payload& trans, const tlm_phase& phase { introduceTransactionToSystem(trans); std::string phaseName = getPhaseName(phase).substr(6); - currentTransactionsInSystem.at(&trans).recordedPhases.emplace_back(phaseName, currentTime + delay); + currentTransactionsInSystem.at(&trans).recordedPhases.emplace_back(phaseName, + currentTime + delay); } if (phase == BEGIN_RESP) { std::string phaseName = getPhaseName(phase).substr(6); - currentTransactionsInSystem.at(&trans).recordedPhases.emplace_back(phaseName, currentTime + delay); + currentTransactionsInSystem.at(&trans).recordedPhases.emplace_back(phaseName, + currentTime + delay); } else if (phase == END_REQ) { // BEGIN_REQ is always the first phase of a normal transaction - currentTransactionsInSystem.at(&trans).recordedPhases.front().interval.end = currentTime + delay; + currentTransactionsInSystem.at(&trans).recordedPhases.front().interval.end = + currentTime + delay; } else if (phase == END_RESP) { // BEGIN_RESP is always the last phase of a normal transaction at this point - currentTransactionsInSystem.at(&trans).recordedPhases.back().interval.end = currentTime + delay; + currentTransactionsInSystem.at(&trans).recordedPhases.back().interval.end = + currentTime + delay; removeTransactionFromSystem(trans); } else if (isFixedCommandPhase(phase)) @@ -174,11 +181,18 @@ void TlmRecorder::recordPhase(tlm_generic_payload& trans, const tlm_phase& phase intervalOnDataStrobe.end = currentTime + intervalOnDataStrobe.end; } - currentTransactionsInSystem.at(keyTrans).recordedPhases.emplace_back(std::move(phaseName), - std::move(TimeInterval(currentTime + delay, - currentTime + delay + memSpec.getExecutionTime(Command(phase), trans))), - std::move(intervalOnDataStrobe), extension.getRank(), extension.getBankGroup(), extension.getBank(), - extension.getRow(), extension.getColumn(), extension.getBurstLength()); + currentTransactionsInSystem.at(keyTrans).recordedPhases.emplace_back( + std::move(phaseName), + std::move(TimeInterval(currentTime + delay, + currentTime + delay + + memSpec.getExecutionTime(Command(phase), trans))), + std::move(intervalOnDataStrobe), + extension.getRank(), + extension.getBankGroup(), + extension.getBank(), + extension.getRow(), + extension.getColumn(), + extension.getBurstLength()); if (isRefreshCommandPhase(phase)) removeTransactionFromSystem(trans); @@ -188,28 +202,32 @@ void TlmRecorder::recordPhase(tlm_generic_payload& trans, const tlm_phase& phase introduceTransactionToSystem(trans); std::string phaseName = getPhaseName(phase).substr(6); // remove "BEGIN_" const ControllerExtension& extension = ControllerExtension::getExtension(trans); - currentTransactionsInSystem.at(&trans).recordedPhases.emplace_back(std::move(phaseName), - std::move(TimeInterval(currentTime + delay, SC_ZERO_TIME)), - std::move(TimeInterval(SC_ZERO_TIME, SC_ZERO_TIME)), - extension.getRank(), extension.getBankGroup(), extension.getBank(), - extension.getRow(), extension.getColumn(), extension.getBurstLength()); + currentTransactionsInSystem.at(&trans).recordedPhases.emplace_back( + std::move(phaseName), + std::move(TimeInterval(currentTime + delay, SC_ZERO_TIME)), + std::move(TimeInterval(SC_ZERO_TIME, SC_ZERO_TIME)), + extension.getRank(), + extension.getBankGroup(), + extension.getBank(), + extension.getRow(), + extension.getColumn(), + extension.getBurstLength()); } else if (isPowerDownExitPhase(phase)) { - currentTransactionsInSystem.at(&trans).recordedPhases.back().interval.end = currentTime + delay - + memSpec.getCommandLength(Command(phase)); + currentTransactionsInSystem.at(&trans).recordedPhases.back().interval.end = + currentTime + delay + memSpec.getCommandLength(Command(phase)); removeTransactionFromSystem(trans); } simulationTimeCoveredByRecording = currentTime + delay; } -void TlmRecorder::recordDebugMessage(const std::string &message, const sc_time &time) +void TlmRecorder::recordDebugMessage(const std::string& message, const sc_time& time) { insertDebugMessageInDB(message, time); } - // ------------- internal ----------------------- void TlmRecorder::introduceTransactionToSystem(tlm_generic_payload& trans) @@ -227,20 +245,27 @@ void TlmRecorder::introduceTransactionToSystem(tlm_generic_payload& trans) const ArbiterExtension& extension = ArbiterExtension::getExtension(trans); - currentTransactionsInSystem.insert({&trans, Transaction(totalNumTransactions, trans.get_address(), - trans.get_data_length(), commandChar, extension.getTimeOfGeneration(), extension.getThread(), - extension.getChannel())}); + currentTransactionsInSystem.insert({&trans, + Transaction(totalNumTransactions, + trans.get_address(), + trans.get_data_length(), + commandChar, + extension.getTimeOfGeneration(), + extension.getThread(), + extension.getChannel())}); - PRINTDEBUGMESSAGE(name, "New transaction #" + std::to_string(totalNumTransactions) + " generation time " + - currentTransactionsInSystem.at(&trans).timeOfGeneration.to_string()); + PRINTDEBUGMESSAGE(name, + "New transaction #" + std::to_string(totalNumTransactions) + + " generation time " + + currentTransactionsInSystem.at(&trans).timeOfGeneration.to_string()); } -void TlmRecorder::removeTransactionFromSystem(tlm_generic_payload &trans) +void TlmRecorder::removeTransactionFromSystem(tlm_generic_payload& trans) { assert(currentTransactionsInSystem.count(&trans) != 0); - PRINTDEBUGMESSAGE(name, "Removing transaction #" + - std::to_string(currentTransactionsInSystem.at(&trans).id)); + PRINTDEBUGMESSAGE( + name, "Removing transaction #" + std::to_string(currentTransactionsInSystem.at(&trans).id)); Transaction& recordingData = currentTransactionsInSystem.at(&trans); currentDataBuffer->push_back(recordingData); @@ -256,16 +281,18 @@ void TlmRecorder::removeTransactionFromSystem(tlm_generic_payload &trans) storageThread = std::thread(&TlmRecorder::commitRecordedDataToDB, this); currentDataBuffer->clear(); } - } void TlmRecorder::terminateRemainingTransactions() { while (!currentTransactionsInSystem.empty()) { - auto transaction = std::min_element(currentTransactionsInSystem.begin(), - currentTransactionsInSystem.end(), [](decltype(currentTransactionsInSystem)::value_type& l, - decltype(currentTransactionsInSystem)::value_type& r) -> bool {return l.second.id < r.second.id;}); + auto transaction = + std::min_element(currentTransactionsInSystem.begin(), + currentTransactionsInSystem.end(), + [](decltype(currentTransactionsInSystem)::value_type& l, + decltype(currentTransactionsInSystem)::value_type& r) -> bool + { return l.second.id < r.second.id; }); if (transaction->second.cmd == 'X') { std::string beginPhase = transaction->second.recordedPhases.front().name; @@ -289,7 +316,8 @@ void TlmRecorder::terminateRemainingTransactions() // Do not terminate transaction as it is not ready to be completed. currentTransactionsInSystem.erase(transaction); - // Decrement totalNumTransactions as this transaction will not be recorded in the database. + // Decrement totalNumTransactions as this transaction will not be recorded in the + // database. totalNumTransactions--; } } @@ -320,7 +348,7 @@ void TlmRecorder::commitRecordedDataToDB() sqlite3_exec(db, "COMMIT;", nullptr, nullptr, nullptr); } -void TlmRecorder::openDB(const std::string &dbName) +void TlmRecorder::openDB(const std::string& dbName) { std::ifstream f(dbName.c_str()); if (f.good()) @@ -341,85 +369,114 @@ void TlmRecorder::openDB(const std::string &dbName) void TlmRecorder::prepareSqlStatements() { insertTransactionString = - "INSERT INTO Transactions VALUES (:id,:rangeID,:address,:dataLength,:thread,:channel," - ":timeOfGeneration,:command)"; + "INSERT INTO Transactions VALUES (:id,:rangeID,:address,:dataLength,:thread,:channel," + ":timeOfGeneration,:command)"; insertRangeString = "INSERT INTO Ranges VALUES (:id,:begin,:end)"; updateRangeString = "UPDATE Ranges SET End = :end WHERE ID = :id"; insertPhaseString = - "INSERT INTO Phases (PhaseName,PhaseBegin,PhaseEnd,DataStrobeBegin,DataStrobeEnd,Rank,BankGroup,Bank," - "Row,Column,BurstLength,Transact) VALUES (:name,:begin,:end,:strobeBegin,:strobeEnd,:rank,:bankGroup,:bank," - ":row,:column,:burstLength,:transaction)"; + "INSERT INTO Phases " + "(PhaseName,PhaseBegin,PhaseEnd,DataStrobeBegin,DataStrobeEnd,Rank,BankGroup,Bank," + "Row,Column,BurstLength,Transact) VALUES " + "(:name,:begin,:end,:strobeBegin,:strobeEnd,:rank,:bankGroup,:bank," + ":row,:column,:burstLength,:transaction)"; updatePhaseString = - "UPDATE Phases SET PhaseEnd = :end WHERE Transact = :trans AND PhaseName = :name"; + "UPDATE Phases SET PhaseEnd = :end WHERE Transact = :trans AND PhaseName = :name"; insertGeneralInfoString = "INSERT INTO GeneralInfo VALUES" "(:numberOfRanks, :numberOfBankGroups, :numberOfBanks, :clk, :unitOfTime, " - ":mcconfig, :memspec, :traces, :windowSize, :refreshMaxPostponed, :refreshMaxPulledin, :controllerThread, " + ":mcconfig, :memspec, :traces, :windowSize, :refreshMaxPostponed, :refreshMaxPulledin, " + ":controllerThread, " ":maxBufferDepth, :per2BankOffset, :rowColumnCommandBus, :pseudoChannelMode)"; insertCommandLengthsString = "INSERT INTO CommandLengths VALUES" "(:command, :length)"; - insertDebugMessageString = - "INSERT INTO DebugMessages (Time,Message) Values (:time,:message)"; + insertDebugMessageString = "INSERT INTO DebugMessages (Time,Message) Values (:time,:message)"; insertPowerString = "INSERT INTO Power VALUES (:time,:averagePower)"; - insertBufferDepthString = "INSERT INTO BufferDepth VALUES (:time,:bufferNumber,:averageBufferDepth)"; + insertBufferDepthString = + "INSERT INTO BufferDepth VALUES (:time,:bufferNumber,:averageBufferDepth)"; insertBandwidthString = "INSERT INTO Bandwidth VALUES (:time,:averageBandwidth)"; - sqlite3_prepare_v2(db, insertTransactionString.c_str(), -1, &insertTransactionStatement, nullptr); + sqlite3_prepare_v2( + db, insertTransactionString.c_str(), -1, &insertTransactionStatement, nullptr); sqlite3_prepare_v2(db, insertRangeString.c_str(), -1, &insertRangeStatement, nullptr); sqlite3_prepare_v2(db, updateRangeString.c_str(), -1, &updateRangeStatement, nullptr); sqlite3_prepare_v2(db, insertPhaseString.c_str(), -1, &insertPhaseStatement, nullptr); sqlite3_prepare_v2(db, updatePhaseString.c_str(), -1, &updatePhaseStatement, nullptr); - sqlite3_prepare_v2(db, insertGeneralInfoString.c_str(), -1, &insertGeneralInfoStatement, nullptr); - sqlite3_prepare_v2(db, insertCommandLengthsString.c_str(), -1, &insertCommandLengthsStatement, nullptr); - sqlite3_prepare_v2(db, insertDebugMessageString.c_str(), -1, &insertDebugMessageStatement, nullptr); + sqlite3_prepare_v2( + db, insertGeneralInfoString.c_str(), -1, &insertGeneralInfoStatement, nullptr); + sqlite3_prepare_v2( + db, insertCommandLengthsString.c_str(), -1, &insertCommandLengthsStatement, nullptr); + sqlite3_prepare_v2( + db, insertDebugMessageString.c_str(), -1, &insertDebugMessageStatement, nullptr); sqlite3_prepare_v2(db, insertPowerString.c_str(), -1, &insertPowerStatement, nullptr); - sqlite3_prepare_v2(db, insertBufferDepthString.c_str(), -1, &insertBufferDepthStatement, nullptr); + sqlite3_prepare_v2( + db, insertBufferDepthString.c_str(), -1, &insertBufferDepthStatement, nullptr); sqlite3_prepare_v2(db, insertBandwidthString.c_str(), -1, &insertBandwidthStatement, nullptr); } -void TlmRecorder::insertDebugMessageInDB(const std::string &message, const sc_time &time) +void TlmRecorder::insertDebugMessageInDB(const std::string& message, const sc_time& time) { sqlite3_bind_int64(insertDebugMessageStatement, 1, static_cast(time.value())); - sqlite3_bind_text(insertDebugMessageStatement, 2, message.c_str(), static_cast(message.length()), nullptr); + sqlite3_bind_text(insertDebugMessageStatement, + 2, + message.c_str(), + static_cast(message.length()), + nullptr); executeSqlStatement(insertDebugMessageStatement); } void TlmRecorder::insertGeneralInfo() { - sqlite3_bind_int(insertGeneralInfoStatement, 1, static_cast(config.memSpec->ranksPerChannel)); - sqlite3_bind_int(insertGeneralInfoStatement, 2, static_cast(config.memSpec->bankGroupsPerChannel)); - sqlite3_bind_int(insertGeneralInfoStatement, 3, static_cast(config.memSpec->banksPerChannel)); - sqlite3_bind_int64(insertGeneralInfoStatement, 4, static_cast(config.memSpec->tCK.value())); + sqlite3_bind_int( + insertGeneralInfoStatement, 1, static_cast(config.memSpec->ranksPerChannel)); + sqlite3_bind_int( + insertGeneralInfoStatement, 2, static_cast(config.memSpec->bankGroupsPerChannel)); + sqlite3_bind_int( + insertGeneralInfoStatement, 3, static_cast(config.memSpec->banksPerChannel)); + sqlite3_bind_int64( + insertGeneralInfoStatement, 4, static_cast(config.memSpec->tCK.value())); sqlite3_bind_text(insertGeneralInfoStatement, 5, "PS", 2, nullptr); - sqlite3_bind_text(insertGeneralInfoStatement, 6, mcconfig.c_str(), static_cast(mcconfig.length()), nullptr); - sqlite3_bind_text(insertGeneralInfoStatement, 7, memspec.c_str(), static_cast(memspec.length()), nullptr); - sqlite3_bind_text(insertGeneralInfoStatement, 8, traces.c_str(), static_cast(traces.length()), nullptr); + sqlite3_bind_text(insertGeneralInfoStatement, + 6, + mcconfig.c_str(), + static_cast(mcconfig.length()), + nullptr); + sqlite3_bind_text(insertGeneralInfoStatement, + 7, + memspec.c_str(), + static_cast(memspec.length()), + nullptr); + sqlite3_bind_text( + insertGeneralInfoStatement, 8, traces.c_str(), static_cast(traces.length()), nullptr); if (config.enableWindowing) - sqlite3_bind_int64(insertGeneralInfoStatement, 9, static_cast((config.memSpec->tCK - * config.windowSize).value())); + sqlite3_bind_int64(insertGeneralInfoStatement, + 9, + static_cast((config.memSpec->tCK * config.windowSize).value())); else sqlite3_bind_int64(insertGeneralInfoStatement, 9, 0); sqlite3_bind_int(insertGeneralInfoStatement, 10, static_cast(config.refreshMaxPostponed)); sqlite3_bind_int(insertGeneralInfoStatement, 11, static_cast(config.refreshMaxPulledin)); sqlite3_bind_int(insertGeneralInfoStatement, 12, static_cast(UINT_MAX)); sqlite3_bind_int(insertGeneralInfoStatement, 13, static_cast(config.requestBufferSize)); - sqlite3_bind_int(insertGeneralInfoStatement, 14, static_cast(config.memSpec->getPer2BankOffset())); + sqlite3_bind_int( + insertGeneralInfoStatement, 14, static_cast(config.memSpec->getPer2BankOffset())); const MemSpec& memSpec = *config.memSpec; const auto memoryType = memSpec.memoryType; - bool rowColumnCommandBus = (memoryType == MemSpec::MemoryType::HBM2) || (memoryType == MemSpec::MemoryType::HBM3); + bool rowColumnCommandBus = + (memoryType == MemSpec::MemoryType::HBM2) || (memoryType == MemSpec::MemoryType::HBM3); - bool pseudoChannelMode = [&memSpec, memoryType]() -> bool { + bool pseudoChannelMode = [&memSpec, memoryType]() -> bool + { if (memoryType != MemSpec::MemoryType::HBM2 && memoryType != MemSpec::MemoryType::HBM3) return false; @@ -435,11 +492,14 @@ void TlmRecorder::insertCommandLengths() { const MemSpec& _memSpec = *config.memSpec; - auto insertCommandLength = [this, &_memSpec](Command command) { + auto insertCommandLength = [this, &_memSpec](Command command) + { auto commandName = command.toString(); - sqlite3_bind_text(insertCommandLengthsStatement, 1, commandName.c_str(), commandName.length(), nullptr); - sqlite3_bind_double(insertCommandLengthsStatement, 2, _memSpec.getCommandLengthInCycles(command)); + sqlite3_bind_text( + insertCommandLengthsStatement, 1, commandName.c_str(), commandName.length(), nullptr); + sqlite3_bind_double( + insertCommandLengthsStatement, 2, _memSpec.getCommandLengthInCycles(command)); executeSqlStatement(insertCommandLengthsStatement); }; @@ -447,26 +507,23 @@ void TlmRecorder::insertCommandLengths() insertCommandLength(static_cast(command)); } -void TlmRecorder::insertTransactionInDB(const Transaction &recordingData) +void TlmRecorder::insertTransactionInDB(const Transaction& recordingData) { sqlite3_bind_int(insertTransactionStatement, 1, static_cast(recordingData.id)); sqlite3_bind_int(insertTransactionStatement, 2, static_cast(recordingData.id)); sqlite3_bind_int64(insertTransactionStatement, 3, static_cast(recordingData.address)); sqlite3_bind_int(insertTransactionStatement, 4, static_cast(recordingData.dataLength)); - sqlite3_bind_int(insertTransactionStatement, 5, - static_cast(recordingData.thread)); - sqlite3_bind_int(insertTransactionStatement, 6, - static_cast(recordingData.channel)); - sqlite3_bind_int64(insertTransactionStatement, 7, + sqlite3_bind_int(insertTransactionStatement, 5, static_cast(recordingData.thread)); + sqlite3_bind_int(insertTransactionStatement, 6, static_cast(recordingData.channel)); + sqlite3_bind_int64(insertTransactionStatement, + 7, static_cast(recordingData.timeOfGeneration.value())); - sqlite3_bind_text(insertTransactionStatement, 8, - &recordingData.cmd, 1, nullptr); + sqlite3_bind_text(insertTransactionStatement, 8, &recordingData.cmd, 1, nullptr); executeSqlStatement(insertTransactionStatement); } -void TlmRecorder::insertRangeInDB(uint64_t id, const sc_time &begin, - const sc_time &end) +void TlmRecorder::insertRangeInDB(uint64_t id, const sc_time& begin, const sc_time& end) { sqlite3_bind_int64(insertRangeStatement, 1, static_cast(id)); sqlite3_bind_int64(insertRangeStatement, 2, static_cast(begin.value())); @@ -476,11 +533,17 @@ void TlmRecorder::insertRangeInDB(uint64_t id, const sc_time &begin, void TlmRecorder::insertPhaseInDB(const Transaction::Phase& phase, uint64_t transactionID) { - sqlite3_bind_text(insertPhaseStatement, 1, phase.name.c_str(), static_cast(phase.name.length()), nullptr); + sqlite3_bind_text(insertPhaseStatement, + 1, + phase.name.c_str(), + static_cast(phase.name.length()), + nullptr); sqlite3_bind_int64(insertPhaseStatement, 2, static_cast(phase.interval.start.value())); sqlite3_bind_int64(insertPhaseStatement, 3, static_cast(phase.interval.end.value())); - sqlite3_bind_int64(insertPhaseStatement, 4, static_cast(phase.intervalOnDataStrobe.start.value())); - sqlite3_bind_int64(insertPhaseStatement, 5, static_cast(phase.intervalOnDataStrobe.end.value())); + sqlite3_bind_int64( + insertPhaseStatement, 4, static_cast(phase.intervalOnDataStrobe.start.value())); + sqlite3_bind_int64( + insertPhaseStatement, 5, static_cast(phase.intervalOnDataStrobe.end.value())); sqlite3_bind_int(insertPhaseStatement, 6, static_cast(phase.rank)); sqlite3_bind_int(insertPhaseStatement, 7, static_cast(phase.bankGroup)); sqlite3_bind_int(insertPhaseStatement, 8, static_cast(phase.bank)); @@ -491,13 +554,14 @@ void TlmRecorder::insertPhaseInDB(const Transaction::Phase& phase, uint64_t tran executeSqlStatement(insertPhaseStatement); } - -void TlmRecorder::executeSqlStatement(sqlite3_stmt *statement) +void TlmRecorder::executeSqlStatement(sqlite3_stmt* statement) { int errorCode = sqlite3_step(statement); if (errorCode != SQLITE_DONE) - SC_REPORT_FATAL("Error in TraceRecorder", - (std::string("Could not execute statement. Error code: ") + std::to_string(errorCode)).c_str()); + SC_REPORT_FATAL( + "Error in TraceRecorder", + (std::string("Could not execute statement. Error code: ") + std::to_string(errorCode)) + .c_str()); sqlite3_reset(statement); } @@ -506,9 +570,10 @@ void TlmRecorder::executeInitialSqlCommand() { PRINTDEBUGMESSAGE(name, "Creating database by running provided sql script"); - char *errMsg = nullptr; + char* errMsg = nullptr; int rc = sqlite3_exec(db, initialCommand.c_str(), nullptr, nullptr, &errMsg); - if (rc != SQLITE_OK) { + if (rc != SQLITE_OK) + { SC_REPORT_FATAL("SQLITE Error", errMsg); sqlite3_free(errMsg); } @@ -523,8 +588,8 @@ void TlmRecorder::closeConnection() storageThread.join(); std::swap(currentDataBuffer, storageDataBuffer); commitRecordedDataToDB(); - PRINTDEBUGMESSAGE(name, "Number of transactions written to DB: " - + std::to_string(totalNumTransactions)); + PRINTDEBUGMESSAGE( + name, "Number of transactions written to DB: " + std::to_string(totalNumTransactions)); PRINTDEBUGMESSAGE(name, "tlmPhaseRecorder:\tEnd Recording"); sqlite3_close(db); db = nullptr; diff --git a/src/libdramsys/DRAMSys/common/TlmRecorder.h b/src/libdramsys/DRAMSys/common/TlmRecorder.h index 15932e79..df8c2cbc 100644 --- a/src/libdramsys/DRAMSys/common/TlmRecorder.h +++ b/src/libdramsys/DRAMSys/common/TlmRecorder.h @@ -41,9 +41,9 @@ #ifndef TLMRECORDER_H #define TLMRECORDER_H -#include "DRAMSys/configuration/Configuration.h" #include "DRAMSys/common/dramExtensions.h" #include "DRAMSys/common/utils.h" +#include "DRAMSys/configuration/Configuration.h" #include #include @@ -63,32 +63,25 @@ class TlmRecorder { public: TlmRecorder(const std::string& name, const Configuration& config, const std::string& dbName); - TlmRecorder(const TlmRecorder &) = delete; - TlmRecorder(TlmRecorder &&) = default; - TlmRecorder &operator=(const TlmRecorder &) = delete; - TlmRecorder &operator=(TlmRecorder &&) = delete; + TlmRecorder(const TlmRecorder&) = delete; + TlmRecorder(TlmRecorder&&) = default; + TlmRecorder& operator=(const TlmRecorder&) = delete; + TlmRecorder& operator=(TlmRecorder&&) = delete; ~TlmRecorder() = default; - void recordMcConfig(std::string _mcconfig) - { - mcconfig = std::move(_mcconfig); - } + void recordMcConfig(std::string _mcconfig) { mcconfig = std::move(_mcconfig); } - void recordMemspec(std::string _memspec) - { - memspec = std::move(_memspec); - } + void recordMemspec(std::string _memspec) { memspec = std::move(_memspec); } - void recordTraceNames(std::string _traces) - { - traces = std::move(_traces); - } + void recordTraceNames(std::string _traces) { traces = std::move(_traces); } - void recordPhase(tlm::tlm_generic_payload& trans, const tlm::tlm_phase& phase, const sc_core::sc_time& delay); + void recordPhase(tlm::tlm_generic_payload& trans, + const tlm::tlm_phase& phase, + const sc_core::sc_time& delay); void recordPower(double timeInSeconds, double averagePower); - void recordBufferDepth(double timeInSeconds, const std::vector &averageBufferDepth); + void recordBufferDepth(double timeInSeconds, const std::vector& averageBufferDepth); void recordBandwidth(double timeInSeconds, double averageBandwidth); - void recordDebugMessage(const std::string &message, const sc_core::sc_time &time); + void recordDebugMessage(const std::string& message, const sc_core::sc_time& time); void finalize(); private: @@ -98,10 +91,22 @@ private: struct Transaction { - Transaction(uint64_t id, uint64_t address, unsigned int dataLength, char cmd, - const sc_core::sc_time& timeOfGeneration, Thread thread, Channel channel) : - id(id), address(address), dataLength(dataLength), cmd(cmd), timeOfGeneration(timeOfGeneration), - thread(thread), channel(channel) {} + Transaction(uint64_t id, + uint64_t address, + unsigned int dataLength, + char cmd, + const sc_core::sc_time& timeOfGeneration, + Thread thread, + Channel channel) : + id(id), + address(address), + dataLength(dataLength), + cmd(cmd), + timeOfGeneration(timeOfGeneration), + thread(thread), + channel(channel) + { + } uint64_t id = 0; uint64_t address = 0; @@ -114,13 +119,31 @@ private: struct Phase { // for BEGIN_REQ and BEGIN_RESP - Phase(std::string name, const sc_core::sc_time& begin) : name(std::move(name)), - interval(begin, sc_core::SC_ZERO_TIME) {} - Phase(std::string name, TimeInterval interval, TimeInterval intervalOnDataStrobe, Rank rank, - BankGroup bankGroup, Bank bank, Row row, Column column, unsigned int burstLength) : - name(std::move(name)), interval(std::move(interval)), - intervalOnDataStrobe(std::move(intervalOnDataStrobe)), rank(rank), bankGroup(bankGroup), bank(bank), - row(row), column(column), burstLength(burstLength) {} + Phase(std::string name, const sc_core::sc_time& begin) : + name(std::move(name)), + interval(begin, sc_core::SC_ZERO_TIME) + { + } + Phase(std::string name, + TimeInterval interval, + TimeInterval intervalOnDataStrobe, + Rank rank, + BankGroup bankGroup, + Bank bank, + Row row, + Column column, + unsigned int burstLength) : + name(std::move(name)), + interval(std::move(interval)), + intervalOnDataStrobe(std::move(intervalOnDataStrobe)), + rank(rank), + bankGroup(bankGroup), + bank(bank), + row(row), + column(column), + burstLength(burstLength) + { + } std::string name; TimeInterval interval; TimeInterval intervalOnDataStrobe = {sc_core::SC_ZERO_TIME, sc_core::SC_ZERO_TIME}; @@ -138,27 +161,27 @@ private: void prepareSqlStatements(); void executeInitialSqlCommand(); - static void executeSqlStatement(sqlite3_stmt *statement); + static void executeSqlStatement(sqlite3_stmt* statement); - void openDB(const std::string &dbName); + void openDB(const std::string& dbName); void closeConnection(); - void introduceTransactionToSystem(tlm::tlm_generic_payload &trans); - void removeTransactionFromSystem(tlm::tlm_generic_payload &trans); + void introduceTransactionToSystem(tlm::tlm_generic_payload& trans); + void removeTransactionFromSystem(tlm::tlm_generic_payload& trans); void terminateRemainingTransactions(); void commitRecordedDataToDB(); void insertGeneralInfo(); void insertCommandLengths(); void insertTransactionInDB(const Transaction& recordingData); - void insertRangeInDB(uint64_t id, const sc_core::sc_time &begin, const sc_core::sc_time &end); + void insertRangeInDB(uint64_t id, const sc_core::sc_time& begin, const sc_core::sc_time& end); void insertPhaseInDB(const Transaction::Phase& phase, uint64_t transactionID); - void insertDebugMessageInDB(const std::string &message, const sc_core::sc_time &time); + void insertDebugMessageInDB(const std::string& message, const sc_core::sc_time& time); static constexpr unsigned transactionCommitRate = 8192; std::array, 2> recordingDataBuffer; - std::vector *currentDataBuffer; - std::vector *storageDataBuffer; + std::vector* currentDataBuffer; + std::vector* storageDataBuffer; std::thread storageThread; std::unordered_map currentTransactionsInSystem; @@ -166,16 +189,16 @@ private: uint64_t totalNumTransactions = 0; sc_core::sc_time simulationTimeCoveredByRecording; - sqlite3 *db = nullptr; + sqlite3* db = nullptr; sqlite3_stmt *insertTransactionStatement = nullptr, *insertRangeStatement = nullptr, - *updateRangeStatement = nullptr, *insertPhaseStatement = nullptr, *updatePhaseStatement = nullptr, - *insertGeneralInfoStatement = nullptr, *insertCommandLengthsStatement = nullptr, - *insertDebugMessageStatement = nullptr, *insertPowerStatement = nullptr, - *insertBufferDepthStatement = nullptr, *insertBandwidthStatement = nullptr; + *updateRangeStatement = nullptr, *insertPhaseStatement = nullptr, + *updatePhaseStatement = nullptr, *insertGeneralInfoStatement = nullptr, + *insertCommandLengthsStatement = nullptr, *insertDebugMessageStatement = nullptr, + *insertPowerStatement = nullptr, *insertBufferDepthStatement = nullptr, + *insertBandwidthStatement = nullptr; std::string insertTransactionString, insertRangeString, updateRangeString, insertPhaseString, - updatePhaseString, insertGeneralInfoString, insertCommandLengthsString, - insertDebugMessageString, insertPowerString, - insertBufferDepthString, insertBandwidthString; + updatePhaseString, insertGeneralInfoString, insertCommandLengthsString, + insertDebugMessageString, insertPowerString, insertBufferDepthString, insertBandwidthString; std::string initialCommand = R"( DROP TABLE IF EXISTS Phases; diff --git a/src/libdramsys/DRAMSys/common/dramExtensions.cpp b/src/libdramsys/DRAMSys/common/dramExtensions.cpp index 2e2bf907..ccf3403b 100644 --- a/src/libdramsys/DRAMSys/common/dramExtensions.cpp +++ b/src/libdramsys/DRAMSys/common/dramExtensions.cpp @@ -44,12 +44,20 @@ using namespace tlm; namespace DRAMSys { -ArbiterExtension::ArbiterExtension(Thread thread, Channel channel, uint64_t threadPayloadID, +ArbiterExtension::ArbiterExtension(Thread thread, + Channel channel, + uint64_t threadPayloadID, const sc_core::sc_time& timeOfGeneration) : - thread(thread), channel(channel), threadPayloadID(threadPayloadID), timeOfGeneration(timeOfGeneration) -{} + thread(thread), + channel(channel), + threadPayloadID(threadPayloadID), + timeOfGeneration(timeOfGeneration) +{ +} -void ArbiterExtension::setAutoExtension(tlm::tlm_generic_payload& trans, Thread thread, Channel channel) +void ArbiterExtension::setAutoExtension(tlm::tlm_generic_payload& trans, + Thread thread, + Channel channel) { auto* extension = trans.get_extension(); @@ -67,15 +75,19 @@ void ArbiterExtension::setAutoExtension(tlm::tlm_generic_payload& trans, Thread } } -void ArbiterExtension::setExtension(tlm::tlm_generic_payload& trans, Thread thread, Channel channel, - uint64_t threadPayloadID, const sc_core::sc_time& timeOfGeneration) +void ArbiterExtension::setExtension(tlm::tlm_generic_payload& trans, + Thread thread, + Channel channel, + uint64_t threadPayloadID, + const sc_core::sc_time& timeOfGeneration) { assert(trans.get_extension() == nullptr); auto* extension = new ArbiterExtension(thread, channel, threadPayloadID, timeOfGeneration); trans.set_extension(extension); } -void ArbiterExtension::setIDAndTimeOfGeneration(tlm::tlm_generic_payload& trans, uint64_t threadPayloadID, +void ArbiterExtension::setIDAndTimeOfGeneration(tlm::tlm_generic_payload& trans, + uint64_t threadPayloadID, const sc_core::sc_time& timeOfGeneration) { assert(trans.get_extension() != nullptr); @@ -144,14 +156,31 @@ sc_time ArbiterExtension::getTimeOfGeneration(const tlm::tlm_generic_payload& tr return trans.get_extension()->timeOfGeneration; } -ControllerExtension::ControllerExtension(uint64_t channelPayloadID, Rank rank, BankGroup bankGroup, Bank bank, Row row, - Column column, unsigned int burstLength) : - channelPayloadID(channelPayloadID), rank(rank), bankGroup(bankGroup), bank(bank), row(row), column(column), - burstLength(burstLength) -{} +ControllerExtension::ControllerExtension(uint64_t channelPayloadID, + Rank rank, + BankGroup bankGroup, + Bank bank, + Row row, + Column column, + unsigned int burstLength) : + channelPayloadID(channelPayloadID), + rank(rank), + bankGroup(bankGroup), + bank(bank), + row(row), + column(column), + burstLength(burstLength) +{ +} -void ControllerExtension::setAutoExtension(tlm::tlm_generic_payload& trans, uint64_t channelPayloadID, Rank rank, - BankGroup bankGroup, Bank bank, Row row, Column column, unsigned int burstLength) +void ControllerExtension::setAutoExtension(tlm::tlm_generic_payload& trans, + uint64_t channelPayloadID, + Rank rank, + BankGroup bankGroup, + Bank bank, + Row row, + Column column, + unsigned int burstLength) { auto* extension = trans.get_extension(); @@ -167,22 +196,31 @@ void ControllerExtension::setAutoExtension(tlm::tlm_generic_payload& trans, uint } else { - extension = new ControllerExtension(channelPayloadID, rank, bankGroup, bank, row, column, burstLength); + extension = new ControllerExtension( + channelPayloadID, rank, bankGroup, bank, row, column, burstLength); trans.set_auto_extension(extension); } } -void ControllerExtension::setExtension(tlm::tlm_generic_payload& trans, uint64_t channelPayloadID, Rank rank, - BankGroup bankGroup, Bank bank, Row row, Column column, unsigned int burstLength) +void ControllerExtension::setExtension(tlm::tlm_generic_payload& trans, + uint64_t channelPayloadID, + Rank rank, + BankGroup bankGroup, + Bank bank, + Row row, + Column column, + unsigned int burstLength) { assert(trans.get_extension() == nullptr); - auto* extension = new ControllerExtension(channelPayloadID, rank, bankGroup, bank, row, column, burstLength); + auto* extension = + new ControllerExtension(channelPayloadID, rank, bankGroup, bank, row, column, burstLength); trans.set_extension(extension); } tlm_extension_base* ControllerExtension::clone() const { - return new ControllerExtension(channelPayloadID, rank, bankGroup, bank, row, column, burstLength); + return new ControllerExtension( + channelPayloadID, rank, bankGroup, bank, row, column, burstLength); } void ControllerExtension::copy_from(const tlm_extension_base& ext) @@ -293,7 +331,8 @@ tlm::tlm_generic_payload& ChildExtension::getParentTrans(tlm::tlm_generic_payloa return childTrans.get_extension()->getParentTrans(); } -void ChildExtension::setExtension(tlm::tlm_generic_payload& childTrans, tlm::tlm_generic_payload& parentTrans) +void ChildExtension::setExtension(tlm::tlm_generic_payload& childTrans, + tlm::tlm_generic_payload& parentTrans) { auto* extension = childTrans.get_extension(); @@ -324,7 +363,8 @@ void ParentExtension::copy_from(const tlm_extension_base& ext) childTranses = cpyFrom.childTranses; } -void ParentExtension::setExtension(tlm::tlm_generic_payload& parentTrans, std::vector childTranses) +void ParentExtension::setExtension(tlm::tlm_generic_payload& parentTrans, + std::vector childTranses) { auto* extension = parentTrans.get_extension(); @@ -350,8 +390,9 @@ bool ParentExtension::notifyChildTransCompletion() completedChildTranses++; if (completedChildTranses == childTranses.size()) { - std::for_each(childTranses.begin(), childTranses.end(), - [](tlm::tlm_generic_payload* childTrans){childTrans->release();}); + std::for_each(childTranses.begin(), + childTranses.end(), + [](tlm::tlm_generic_payload* childTrans) { childTrans->release(); }); childTranses.clear(); return true; } diff --git a/src/libdramsys/DRAMSys/common/dramExtensions.h b/src/libdramsys/DRAMSys/common/dramExtensions.h index 63765b8d..f6d56f1c 100644 --- a/src/libdramsys/DRAMSys/common/dramExtensions.h +++ b/src/libdramsys/DRAMSys/common/dramExtensions.h @@ -57,7 +57,7 @@ enum class Bank : std::size_t; enum class Row : std::size_t; enum class Column : std::size_t; -template +template class ControllerVector : private std::vector { public: @@ -82,9 +82,13 @@ class ArbiterExtension : public tlm::tlm_extension { public: static void setAutoExtension(tlm::tlm_generic_payload& trans, Thread thread, Channel channel); - static void setExtension(tlm::tlm_generic_payload& trans, Thread thread, Channel channel, - uint64_t threadPayloadID, const sc_core::sc_time& timeOfGeneration); - static void setIDAndTimeOfGeneration(tlm::tlm_generic_payload& trans, uint64_t threadPayloadID, + static void setExtension(tlm::tlm_generic_payload& trans, + Thread thread, + Channel channel, + uint64_t threadPayloadID, + const sc_core::sc_time& timeOfGeneration); + static void setIDAndTimeOfGeneration(tlm::tlm_generic_payload& trans, + uint64_t threadPayloadID, const sc_core::sc_time& timeOfGeneration); [[nodiscard]] tlm::tlm_extension_base* clone() const override; @@ -102,7 +106,10 @@ public: static sc_core::sc_time getTimeOfGeneration(const tlm::tlm_generic_payload& trans); private: - ArbiterExtension(Thread thread, Channel channel, uint64_t threadPayloadID, const sc_core::sc_time& timeOfGeneration); + ArbiterExtension(Thread thread, + Channel channel, + uint64_t threadPayloadID, + const sc_core::sc_time& timeOfGeneration); Thread thread; Channel channel; uint64_t threadPayloadID; @@ -112,13 +119,25 @@ private: class ControllerExtension : public tlm::tlm_extension { public: - static void setAutoExtension(tlm::tlm_generic_payload& trans, uint64_t channelPayloadID, Rank rank, BankGroup bankGroup, - Bank bank, Row row, Column column, unsigned burstLength); + static void setAutoExtension(tlm::tlm_generic_payload& trans, + uint64_t channelPayloadID, + Rank rank, + BankGroup bankGroup, + Bank bank, + Row row, + Column column, + unsigned burstLength); - static void setExtension(tlm::tlm_generic_payload& trans, uint64_t channelPayloadID, Rank rank, BankGroup bankGroup, - Bank bank, Row row, Column column, unsigned burstLength); + static void setExtension(tlm::tlm_generic_payload& trans, + uint64_t channelPayloadID, + Rank rank, + BankGroup bankGroup, + Bank bank, + Row row, + Column column, + unsigned burstLength); - //static ControllerExtension& getExtension(const tlm::tlm_generic_payload& trans); + // static ControllerExtension& getExtension(const tlm::tlm_generic_payload& trans); [[nodiscard]] tlm::tlm_extension_base* clone() const override; void copy_from(const tlm::tlm_extension_base& ext) override; @@ -141,7 +160,12 @@ public: static unsigned getBurstLength(const tlm::tlm_generic_payload& trans); private: - ControllerExtension(uint64_t channelPayloadID, Rank rank, BankGroup bankGroup, Bank bank, Row row, Column column, + ControllerExtension(uint64_t channelPayloadID, + Rank rank, + BankGroup bankGroup, + Bank bank, + Row row, + Column column, unsigned burstLength); uint64_t channelPayloadID; Rank rank; @@ -159,13 +183,14 @@ private: explicit ChildExtension(tlm::tlm_generic_payload& parentTrans) : parentTrans(&parentTrans) {} public: - //ChildExtension() = delete; + // ChildExtension() = delete; [[nodiscard]] tlm::tlm_extension_base* clone() const override; void copy_from(const tlm::tlm_extension_base& ext) override; tlm::tlm_generic_payload& getParentTrans(); static tlm::tlm_generic_payload& getParentTrans(tlm::tlm_generic_payload& childTrans); - static void setExtension(tlm::tlm_generic_payload& childTrans, tlm::tlm_generic_payload& parentTrans); + static void setExtension(tlm::tlm_generic_payload& childTrans, + tlm::tlm_generic_payload& parentTrans); static bool isChildTrans(const tlm::tlm_generic_payload& trans); }; @@ -174,15 +199,18 @@ class ParentExtension : public tlm::tlm_extension private: std::vector childTranses; unsigned completedChildTranses = 0; - explicit ParentExtension(std::vector _childTranses) - : childTranses(std::move(_childTranses)) {} + explicit ParentExtension(std::vector _childTranses) : + childTranses(std::move(_childTranses)) + { + } public: ParentExtension() = delete; [[nodiscard]] tlm_extension_base* clone() const override; void copy_from(const tlm_extension_base& ext) override; - static void setExtension(tlm::tlm_generic_payload& parentTrans, std::vector childTranses); + static void setExtension(tlm::tlm_generic_payload& parentTrans, + std::vector childTranses); const std::vector& getChildTranses(); bool notifyChildTransCompletion(); static bool notifyChildTransCompletion(tlm::tlm_generic_payload& trans); @@ -191,12 +219,9 @@ public: class EccExtension : public tlm::tlm_extension { public: - [[nodiscard]] tlm_extension_base* clone() const override - { - return new EccExtension; - } + [[nodiscard]] tlm_extension_base* clone() const override { return new EccExtension; } - void copy_from([[maybe_unused]] tlm_extension_base const & ext) override {} + void copy_from([[maybe_unused]] tlm_extension_base const& ext) override {} }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/common/utils.cpp b/src/libdramsys/DRAMSys/common/utils.cpp index 3eb03d4a..c0400fab 100644 --- a/src/libdramsys/DRAMSys/common/utils.cpp +++ b/src/libdramsys/DRAMSys/common/utils.cpp @@ -47,33 +47,36 @@ using namespace tlm; namespace DRAMSys { -bool TimeInterval::timeIsInInterval(const sc_time &time) const +bool TimeInterval::timeIsInInterval(const sc_time& time) const { return (start < time && time < end); } -bool TimeInterval::intersects(const TimeInterval &other) const +bool TimeInterval::intersects(const TimeInterval& other) const { - return other.timeIsInInterval(this->start) - || this->timeIsInInterval(other.start); + return other.timeIsInInterval(this->start) || this->timeIsInInterval(other.start); } sc_time TimeInterval::getLength() const { if (start > end) return start - end; - + return end - start; } -std::string getPhaseName(const tlm_phase &phase) +std::string getPhaseName(const tlm_phase& phase) { std::ostringstream oss; oss << phase; return oss.str(); } -void setUpDummy(tlm_generic_payload &payload, uint64_t channelPayloadID, Rank rank, BankGroup bankGroup, Bank bank) +void setUpDummy(tlm_generic_payload& payload, + uint64_t channelPayloadID, + Rank rank, + BankGroup bankGroup, + Bank bank) { payload.set_address(0); payload.set_command(TLM_IGNORE_COMMAND); @@ -82,7 +85,8 @@ void setUpDummy(tlm_generic_payload &payload, uint64_t channelPayloadID, Rank ra payload.set_dmi_allowed(false); payload.set_byte_enable_length(0); payload.set_streaming_width(0); - ControllerExtension::setExtension(payload, channelPayloadID, rank, bankGroup, bank, Row(0), Column(0), 0); + ControllerExtension::setExtension( + payload, channelPayloadID, rank, bankGroup, bank, Row(0), Column(0), 0); ArbiterExtension::setExtension(payload, Thread(UINT_MAX), Channel(0), 0, SC_ZERO_TIME); } diff --git a/src/libdramsys/DRAMSys/common/utils.h b/src/libdramsys/DRAMSys/common/utils.h index 85d2da3e..0544a738 100644 --- a/src/libdramsys/DRAMSys/common/utils.h +++ b/src/libdramsys/DRAMSys/common/utils.h @@ -42,9 +42,9 @@ #include "DRAMSys/common/dramExtensions.h" +#include #include #include -#include namespace DRAMSys { @@ -54,20 +54,27 @@ class TimeInterval public: sc_core::sc_time start, end; TimeInterval() : start(sc_core::SC_ZERO_TIME), end(sc_core::SC_ZERO_TIME) {} - TimeInterval(const sc_core::sc_time& start, const sc_core::sc_time& end) : start(start), end(end) {} + TimeInterval(const sc_core::sc_time& start, const sc_core::sc_time& end) : + start(start), + end(end) + { + } [[nodiscard]] sc_core::sc_time getLength() const; - [[nodiscard]] bool timeIsInInterval(const sc_core::sc_time &time) const; - [[nodiscard]] bool intersects(const TimeInterval &other) const; + [[nodiscard]] bool timeIsInInterval(const sc_core::sc_time& time) const; + [[nodiscard]] bool intersects(const TimeInterval& other) const; }; constexpr const std::string_view headline = "==========================================================================="; -std::string getPhaseName(const tlm::tlm_phase &phase); +std::string getPhaseName(const tlm::tlm_phase& phase); -void setUpDummy(tlm::tlm_generic_payload &payload, uint64_t channelPayloadID, - Rank rank = Rank(0), BankGroup bankGroup = BankGroup(0), Bank bank = Bank(0)); +void setUpDummy(tlm::tlm_generic_payload& payload, + uint64_t channelPayloadID, + Rank rank = Rank(0), + BankGroup bankGroup = BankGroup(0), + Bank bank = Bank(0)); bool isFullCycle(sc_core::sc_time time, sc_core::sc_time cycleTime); sc_core::sc_time alignAtNext(sc_core::sc_time time, sc_core::sc_time alignment); diff --git a/src/libdramsys/DRAMSys/configuration/Configuration.cpp b/src/libdramsys/DRAMSys/configuration/Configuration.cpp index b13d4bc6..ce98efc9 100644 --- a/src/libdramsys/DRAMSys/configuration/Configuration.cpp +++ b/src/libdramsys/DRAMSys/configuration/Configuration.cpp @@ -43,14 +43,14 @@ #include "DRAMSys/configuration/memspec/MemSpecDDR3.h" #include "DRAMSys/configuration/memspec/MemSpecDDR4.h" -#include "DRAMSys/configuration/memspec/MemSpecWideIO.h" -#include "DRAMSys/configuration/memspec/MemSpecLPDDR4.h" -#include "DRAMSys/configuration/memspec/MemSpecWideIO2.h" -#include "DRAMSys/configuration/memspec/MemSpecHBM2.h" #include "DRAMSys/configuration/memspec/MemSpecGDDR5.h" #include "DRAMSys/configuration/memspec/MemSpecGDDR5X.h" #include "DRAMSys/configuration/memspec/MemSpecGDDR6.h" +#include "DRAMSys/configuration/memspec/MemSpecHBM2.h" +#include "DRAMSys/configuration/memspec/MemSpecLPDDR4.h" #include "DRAMSys/configuration/memspec/MemSpecSTTMRAM.h" +#include "DRAMSys/configuration/memspec/MemSpecWideIO.h" +#include "DRAMSys/configuration/memspec/MemSpecWideIO2.h" #ifdef DDR5_SIM #include "DRAMSys/configuration/memspec/MemSpecDDR5.h" @@ -67,7 +67,7 @@ using namespace sc_core; namespace DRAMSys { -enum sc_time_unit string2TimeUnit(const std::string &s) +enum sc_time_unit string2TimeUnit(const std::string& s) { if (s == "s") return SC_SEC; @@ -87,12 +87,11 @@ enum sc_time_unit string2TimeUnit(const std::string &s) if (s == "fs") return SC_FS; - SC_REPORT_FATAL("Configuration", - ("Could not convert to enum sc_time_unit: " + s).c_str()); + SC_REPORT_FATAL("Configuration", ("Could not convert to enum sc_time_unit: " + s).c_str()); throw; } -void Configuration::loadSimConfig(const DRAMSys::Config::SimConfig &simConfig) +void Configuration::loadSimConfig(const DRAMSys::Config::SimConfig& simConfig) { addressOffset = simConfig.AddressOffset.value_or(addressOffset); checkTLM2Protocol = simConfig.CheckTLM2Protocol.value_or(checkTLM2Protocol); @@ -103,7 +102,7 @@ void Configuration::loadSimConfig(const DRAMSys::Config::SimConfig &simConfig) simulationProgressBar = simConfig.SimulationProgressBar.value_or(simulationProgressBar); useMalloc = simConfig.UseMalloc.value_or(useMalloc); - if (const auto &_storeMode = simConfig.StoreMode) + if (const auto& _storeMode = simConfig.StoreMode) storeMode = [=] { switch (*_storeMode) @@ -120,18 +119,19 @@ void Configuration::loadSimConfig(const DRAMSys::Config::SimConfig &simConfig) windowSize = simConfig.WindowSize.value_or(windowSize); if (windowSize == 0) - SC_REPORT_FATAL("Configuration", "Minimum window size is 1"); + SC_REPORT_FATAL("Configuration", "Minimum window size is 1"); powerAnalysis = simConfig.PowerAnalysis.value_or(powerAnalysis); #ifndef DRAMPOWER if (powerAnalysis) - SC_REPORT_FATAL("Configuration", "Power analysis is only supported with included DRAMPower library!"); + SC_REPORT_FATAL("Configuration", + "Power analysis is only supported with included DRAMPower library!"); #endif } -void Configuration::loadMCConfig(const DRAMSys::Config::McConfig &mcConfig) +void Configuration::loadMCConfig(const DRAMSys::Config::McConfig& mcConfig) { - if (const auto &_pagePolicy = mcConfig.PagePolicy) + if (const auto& _pagePolicy = mcConfig.PagePolicy) pagePolicy = [=] { switch (*_pagePolicy) @@ -150,7 +150,7 @@ void Configuration::loadMCConfig(const DRAMSys::Config::McConfig &mcConfig) } }(); - if (const auto &_scheduler = mcConfig.Scheduler) + if (const auto& _scheduler = mcConfig.Scheduler) scheduler = [=] { switch (*_scheduler) @@ -171,7 +171,7 @@ void Configuration::loadMCConfig(const DRAMSys::Config::McConfig &mcConfig) } }(); - if (const auto &_schedulerBuffer = mcConfig.SchedulerBuffer) + if (const auto& _schedulerBuffer = mcConfig.SchedulerBuffer) schedulerBuffer = [=] { switch (*_schedulerBuffer) @@ -188,7 +188,7 @@ void Configuration::loadMCConfig(const DRAMSys::Config::McConfig &mcConfig) } }(); - if (const auto &_cmdMux = mcConfig.CmdMux) + if (const auto& _cmdMux = mcConfig.CmdMux) cmdMux = [=] { switch (*_cmdMux) @@ -203,7 +203,7 @@ void Configuration::loadMCConfig(const DRAMSys::Config::McConfig &mcConfig) } }(); - if (const auto &_respQueue = mcConfig.RespQueue) + if (const auto& _respQueue = mcConfig.RespQueue) respQueue = [=] { switch (*_respQueue) @@ -218,7 +218,7 @@ void Configuration::loadMCConfig(const DRAMSys::Config::McConfig &mcConfig) } }(); - if (const auto &_refreshPolicy = mcConfig.RefreshPolicy) + if (const auto& _refreshPolicy = mcConfig.RefreshPolicy) refreshPolicy = [=] { switch (*_refreshPolicy) @@ -239,7 +239,7 @@ void Configuration::loadMCConfig(const DRAMSys::Config::McConfig &mcConfig) } }(); - if (const auto &_powerDownPolicy = mcConfig.PowerDownPolicy) + if (const auto& _powerDownPolicy = mcConfig.PowerDownPolicy) powerDownPolicy = [=] { switch (*_powerDownPolicy) @@ -254,7 +254,7 @@ void Configuration::loadMCConfig(const DRAMSys::Config::McConfig &mcConfig) } }(); - if (const auto &_arbiter = mcConfig.Arbiter) + if (const auto& _arbiter = mcConfig.Arbiter) arbiter = [=] { switch (*_arbiter) @@ -284,46 +284,50 @@ void Configuration::loadMCConfig(const DRAMSys::Config::McConfig &mcConfig) if (const auto& _arbitrationDelayFw = mcConfig.ArbitrationDelayFw) { - arbitrationDelayFw = std::round(sc_time(*_arbitrationDelayFw, SC_NS) / memSpec->tCK) * memSpec->tCK; + arbitrationDelayFw = + std::round(sc_time(*_arbitrationDelayFw, SC_NS) / memSpec->tCK) * memSpec->tCK; } if (const auto& _arbitrationDelayBw = mcConfig.ArbitrationDelayBw) { - arbitrationDelayBw = std::round(sc_time(*_arbitrationDelayBw, SC_NS) / memSpec->tCK) * memSpec->tCK; + arbitrationDelayBw = + std::round(sc_time(*_arbitrationDelayBw, SC_NS) / memSpec->tCK) * memSpec->tCK; } if (const auto& _thinkDelayFw = mcConfig.ThinkDelayFw) { - thinkDelayFw = std::round(sc_time(*_thinkDelayFw, SC_NS) / memSpec->tCK) * memSpec->tCK; + thinkDelayFw = std::round(sc_time(*_thinkDelayFw, SC_NS) / memSpec->tCK) * memSpec->tCK; } if (const auto& _thinkDelayBw = mcConfig.ThinkDelayBw) { - thinkDelayBw = std::round(sc_time(*_thinkDelayBw, SC_NS) / memSpec->tCK) * memSpec->tCK; + thinkDelayBw = std::round(sc_time(*_thinkDelayBw, SC_NS) / memSpec->tCK) * memSpec->tCK; } if (const auto& _phyDelayFw = mcConfig.PhyDelayFw) { - phyDelayFw = std::round(sc_time(*_phyDelayFw, SC_NS) / memSpec->tCK) * memSpec->tCK; + phyDelayFw = std::round(sc_time(*_phyDelayFw, SC_NS) / memSpec->tCK) * memSpec->tCK; } if (const auto& _phyDelayBw = mcConfig.PhyDelayBw) { - phyDelayBw = std::round(sc_time(*_phyDelayBw, SC_NS) / memSpec->tCK) * memSpec->tCK; + phyDelayBw = std::round(sc_time(*_phyDelayBw, SC_NS) / memSpec->tCK) * memSpec->tCK; } { auto _blockingReadDelay = mcConfig.BlockingReadDelay.value_or(60); - blockingReadDelay = std::round(sc_time(_blockingReadDelay, SC_NS) / memSpec->tCK) * memSpec->tCK; + blockingReadDelay = + std::round(sc_time(_blockingReadDelay, SC_NS) / memSpec->tCK) * memSpec->tCK; } { auto _blockingWriteDelay = mcConfig.BlockingWriteDelay.value_or(60); - blockingWriteDelay = std::round(sc_time(_blockingWriteDelay, SC_NS) / memSpec->tCK) * memSpec->tCK; + blockingWriteDelay = + std::round(sc_time(_blockingWriteDelay, SC_NS) / memSpec->tCK) * memSpec->tCK; } } -void Configuration::loadMemSpec(const DRAMSys::Config::MemSpec &memSpecConfig) +void Configuration::loadMemSpec(const DRAMSys::Config::MemSpec& memSpecConfig) { std::string memoryType = memSpecConfig.memoryType; diff --git a/src/libdramsys/DRAMSys/configuration/Configuration.h b/src/libdramsys/DRAMSys/configuration/Configuration.h index 55700028..db9c85ee 100644 --- a/src/libdramsys/DRAMSys/configuration/Configuration.h +++ b/src/libdramsys/DRAMSys/configuration/Configuration.h @@ -43,11 +43,11 @@ #ifndef CONFIGURATION_H #define CONFIGURATION_H -#include "DRAMSys/configuration/memspec/MemSpec.h" #include "DRAMSys/config/DRAMSysConfiguration.h" +#include "DRAMSys/configuration/memspec/MemSpec.h" -#include #include +#include namespace DRAMSys { @@ -56,19 +56,61 @@ class Configuration { public: // MCConfig: - enum class PagePolicy {Open, Closed, OpenAdaptive, ClosedAdaptive} pagePolicy = PagePolicy::Open; - enum class Scheduler {Fifo, FrFcfs, FrFcfsGrp, GrpFrFcfs, GrpFrFcfsWm} scheduler = Scheduler::FrFcfs; - enum class SchedulerBuffer {Bankwise, ReadWrite, Shared} schedulerBuffer = SchedulerBuffer::Bankwise; + enum class PagePolicy + { + Open, + Closed, + OpenAdaptive, + ClosedAdaptive + } pagePolicy = PagePolicy::Open; + enum class Scheduler + { + Fifo, + FrFcfs, + FrFcfsGrp, + GrpFrFcfs, + GrpFrFcfsWm + } scheduler = Scheduler::FrFcfs; + enum class SchedulerBuffer + { + Bankwise, + ReadWrite, + Shared + } schedulerBuffer = SchedulerBuffer::Bankwise; unsigned int lowWatermark = 0; unsigned int highWatermark = 0; - enum class CmdMux {Oldest, Strict} cmdMux = CmdMux::Oldest; - enum class RespQueue {Fifo, Reorder} respQueue = RespQueue::Fifo; - enum class Arbiter {Simple, Fifo, Reorder} arbiter = Arbiter::Simple; + enum class CmdMux + { + Oldest, + Strict + } cmdMux = CmdMux::Oldest; + enum class RespQueue + { + Fifo, + Reorder + } respQueue = RespQueue::Fifo; + enum class Arbiter + { + Simple, + Fifo, + Reorder + } arbiter = Arbiter::Simple; unsigned int requestBufferSize = 8; - enum class RefreshPolicy {NoRefresh, PerBank, Per2Bank, SameBank, AllBank} refreshPolicy = RefreshPolicy::AllBank; + enum class RefreshPolicy + { + NoRefresh, + PerBank, + Per2Bank, + SameBank, + AllBank + } refreshPolicy = RefreshPolicy::AllBank; unsigned int refreshMaxPostponed = 0; unsigned int refreshMaxPulledin = 0; - enum class PowerDownPolicy {NoPowerDown, Staggered} powerDownPolicy = PowerDownPolicy::NoPowerDown; + enum class PowerDownPolicy + { + NoPowerDown, + Staggered + } powerDownPolicy = PowerDownPolicy::NoPowerDown; unsigned int maxActiveTransactions = 64; bool refreshManagement = false; sc_core::sc_time arbitrationDelayFw = sc_core::SC_ZERO_TIME; @@ -92,7 +134,11 @@ public: bool useMalloc = false; unsigned long long int addressOffset = 0; - enum class StoreMode {NoStorage, Store} storeMode = StoreMode::NoStorage; + enum class StoreMode + { + NoStorage, + Store + } storeMode = StoreMode::NoStorage; // MemSpec (from DRAM-Power) std::unique_ptr memSpec; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp index 2c9dc0a1..54e8599f 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp @@ -1,38 +1,38 @@ /* -* Copyright (c) 2015, RPTU Kaiserslautern-Landau -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are -* met: -* -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its -* contributors may be used to endorse or promote products derived from -* this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER -* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* Authors: -* Lukas Steiner -* Derek Christ -*/ + * Copyright (c) 2015, RPTU Kaiserslautern-Landau + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + * Derek Christ + */ #include "MemSpec.h" @@ -43,13 +43,17 @@ namespace DRAMSys { MemSpec::MemSpec(const DRAMSys::Config::MemSpec& memSpec, - MemoryType memoryType, - unsigned numberOfChannels, unsigned pseudoChannelsPerChannel, - unsigned ranksPerChannel, unsigned banksPerRank, - unsigned groupsPerRank, unsigned banksPerGroup, - unsigned banksPerChannel, unsigned bankGroupsPerChannel, - unsigned devicesPerRank) - : numberOfChannels(numberOfChannels), + MemoryType memoryType, + unsigned numberOfChannels, + unsigned pseudoChannelsPerChannel, + unsigned ranksPerChannel, + unsigned banksPerRank, + unsigned groupsPerRank, + unsigned banksPerGroup, + unsigned banksPerChannel, + unsigned bankGroupsPerChannel, + unsigned devicesPerRank) : + numberOfChannels(numberOfChannels), pseudoChannelsPerChannel(pseudoChannelsPerChannel), ranksPerChannel(ranksPerChannel), banksPerRank(banksPerRank), @@ -62,21 +66,21 @@ MemSpec::MemSpec(const DRAMSys::Config::MemSpec& memSpec, columnsPerRow(memSpec.memarchitecturespec.entries.at("nbrOfColumns")), defaultBurstLength(memSpec.memarchitecturespec.entries.at("burstLength")), maxBurstLength(memSpec.memarchitecturespec.entries.find("maxBurstLength") != - memSpec.memarchitecturespec.entries.end() - ? memSpec.memarchitecturespec.entries.at("maxBurstLength") - : defaultBurstLength), + memSpec.memarchitecturespec.entries.end() + ? memSpec.memarchitecturespec.entries.at("maxBurstLength") + : defaultBurstLength), dataRate(memSpec.memarchitecturespec.entries.at("dataRate")), bitWidth(memSpec.memarchitecturespec.entries.at("width")), - dataBusWidth(bitWidth* devicesPerRank), + dataBusWidth(bitWidth * devicesPerRank), bytesPerBeat(dataBusWidth / 8), - defaultBytesPerBurst((defaultBurstLength* dataBusWidth) / 8), - maxBytesPerBurst((maxBurstLength* dataBusWidth) / 8), + defaultBytesPerBurst((defaultBurstLength * dataBusWidth) / 8), + maxBytesPerBurst((maxBurstLength * dataBusWidth) / 8), fCKMHz(memSpec.memtimingspec.entries.at("clkMhz")), tCK(sc_time(1.0 / fCKMHz, SC_US)), memoryId(memSpec.memoryId), memoryType(memoryType), - burstDuration(tCK* (static_cast(defaultBurstLength) / dataRate)) - + burstDuration(tCK * (static_cast(defaultBurstLength) / dataRate)) + { commandLengthInCycles = std::vector(Command::numberOfCommands(), 1); } diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h index 31ab977c..5749a1b8 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h @@ -1,52 +1,52 @@ /* -* Copyright (c) 2015, RPTU Kaiserslautern-Landau -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are -* met: -* -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its -* contributors may be used to endorse or promote products derived from -* this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER -* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* Authors: -* Janik Schlemminger -* Matthias Jung -* Lukas Steiner -* Derek Christ -*/ + * Copyright (c) 2015, RPTU Kaiserslautern-Landau + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Janik Schlemminger + * Matthias Jung + * Lukas Steiner + * Derek Christ + */ #ifndef MEMSPEC_H #define MEMSPEC_H -#include "DRAMSys/config/DRAMSysConfiguration.h" #include "DRAMSys/common/utils.h" +#include "DRAMSys/config/DRAMSysConfiguration.h" #include "DRAMSys/controller/Command.h" +#include #include #include #include -#include namespace DRAMSys { @@ -54,8 +54,8 @@ namespace DRAMSys class MemSpec { public: - MemSpec &operator=(const MemSpec &) = delete; - MemSpec &operator=(MemSpec &&) = delete; + MemSpec& operator=(const MemSpec&) = delete; + MemSpec& operator=(MemSpec&&) = delete; virtual ~MemSpec() = default; const unsigned numberOfChannels; @@ -84,8 +84,19 @@ public: const std::string memoryId; const enum class MemoryType { - DDR3, DDR4, DDR5, LPDDR4, LPDDR5, WideIO, - WideIO2, GDDR5, GDDR5X, GDDR6, HBM2, HBM3, STTMRAM + DDR3, + DDR4, + DDR5, + LPDDR4, + LPDDR5, + WideIO, + WideIO2, + GDDR5, + GDDR5X, + GDDR6, + HBM2, + HBM3, + STTMRAM } memoryType; [[nodiscard]] virtual sc_core::sc_time getRefreshIntervalAB() const; @@ -101,8 +112,10 @@ public: [[nodiscard]] virtual bool hasRasAndCasBus() const; - [[nodiscard]] virtual sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload& payload) const = 0; - [[nodiscard]] virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload& payload) const = 0; + [[nodiscard]] virtual sc_core::sc_time + getExecutionTime(Command command, const tlm::tlm_generic_payload& payload) const = 0; + [[nodiscard]] virtual TimeInterval + getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload& payload) const = 0; [[nodiscard]] virtual bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const; [[nodiscard]] sc_core::sc_time getCommandLength(Command command) const; @@ -111,17 +124,21 @@ public: protected: MemSpec(const DRAMSys::Config::MemSpec& memSpec, - MemoryType memoryType, - unsigned numberOfChannels, unsigned pseudoChannelsPerChannel, - unsigned ranksPerChannel, unsigned banksPerRank, - unsigned groupsPerRank, unsigned banksPerGroup, - unsigned banksPerChannel, unsigned bankGroupsPerChannel, - unsigned devicesPerRank); + MemoryType memoryType, + unsigned numberOfChannels, + unsigned pseudoChannelsPerChannel, + unsigned ranksPerChannel, + unsigned banksPerRank, + unsigned groupsPerRank, + unsigned banksPerGroup, + unsigned banksPerChannel, + unsigned bankGroupsPerChannel, + unsigned devicesPerRank); [[nodiscard]] static bool allBytesEnabled(const tlm::tlm_generic_payload& trans); - MemSpec(const MemSpec &) = default; - MemSpec(MemSpec &&) = default; + MemSpec(const MemSpec&) = default; + MemSpec(MemSpec&&) = default; // Command lengths in cycles on bus, usually one clock cycle std::vector commandLengthInCycles; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp index 9f486e65..b830b971 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp @@ -46,59 +46,64 @@ using namespace tlm; namespace DRAMSys { -MemSpecDDR3::MemSpecDDR3(const DRAMSys::Config::MemSpec &memSpec) - : MemSpec(memSpec, MemoryType::DDR3, - memSpec.memarchitecturespec.entries.at("nbrOfChannels"), - 1, - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks"), - 1, - memSpec.memarchitecturespec.entries.at("nbrOfBanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks") - * memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfDevices")), - tCKE (tCK * memSpec.memtimingspec.entries.at("CKE")), - tPD (tCKE), - tCKESR (tCK * memSpec.memtimingspec.entries.at("CKESR")), - tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")), - tRC (tCK * memSpec.memtimingspec.entries.at("RC")), - tRCD (tCK * memSpec.memtimingspec.entries.at("RCD")), - tRL (tCK * memSpec.memtimingspec.entries.at("RL")), - tRTP (tCK * memSpec.memtimingspec.entries.at("RTP")), - tWL (tCK * memSpec.memtimingspec.entries.at("WL")), - tWR (tCK * memSpec.memtimingspec.entries.at("WR")), - tXP (tCK * memSpec.memtimingspec.entries.at("XP")), - tXS (tCK * memSpec.memtimingspec.entries.at("XS")), - tREFI (tCK * memSpec.memtimingspec.entries.at("REFI")), - tRFC (tCK * memSpec.memtimingspec.entries.at("RFC")), - tRP (tCK * memSpec.memtimingspec.entries.at("RP")), - tDQSCK (tCK * memSpec.memtimingspec.entries.at("DQSCK")), - tCCD (tCK * memSpec.memtimingspec.entries.at("CCD")), - tFAW (tCK * memSpec.memtimingspec.entries.at("FAW")), - tRRD (tCK * memSpec.memtimingspec.entries.at("RRD")), - tWTR (tCK * memSpec.memtimingspec.entries.at("WTR")), - tXPDLL (tCK * memSpec.memtimingspec.entries.at("XPDLL")), - tXSDLL (tCK * memSpec.memtimingspec.entries.at("XSDLL")), - tAL (tCK * memSpec.memtimingspec.entries.at("AL")), - tACTPDEN (tCK * memSpec.memtimingspec.entries.at("ACTPDEN")), - tPRPDEN (tCK * memSpec.memtimingspec.entries.at("PRPDEN")), - tREFPDEN (tCK * memSpec.memtimingspec.entries.at("REFPDEN")), - tRTRS (tCK * memSpec.memtimingspec.entries.at("RTRS")), - iDD0 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd0") : 0), - iDD2N (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2n") : 0), - iDD3N (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3n") : 0), - iDD4R (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd4r") : 0), - iDD4W (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd4w") : 0), - iDD5 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd5") : 0), - iDD6 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd6") : 0), - vDD (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("vdd") : 0), - iDD2P0 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2p0") : 0), - iDD2P1 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2p1") : 0), - iDD3P0 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3p0") : 0), - iDD3P1 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3p1") : 0) +MemSpecDDR3::MemSpecDDR3(const DRAMSys::Config::MemSpec& memSpec) : + MemSpec(memSpec, + MemoryType::DDR3, + memSpec.memarchitecturespec.entries.at("nbrOfChannels"), + 1, + memSpec.memarchitecturespec.entries.at("nbrOfRanks"), + memSpec.memarchitecturespec.entries.at("nbrOfBanks"), + 1, + memSpec.memarchitecturespec.entries.at("nbrOfBanks"), + memSpec.memarchitecturespec.entries.at("nbrOfBanks") * + memSpec.memarchitecturespec.entries.at("nbrOfRanks"), + memSpec.memarchitecturespec.entries.at("nbrOfRanks"), + memSpec.memarchitecturespec.entries.at("nbrOfDevices")), + tCKE(tCK * memSpec.memtimingspec.entries.at("CKE")), + tPD(tCKE), + tCKESR(tCK * memSpec.memtimingspec.entries.at("CKESR")), + tRAS(tCK * memSpec.memtimingspec.entries.at("RAS")), + tRC(tCK * memSpec.memtimingspec.entries.at("RC")), + tRCD(tCK * memSpec.memtimingspec.entries.at("RCD")), + tRL(tCK * memSpec.memtimingspec.entries.at("RL")), + tRTP(tCK * memSpec.memtimingspec.entries.at("RTP")), + tWL(tCK * memSpec.memtimingspec.entries.at("WL")), + tWR(tCK * memSpec.memtimingspec.entries.at("WR")), + tXP(tCK * memSpec.memtimingspec.entries.at("XP")), + tXS(tCK * memSpec.memtimingspec.entries.at("XS")), + tREFI(tCK * memSpec.memtimingspec.entries.at("REFI")), + tRFC(tCK * memSpec.memtimingspec.entries.at("RFC")), + tRP(tCK * memSpec.memtimingspec.entries.at("RP")), + tDQSCK(tCK * memSpec.memtimingspec.entries.at("DQSCK")), + tCCD(tCK * memSpec.memtimingspec.entries.at("CCD")), + tFAW(tCK * memSpec.memtimingspec.entries.at("FAW")), + tRRD(tCK * memSpec.memtimingspec.entries.at("RRD")), + tWTR(tCK * memSpec.memtimingspec.entries.at("WTR")), + tXPDLL(tCK * memSpec.memtimingspec.entries.at("XPDLL")), + tXSDLL(tCK * memSpec.memtimingspec.entries.at("XSDLL")), + tAL(tCK * memSpec.memtimingspec.entries.at("AL")), + tACTPDEN(tCK * memSpec.memtimingspec.entries.at("ACTPDEN")), + tPRPDEN(tCK * memSpec.memtimingspec.entries.at("PRPDEN")), + tREFPDEN(tCK * memSpec.memtimingspec.entries.at("REFPDEN")), + tRTRS(tCK * memSpec.memtimingspec.entries.at("RTRS")), + iDD0(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd0") : 0), + iDD2N(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2n") : 0), + iDD3N(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3n") : 0), + iDD4R(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd4r") : 0), + iDD4W(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd4w") : 0), + iDD5(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd5") : 0), + iDD6(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd6") : 0), + vDD(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("vdd") : 0), + iDD2P0(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2p0") + : 0), + iDD2P1(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2p1") + : 0), + iDD3P0(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3p0") + : 0), + iDD3P1(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3p1") : 0) { - uint64_t deviceSizeBits = static_cast(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth; + uint64_t deviceSizeBits = + static_cast(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth; uint64_t deviceSizeBytes = deviceSizeBits / 8; memorySizeBytes = deviceSizeBytes * devicesPerRank * ranksPerChannel * numberOfChannels; @@ -107,16 +112,17 @@ MemSpecDDR3::MemSpecDDR3(const DRAMSys::Config::MemSpec &memSpec) std::cout << headline << std::endl; std::cout << "Memory Configuration:" << std::endl << std::endl; - std::cout << " Memory type: " << "DDR3" << std::endl; - std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl; + std::cout << " Memory type: " + << "DDR3" << std::endl; + std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl; std::cout << " Channels: " << numberOfChannels << std::endl; std::cout << " Ranks per channel: " << ranksPerChannel << std::endl; - std::cout << " Banks per rank: " << banksPerRank << std::endl; + std::cout << " Banks per rank: " << banksPerRank << std::endl; std::cout << " Rows per bank: " << rowsPerBank << std::endl; std::cout << " Columns per row: " << columnsPerRow << std::endl; - std::cout << " Device width in bits: " << bitWidth << std::endl; - std::cout << " Device size in bits: " << deviceSizeBits << std::endl; - std::cout << " Device size in bytes: " << deviceSizeBytes << std::endl; + std::cout << " Device width in bits: " << bitWidth << std::endl; + std::cout << " Device size in bits: " << deviceSizeBits << std::endl; + std::cout << " Device size in bytes: " << deviceSizeBytes << std::endl; std::cout << " Devices per rank: " << devicesPerRank << std::endl; std::cout << std::endl; } @@ -127,7 +133,8 @@ sc_time MemSpecDDR3::getRefreshIntervalAB() const } // Returns the execution time for commands that have a fixed execution time -sc_time MemSpecDDR3::getExecutionTime(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const +sc_time MemSpecDDR3::getExecutionTime(Command command, + [[maybe_unused]] const tlm_generic_payload& payload) const { if (command == Command::PREPB || command == Command::PREAB) return tRP; @@ -150,18 +157,20 @@ sc_time MemSpecDDR3::getExecutionTime(Command command, [[maybe_unused]] const tl if (command == Command::REFAB) return tRFC; - SC_REPORT_FATAL("getExecutionTime", "command not known or command doesn't have a fixed execution time"); throw; } -TimeInterval MemSpecDDR3::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const +TimeInterval +MemSpecDDR3::getIntervalOnDataStrobe(Command command, + [[maybe_unused]] const tlm_generic_payload& payload) const { if (command == Command::RD || command == Command::RDA) return {tRL, tRL + burstDuration}; - if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA) + if (command == Command::WR || command == Command::WRA || command == Command::MWR || + command == Command::MWRA) return {tWL, tWL + burstDuration}; SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.h index 0bcc7de3..95016323 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.h @@ -37,8 +37,8 @@ #ifndef MEMSPECDDR3_H #define MEMSPECDDR3_H -#include "DRAMSys/configuration/memspec/MemSpec.h" #include "DRAMSys/config/DRAMSysConfiguration.h" +#include "DRAMSys/configuration/memspec/MemSpec.h" #include @@ -48,7 +48,7 @@ namespace DRAMSys class MemSpecDDR3 final : public MemSpec { public: - explicit MemSpecDDR3(const DRAMSys::Config::MemSpec &memSpec); + explicit MemSpecDDR3(const DRAMSys::Config::MemSpec& memSpec); // Memspec Variables: const sc_core::sc_time tCKE; @@ -95,8 +95,11 @@ public: [[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override; - [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] sc_core::sc_time + getExecutionTime(Command command, const tlm::tlm_generic_payload& payload) const override; + [[nodiscard]] TimeInterval + getIntervalOnDataStrobe(Command command, + const tlm::tlm_generic_payload& payload) const override; [[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override; }; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp index 5e09d024..0ffba02e 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp @@ -46,77 +46,83 @@ using namespace tlm; namespace DRAMSys { -MemSpecDDR4::MemSpecDDR4(const DRAMSys::Config::MemSpec &memSpec) - : MemSpec(memSpec, MemoryType::DDR4, - memSpec.memarchitecturespec.entries.at("nbrOfChannels"), - 1, - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks") - / memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks") - * memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBankGroups") - * memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfDevices")), - tCKE (tCK * memSpec.memtimingspec.entries.at("CKE")), - tPD (tCKE), - tCKESR (tCK * memSpec.memtimingspec.entries.at("CKESR")), - tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")), - tRC (tCK * memSpec.memtimingspec.entries.at("RC")), - tRCD (tCK * memSpec.memtimingspec.entries.at("RCD")), - tRL (tCK * memSpec.memtimingspec.entries.at("RL")), - tRPRE (tCK * memSpec.memtimingspec.entries.at("RPRE")), - tRTP (tCK * memSpec.memtimingspec.entries.at("RTP")), - tWL (tCK * memSpec.memtimingspec.entries.at("WL")), - tWPRE (tCK * memSpec.memtimingspec.entries.at("WPRE")), - tWR (tCK * memSpec.memtimingspec.entries.at("WR")), - tXP (tCK * memSpec.memtimingspec.entries.at("XP")), - tXS (tCK * memSpec.memtimingspec.entries.at("XS")), - tREFI ((memSpec.memtimingspec.entries.at("REFM") == 4) ? - (tCK * (static_cast(memSpec.memtimingspec.entries.at("REFI")) / 4)) : - ((memSpec.memtimingspec.entries.at("REFM") == 2) ? - (tCK * (static_cast(memSpec.memtimingspec.entries.at("REFI")) / 2)) : - (tCK * memSpec.memtimingspec.entries.at("REFI")))), - tRFC ((memSpec.memtimingspec.entries.at("REFM") == 4) ? - (tCK * memSpec.memtimingspec.entries.at("RFC4")) : - ((memSpec.memtimingspec.entries.at("REFM") == 2) ? - (tCK * memSpec.memtimingspec.entries.at("RFC2")) : - (tCK * memSpec.memtimingspec.entries.at("RFC")))), - tRP (tCK * memSpec.memtimingspec.entries.at("RP")), - tDQSCK (tCK * memSpec.memtimingspec.entries.at("DQSCK")), - tCCD_S (tCK * memSpec.memtimingspec.entries.at("CCD_S")), - tCCD_L (tCK * memSpec.memtimingspec.entries.at("CCD_L")), - tFAW (tCK * memSpec.memtimingspec.entries.at("FAW")), - tRRD_S (tCK * memSpec.memtimingspec.entries.at("RRD_S")), - tRRD_L (tCK * memSpec.memtimingspec.entries.at("RRD_L")), - tWTR_S (tCK * memSpec.memtimingspec.entries.at("WTR_S")), - tWTR_L (tCK * memSpec.memtimingspec.entries.at("WTR_L")), - tAL (tCK * memSpec.memtimingspec.entries.at("AL")), - tXPDLL (tCK * memSpec.memtimingspec.entries.at("XPDLL")), - tXSDLL (tCK * memSpec.memtimingspec.entries.at("XSDLL")), - tACTPDEN (tCK * memSpec.memtimingspec.entries.at("ACTPDEN")), - tPRPDEN (tCK * memSpec.memtimingspec.entries.at("PRPDEN")), - tREFPDEN (tCK * memSpec.memtimingspec.entries.at("REFPDEN")), - tRTRS (tCK * memSpec.memtimingspec.entries.at("RTRS")), - iDD0 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd0") : 0), - iDD2N (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2n") : 0), - iDD3N (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3n") : 0), - iDD4R (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd4r") : 0), - iDD4W (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd4w") : 0), - iDD5 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd5") : 0), - iDD6 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd6") : 0), - vDD (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("vdd") : 0), - iDD02 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd02") : 0), - iDD2P0 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2p0") : 0), - iDD2P1 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2p1") : 0), - iDD3P0 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3p0") : 0), - iDD3P1 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3p1") : 0), - iDD62 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd62") : 0), - vDD2 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("vdd2") : 0) +MemSpecDDR4::MemSpecDDR4(const DRAMSys::Config::MemSpec& memSpec) : + MemSpec(memSpec, + MemoryType::DDR4, + memSpec.memarchitecturespec.entries.at("nbrOfChannels"), + 1, + memSpec.memarchitecturespec.entries.at("nbrOfRanks"), + memSpec.memarchitecturespec.entries.at("nbrOfBanks"), + memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"), + memSpec.memarchitecturespec.entries.at("nbrOfBanks") / + memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"), + memSpec.memarchitecturespec.entries.at("nbrOfBanks") * + memSpec.memarchitecturespec.entries.at("nbrOfRanks"), + memSpec.memarchitecturespec.entries.at("nbrOfBankGroups") * + memSpec.memarchitecturespec.entries.at("nbrOfRanks"), + memSpec.memarchitecturespec.entries.at("nbrOfDevices")), + tCKE(tCK * memSpec.memtimingspec.entries.at("CKE")), + tPD(tCKE), + tCKESR(tCK * memSpec.memtimingspec.entries.at("CKESR")), + tRAS(tCK * memSpec.memtimingspec.entries.at("RAS")), + tRC(tCK * memSpec.memtimingspec.entries.at("RC")), + tRCD(tCK * memSpec.memtimingspec.entries.at("RCD")), + tRL(tCK * memSpec.memtimingspec.entries.at("RL")), + tRPRE(tCK * memSpec.memtimingspec.entries.at("RPRE")), + tRTP(tCK * memSpec.memtimingspec.entries.at("RTP")), + tWL(tCK * memSpec.memtimingspec.entries.at("WL")), + tWPRE(tCK * memSpec.memtimingspec.entries.at("WPRE")), + tWR(tCK * memSpec.memtimingspec.entries.at("WR")), + tXP(tCK * memSpec.memtimingspec.entries.at("XP")), + tXS(tCK * memSpec.memtimingspec.entries.at("XS")), + tREFI((memSpec.memtimingspec.entries.at("REFM") == 4) + ? (tCK * (static_cast(memSpec.memtimingspec.entries.at("REFI")) / 4)) + : ((memSpec.memtimingspec.entries.at("REFM") == 2) + ? (tCK * (static_cast(memSpec.memtimingspec.entries.at("REFI")) / 2)) + : (tCK * memSpec.memtimingspec.entries.at("REFI")))), + tRFC((memSpec.memtimingspec.entries.at("REFM") == 4) + ? (tCK * memSpec.memtimingspec.entries.at("RFC4")) + : ((memSpec.memtimingspec.entries.at("REFM") == 2) + ? (tCK * memSpec.memtimingspec.entries.at("RFC2")) + : (tCK * memSpec.memtimingspec.entries.at("RFC")))), + tRP(tCK * memSpec.memtimingspec.entries.at("RP")), + tDQSCK(tCK * memSpec.memtimingspec.entries.at("DQSCK")), + tCCD_S(tCK * memSpec.memtimingspec.entries.at("CCD_S")), + tCCD_L(tCK * memSpec.memtimingspec.entries.at("CCD_L")), + tFAW(tCK * memSpec.memtimingspec.entries.at("FAW")), + tRRD_S(tCK * memSpec.memtimingspec.entries.at("RRD_S")), + tRRD_L(tCK * memSpec.memtimingspec.entries.at("RRD_L")), + tWTR_S(tCK * memSpec.memtimingspec.entries.at("WTR_S")), + tWTR_L(tCK * memSpec.memtimingspec.entries.at("WTR_L")), + tAL(tCK * memSpec.memtimingspec.entries.at("AL")), + tXPDLL(tCK * memSpec.memtimingspec.entries.at("XPDLL")), + tXSDLL(tCK * memSpec.memtimingspec.entries.at("XSDLL")), + tACTPDEN(tCK * memSpec.memtimingspec.entries.at("ACTPDEN")), + tPRPDEN(tCK * memSpec.memtimingspec.entries.at("PRPDEN")), + tREFPDEN(tCK * memSpec.memtimingspec.entries.at("REFPDEN")), + tRTRS(tCK * memSpec.memtimingspec.entries.at("RTRS")), + iDD0(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd0") : 0), + iDD2N(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2n") : 0), + iDD3N(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3n") : 0), + iDD4R(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd4r") : 0), + iDD4W(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd4w") : 0), + iDD5(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd5") : 0), + iDD6(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd6") : 0), + vDD(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("vdd") : 0), + iDD02(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd02") : 0), + iDD2P0(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2p0") + : 0), + iDD2P1(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2p1") + : 0), + iDD3P0(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3p0") + : 0), + iDD3P1(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3p1") + : 0), + iDD62(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd62") : 0), + vDD2(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("vdd2") : 0) { - uint64_t deviceSizeBits = static_cast(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth; + uint64_t deviceSizeBits = + static_cast(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth; uint64_t deviceSizeBytes = deviceSizeBits / 8; memorySizeBytes = deviceSizeBytes * devicesPerRank * ranksPerChannel * numberOfChannels; @@ -125,17 +131,18 @@ MemSpecDDR4::MemSpecDDR4(const DRAMSys::Config::MemSpec &memSpec) std::cout << headline << std::endl; std::cout << "Memory Configuration:" << std::endl << std::endl; - std::cout << " Memory type: " << "DDR4" << std::endl; - std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl; + std::cout << " Memory type: " + << "DDR4" << std::endl; + std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl; std::cout << " Channels: " << numberOfChannels << std::endl; std::cout << " Ranks per channel: " << ranksPerChannel << std::endl; - std::cout << " Bank groups per rank: " << groupsPerRank << std::endl; - std::cout << " Banks per rank: " << banksPerRank << std::endl; + std::cout << " Bank groups per rank: " << groupsPerRank << std::endl; + std::cout << " Banks per rank: " << banksPerRank << std::endl; std::cout << " Rows per bank: " << rowsPerBank << std::endl; std::cout << " Columns per row: " << columnsPerRow << std::endl; - std::cout << " Device width in bits: " << bitWidth << std::endl; - std::cout << " Device size in bits: " << deviceSizeBits << std::endl; - std::cout << " Device size in bytes: " << deviceSizeBytes << std::endl; + std::cout << " Device width in bits: " << bitWidth << std::endl; + std::cout << " Device size in bits: " << deviceSizeBits << std::endl; + std::cout << " Device size in bytes: " << deviceSizeBytes << std::endl; std::cout << " Devices per rank: " << devicesPerRank << std::endl; std::cout << std::endl; } @@ -146,7 +153,8 @@ sc_time MemSpecDDR4::getRefreshIntervalAB() const } // Returns the execution time for commands that have a fixed execution time -sc_time MemSpecDDR4::getExecutionTime(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const +sc_time MemSpecDDR4::getExecutionTime(Command command, + [[maybe_unused]] const tlm_generic_payload& payload) const { if (command == Command::PREPB || command == Command::PREAB) return tRP; @@ -174,12 +182,15 @@ sc_time MemSpecDDR4::getExecutionTime(Command command, [[maybe_unused]] const tl throw; } -TimeInterval MemSpecDDR4::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm::tlm_generic_payload & payload) const +TimeInterval +MemSpecDDR4::getIntervalOnDataStrobe(Command command, + [[maybe_unused]] const tlm::tlm_generic_payload& payload) const { if (command == Command::RD || command == Command::RDA) return {tRL, tRL + burstDuration}; - if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA) + if (command == Command::WR || command == Command::WRA || command == Command::MWR || + command == Command::MWRA) return {tWL, tWL + burstDuration}; SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.h index 773b2e26..315f12de 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.h @@ -47,7 +47,7 @@ namespace DRAMSys class MemSpecDDR4 final : public MemSpec { public: - explicit MemSpecDDR4(const DRAMSys::Config::MemSpec &memSpec); + explicit MemSpecDDR4(const DRAMSys::Config::MemSpec& memSpec); // Memspec Variables: const sc_core::sc_time tCKE; @@ -102,8 +102,11 @@ public: [[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override; - [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] sc_core::sc_time + getExecutionTime(Command command, const tlm::tlm_generic_payload& payload) const override; + [[nodiscard]] TimeInterval + getIntervalOnDataStrobe(Command command, + const tlm::tlm_generic_payload& payload) const override; [[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override; }; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp index 63a6b5e7..5aa3fd50 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp @@ -46,72 +46,75 @@ using namespace tlm; namespace DRAMSys { -MemSpecGDDR5::MemSpecGDDR5(const DRAMSys::Config::MemSpec &memSpec) - : MemSpec(memSpec, MemoryType::GDDR5, - memSpec.memarchitecturespec.entries.at("nbrOfChannels"), - 1, - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks") - / memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks") - * memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBankGroups") - * memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfDevices")), - tRP (tCK * memSpec.memtimingspec.entries.at("RP")), - tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")), - tRC (tCK * memSpec.memtimingspec.entries.at("RC")), - tRCDRD (tCK * memSpec.memtimingspec.entries.at("RCDRD")), - tRCDWR (tCK * memSpec.memtimingspec.entries.at("RCDWR")), - tRTP (tCK * memSpec.memtimingspec.entries.at("RTP")), - tRRDS (tCK * memSpec.memtimingspec.entries.at("RRDS")), - tRRDL (tCK * memSpec.memtimingspec.entries.at("RRDL")), - tCCDS (tCK * memSpec.memtimingspec.entries.at("CCDS")), - tCCDL (tCK * memSpec.memtimingspec.entries.at("CCDL")), - tCL (tCK * memSpec.memtimingspec.entries.at("CL")), - tWCK2CKPIN (tCK * memSpec.memtimingspec.entries.at("WCK2CKPIN")), - tWCK2CK (tCK * memSpec.memtimingspec.entries.at("WCK2CK")), - tWCK2DQO (tCK * memSpec.memtimingspec.entries.at("WCK2DQO")), - tRTW (tCK * memSpec.memtimingspec.entries.at("RTW")), - tWL (tCK * memSpec.memtimingspec.entries.at("WL")), - tWCK2DQI (tCK * memSpec.memtimingspec.entries.at("WCK2DQI")), - tWR (tCK * memSpec.memtimingspec.entries.at("WR")), - tWTRS (tCK * memSpec.memtimingspec.entries.at("WTRS")), - tWTRL (tCK * memSpec.memtimingspec.entries.at("WTRL")), - tCKE (tCK * memSpec.memtimingspec.entries.at("CKE")), - tPD (tCK * memSpec.memtimingspec.entries.at("PD")), - tXPN (tCK * memSpec.memtimingspec.entries.at("XPN")), - tREFI (tCK * memSpec.memtimingspec.entries.at("REFI")), - tREFIPB (tCK * memSpec.memtimingspec.entries.at("REFIPB")), - tRFC (tCK * memSpec.memtimingspec.entries.at("RFC")), - tRFCPB (tCK * memSpec.memtimingspec.entries.at("RFCPB")), - tRREFD (tCK * memSpec.memtimingspec.entries.at("RREFD")), - tXS (tCK * memSpec.memtimingspec.entries.at("XS")), - tFAW (tCK * memSpec.memtimingspec.entries.at("FAW")), - t32AW (tCK * memSpec.memtimingspec.entries.at("32AW")), - tPPD (tCK * memSpec.memtimingspec.entries.at("PPD")), - tLK (tCK * memSpec.memtimingspec.entries.at("LK")), - tRTRS (tCK * memSpec.memtimingspec.entries.at("RTRS")) +MemSpecGDDR5::MemSpecGDDR5(const DRAMSys::Config::MemSpec& memSpec) : + MemSpec(memSpec, + MemoryType::GDDR5, + memSpec.memarchitecturespec.entries.at("nbrOfChannels"), + 1, + memSpec.memarchitecturespec.entries.at("nbrOfRanks"), + memSpec.memarchitecturespec.entries.at("nbrOfBanks"), + memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"), + memSpec.memarchitecturespec.entries.at("nbrOfBanks") / + memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"), + memSpec.memarchitecturespec.entries.at("nbrOfBanks") * + memSpec.memarchitecturespec.entries.at("nbrOfRanks"), + memSpec.memarchitecturespec.entries.at("nbrOfBankGroups") * + memSpec.memarchitecturespec.entries.at("nbrOfRanks"), + memSpec.memarchitecturespec.entries.at("nbrOfDevices")), + tRP(tCK * memSpec.memtimingspec.entries.at("RP")), + tRAS(tCK * memSpec.memtimingspec.entries.at("RAS")), + tRC(tCK * memSpec.memtimingspec.entries.at("RC")), + tRCDRD(tCK * memSpec.memtimingspec.entries.at("RCDRD")), + tRCDWR(tCK * memSpec.memtimingspec.entries.at("RCDWR")), + tRTP(tCK * memSpec.memtimingspec.entries.at("RTP")), + tRRDS(tCK * memSpec.memtimingspec.entries.at("RRDS")), + tRRDL(tCK * memSpec.memtimingspec.entries.at("RRDL")), + tCCDS(tCK * memSpec.memtimingspec.entries.at("CCDS")), + tCCDL(tCK * memSpec.memtimingspec.entries.at("CCDL")), + tCL(tCK * memSpec.memtimingspec.entries.at("CL")), + tWCK2CKPIN(tCK * memSpec.memtimingspec.entries.at("WCK2CKPIN")), + tWCK2CK(tCK * memSpec.memtimingspec.entries.at("WCK2CK")), + tWCK2DQO(tCK * memSpec.memtimingspec.entries.at("WCK2DQO")), + tRTW(tCK * memSpec.memtimingspec.entries.at("RTW")), + tWL(tCK * memSpec.memtimingspec.entries.at("WL")), + tWCK2DQI(tCK * memSpec.memtimingspec.entries.at("WCK2DQI")), + tWR(tCK * memSpec.memtimingspec.entries.at("WR")), + tWTRS(tCK * memSpec.memtimingspec.entries.at("WTRS")), + tWTRL(tCK * memSpec.memtimingspec.entries.at("WTRL")), + tCKE(tCK * memSpec.memtimingspec.entries.at("CKE")), + tPD(tCK * memSpec.memtimingspec.entries.at("PD")), + tXPN(tCK * memSpec.memtimingspec.entries.at("XPN")), + tREFI(tCK * memSpec.memtimingspec.entries.at("REFI")), + tREFIPB(tCK * memSpec.memtimingspec.entries.at("REFIPB")), + tRFC(tCK * memSpec.memtimingspec.entries.at("RFC")), + tRFCPB(tCK * memSpec.memtimingspec.entries.at("RFCPB")), + tRREFD(tCK * memSpec.memtimingspec.entries.at("RREFD")), + tXS(tCK * memSpec.memtimingspec.entries.at("XS")), + tFAW(tCK * memSpec.memtimingspec.entries.at("FAW")), + t32AW(tCK * memSpec.memtimingspec.entries.at("32AW")), + tPPD(tCK * memSpec.memtimingspec.entries.at("PPD")), + tLK(tCK * memSpec.memtimingspec.entries.at("LK")), + tRTRS(tCK * memSpec.memtimingspec.entries.at("RTRS")) { - uint64_t deviceSizeBits = static_cast(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth; + uint64_t deviceSizeBits = + static_cast(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth; uint64_t deviceSizeBytes = deviceSizeBits / 8; memorySizeBytes = deviceSizeBytes * ranksPerChannel * numberOfChannels; std::cout << headline << std::endl; std::cout << "Memory Configuration:" << std::endl << std::endl; - std::cout << " Memory type: " << "GDDR5" << std::endl; - std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl; - std::cout << " Channels: " << numberOfChannels << std::endl; + std::cout << " Memory type: " + << "GDDR5" << std::endl; + std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl; + std::cout << " Channels: " << numberOfChannels << std::endl; std::cout << " Ranks per channel: " << ranksPerChannel << std::endl; - std::cout << " Bank groups per rank: " << groupsPerRank << std::endl; - std::cout << " Banks per rank: " << banksPerRank << std::endl; + std::cout << " Bank groups per rank: " << groupsPerRank << std::endl; + std::cout << " Banks per rank: " << banksPerRank << std::endl; std::cout << " Rows per bank: " << rowsPerBank << std::endl; std::cout << " Columns per row: " << columnsPerRow << std::endl; - std::cout << " Device width in bits: " << bitWidth << std::endl; - std::cout << " Device size in bits: " << deviceSizeBits << std::endl; - std::cout << " Device size in bytes: " << deviceSizeBytes << std::endl; + std::cout << " Device width in bits: " << bitWidth << std::endl; + std::cout << " Device size in bits: " << deviceSizeBits << std::endl; + std::cout << " Device size in bytes: " << deviceSizeBytes << std::endl; std::cout << " Devices per rank: " << devicesPerRank << std::endl; std::cout << std::endl; } @@ -126,7 +129,7 @@ sc_time MemSpecGDDR5::getRefreshIntervalPB() const return tREFIPB; } -sc_time MemSpecGDDR5::getExecutionTime(Command command, const tlm_generic_payload &payload) const +sc_time MemSpecGDDR5::getExecutionTime(Command command, const tlm_generic_payload& payload) const { if (command == Command::PREPB || command == Command::PREAB) return tRP; @@ -162,13 +165,17 @@ sc_time MemSpecGDDR5::getExecutionTime(Command command, const tlm_generic_payloa throw; } -TimeInterval MemSpecGDDR5::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const +TimeInterval +MemSpecGDDR5::getIntervalOnDataStrobe(Command command, + [[maybe_unused]] const tlm_generic_payload& payload) const { if (command == Command::RD || command == Command::RDA) - return {tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration}; + return {tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, + tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration}; if (command == Command::WR || command == Command::WRA) - return {tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration}; + return {tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, + tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration}; SC_REPORT_FATAL("MemSpecGDDR5", "Method was called with invalid argument"); throw; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.h index 7b1da4c2..149a3796 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.h @@ -47,7 +47,7 @@ namespace DRAMSys class MemSpecGDDR5 final : public MemSpec { public: - explicit MemSpecGDDR5(const DRAMSys::Config::MemSpec &memSpec); + explicit MemSpecGDDR5(const DRAMSys::Config::MemSpec& memSpec); // Memspec Variables: const sc_core::sc_time tRP; @@ -81,8 +81,8 @@ public: const sc_core::sc_time tXS; const sc_core::sc_time tFAW; const sc_core::sc_time t32AW; -// sc_time tRDSRE; // = tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + BurstLength / DataRate * tCK; -// sc_time tWRSRE; // = tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + BurstLength / DataRate * tCK; + // sc_time tRDSRE; // = tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + BurstLength / DataRate * tCK; + // sc_time tWRSRE; // = tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + BurstLength / DataRate * tCK; const sc_core::sc_time tPPD; const sc_core::sc_time tLK; const sc_core::sc_time tRTRS; @@ -93,8 +93,11 @@ public: [[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override; [[nodiscard]] sc_core::sc_time getRefreshIntervalPB() const override; - [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] sc_core::sc_time + getExecutionTime(Command command, const tlm::tlm_generic_payload& payload) const override; + [[nodiscard]] TimeInterval + getIntervalOnDataStrobe(Command command, + const tlm::tlm_generic_payload& payload) const override; }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp index f536f8b9..39653b38 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp @@ -46,72 +46,75 @@ using namespace tlm; namespace DRAMSys { -MemSpecGDDR5X::MemSpecGDDR5X(const DRAMSys::Config::MemSpec &memSpec) - : MemSpec(memSpec, MemoryType::GDDR5X, - memSpec.memarchitecturespec.entries.at("nbrOfChannels"), - 1, - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks") - / memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks") - * memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBankGroups") - * memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfDevices")), - tRP (tCK * memSpec.memtimingspec.entries.at("RP")), - tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")), - tRC (tCK * memSpec.memtimingspec.entries.at("RC")), - tRCDRD (tCK * memSpec.memtimingspec.entries.at("RCDRD")), - tRCDWR (tCK * memSpec.memtimingspec.entries.at("RCDWR")), - tRTP (tCK * memSpec.memtimingspec.entries.at("RTP")), - tRRDS (tCK * memSpec.memtimingspec.entries.at("RRDS")), - tRRDL (tCK * memSpec.memtimingspec.entries.at("RRDL")), - tCCDS (tCK * memSpec.memtimingspec.entries.at("CCDS")), - tCCDL (tCK * memSpec.memtimingspec.entries.at("CCDL")), - tRL (tCK * memSpec.memtimingspec.entries.at("CL")), - tWCK2CKPIN (tCK * memSpec.memtimingspec.entries.at("WCK2CKPIN")), - tWCK2CK (tCK * memSpec.memtimingspec.entries.at("WCK2CK")), - tWCK2DQO (tCK * memSpec.memtimingspec.entries.at("WCK2DQO")), - tRTW (tCK * memSpec.memtimingspec.entries.at("RTW")), - tWL (tCK * memSpec.memtimingspec.entries.at("WL")), - tWCK2DQI (tCK * memSpec.memtimingspec.entries.at("WCK2DQI")), - tWR (tCK * memSpec.memtimingspec.entries.at("WR")), - tWTRS (tCK * memSpec.memtimingspec.entries.at("WTRS")), - tWTRL (tCK * memSpec.memtimingspec.entries.at("WTRL")), - tCKE (tCK * memSpec.memtimingspec.entries.at("CKE")), - tPD (tCK * memSpec.memtimingspec.entries.at("PD")), - tXP (tCK * memSpec.memtimingspec.entries.at("XP")), - tREFI (tCK * memSpec.memtimingspec.entries.at("REFI")), - tREFIPB (tCK * memSpec.memtimingspec.entries.at("REFIPB")), - tRFC (tCK * memSpec.memtimingspec.entries.at("RFC")), - tRFCPB (tCK * memSpec.memtimingspec.entries.at("RFCPB")), - tRREFD (tCK * memSpec.memtimingspec.entries.at("RREFD")), - tXS (tCK * memSpec.memtimingspec.entries.at("XS")), - tFAW (tCK * memSpec.memtimingspec.entries.at("FAW")), - t32AW (tCK * memSpec.memtimingspec.entries.at("32AW")), - tPPD (tCK * memSpec.memtimingspec.entries.at("PPD")), - tLK (tCK * memSpec.memtimingspec.entries.at("LK")), - tRTRS (tCK * memSpec.memtimingspec.entries.at("TRS")) +MemSpecGDDR5X::MemSpecGDDR5X(const DRAMSys::Config::MemSpec& memSpec) : + MemSpec(memSpec, + MemoryType::GDDR5X, + memSpec.memarchitecturespec.entries.at("nbrOfChannels"), + 1, + memSpec.memarchitecturespec.entries.at("nbrOfRanks"), + memSpec.memarchitecturespec.entries.at("nbrOfBanks"), + memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"), + memSpec.memarchitecturespec.entries.at("nbrOfBanks") / + memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"), + memSpec.memarchitecturespec.entries.at("nbrOfBanks") * + memSpec.memarchitecturespec.entries.at("nbrOfRanks"), + memSpec.memarchitecturespec.entries.at("nbrOfBankGroups") * + memSpec.memarchitecturespec.entries.at("nbrOfRanks"), + memSpec.memarchitecturespec.entries.at("nbrOfDevices")), + tRP(tCK * memSpec.memtimingspec.entries.at("RP")), + tRAS(tCK * memSpec.memtimingspec.entries.at("RAS")), + tRC(tCK * memSpec.memtimingspec.entries.at("RC")), + tRCDRD(tCK * memSpec.memtimingspec.entries.at("RCDRD")), + tRCDWR(tCK * memSpec.memtimingspec.entries.at("RCDWR")), + tRTP(tCK * memSpec.memtimingspec.entries.at("RTP")), + tRRDS(tCK * memSpec.memtimingspec.entries.at("RRDS")), + tRRDL(tCK * memSpec.memtimingspec.entries.at("RRDL")), + tCCDS(tCK * memSpec.memtimingspec.entries.at("CCDS")), + tCCDL(tCK * memSpec.memtimingspec.entries.at("CCDL")), + tRL(tCK * memSpec.memtimingspec.entries.at("CL")), + tWCK2CKPIN(tCK * memSpec.memtimingspec.entries.at("WCK2CKPIN")), + tWCK2CK(tCK * memSpec.memtimingspec.entries.at("WCK2CK")), + tWCK2DQO(tCK * memSpec.memtimingspec.entries.at("WCK2DQO")), + tRTW(tCK * memSpec.memtimingspec.entries.at("RTW")), + tWL(tCK * memSpec.memtimingspec.entries.at("WL")), + tWCK2DQI(tCK * memSpec.memtimingspec.entries.at("WCK2DQI")), + tWR(tCK * memSpec.memtimingspec.entries.at("WR")), + tWTRS(tCK * memSpec.memtimingspec.entries.at("WTRS")), + tWTRL(tCK * memSpec.memtimingspec.entries.at("WTRL")), + tCKE(tCK * memSpec.memtimingspec.entries.at("CKE")), + tPD(tCK * memSpec.memtimingspec.entries.at("PD")), + tXP(tCK * memSpec.memtimingspec.entries.at("XP")), + tREFI(tCK * memSpec.memtimingspec.entries.at("REFI")), + tREFIPB(tCK * memSpec.memtimingspec.entries.at("REFIPB")), + tRFC(tCK * memSpec.memtimingspec.entries.at("RFC")), + tRFCPB(tCK * memSpec.memtimingspec.entries.at("RFCPB")), + tRREFD(tCK * memSpec.memtimingspec.entries.at("RREFD")), + tXS(tCK * memSpec.memtimingspec.entries.at("XS")), + tFAW(tCK * memSpec.memtimingspec.entries.at("FAW")), + t32AW(tCK * memSpec.memtimingspec.entries.at("32AW")), + tPPD(tCK * memSpec.memtimingspec.entries.at("PPD")), + tLK(tCK * memSpec.memtimingspec.entries.at("LK")), + tRTRS(tCK * memSpec.memtimingspec.entries.at("TRS")) { - uint64_t deviceSizeBits = static_cast(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth; + uint64_t deviceSizeBits = + static_cast(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth; uint64_t deviceSizeBytes = deviceSizeBits / 8; memorySizeBytes = deviceSizeBytes * ranksPerChannel * numberOfChannels; std::cout << headline << std::endl; std::cout << "Memory Configuration:" << std::endl << std::endl; - std::cout << " Memory type: " << "GDDR5X" << std::endl; - std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl; - std::cout << " Channels: " << numberOfChannels << std::endl; + std::cout << " Memory type: " + << "GDDR5X" << std::endl; + std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl; + std::cout << " Channels: " << numberOfChannels << std::endl; std::cout << " Ranks per channel: " << ranksPerChannel << std::endl; - std::cout << " Bank groups per rank: " << groupsPerRank << std::endl; - std::cout << " Banks per rank: " << banksPerRank << std::endl; + std::cout << " Bank groups per rank: " << groupsPerRank << std::endl; + std::cout << " Banks per rank: " << banksPerRank << std::endl; std::cout << " Rows per bank: " << rowsPerBank << std::endl; std::cout << " Columns per row: " << columnsPerRow << std::endl; - std::cout << " Device width in bits: " << bitWidth << std::endl; - std::cout << " Device size in bits: " << deviceSizeBits << std::endl; - std::cout << " Device size in bytes: " << deviceSizeBytes << std::endl; + std::cout << " Device width in bits: " << bitWidth << std::endl; + std::cout << " Device size in bits: " << deviceSizeBits << std::endl; + std::cout << " Device size in bytes: " << deviceSizeBytes << std::endl; std::cout << " Devices per rank: " << devicesPerRank << std::endl; std::cout << std::endl; } @@ -126,7 +129,7 @@ sc_time MemSpecGDDR5X::getRefreshIntervalPB() const return tREFIPB; } -sc_time MemSpecGDDR5X::getExecutionTime(Command command, const tlm_generic_payload &payload) const +sc_time MemSpecGDDR5X::getExecutionTime(Command command, const tlm_generic_payload& payload) const { if (command == Command::PREPB || command == Command::PREAB) return tRP; @@ -162,13 +165,17 @@ sc_time MemSpecGDDR5X::getExecutionTime(Command command, const tlm_generic_paylo throw; } -TimeInterval MemSpecGDDR5X::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const +TimeInterval +MemSpecGDDR5X::getIntervalOnDataStrobe(Command command, + [[maybe_unused]] const tlm_generic_payload& payload) const { if (command == Command::RD || command == Command::RDA) - return {tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration}; + return {tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, + tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration}; if (command == Command::WR || command == Command::WRA) - return {tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration}; + return {tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, + tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration}; SC_REPORT_FATAL("MemSpecGDDR5X", "Method was called with invalid argument"); throw; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.h index 87ad3570..e86de47b 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.h @@ -47,7 +47,7 @@ namespace DRAMSys class MemSpecGDDR5X final : public MemSpec { public: - explicit MemSpecGDDR5X(const DRAMSys::Config::MemSpec &memSpec); + explicit MemSpecGDDR5X(const DRAMSys::Config::MemSpec& memSpec); // Memspec Variables: const sc_core::sc_time tRP; @@ -81,8 +81,8 @@ public: const sc_core::sc_time tXS; const sc_core::sc_time tFAW; const sc_core::sc_time t32AW; -// sc_time tRDSRE; // = tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + BurstLength / DataRate * tCK; -// sc_time tWRSRE; // = tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + BurstLength / DataRate * tCK; + // sc_time tRDSRE; // = tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + BurstLength / DataRate * tCK; + // sc_time tWRSRE; // = tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + BurstLength / DataRate * tCK; const sc_core::sc_time tPPD; const sc_core::sc_time tLK; const sc_core::sc_time tRTRS; @@ -93,8 +93,11 @@ public: [[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override; [[nodiscard]] sc_core::sc_time getRefreshIntervalPB() const override; - [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] sc_core::sc_time + getExecutionTime(Command command, const tlm::tlm_generic_payload& payload) const override; + [[nodiscard]] TimeInterval + getIntervalOnDataStrobe(Command command, + const tlm::tlm_generic_payload& payload) const override; }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp index 23fae0c4..a337ac54 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp @@ -46,75 +46,78 @@ using namespace tlm; namespace DRAMSys { -MemSpecGDDR6::MemSpecGDDR6(const DRAMSys::Config::MemSpec &memSpec) - : MemSpec(memSpec, MemoryType::GDDR6, - memSpec.memarchitecturespec.entries.at("nbrOfChannels"), - 1, - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks"), - memSpec.memarchitecturespec.entries.at( "nbrOfBankGroups"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks") - / memSpec.memarchitecturespec.entries.at( "nbrOfBankGroups"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks") - * memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at( "nbrOfBankGroups") - * memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfDevices")), - tRP (tCK * memSpec.memtimingspec.entries.at("RP")), - tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")), - tRC (tCK * memSpec.memtimingspec.entries.at("RC")), - tRCDRD (tCK * memSpec.memtimingspec.entries.at("RCDRD")), - tRCDWR (tCK * memSpec.memtimingspec.entries.at("RCDWR")), - tRTP (tCK * memSpec.memtimingspec.entries.at("RTP")), - tRRDS (tCK * memSpec.memtimingspec.entries.at("RRDS")), - tRRDL (tCK * memSpec.memtimingspec.entries.at("RRDL")), - tCCDS (tCK * memSpec.memtimingspec.entries.at("CCDS")), - tCCDL (tCK * memSpec.memtimingspec.entries.at("CCDL")), - tRL (tCK * memSpec.memtimingspec.entries.at("RL")), - tWCK2CKPIN (tCK * memSpec.memtimingspec.entries.at("WCK2CKPIN")), - tWCK2CK (tCK * memSpec.memtimingspec.entries.at("WCK2CK")), - tWCK2DQO (tCK * memSpec.memtimingspec.entries.at("WCK2DQO")), - tRTW (tCK * memSpec.memtimingspec.entries.at("RTW")), - tWL (tCK * memSpec.memtimingspec.entries.at("WL")), - tWCK2DQI (tCK * memSpec.memtimingspec.entries.at("WCK2DQI")), - tWR (tCK * memSpec.memtimingspec.entries.at("WR")), - tWTRS (tCK * memSpec.memtimingspec.entries.at("WTRS")), - tWTRL (tCK * memSpec.memtimingspec.entries.at("WTRL")), - tPD (tCK * memSpec.memtimingspec.entries.at("PD")), - tCKESR (tCK * memSpec.memtimingspec.entries.at("CKESR")), - tXP (tCK * memSpec.memtimingspec.entries.at("XP")), - tREFI (tCK * memSpec.memtimingspec.entries.at("REFI")), - tREFIpb (tCK * memSpec.memtimingspec.entries.at("REFIpb")), - tRFCab (tCK * memSpec.memtimingspec.entries.at("RFCab")), - tRFCpb (tCK * memSpec.memtimingspec.entries.at("RFCpb")), - tRREFD (tCK * memSpec.memtimingspec.entries.at("RREFD")), - tXS (tCK * memSpec.memtimingspec.entries.at("XS")), - tFAW (tCK * memSpec.memtimingspec.entries.at("FAW")), - tPPD (tCK * memSpec.memtimingspec.entries.at("PPD")), - tLK (tCK * memSpec.memtimingspec.entries.at("LK")), - tACTPDE (tCK * memSpec.memtimingspec.entries.at("ACTPDE")), - tPREPDE (tCK * memSpec.memtimingspec.entries.at("PREPDE")), - tREFPDE (tCK * memSpec.memtimingspec.entries.at("REFPDE")), - tRTRS (tCK * memSpec.memtimingspec.entries.at("RTRS")), - per2BankOffset(memSpec.memarchitecturespec.entries.at("per2BankOffset")) +MemSpecGDDR6::MemSpecGDDR6(const DRAMSys::Config::MemSpec& memSpec) : + MemSpec(memSpec, + MemoryType::GDDR6, + memSpec.memarchitecturespec.entries.at("nbrOfChannels"), + 1, + memSpec.memarchitecturespec.entries.at("nbrOfRanks"), + memSpec.memarchitecturespec.entries.at("nbrOfBanks"), + memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"), + memSpec.memarchitecturespec.entries.at("nbrOfBanks") / + memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"), + memSpec.memarchitecturespec.entries.at("nbrOfBanks") * + memSpec.memarchitecturespec.entries.at("nbrOfRanks"), + memSpec.memarchitecturespec.entries.at("nbrOfBankGroups") * + memSpec.memarchitecturespec.entries.at("nbrOfRanks"), + memSpec.memarchitecturespec.entries.at("nbrOfDevices")), + tRP(tCK * memSpec.memtimingspec.entries.at("RP")), + tRAS(tCK * memSpec.memtimingspec.entries.at("RAS")), + tRC(tCK * memSpec.memtimingspec.entries.at("RC")), + tRCDRD(tCK * memSpec.memtimingspec.entries.at("RCDRD")), + tRCDWR(tCK * memSpec.memtimingspec.entries.at("RCDWR")), + tRTP(tCK * memSpec.memtimingspec.entries.at("RTP")), + tRRDS(tCK * memSpec.memtimingspec.entries.at("RRDS")), + tRRDL(tCK * memSpec.memtimingspec.entries.at("RRDL")), + tCCDS(tCK * memSpec.memtimingspec.entries.at("CCDS")), + tCCDL(tCK * memSpec.memtimingspec.entries.at("CCDL")), + tRL(tCK * memSpec.memtimingspec.entries.at("RL")), + tWCK2CKPIN(tCK * memSpec.memtimingspec.entries.at("WCK2CKPIN")), + tWCK2CK(tCK * memSpec.memtimingspec.entries.at("WCK2CK")), + tWCK2DQO(tCK * memSpec.memtimingspec.entries.at("WCK2DQO")), + tRTW(tCK * memSpec.memtimingspec.entries.at("RTW")), + tWL(tCK * memSpec.memtimingspec.entries.at("WL")), + tWCK2DQI(tCK * memSpec.memtimingspec.entries.at("WCK2DQI")), + tWR(tCK * memSpec.memtimingspec.entries.at("WR")), + tWTRS(tCK * memSpec.memtimingspec.entries.at("WTRS")), + tWTRL(tCK * memSpec.memtimingspec.entries.at("WTRL")), + tPD(tCK * memSpec.memtimingspec.entries.at("PD")), + tCKESR(tCK * memSpec.memtimingspec.entries.at("CKESR")), + tXP(tCK * memSpec.memtimingspec.entries.at("XP")), + tREFI(tCK * memSpec.memtimingspec.entries.at("REFI")), + tREFIpb(tCK * memSpec.memtimingspec.entries.at("REFIpb")), + tRFCab(tCK * memSpec.memtimingspec.entries.at("RFCab")), + tRFCpb(tCK * memSpec.memtimingspec.entries.at("RFCpb")), + tRREFD(tCK * memSpec.memtimingspec.entries.at("RREFD")), + tXS(tCK * memSpec.memtimingspec.entries.at("XS")), + tFAW(tCK * memSpec.memtimingspec.entries.at("FAW")), + tPPD(tCK * memSpec.memtimingspec.entries.at("PPD")), + tLK(tCK * memSpec.memtimingspec.entries.at("LK")), + tACTPDE(tCK * memSpec.memtimingspec.entries.at("ACTPDE")), + tPREPDE(tCK * memSpec.memtimingspec.entries.at("PREPDE")), + tREFPDE(tCK * memSpec.memtimingspec.entries.at("REFPDE")), + tRTRS(tCK * memSpec.memtimingspec.entries.at("RTRS")), + per2BankOffset(memSpec.memarchitecturespec.entries.at("per2BankOffset")) { - uint64_t deviceSizeBits = static_cast(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth; + uint64_t deviceSizeBits = + static_cast(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth; uint64_t deviceSizeBytes = deviceSizeBits / 8; memorySizeBytes = deviceSizeBytes * ranksPerChannel * numberOfChannels; std::cout << headline << std::endl; std::cout << "Memory Configuration:" << std::endl << std::endl; - std::cout << " Memory type: " << "GDDR6" << std::endl; - std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl; - std::cout << " Channels: " << numberOfChannels << std::endl; + std::cout << " Memory type: " + << "GDDR6" << std::endl; + std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl; + std::cout << " Channels: " << numberOfChannels << std::endl; std::cout << " Ranks per channel: " << ranksPerChannel << std::endl; - std::cout << " Bank groups per rank: " << groupsPerRank << std::endl; - std::cout << " Banks per rank: " << banksPerRank << std::endl; + std::cout << " Bank groups per rank: " << groupsPerRank << std::endl; + std::cout << " Banks per rank: " << banksPerRank << std::endl; std::cout << " Rows per bank: " << rowsPerBank << std::endl; std::cout << " Columns per row: " << columnsPerRow << std::endl; - std::cout << " Device width in bits: " << bitWidth << std::endl; - std::cout << " Device size in bits: " << deviceSizeBits << std::endl; - std::cout << " Device size in bytes: " << deviceSizeBytes << std::endl; + std::cout << " Device width in bits: " << bitWidth << std::endl; + std::cout << " Device size in bits: " << deviceSizeBits << std::endl; + std::cout << " Device size in bytes: " << deviceSizeBytes << std::endl; std::cout << " Devices per rank: " << devicesPerRank << std::endl; std::cout << std::endl; } @@ -139,7 +142,7 @@ unsigned MemSpecGDDR6::getPer2BankOffset() const return per2BankOffset; } -sc_time MemSpecGDDR6::getExecutionTime(Command command, const tlm_generic_payload &payload) const +sc_time MemSpecGDDR6::getExecutionTime(Command command, const tlm_generic_payload& payload) const { if (command == Command::PREPB || command == Command::PREAB) return tRP; @@ -175,13 +178,17 @@ sc_time MemSpecGDDR6::getExecutionTime(Command command, const tlm_generic_payloa throw; } -TimeInterval MemSpecGDDR6::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const +TimeInterval +MemSpecGDDR6::getIntervalOnDataStrobe(Command command, + [[maybe_unused]] const tlm_generic_payload& payload) const { if (command == Command::RD || command == Command::RDA) - return {tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration}; + return {tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, + tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration}; if (command == Command::WR || command == Command::WRA) - return {tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration}; + return {tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, + tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration}; SC_REPORT_FATAL("MemSpecGDDR6", "Method was called with invalid argument"); throw; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.h index a216fca8..404d7462 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.h @@ -46,7 +46,7 @@ namespace DRAMSys struct MemSpecGDDR6 final : public MemSpec { public: - explicit MemSpecGDDR6(const DRAMSys::Config::MemSpec &memSpec); + explicit MemSpecGDDR6(const DRAMSys::Config::MemSpec& memSpec); // Memspec Variables: const sc_core::sc_time tRP; @@ -79,8 +79,8 @@ public: const sc_core::sc_time tRREFD; const sc_core::sc_time tXS; const sc_core::sc_time tFAW; -// sc_time tRDSRE; // = tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + BurstLength / DataRate * tCK; -// sc_time tWRSRE; // = tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + BurstLength / DataRate * tCK; + // sc_time tRDSRE; // = tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + BurstLength / DataRate * tCK; + // sc_time tWRSRE; // = tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + BurstLength / DataRate * tCK; const sc_core::sc_time tPPD; const sc_core::sc_time tLK; const sc_core::sc_time tACTPDE; @@ -96,8 +96,11 @@ public: [[nodiscard]] sc_core::sc_time getRefreshIntervalP2B() const override; [[nodiscard]] unsigned getPer2BankOffset() const override; - [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] sc_core::sc_time + getExecutionTime(Command command, const tlm::tlm_generic_payload& payload) const override; + [[nodiscard]] TimeInterval + getIntervalOnDataStrobe(Command command, + const tlm::tlm_generic_payload& payload) const override; private: unsigned per2BankOffset; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp index 83035450..a766f9b1 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp @@ -46,69 +46,72 @@ using namespace tlm; namespace DRAMSys { -MemSpecHBM2::MemSpecHBM2(const DRAMSys::Config::MemSpec &memSpec) - : MemSpec(memSpec, MemoryType::HBM2, - memSpec.memarchitecturespec.entries.at("nbrOfChannels"), - memSpec.memarchitecturespec.entries.at("nbrOfPseudoChannels"), - memSpec.memarchitecturespec.entries.at("nbrOfPseudoChannels"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks") - / memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks") - * memSpec.memarchitecturespec.entries.at("nbrOfPseudoChannels"), - memSpec.memarchitecturespec.entries.at("nbrOfBankGroups") - * memSpec.memarchitecturespec.entries.at("nbrOfPseudoChannels"), - memSpec.memarchitecturespec.entries.at("nbrOfDevices")), - tDQSCK (tCK * memSpec.memtimingspec.entries.at("DQSCK")), - tRC (tCK * memSpec.memtimingspec.entries.at("RC")), - tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")), - tRCDRD (tCK * memSpec.memtimingspec.entries.at("RCDRD")), - tRCDWR (tCK * memSpec.memtimingspec.entries.at("RCDWR")), - tRRDL (tCK * memSpec.memtimingspec.entries.at("RRDL")), - tRRDS (tCK * memSpec.memtimingspec.entries.at("RRDS")), - tFAW (tCK * memSpec.memtimingspec.entries.at("FAW")), - tRTP (tCK * memSpec.memtimingspec.entries.at("RTP")), - tRP (tCK * memSpec.memtimingspec.entries.at("RP")), - tRL (tCK * memSpec.memtimingspec.entries.at("RL")), - tWL (tCK * memSpec.memtimingspec.entries.at("WL")), - tPL (tCK * memSpec.memtimingspec.entries.at("PL")), - tWR (tCK * memSpec.memtimingspec.entries.at("WR")), - tCCDL (tCK * memSpec.memtimingspec.entries.at("CCDL")), - tCCDS (tCK * memSpec.memtimingspec.entries.at("CCDS")), - tWTRL (tCK * memSpec.memtimingspec.entries.at("WTRL")), - tWTRS (tCK * memSpec.memtimingspec.entries.at("WTRS")), - tRTW (tCK * memSpec.memtimingspec.entries.at("RTW")), - tXP (tCK * memSpec.memtimingspec.entries.at("XP")), - tCKE (tCK * memSpec.memtimingspec.entries.at("CKE")), - tPD (tCKE), - tCKESR (tCKE + tCK), - tXS (tCK * memSpec.memtimingspec.entries.at("XS")), - tRFC (tCK * memSpec.memtimingspec.entries.at("RFC")), - tRFCSB (tCK * memSpec.memtimingspec.entries.at("RFCSB")), - tRREFD (tCK * memSpec.memtimingspec.entries.at("RREFD")), - tREFI (tCK * memSpec.memtimingspec.entries.at("REFI")), - tREFISB (tCK * memSpec.memtimingspec.entries.at("REFISB")) +MemSpecHBM2::MemSpecHBM2(const DRAMSys::Config::MemSpec& memSpec) : + MemSpec(memSpec, + MemoryType::HBM2, + memSpec.memarchitecturespec.entries.at("nbrOfChannels"), + memSpec.memarchitecturespec.entries.at("nbrOfPseudoChannels"), + memSpec.memarchitecturespec.entries.at("nbrOfPseudoChannels"), + memSpec.memarchitecturespec.entries.at("nbrOfBanks"), + memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"), + memSpec.memarchitecturespec.entries.at("nbrOfBanks") / + memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"), + memSpec.memarchitecturespec.entries.at("nbrOfBanks") * + memSpec.memarchitecturespec.entries.at("nbrOfPseudoChannels"), + memSpec.memarchitecturespec.entries.at("nbrOfBankGroups") * + memSpec.memarchitecturespec.entries.at("nbrOfPseudoChannels"), + memSpec.memarchitecturespec.entries.at("nbrOfDevices")), + tDQSCK(tCK * memSpec.memtimingspec.entries.at("DQSCK")), + tRC(tCK * memSpec.memtimingspec.entries.at("RC")), + tRAS(tCK * memSpec.memtimingspec.entries.at("RAS")), + tRCDRD(tCK * memSpec.memtimingspec.entries.at("RCDRD")), + tRCDWR(tCK * memSpec.memtimingspec.entries.at("RCDWR")), + tRRDL(tCK * memSpec.memtimingspec.entries.at("RRDL")), + tRRDS(tCK * memSpec.memtimingspec.entries.at("RRDS")), + tFAW(tCK * memSpec.memtimingspec.entries.at("FAW")), + tRTP(tCK * memSpec.memtimingspec.entries.at("RTP")), + tRP(tCK * memSpec.memtimingspec.entries.at("RP")), + tRL(tCK * memSpec.memtimingspec.entries.at("RL")), + tWL(tCK * memSpec.memtimingspec.entries.at("WL")), + tPL(tCK * memSpec.memtimingspec.entries.at("PL")), + tWR(tCK * memSpec.memtimingspec.entries.at("WR")), + tCCDL(tCK * memSpec.memtimingspec.entries.at("CCDL")), + tCCDS(tCK * memSpec.memtimingspec.entries.at("CCDS")), + tWTRL(tCK * memSpec.memtimingspec.entries.at("WTRL")), + tWTRS(tCK * memSpec.memtimingspec.entries.at("WTRS")), + tRTW(tCK * memSpec.memtimingspec.entries.at("RTW")), + tXP(tCK * memSpec.memtimingspec.entries.at("XP")), + tCKE(tCK * memSpec.memtimingspec.entries.at("CKE")), + tPD(tCKE), + tCKESR(tCKE + tCK), + tXS(tCK * memSpec.memtimingspec.entries.at("XS")), + tRFC(tCK * memSpec.memtimingspec.entries.at("RFC")), + tRFCSB(tCK * memSpec.memtimingspec.entries.at("RFCSB")), + tRREFD(tCK * memSpec.memtimingspec.entries.at("RREFD")), + tREFI(tCK * memSpec.memtimingspec.entries.at("REFI")), + tREFISB(tCK * memSpec.memtimingspec.entries.at("REFISB")) { commandLengthInCycles[Command::ACT] = 2; - uint64_t deviceSizeBits = static_cast(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth; + uint64_t deviceSizeBits = + static_cast(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth; uint64_t deviceSizeBytes = deviceSizeBits / 8; memorySizeBytes = deviceSizeBytes * ranksPerChannel * numberOfChannels; std::cout << headline << std::endl; std::cout << "Memory Configuration:" << std::endl << std::endl; - std::cout << " Memory type: " << "HBM2" << std::endl; - std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl; + std::cout << " Memory type: " + << "HBM2" << std::endl; + std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl; std::cout << " Channels: " << numberOfChannels << std::endl; - std::cout << " Pseudo channels per channel: " << ranksPerChannel << std::endl; - std::cout << " Bank groups per pseudo channel: " << groupsPerRank << std::endl; - std::cout << " Banks per pseudo channel: " << banksPerRank << std::endl; - std::cout << " Rows per bank: " << rowsPerBank << std::endl; - std::cout << " Columns per row: " << columnsPerRow << std::endl; - std::cout << " Pseudo channel width in bits: " << bitWidth << std::endl; - std::cout << " Pseudo channel size in bits: " << deviceSizeBits << std::endl; - std::cout << " Pseudo channel size in bytes: " << deviceSizeBytes << std::endl; + std::cout << " Pseudo channels per channel: " << ranksPerChannel << std::endl; + std::cout << " Bank groups per pseudo channel: " << groupsPerRank << std::endl; + std::cout << " Banks per pseudo channel: " << banksPerRank << std::endl; + std::cout << " Rows per bank: " << rowsPerBank << std::endl; + std::cout << " Columns per row: " << columnsPerRow << std::endl; + std::cout << " Pseudo channel width in bits: " << bitWidth << std::endl; + std::cout << " Pseudo channel size in bits: " << deviceSizeBits << std::endl; + std::cout << " Pseudo channel size in bytes: " << deviceSizeBytes << std::endl; std::cout << std::endl; } @@ -127,7 +130,7 @@ bool MemSpecHBM2::hasRasAndCasBus() const return true; } -sc_time MemSpecHBM2::getExecutionTime(Command command, const tlm_generic_payload &payload) const +sc_time MemSpecHBM2::getExecutionTime(Command command, const tlm_generic_payload& payload) const { if (command == Command::PREPB || command == Command::PREAB) return tRP; @@ -163,12 +166,15 @@ sc_time MemSpecHBM2::getExecutionTime(Command command, const tlm_generic_payload throw; } -TimeInterval MemSpecHBM2::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const +TimeInterval +MemSpecHBM2::getIntervalOnDataStrobe(Command command, + [[maybe_unused]] const tlm_generic_payload& payload) const { if (command == Command::RD || command == Command::RDA) return {tRL + tDQSCK, tRL + tDQSCK + burstDuration}; - if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA) + if (command == Command::WR || command == Command::WRA || command == Command::MWR || + command == Command::MWRA) return {tWL, tWL + burstDuration}; SC_REPORT_FATAL("MemSpecHBM2", "Method was called with invalid argument"); diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.h index 38022b33..ec435978 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.h @@ -47,11 +47,11 @@ namespace DRAMSys class MemSpecHBM2 final : public MemSpec { public: - explicit MemSpecHBM2(const DRAMSys::Config::MemSpec &memSpec); + explicit MemSpecHBM2(const DRAMSys::Config::MemSpec& memSpec); // Memspec Variables: const sc_core::sc_time tDQSCK; -// sc_time tDQSQ; // TODO: check actual value of this parameter + // sc_time tDQSQ; // TODO: check actual value of this parameter const sc_core::sc_time tRC; const sc_core::sc_time tRAS; const sc_core::sc_time tRCDRD; @@ -67,13 +67,13 @@ public: const sc_core::sc_time tWR; const sc_core::sc_time tCCDL; const sc_core::sc_time tCCDS; -// sc_time tCCDR; // TODO: consecutive reads to different stack IDs + // sc_time tCCDR; // TODO: consecutive reads to different stack IDs const sc_core::sc_time tWTRL; const sc_core::sc_time tWTRS; const sc_core::sc_time tRTW; const sc_core::sc_time tXP; const sc_core::sc_time tCKE; - const sc_core::sc_time tPD; // = tCKE; + const sc_core::sc_time tPD; // = tCKE; const sc_core::sc_time tCKESR; // = tCKE + tCK; const sc_core::sc_time tXS; const sc_core::sc_time tRFC; @@ -90,8 +90,11 @@ public: [[nodiscard]] bool hasRasAndCasBus() const override; - [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] sc_core::sc_time + getExecutionTime(Command command, const tlm::tlm_generic_payload& payload) const override; + [[nodiscard]] TimeInterval + getIntervalOnDataStrobe(Command command, + const tlm::tlm_generic_payload& payload) const override; [[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override; }; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp index 7a97b67d..57fa74c8 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp @@ -46,50 +46,51 @@ using namespace tlm; namespace DRAMSys { -MemSpecLPDDR4::MemSpecLPDDR4(const DRAMSys::Config::MemSpec &memSpec) - : MemSpec(memSpec, MemoryType::LPDDR4, - memSpec.memarchitecturespec.entries.at("nbrOfChannels"), - 1, - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks"), - 1, - memSpec.memarchitecturespec.entries.at("nbrOfBanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks") - * memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfDevices")), - tREFI (tCK * memSpec.memtimingspec.entries.at("REFI")), - tREFIpb (tCK * memSpec.memtimingspec.entries.at("REFIPB")), - tRFCab (tCK * memSpec.memtimingspec.entries.at("RFCAB")), - tRFCpb (tCK * memSpec.memtimingspec.entries.at("RFCPB")), - tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")), - tRPab (tCK * memSpec.memtimingspec.entries.at("RPAB")), - tRPpb (tCK * memSpec.memtimingspec.entries.at("RPPB")), - tRCpb (tCK * memSpec.memtimingspec.entries.at("RCPB")), - tRCab (tCK * memSpec.memtimingspec.entries.at("RCAB")), - tPPD (tCK * memSpec.memtimingspec.entries.at("PPD")), - tRCD (tCK * memSpec.memtimingspec.entries.at("RCD")), - tFAW (tCK * memSpec.memtimingspec.entries.at("FAW")), - tRRD (tCK * memSpec.memtimingspec.entries.at("RRD")), - tCCD (tCK * memSpec.memtimingspec.entries.at("CCD")), - tCCDMW (tCK * memSpec.memtimingspec.entries.at("CCDMW")), - tRL (tCK * memSpec.memtimingspec.entries.at("RL")), - tRPST (tCK * memSpec.memtimingspec.entries.at("RPST")), - tDQSCK (tCK * memSpec.memtimingspec.entries.at("DQSCK")), - tRTP (tCK * memSpec.memtimingspec.entries.at("RTP")), - tWL (tCK * memSpec.memtimingspec.entries.at("WL")), - tDQSS (tCK * memSpec.memtimingspec.entries.at("DQSS")), - tDQS2DQ (tCK * memSpec.memtimingspec.entries.at("DQS2DQ")), - tWR (tCK * memSpec.memtimingspec.entries.at("WR")), - tWPRE (tCK * memSpec.memtimingspec.entries.at("WPRE")), - tWTR (tCK * memSpec.memtimingspec.entries.at("WTR")), - tXP (tCK * memSpec.memtimingspec.entries.at("XP")), - tSR (tCK * memSpec.memtimingspec.entries.at("SR")), - tXSR (tCK * memSpec.memtimingspec.entries.at("XSR")), - tESCKE (tCK * memSpec.memtimingspec.entries.at("ESCKE")), - tCKE (tCK * memSpec.memtimingspec.entries.at("CKE")), - tCMDCKE (tCK * memSpec.memtimingspec.entries.at("CMDCKE")), - tRTRS (tCK * memSpec.memtimingspec.entries.at("RTRS")) +MemSpecLPDDR4::MemSpecLPDDR4(const DRAMSys::Config::MemSpec& memSpec) : + MemSpec(memSpec, + MemoryType::LPDDR4, + memSpec.memarchitecturespec.entries.at("nbrOfChannels"), + 1, + memSpec.memarchitecturespec.entries.at("nbrOfRanks"), + memSpec.memarchitecturespec.entries.at("nbrOfBanks"), + 1, + memSpec.memarchitecturespec.entries.at("nbrOfBanks"), + memSpec.memarchitecturespec.entries.at("nbrOfBanks") * + memSpec.memarchitecturespec.entries.at("nbrOfRanks"), + memSpec.memarchitecturespec.entries.at("nbrOfRanks"), + memSpec.memarchitecturespec.entries.at("nbrOfDevices")), + tREFI(tCK * memSpec.memtimingspec.entries.at("REFI")), + tREFIpb(tCK * memSpec.memtimingspec.entries.at("REFIPB")), + tRFCab(tCK * memSpec.memtimingspec.entries.at("RFCAB")), + tRFCpb(tCK * memSpec.memtimingspec.entries.at("RFCPB")), + tRAS(tCK * memSpec.memtimingspec.entries.at("RAS")), + tRPab(tCK * memSpec.memtimingspec.entries.at("RPAB")), + tRPpb(tCK * memSpec.memtimingspec.entries.at("RPPB")), + tRCpb(tCK * memSpec.memtimingspec.entries.at("RCPB")), + tRCab(tCK * memSpec.memtimingspec.entries.at("RCAB")), + tPPD(tCK * memSpec.memtimingspec.entries.at("PPD")), + tRCD(tCK * memSpec.memtimingspec.entries.at("RCD")), + tFAW(tCK * memSpec.memtimingspec.entries.at("FAW")), + tRRD(tCK * memSpec.memtimingspec.entries.at("RRD")), + tCCD(tCK * memSpec.memtimingspec.entries.at("CCD")), + tCCDMW(tCK * memSpec.memtimingspec.entries.at("CCDMW")), + tRL(tCK * memSpec.memtimingspec.entries.at("RL")), + tRPST(tCK * memSpec.memtimingspec.entries.at("RPST")), + tDQSCK(tCK * memSpec.memtimingspec.entries.at("DQSCK")), + tRTP(tCK * memSpec.memtimingspec.entries.at("RTP")), + tWL(tCK * memSpec.memtimingspec.entries.at("WL")), + tDQSS(tCK * memSpec.memtimingspec.entries.at("DQSS")), + tDQS2DQ(tCK * memSpec.memtimingspec.entries.at("DQS2DQ")), + tWR(tCK * memSpec.memtimingspec.entries.at("WR")), + tWPRE(tCK * memSpec.memtimingspec.entries.at("WPRE")), + tWTR(tCK * memSpec.memtimingspec.entries.at("WTR")), + tXP(tCK * memSpec.memtimingspec.entries.at("XP")), + tSR(tCK * memSpec.memtimingspec.entries.at("SR")), + tXSR(tCK * memSpec.memtimingspec.entries.at("XSR")), + tESCKE(tCK * memSpec.memtimingspec.entries.at("ESCKE")), + tCKE(tCK * memSpec.memtimingspec.entries.at("CKE")), + tCMDCKE(tCK * memSpec.memtimingspec.entries.at("CMDCKE")), + tRTRS(tCK * memSpec.memtimingspec.entries.at("RTRS")) { commandLengthInCycles[Command::ACT] = 4; commandLengthInCycles[Command::PREPB] = 2; @@ -105,22 +106,24 @@ MemSpecLPDDR4::MemSpecLPDDR4(const DRAMSys::Config::MemSpec &memSpec) commandLengthInCycles[Command::SREFEN] = 2; commandLengthInCycles[Command::SREFEX] = 2; - uint64_t deviceSizeBits = static_cast(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth; + uint64_t deviceSizeBits = + static_cast(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth; uint64_t deviceSizeBytes = deviceSizeBits / 8; memorySizeBytes = deviceSizeBytes * ranksPerChannel * numberOfChannels; std::cout << headline << std::endl; std::cout << "Memory Configuration:" << std::endl << std::endl; - std::cout << " Memory type: " << "LPDDR4" << std::endl; - std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl; - std::cout << " Channels: " << numberOfChannels << std::endl; + std::cout << " Memory type: " + << "LPDDR4" << std::endl; + std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl; + std::cout << " Channels: " << numberOfChannels << std::endl; std::cout << " Ranks per channel: " << ranksPerChannel << std::endl; - std::cout << " Banks per rank: " << banksPerRank << std::endl; + std::cout << " Banks per rank: " << banksPerRank << std::endl; std::cout << " Rows per bank: " << rowsPerBank << std::endl; std::cout << " Columns per row: " << columnsPerRow << std::endl; - std::cout << " Device width in bits: " << bitWidth << std::endl; - std::cout << " Device size in bits: " << deviceSizeBits << std::endl; - std::cout << " Device size in bytes: " << deviceSizeBytes << std::endl; + std::cout << " Device width in bits: " << bitWidth << std::endl; + std::cout << " Device size in bits: " << deviceSizeBits << std::endl; + std::cout << " Device size in bytes: " << deviceSizeBytes << std::endl; std::cout << " Devices per rank: " << devicesPerRank << std::endl; std::cout << std::endl; } @@ -135,7 +138,8 @@ sc_time MemSpecLPDDR4::getRefreshIntervalPB() const return tREFIpb; } -sc_time MemSpecLPDDR4::getExecutionTime(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const +sc_time MemSpecLPDDR4::getExecutionTime(Command command, + [[maybe_unused]] const tlm_generic_payload& payload) const { if (command == Command::PREPB) return tRPpb + tCK; @@ -169,12 +173,15 @@ sc_time MemSpecLPDDR4::getExecutionTime(Command command, [[maybe_unused]] const throw; } -TimeInterval MemSpecLPDDR4::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const +TimeInterval +MemSpecLPDDR4::getIntervalOnDataStrobe(Command command, + [[maybe_unused]] const tlm_generic_payload& payload) const { if (command == Command::RD || command == Command::RDA) return {tRL + tDQSCK + 3 * tCK, tRL + tDQSCK + burstDuration + 3 * tCK}; - if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA) + if (command == Command::WR || command == Command::WRA || command == Command::MWR || + command == Command::MWRA) return {tWL + tDQSS + tDQS2DQ + 3 * tCK, tWL + tDQSS + tDQS2DQ + burstDuration + 3 * tCK}; SC_REPORT_FATAL("MemSpecLPDDR4", "Method was called with invalid argument"); diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.h index 2a0982a8..b88a235c 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.h @@ -44,11 +44,10 @@ namespace DRAMSys { - class MemSpecLPDDR4 final : public MemSpec { public: - explicit MemSpecLPDDR4(const DRAMSys::Config::MemSpec &memSpec); + explicit MemSpecLPDDR4(const DRAMSys::Config::MemSpec& memSpec); // Memspec Variables: const sc_core::sc_time tREFI; @@ -90,8 +89,11 @@ public: [[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override; [[nodiscard]] sc_core::sc_time getRefreshIntervalPB() const override; - [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] sc_core::sc_time + getExecutionTime(Command command, const tlm::tlm_generic_payload& payload) const override; + [[nodiscard]] TimeInterval + getIntervalOnDataStrobe(Command command, + const tlm::tlm_generic_payload& payload) const override; [[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override; }; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp index 037d0e49..e3593450 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp @@ -46,65 +46,69 @@ using namespace tlm; namespace DRAMSys { -MemSpecSTTMRAM::MemSpecSTTMRAM(const DRAMSys::Config::MemSpec &memSpec) - : MemSpec(memSpec, MemoryType::STTMRAM, - memSpec.memarchitecturespec.entries.at("nbrOfChannels"), - 1, - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks"), - 1, - memSpec.memarchitecturespec.entries.at("nbrOfBanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks") - * memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfDevices")), - tCKE (tCK * memSpec.memtimingspec.entries.at("CKE")), - tPD (tCKE), - tCKESR (tCK * memSpec.memtimingspec.entries.at("CKESR")), - tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")), - tRC (tCK * memSpec.memtimingspec.entries.at("RC")), - tRCD (tCK * memSpec.memtimingspec.entries.at("RCD")), - tRL (tCK * memSpec.memtimingspec.entries.at("RL")), - tRTP (tCK * memSpec.memtimingspec.entries.at("RTP")), - tWL (tCK * memSpec.memtimingspec.entries.at("WL")), - tWR (tCK * memSpec.memtimingspec.entries.at("WR")), - tXP (tCK * memSpec.memtimingspec.entries.at("XP")), - tXS (tCK * memSpec.memtimingspec.entries.at("XS")), - tRP (tCK * memSpec.memtimingspec.entries.at("RP")), - tDQSCK (tCK * memSpec.memtimingspec.entries.at("DQSCK")), - tCCD (tCK * memSpec.memtimingspec.entries.at("CCD")), - tFAW (tCK * memSpec.memtimingspec.entries.at("FAW")), - tRRD (tCK * memSpec.memtimingspec.entries.at("RRD")), - tWTR (tCK * memSpec.memtimingspec.entries.at("WTR")), - tXPDLL (tCK * memSpec.memtimingspec.entries.at("XPDLL")), - tXSDLL (tCK * memSpec.memtimingspec.entries.at("XSDLL")), - tAL (tCK * memSpec.memtimingspec.entries.at("AL")), - tACTPDEN (tCK * memSpec.memtimingspec.entries.at("ACTPDEN")), - tPRPDEN (tCK * memSpec.memtimingspec.entries.at("PRPDEN")), - tRTRS (tCK * memSpec.memtimingspec.entries.at("RTRS")) +MemSpecSTTMRAM::MemSpecSTTMRAM(const DRAMSys::Config::MemSpec& memSpec) : + MemSpec(memSpec, + MemoryType::STTMRAM, + memSpec.memarchitecturespec.entries.at("nbrOfChannels"), + 1, + memSpec.memarchitecturespec.entries.at("nbrOfRanks"), + memSpec.memarchitecturespec.entries.at("nbrOfBanks"), + 1, + memSpec.memarchitecturespec.entries.at("nbrOfBanks"), + memSpec.memarchitecturespec.entries.at("nbrOfBanks") * + memSpec.memarchitecturespec.entries.at("nbrOfRanks"), + memSpec.memarchitecturespec.entries.at("nbrOfRanks"), + memSpec.memarchitecturespec.entries.at("nbrOfDevices")), + tCKE(tCK * memSpec.memtimingspec.entries.at("CKE")), + tPD(tCKE), + tCKESR(tCK * memSpec.memtimingspec.entries.at("CKESR")), + tRAS(tCK * memSpec.memtimingspec.entries.at("RAS")), + tRC(tCK * memSpec.memtimingspec.entries.at("RC")), + tRCD(tCK * memSpec.memtimingspec.entries.at("RCD")), + tRL(tCK * memSpec.memtimingspec.entries.at("RL")), + tRTP(tCK * memSpec.memtimingspec.entries.at("RTP")), + tWL(tCK * memSpec.memtimingspec.entries.at("WL")), + tWR(tCK * memSpec.memtimingspec.entries.at("WR")), + tXP(tCK * memSpec.memtimingspec.entries.at("XP")), + tXS(tCK * memSpec.memtimingspec.entries.at("XS")), + tRP(tCK * memSpec.memtimingspec.entries.at("RP")), + tDQSCK(tCK * memSpec.memtimingspec.entries.at("DQSCK")), + tCCD(tCK * memSpec.memtimingspec.entries.at("CCD")), + tFAW(tCK * memSpec.memtimingspec.entries.at("FAW")), + tRRD(tCK * memSpec.memtimingspec.entries.at("RRD")), + tWTR(tCK * memSpec.memtimingspec.entries.at("WTR")), + tXPDLL(tCK * memSpec.memtimingspec.entries.at("XPDLL")), + tXSDLL(tCK * memSpec.memtimingspec.entries.at("XSDLL")), + tAL(tCK * memSpec.memtimingspec.entries.at("AL")), + tACTPDEN(tCK * memSpec.memtimingspec.entries.at("ACTPDEN")), + tPRPDEN(tCK * memSpec.memtimingspec.entries.at("PRPDEN")), + tRTRS(tCK * memSpec.memtimingspec.entries.at("RTRS")) { - uint64_t deviceSizeBits = static_cast(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth; + uint64_t deviceSizeBits = + static_cast(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth; uint64_t deviceSizeBytes = deviceSizeBits / 8; memorySizeBytes = deviceSizeBytes * devicesPerRank * ranksPerChannel * numberOfChannels; std::cout << headline << std::endl; std::cout << "Memory Configuration:" << std::endl << std::endl; - std::cout << " Memory type: " << "STT-MRAM" << std::endl; - std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl; - std::cout << " Channels: " << numberOfChannels << std::endl; + std::cout << " Memory type: " + << "STT-MRAM" << std::endl; + std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl; + std::cout << " Channels: " << numberOfChannels << std::endl; std::cout << " Ranks per channel: " << ranksPerChannel << std::endl; - std::cout << " Banks per rank: " << banksPerRank << std::endl; + std::cout << " Banks per rank: " << banksPerRank << std::endl; std::cout << " Rows per bank: " << rowsPerBank << std::endl; std::cout << " Columns per row: " << columnsPerRow << std::endl; - std::cout << " Device width in bits: " << bitWidth << std::endl; - std::cout << " Device size in bits: " << deviceSizeBits << std::endl; - std::cout << " Device size in bytes: " << deviceSizeBytes << std::endl; + std::cout << " Device width in bits: " << bitWidth << std::endl; + std::cout << " Device size in bits: " << deviceSizeBits << std::endl; + std::cout << " Device size in bytes: " << deviceSizeBytes << std::endl; std::cout << " Devices per rank: " << devicesPerRank << std::endl; std::cout << std::endl; } // Returns the execution time for commands that have a fixed execution time -sc_time MemSpecSTTMRAM::getExecutionTime(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const +sc_time MemSpecSTTMRAM::getExecutionTime(Command command, + [[maybe_unused]] const tlm_generic_payload& payload) const { if (command == Command::PREPB || command == Command::PREAB) return tRP; @@ -129,12 +133,14 @@ sc_time MemSpecSTTMRAM::getExecutionTime(Command command, [[maybe_unused]] const return SC_ZERO_TIME; } -TimeInterval MemSpecSTTMRAM::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm::tlm_generic_payload & payload) const +TimeInterval MemSpecSTTMRAM::getIntervalOnDataStrobe( + Command command, [[maybe_unused]] const tlm::tlm_generic_payload& payload) const { if (command == Command::RD || command == Command::RDA) return {tRL, tRL + burstDuration}; - if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA) + if (command == Command::WR || command == Command::WRA || command == Command::MWR || + command == Command::MWRA) return {tWL, tWL + burstDuration}; SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.h index 9de3a320..e6c53f02 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.h @@ -47,7 +47,7 @@ namespace DRAMSys class MemSpecSTTMRAM final : public MemSpec { public: - explicit MemSpecSTTMRAM(const DRAMSys::Config::MemSpec &memSpec); + explicit MemSpecSTTMRAM(const DRAMSys::Config::MemSpec& memSpec); // Memspec Variables: const sc_core::sc_time tCKE; @@ -78,8 +78,11 @@ public: // Currents and Voltages: // TODO: to be completed - [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] sc_core::sc_time + getExecutionTime(Command command, const tlm::tlm_generic_payload& payload) const override; + [[nodiscard]] TimeInterval + getIntervalOnDataStrobe(Command command, + const tlm::tlm_generic_payload& payload) const override; [[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override; }; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp index cb4b5289..26e5bfc8 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp @@ -46,65 +46,79 @@ using namespace tlm; namespace DRAMSys { -MemSpecWideIO::MemSpecWideIO(const DRAMSys::Config::MemSpec &memSpec) - : MemSpec(memSpec, MemoryType::WideIO, - memSpec.memarchitecturespec.entries.at("nbrOfChannels"), - 1, - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks"), - 1, - memSpec.memarchitecturespec.entries.at("nbrOfBanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks") - * memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfDevices")), - tCKE (tCK * memSpec.memtimingspec.entries.at("CKE")), - tCKESR (tCK * memSpec.memtimingspec.entries.at("CKESR")), - tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")), - tRC (tCK * memSpec.memtimingspec.entries.at("RC")), - tRCD (tCK * memSpec.memtimingspec.entries.at("RCD")), - tRL (tCK * memSpec.memtimingspec.entries.at("RL")), - tWL (tCK * memSpec.memtimingspec.entries.at("WL")), - tWR (tCK * memSpec.memtimingspec.entries.at("WR")), - tXP (tCK * memSpec.memtimingspec.entries.at("XP")), - tXSR (tCK * memSpec.memtimingspec.entries.at("XSR")), - tREFI (tCK * memSpec.memtimingspec.entries.at("REFI")), - tRFC (tCK * memSpec.memtimingspec.entries.at("RFC")), - tRP (tCK * memSpec.memtimingspec.entries.at("RP")), - tDQSCK (tCK * memSpec.memtimingspec.entries.at("DQSCK")), - tAC (tCK * memSpec.memtimingspec.entries.at("AC")), - tCCD_R (tCK * memSpec.memtimingspec.entries.at("CCD_R")), - tCCD_W (tCK * memSpec.memtimingspec.entries.at("CCD_W")), - tRRD (tCK * memSpec.memtimingspec.entries.at("RRD")), - tTAW (tCK * memSpec.memtimingspec.entries.at("TAW")), - tWTR (tCK * memSpec.memtimingspec.entries.at("WTR")), - tRTRS (tCK * memSpec.memtimingspec.entries.at("RTRS")), - iDD0 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd0") : 0), - iDD2N (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2n") : 0), - iDD3N (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3n") : 0), - iDD4R (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd4r") : 0), - iDD4W (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd4w") : 0), - iDD5 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd5") : 0), - iDD6 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd6") : 0), - vDD (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("vdd") : 0), - iDD02 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd02") : 0), - iDD2P0 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2p0") : 0), - iDD2P02 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2p02") : 0), - iDD2P1 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2p1") : 0), - iDD2P12 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2p12") : 0), - iDD2N2 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2n2") : 0), - iDD3P0 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3p0") : 0), - iDD3P02 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3p02") : 0), - iDD3P1 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3p1") : 0), - iDD3P12 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3p12") : 0), - iDD3N2 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3n2") : 0), - iDD4R2 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd4r2") : 0), - iDD4W2 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd4w2") : 0), - iDD52 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd52") : 0), - iDD62 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd62") : 0), - vDD2 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("vdd2") : 0) +MemSpecWideIO::MemSpecWideIO(const DRAMSys::Config::MemSpec& memSpec) : + MemSpec(memSpec, + MemoryType::WideIO, + memSpec.memarchitecturespec.entries.at("nbrOfChannels"), + 1, + memSpec.memarchitecturespec.entries.at("nbrOfRanks"), + memSpec.memarchitecturespec.entries.at("nbrOfBanks"), + 1, + memSpec.memarchitecturespec.entries.at("nbrOfBanks"), + memSpec.memarchitecturespec.entries.at("nbrOfBanks") * + memSpec.memarchitecturespec.entries.at("nbrOfRanks"), + memSpec.memarchitecturespec.entries.at("nbrOfRanks"), + memSpec.memarchitecturespec.entries.at("nbrOfDevices")), + tCKE(tCK * memSpec.memtimingspec.entries.at("CKE")), + tCKESR(tCK * memSpec.memtimingspec.entries.at("CKESR")), + tRAS(tCK * memSpec.memtimingspec.entries.at("RAS")), + tRC(tCK * memSpec.memtimingspec.entries.at("RC")), + tRCD(tCK * memSpec.memtimingspec.entries.at("RCD")), + tRL(tCK * memSpec.memtimingspec.entries.at("RL")), + tWL(tCK * memSpec.memtimingspec.entries.at("WL")), + tWR(tCK * memSpec.memtimingspec.entries.at("WR")), + tXP(tCK * memSpec.memtimingspec.entries.at("XP")), + tXSR(tCK * memSpec.memtimingspec.entries.at("XSR")), + tREFI(tCK * memSpec.memtimingspec.entries.at("REFI")), + tRFC(tCK * memSpec.memtimingspec.entries.at("RFC")), + tRP(tCK * memSpec.memtimingspec.entries.at("RP")), + tDQSCK(tCK * memSpec.memtimingspec.entries.at("DQSCK")), + tAC(tCK * memSpec.memtimingspec.entries.at("AC")), + tCCD_R(tCK * memSpec.memtimingspec.entries.at("CCD_R")), + tCCD_W(tCK * memSpec.memtimingspec.entries.at("CCD_W")), + tRRD(tCK * memSpec.memtimingspec.entries.at("RRD")), + tTAW(tCK * memSpec.memtimingspec.entries.at("TAW")), + tWTR(tCK * memSpec.memtimingspec.entries.at("WTR")), + tRTRS(tCK * memSpec.memtimingspec.entries.at("RTRS")), + iDD0(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd0") : 0), + iDD2N(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2n") : 0), + iDD3N(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3n") : 0), + iDD4R(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd4r") : 0), + iDD4W(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd4w") : 0), + iDD5(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd5") : 0), + iDD6(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd6") : 0), + vDD(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("vdd") : 0), + iDD02(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd02") : 0), + iDD2P0(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2p0") + : 0), + iDD2P02(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2p02") + : 0), + iDD2P1(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2p1") + : 0), + iDD2P12(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2p12") + : 0), + iDD2N2(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2n2") + : 0), + iDD3P0(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3p0") + : 0), + iDD3P02(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3p02") + : 0), + iDD3P1(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3p1") + : 0), + iDD3P12(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3p12") + : 0), + iDD3N2(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3n2") + : 0), + iDD4R2(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd4r2") + : 0), + iDD4W2(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd4w2") + : 0), + iDD52(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd52") : 0), + iDD62(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd62") : 0), + vDD2(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("vdd2") : 0) { - uint64_t deviceSizeBits = static_cast(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth; + uint64_t deviceSizeBits = + static_cast(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth; uint64_t deviceSizeBytes = deviceSizeBits / 8; memorySizeBytes = deviceSizeBytes * ranksPerChannel * numberOfChannels; @@ -113,16 +127,17 @@ MemSpecWideIO::MemSpecWideIO(const DRAMSys::Config::MemSpec &memSpec) std::cout << headline << std::endl; std::cout << "Memory Configuration:" << std::endl << std::endl; - std::cout << " Memory type: " << "Wide I/O" << std::endl; - std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl; - std::cout << " Channels: " << numberOfChannels << std::endl; + std::cout << " Memory type: " + << "Wide I/O" << std::endl; + std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl; + std::cout << " Channels: " << numberOfChannels << std::endl; std::cout << " Ranks per channel: " << ranksPerChannel << std::endl; - std::cout << " Banks per rank: " << banksPerRank << std::endl; + std::cout << " Banks per rank: " << banksPerRank << std::endl; std::cout << " Rows per bank: " << rowsPerBank << std::endl; std::cout << " Columns per row: " << columnsPerRow << std::endl; - std::cout << " Device width in bits: " << bitWidth << std::endl; - std::cout << " Device size in bits: " << deviceSizeBits << std::endl; - std::cout << " Device size in bytes: " << deviceSizeBytes << std::endl; + std::cout << " Device width in bits: " << bitWidth << std::endl; + std::cout << " Device size in bits: " << deviceSizeBits << std::endl; + std::cout << " Device size in bytes: " << deviceSizeBytes << std::endl; std::cout << " Devices per rank: " << devicesPerRank << std::endl; std::cout << std::endl; } @@ -133,7 +148,8 @@ sc_time MemSpecWideIO::getRefreshIntervalAB() const } // Returns the execution time for commands that have a fixed execution time -sc_time MemSpecWideIO::getExecutionTime(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const +sc_time MemSpecWideIO::getExecutionTime(Command command, + [[maybe_unused]] const tlm_generic_payload& payload) const { if (command == Command::PREPB || command == Command::PREAB) return tRP; @@ -161,12 +177,15 @@ sc_time MemSpecWideIO::getExecutionTime(Command command, [[maybe_unused]] const throw; } -TimeInterval MemSpecWideIO::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const +TimeInterval +MemSpecWideIO::getIntervalOnDataStrobe(Command command, + [[maybe_unused]] const tlm_generic_payload& payload) const { if (command == Command::RD || command == Command::RDA) return {tRL + tAC, tRL + tAC + burstDuration}; - if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA) + if (command == Command::WR || command == Command::WRA || command == Command::MWR || + command == Command::MWRA) return {tWL, tWL + burstDuration}; SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.h index 4b76fa2f..2daad86f 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.h @@ -47,7 +47,7 @@ namespace DRAMSys class MemSpecWideIO final : public MemSpec { public: - explicit MemSpecWideIO(const DRAMSys::Config::MemSpec &memSpec); + explicit MemSpecWideIO(const DRAMSys::Config::MemSpec& memSpec); // Memspec Variables: const sc_core::sc_time tCKE; @@ -100,8 +100,11 @@ public: [[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override; - [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] sc_core::sc_time + getExecutionTime(Command command, const tlm::tlm_generic_payload& payload) const override; + [[nodiscard]] TimeInterval + getIntervalOnDataStrobe(Command command, + const tlm::tlm_generic_payload& payload) const override; [[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override; }; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp index 533665e4..15b0e8b4 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp @@ -46,62 +46,65 @@ using namespace tlm; namespace DRAMSys { -MemSpecWideIO2::MemSpecWideIO2(const DRAMSys::Config::MemSpec &memSpec) - : MemSpec(memSpec, MemoryType::WideIO2, - memSpec.memarchitecturespec.entries.at("nbrOfChannels"), - 1, - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks"), - 1, - memSpec.memarchitecturespec.entries.at("nbrOfBanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks") - * memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfDevices")), - tDQSCK (tCK * memSpec.memtimingspec.entries.at("DQSCK")), - tDQSS (tCK * memSpec.memtimingspec.entries.at("DQSS")), - tCKE (tCK * memSpec.memtimingspec.entries.at("CKE")), - tRL (tCK * memSpec.memtimingspec.entries.at("RL")), - tWL (tCK * memSpec.memtimingspec.entries.at("WL")), - tRCpb (tCK * memSpec.memtimingspec.entries.at("RCPB")), - tRCab (tCK * memSpec.memtimingspec.entries.at("RCAB")), - tCKESR (tCK * memSpec.memtimingspec.entries.at("CKESR")), - tXSR (tCK * memSpec.memtimingspec.entries.at("XSR")), - tXP (tCK * memSpec.memtimingspec.entries.at("XP")), - tCCD (tCK * memSpec.memtimingspec.entries.at("CCD")), - tRTP (tCK * memSpec.memtimingspec.entries.at("RTP")), - tRCD (tCK * memSpec.memtimingspec.entries.at("RCD")), - tRPpb (tCK * memSpec.memtimingspec.entries.at("RPPB")), - tRPab (tCK * memSpec.memtimingspec.entries.at("RPAB")), - tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")), - tWR (tCK * memSpec.memtimingspec.entries.at("WR")), - tWTR (tCK * memSpec.memtimingspec.entries.at("WTR")), - tRRD (tCK * memSpec.memtimingspec.entries.at("RRD")), - tFAW (tCK * memSpec.memtimingspec.entries.at("FAW")), - tREFI (tCK * static_cast(memSpec.memtimingspec.entries.at("REFI") - * memSpec.memtimingspec.entries.at("REFM"))), - tREFIpb (tCK * static_cast(memSpec.memtimingspec.entries.at("REFIPB") - * memSpec.memtimingspec.entries.at("REFM"))), - tRFCab (tCK * memSpec.memtimingspec.entries.at("RFCAB")), - tRFCpb (tCK * memSpec.memtimingspec.entries.at("RFCPB")), - tRTRS (tCK * memSpec.memtimingspec.entries.at("RTRS")) +MemSpecWideIO2::MemSpecWideIO2(const DRAMSys::Config::MemSpec& memSpec) : + MemSpec(memSpec, + MemoryType::WideIO2, + memSpec.memarchitecturespec.entries.at("nbrOfChannels"), + 1, + memSpec.memarchitecturespec.entries.at("nbrOfRanks"), + memSpec.memarchitecturespec.entries.at("nbrOfBanks"), + 1, + memSpec.memarchitecturespec.entries.at("nbrOfBanks"), + memSpec.memarchitecturespec.entries.at("nbrOfBanks") * + memSpec.memarchitecturespec.entries.at("nbrOfRanks"), + memSpec.memarchitecturespec.entries.at("nbrOfRanks"), + memSpec.memarchitecturespec.entries.at("nbrOfDevices")), + tDQSCK(tCK * memSpec.memtimingspec.entries.at("DQSCK")), + tDQSS(tCK * memSpec.memtimingspec.entries.at("DQSS")), + tCKE(tCK * memSpec.memtimingspec.entries.at("CKE")), + tRL(tCK * memSpec.memtimingspec.entries.at("RL")), + tWL(tCK * memSpec.memtimingspec.entries.at("WL")), + tRCpb(tCK * memSpec.memtimingspec.entries.at("RCPB")), + tRCab(tCK * memSpec.memtimingspec.entries.at("RCAB")), + tCKESR(tCK * memSpec.memtimingspec.entries.at("CKESR")), + tXSR(tCK * memSpec.memtimingspec.entries.at("XSR")), + tXP(tCK * memSpec.memtimingspec.entries.at("XP")), + tCCD(tCK * memSpec.memtimingspec.entries.at("CCD")), + tRTP(tCK * memSpec.memtimingspec.entries.at("RTP")), + tRCD(tCK * memSpec.memtimingspec.entries.at("RCD")), + tRPpb(tCK * memSpec.memtimingspec.entries.at("RPPB")), + tRPab(tCK * memSpec.memtimingspec.entries.at("RPAB")), + tRAS(tCK * memSpec.memtimingspec.entries.at("RAS")), + tWR(tCK * memSpec.memtimingspec.entries.at("WR")), + tWTR(tCK * memSpec.memtimingspec.entries.at("WTR")), + tRRD(tCK * memSpec.memtimingspec.entries.at("RRD")), + tFAW(tCK * memSpec.memtimingspec.entries.at("FAW")), + tREFI(tCK * static_cast(memSpec.memtimingspec.entries.at("REFI") * + memSpec.memtimingspec.entries.at("REFM"))), + tREFIpb(tCK * static_cast(memSpec.memtimingspec.entries.at("REFIPB") * + memSpec.memtimingspec.entries.at("REFM"))), + tRFCab(tCK * memSpec.memtimingspec.entries.at("RFCAB")), + tRFCpb(tCK * memSpec.memtimingspec.entries.at("RFCPB")), + tRTRS(tCK * memSpec.memtimingspec.entries.at("RTRS")) { - uint64_t deviceSizeBits = static_cast(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth; + uint64_t deviceSizeBits = + static_cast(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth; uint64_t deviceSizeBytes = deviceSizeBits / 8; memorySizeBytes = deviceSizeBytes * ranksPerChannel * numberOfChannels; std::cout << headline << std::endl; std::cout << "Memory Configuration:" << std::endl << std::endl; - std::cout << " Memory type: " << "Wide I/O 2" << std::endl; - std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl; - std::cout << " Channels: " << numberOfChannels << std::endl; + std::cout << " Memory type: " + << "Wide I/O 2" << std::endl; + std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl; + std::cout << " Channels: " << numberOfChannels << std::endl; std::cout << " Ranks per channel: " << ranksPerChannel << std::endl; - std::cout << " Banks per rank: " << banksPerRank << std::endl; + std::cout << " Banks per rank: " << banksPerRank << std::endl; std::cout << " Rows per bank: " << rowsPerBank << std::endl; std::cout << " Columns per row: " << columnsPerRow << std::endl; - std::cout << " Device width in bits: " << bitWidth << std::endl; - std::cout << " Device size in bits: " << deviceSizeBits << std::endl; - std::cout << " Device size in bytes: " << deviceSizeBytes << std::endl; + std::cout << " Device width in bits: " << bitWidth << std::endl; + std::cout << " Device size in bits: " << deviceSizeBits << std::endl; + std::cout << " Device size in bytes: " << deviceSizeBytes << std::endl; std::cout << " Devices per rank: " << devicesPerRank << std::endl; std::cout << std::endl; } @@ -117,7 +120,8 @@ sc_time MemSpecWideIO2::getRefreshIntervalPB() const } // Returns the execution time for commands that have a fixed execution time -sc_time MemSpecWideIO2::getExecutionTime(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const +sc_time MemSpecWideIO2::getExecutionTime(Command command, + [[maybe_unused]] const tlm_generic_payload& payload) const { if (command == Command::PREPB) return tRPpb; @@ -151,12 +155,15 @@ sc_time MemSpecWideIO2::getExecutionTime(Command command, [[maybe_unused]] const throw; } -TimeInterval MemSpecWideIO2::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const +TimeInterval +MemSpecWideIO2::getIntervalOnDataStrobe(Command command, + [[maybe_unused]] const tlm_generic_payload& payload) const { if (command == Command::RD || command == Command::RDA) return {tRL + tDQSCK, tRL + tDQSCK + burstDuration}; - if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA) + if (command == Command::WR || command == Command::WRA || command == Command::MWR || + command == Command::MWRA) return {tWL + tDQSS, tWL + tDQSS + burstDuration}; SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.h index e6a62637..19e32455 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.h @@ -47,7 +47,7 @@ namespace DRAMSys class MemSpecWideIO2 final : public MemSpec { public: - explicit MemSpecWideIO2(const DRAMSys::Config::MemSpec &memSpec); + explicit MemSpecWideIO2(const DRAMSys::Config::MemSpec& memSpec); // Memspec Variables: const sc_core::sc_time tDQSCK; @@ -82,8 +82,11 @@ public: [[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override; [[nodiscard]] sc_core::sc_time getRefreshIntervalPB() const override; - [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] sc_core::sc_time + getExecutionTime(Command command, const tlm::tlm_generic_payload& payload) const override; + [[nodiscard]] TimeInterval + getIntervalOnDataStrobe(Command command, + const tlm::tlm_generic_payload& payload) const override; [[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override; }; diff --git a/src/libdramsys/DRAMSys/controller/BankMachine.cpp b/src/libdramsys/DRAMSys/controller/BankMachine.cpp index 84ffe90b..288b816e 100644 --- a/src/libdramsys/DRAMSys/controller/BankMachine.cpp +++ b/src/libdramsys/DRAMSys/controller/BankMachine.cpp @@ -69,24 +69,35 @@ void BankMachine::update(Command command) keepTrans = true; refreshManagementCounter++; break; - case Command::PREPB: case Command::PRESB: case Command::PREAB: + case Command::PREPB: + case Command::PRESB: + case Command::PREAB: state = State::Precharged; keepTrans = false; break; - case Command::RD: case Command::WR: case Command::MWR: + case Command::RD: + case Command::WR: + case Command::MWR: currentPayload = nullptr; keepTrans = false; break; - case Command::RDA: case Command::WRA: case Command::MWRA: + case Command::RDA: + case Command::WRA: + case Command::MWRA: state = State::Precharged; currentPayload = nullptr; keepTrans = false; break; - case Command::PDEA: case Command::PDEP: case Command::SREFEN: + case Command::PDEA: + case Command::PDEP: + case Command::SREFEN: assert(!keepTrans); sleeping = true; break; - case Command::REFPB: case Command::REFP2B: case Command::REFSB: case Command::REFAB: + case Command::REFPB: + case Command::REFP2B: + case Command::REFSB: + case Command::REFAB: sleeping = false; blocked = false; @@ -98,7 +109,10 @@ void BankMachine::update(Command command) refreshManagementCounter = 0; } break; - case Command::RFMPB: case Command::RFMP2B: case Command::RFMSB: case Command::RFMAB: + case Command::RFMPB: + case Command::RFMP2B: + case Command::RFMSB: + case Command::RFMAB: assert(!keepTrans); sleeping = false; blocked = false; @@ -111,7 +125,8 @@ void BankMachine::update(Command command) refreshManagementCounter = 0; } break; - case Command::PDXA: case Command::PDXP: + case Command::PDXA: + case Command::PDXP: assert(!keepTrans); sleeping = false; break; @@ -166,8 +181,12 @@ bool BankMachine::isPrecharged() const return state == State::Precharged; } -BankMachineOpen::BankMachineOpen(const Configuration& config, const SchedulerIF& scheduler, Bank bank) - : BankMachine(config, scheduler, bank) {} +BankMachineOpen::BankMachineOpen(const Configuration& config, + const SchedulerIF& scheduler, + Bank bank) : + BankMachine(config, scheduler, bank) +{ +} void BankMachineOpen::evaluate() { @@ -175,7 +194,7 @@ void BankMachineOpen::evaluate() if (!(sleeping || blocked)) { - tlm_generic_payload *newPayload = scheduler.getNextRequest(*this); + tlm_generic_payload* newPayload = scheduler.getNextRequest(*this); if (newPayload == nullptr) return; @@ -201,7 +220,8 @@ void BankMachineOpen::evaluate() nextCommand = Command::RD; else { - nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWR : Command::WR; + nextCommand = + memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWR : Command::WR; } } else // row miss @@ -210,8 +230,12 @@ void BankMachineOpen::evaluate() } } -BankMachineClosed::BankMachineClosed(const Configuration& config, const SchedulerIF& scheduler, Bank bank) - : BankMachine(config, scheduler, bank) {} +BankMachineClosed::BankMachineClosed(const Configuration& config, + const SchedulerIF& scheduler, + Bank bank) : + BankMachine(config, scheduler, bank) +{ +} void BankMachineClosed::evaluate() { @@ -219,7 +243,7 @@ void BankMachineClosed::evaluate() if (!(sleeping || blocked)) { - tlm_generic_payload *newPayload = scheduler.getNextRequest(*this); + tlm_generic_payload* newPayload = scheduler.getNextRequest(*this); if (newPayload == nullptr) return; @@ -243,14 +267,19 @@ void BankMachineClosed::evaluate() nextCommand = Command::RDA; else { - nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWRA : Command::WRA; + nextCommand = + memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWRA : Command::WRA; } } } } -BankMachineOpenAdaptive::BankMachineOpenAdaptive(const Configuration& config, const SchedulerIF& scheduler, Bank bank) - : BankMachine(config, scheduler, bank) {} +BankMachineOpenAdaptive::BankMachineOpenAdaptive(const Configuration& config, + const SchedulerIF& scheduler, + Bank bank) : + BankMachine(config, scheduler, bank) +{ +} void BankMachineOpenAdaptive::evaluate() { @@ -258,7 +287,7 @@ void BankMachineOpenAdaptive::evaluate() if (!(sleeping || blocked)) { - tlm_generic_payload *newPayload = scheduler.getNextRequest(*this); + tlm_generic_payload* newPayload = scheduler.getNextRequest(*this); if (newPayload == nullptr) return; @@ -287,7 +316,8 @@ void BankMachineOpenAdaptive::evaluate() nextCommand = Command::RDA; else { - nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWRA : Command::WRA; + nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWRA + : Command::WRA; } } else @@ -297,7 +327,8 @@ void BankMachineOpenAdaptive::evaluate() nextCommand = Command::RD; else { - nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWR : Command::WR; + nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWR + : Command::WR; } } } @@ -307,9 +338,12 @@ void BankMachineOpenAdaptive::evaluate() } } -BankMachineClosedAdaptive::BankMachineClosedAdaptive(const Configuration& config, const SchedulerIF& scheduler, - Bank bank) - : BankMachine(config, scheduler, bank) {} +BankMachineClosedAdaptive::BankMachineClosedAdaptive(const Configuration& config, + const SchedulerIF& scheduler, + Bank bank) : + BankMachine(config, scheduler, bank) +{ +} void BankMachineClosedAdaptive::evaluate() { @@ -317,7 +351,7 @@ void BankMachineClosedAdaptive::evaluate() if (!(sleeping || blocked)) { - tlm_generic_payload *newPayload = scheduler.getNextRequest(*this); + tlm_generic_payload* newPayload = scheduler.getNextRequest(*this); if (newPayload == nullptr) return; @@ -345,7 +379,8 @@ void BankMachineClosedAdaptive::evaluate() nextCommand = Command::RD; else { - nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWR : Command::WR; + nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWR + : Command::WR; } } else @@ -355,7 +390,8 @@ void BankMachineClosedAdaptive::evaluate() nextCommand = Command::RDA; else { - nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWRA : Command::WRA; + nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWRA + : Command::WRA; } } } diff --git a/src/libdramsys/DRAMSys/controller/BankMachine.h b/src/libdramsys/DRAMSys/controller/BankMachine.h index 8dd4ab1a..00d805f2 100644 --- a/src/libdramsys/DRAMSys/controller/BankMachine.h +++ b/src/libdramsys/DRAMSys/controller/BankMachine.h @@ -35,13 +35,13 @@ #ifndef BANKMACHINE_H #define BANKMACHINE_H -#include "DRAMSys/controller/ManagerIF.h" -#include "DRAMSys/controller/scheduler/SchedulerIF.h" -#include "DRAMSys/controller/checker/CheckerIF.h" -#include "DRAMSys/controller/Command.h" #include "DRAMSys/common/dramExtensions.h" -#include "DRAMSys/configuration/memspec/MemSpec.h" #include "DRAMSys/configuration/Configuration.h" +#include "DRAMSys/configuration/memspec/MemSpec.h" +#include "DRAMSys/controller/Command.h" +#include "DRAMSys/controller/ManagerIF.h" +#include "DRAMSys/controller/checker/CheckerIF.h" +#include "DRAMSys/controller/scheduler/SchedulerIF.h" #include #include @@ -66,7 +66,11 @@ public: [[nodiscard]] uint64_t getRefreshManagementCounter() const; protected: - enum class State {Precharged, Activated} state = State::Precharged; + enum class State + { + Precharged, + Activated + } state = State::Precharged; BankMachine(const Configuration& config, const SchedulerIF& scheduler, Bank bank); const MemSpec& memSpec; tlm::tlm_generic_payload* currentPayload = nullptr; diff --git a/src/libdramsys/DRAMSys/controller/Command.cpp b/src/libdramsys/DRAMSys/controller/Command.cpp index 577ca9d2..d66b332c 100644 --- a/src/libdramsys/DRAMSys/controller/Command.cpp +++ b/src/libdramsys/DRAMSys/controller/Command.cpp @@ -71,77 +71,78 @@ bool isFixedCommandPhase(tlm::tlm_phase phase) bool isRefreshCommandPhase(tlm::tlm_phase phase) { - return (phase == BEGIN_REFPB || phase == BEGIN_REFP2B || phase == BEGIN_REFSB || phase == BEGIN_REFAB - || phase == BEGIN_RFMPB || phase == BEGIN_RFMP2B || phase == BEGIN_RFMSB || phase == BEGIN_RFMAB); + return (phase == BEGIN_REFPB || phase == BEGIN_REFP2B || phase == BEGIN_REFSB || + phase == BEGIN_REFAB || phase == BEGIN_RFMPB || phase == BEGIN_RFMP2B || + phase == BEGIN_RFMSB || phase == BEGIN_RFMAB); } -Command::Command(Command::Type type) : type(type) {} +Command::Command(Command::Type type) : type(type) +{ +} Command::Command(tlm_phase phase) { assert(phase >= BEGIN_NOP && phase <= END_SREF); - static constexpr std::array commandOfPhase = - { - Command::NOP, // 0 - Command::RD, // 1 - Command::WR, // 2 - Command::MWR, // 3 - Command::RDA, // 4 - Command::WRA, // 5 - Command::MWRA, // 6 - Command::ACT, // 7 - Command::PREPB, // 8 - Command::REFPB, // 9 - Command::RFMPB, // 10 - Command::REFP2B, // 11 - Command::RFMP2B, // 12 - Command::PRESB, // 13 - Command::REFSB, // 14 - Command::RFMSB, // 15 - Command::PREAB, // 16 - Command::REFAB, // 17 - Command::RFMAB, // 18 - Command::PDEA, // 19 - Command::PDEP, // 20 - Command::SREFEN, // 21 - Command::PDXA, // 22 - Command::PDXP, // 23 - Command::SREFEX // 24 - }; + static constexpr std::array commandOfPhase = { + Command::NOP, // 0 + Command::RD, // 1 + Command::WR, // 2 + Command::MWR, // 3 + Command::RDA, // 4 + Command::WRA, // 5 + Command::MWRA, // 6 + Command::ACT, // 7 + Command::PREPB, // 8 + Command::REFPB, // 9 + Command::RFMPB, // 10 + Command::REFP2B, // 11 + Command::RFMP2B, // 12 + Command::PRESB, // 13 + Command::REFSB, // 14 + Command::RFMSB, // 15 + Command::PREAB, // 16 + Command::REFAB, // 17 + Command::RFMAB, // 18 + Command::PDEA, // 19 + Command::PDEP, // 20 + Command::SREFEN, // 21 + Command::PDXA, // 22 + Command::PDXP, // 23 + Command::SREFEX // 24 + }; type = commandOfPhase[phase - BEGIN_NOP]; } std::string Command::toString() const { assert(type >= Command::NOP && type <= Command::SREFEX); - static std::array stringOfCommand = - { - "NOP", // 0 - "RD", // 1 - "WR", // 2 - "MWR", // 3 - "RDA", // 4 - "WRA", // 5 - "MWRA", // 6 - "ACT", // 7 - "PREPB", // 8 - "REFPB", // 9 - "RFMPB", // 10 - "REFP2B", // 11 - "RFMP2B", // 12 - "PRESB", // 13 - "REFSB", // 14 - "RFMSB", // 15 - "PREAB", // 16 - "REFAB", // 17 - "RFMAB", // 18 - "PDEA", // 19 - "PDEP", // 20 - "SREFEN", // 21 - "PDXA", // 22 - "PDXP", // 23 - "SREFEX" // 24 - }; + static std::array stringOfCommand = { + "NOP", // 0 + "RD", // 1 + "WR", // 2 + "MWR", // 3 + "RDA", // 4 + "WRA", // 5 + "MWRA", // 6 + "ACT", // 7 + "PREPB", // 8 + "REFPB", // 9 + "RFMPB", // 10 + "REFP2B", // 11 + "RFMP2B", // 12 + "PRESB", // 13 + "REFSB", // 14 + "RFMSB", // 15 + "PREAB", // 16 + "REFAB", // 17 + "RFMAB", // 18 + "PDEA", // 19 + "PDEP", // 20 + "SREFEN", // 21 + "PDXA", // 22 + "PDXP", // 23 + "SREFEX" // 24 + }; return stringOfCommand[type]; } @@ -153,34 +154,33 @@ unsigned Command::numberOfCommands() tlm_phase Command::toPhase() const { assert(type >= Command::NOP && type <= Command::SREFEX); - static std::array phaseOfCommand = - { - BEGIN_NOP, // 0 - BEGIN_RD, // 1 - BEGIN_WR, // 2 - BEGIN_MWR, // 3 - BEGIN_RDA, // 4 - BEGIN_WRA, // 5 - BEGIN_MWRA, // 6 - BEGIN_ACT, // 7 - BEGIN_PREPB, // 8 - BEGIN_REFPB, // 9 - BEGIN_RFMPB, // 10 - BEGIN_REFP2B, // 11 - BEGIN_RFMP2B, // 12 - BEGIN_PRESB, // 13 - BEGIN_REFSB, // 14 - BEGIN_RFMSB, // 15 - BEGIN_PREAB, // 16 - BEGIN_REFAB, // 17 - BEGIN_RFMAB, // 18 - BEGIN_PDNA, // 19 - BEGIN_PDNP, // 20 - BEGIN_SREF, // 21 - END_PDNA, // 22 - END_PDNP, // 23 - END_SREF // 24 - }; + static std::array phaseOfCommand = { + BEGIN_NOP, // 0 + BEGIN_RD, // 1 + BEGIN_WR, // 2 + BEGIN_MWR, // 3 + BEGIN_RDA, // 4 + BEGIN_WRA, // 5 + BEGIN_MWRA, // 6 + BEGIN_ACT, // 7 + BEGIN_PREPB, // 8 + BEGIN_REFPB, // 9 + BEGIN_RFMPB, // 10 + BEGIN_REFP2B, // 11 + BEGIN_RFMP2B, // 12 + BEGIN_PRESB, // 13 + BEGIN_REFSB, // 14 + BEGIN_RFMSB, // 15 + BEGIN_PREAB, // 16 + BEGIN_REFAB, // 17 + BEGIN_RFMAB, // 18 + BEGIN_PDNA, // 19 + BEGIN_PDNP, // 20 + BEGIN_SREF, // 21 + END_PDNA, // 22 + END_PDNP, // 23 + END_SREF // 24 + }; return phaseOfCommand[type]; } @@ -189,34 +189,33 @@ MemCommand::cmds phaseToDRAMPowerCommand(tlm_phase phase) { // TODO: add correct phases when DRAMPower supports DDR5 same bank refresh assert(phase >= BEGIN_NOP && phase <= END_SREF); - static std::array phaseOfCommand = - { - MemCommand::NOP, // 0 - MemCommand::RD, // 1 - MemCommand::WR, // 2 - MemCommand::NOP, // 3 - MemCommand::RDA, // 4 - MemCommand::WRA, // 5 - MemCommand::NOP, // 6 - MemCommand::ACT, // 7 - MemCommand::PRE, // 8, PREPB - MemCommand::REFB, // 9, REFPB - MemCommand::NOP, // 10, RFMPB - MemCommand::NOP, // 11, REFP2B - MemCommand::NOP, // 12, RFMP2B - MemCommand::NOP, // 13, PRESB - MemCommand::NOP, // 14, REFSB - MemCommand::NOP, // 15, RFMSB - MemCommand::PREA, // 16, PREAB - MemCommand::REF, // 17, REFAB - MemCommand::NOP, // 18, RFMAB - MemCommand::PDN_S_ACT, // 19 - MemCommand::PDN_S_PRE, // 20 - MemCommand::SREN, // 21 - MemCommand::PUP_ACT, // 22 - MemCommand::PUP_PRE, // 23 - MemCommand::SREX // 24 - }; + static std::array phaseOfCommand = { + MemCommand::NOP, // 0 + MemCommand::RD, // 1 + MemCommand::WR, // 2 + MemCommand::NOP, // 3 + MemCommand::RDA, // 4 + MemCommand::WRA, // 5 + MemCommand::NOP, // 6 + MemCommand::ACT, // 7 + MemCommand::PRE, // 8, PREPB + MemCommand::REFB, // 9, REFPB + MemCommand::NOP, // 10, RFMPB + MemCommand::NOP, // 11, REFP2B + MemCommand::NOP, // 12, RFMP2B + MemCommand::NOP, // 13, PRESB + MemCommand::NOP, // 14, REFSB + MemCommand::NOP, // 15, RFMSB + MemCommand::PREA, // 16, PREAB + MemCommand::REF, // 17, REFAB + MemCommand::NOP, // 18, RFMAB + MemCommand::PDN_S_ACT, // 19 + MemCommand::PDN_S_PRE, // 20 + MemCommand::SREN, // 21 + MemCommand::PUP_ACT, // 22 + MemCommand::PUP_PRE, // 23 + MemCommand::SREX // 24 + }; return phaseOfCommand[phase - BEGIN_NOP]; } #endif diff --git a/src/libdramsys/DRAMSys/controller/Command.h b/src/libdramsys/DRAMSys/controller/Command.h index 26d39df3..952be4be 100644 --- a/src/libdramsys/DRAMSys/controller/Command.h +++ b/src/libdramsys/DRAMSys/controller/Command.h @@ -42,10 +42,10 @@ #endif #include -#include -#include #include #include +#include +#include namespace DRAMSys { @@ -77,13 +77,13 @@ DECLARE_EXTENDED_PHASE(BEGIN_PREAB); // 21 DECLARE_EXTENDED_PHASE(BEGIN_REFAB); // 22 DECLARE_EXTENDED_PHASE(BEGIN_RFMAB); // 23 -DECLARE_EXTENDED_PHASE(BEGIN_PDNA); // 24 -DECLARE_EXTENDED_PHASE(BEGIN_PDNP); // 25 -DECLARE_EXTENDED_PHASE(BEGIN_SREF); // 26 +DECLARE_EXTENDED_PHASE(BEGIN_PDNA); // 24 +DECLARE_EXTENDED_PHASE(BEGIN_PDNP); // 25 +DECLARE_EXTENDED_PHASE(BEGIN_SREF); // 26 -DECLARE_EXTENDED_PHASE(END_PDNA); // 27 -DECLARE_EXTENDED_PHASE(END_PDNP); // 28 -DECLARE_EXTENDED_PHASE(END_SREF); // 29 +DECLARE_EXTENDED_PHASE(END_PDNA); // 27 +DECLARE_EXTENDED_PHASE(END_PDNP); // 28 +DECLARE_EXTENDED_PHASE(END_SREF); // 29 #ifdef DRAMPOWER DRAMPower::MemCommand::cmds phaseToDRAMPowerCommand(tlm::tlm_phase phase); @@ -146,10 +146,7 @@ public: [[nodiscard]] bool isCasCommand() const; [[nodiscard]] bool isRasCommand() const; - constexpr operator uint8_t() const - { - return type; - } + constexpr operator uint8_t() const { return type; } }; struct CommandTuple diff --git a/src/libdramsys/DRAMSys/controller/Controller.cpp b/src/libdramsys/DRAMSys/controller/Controller.cpp index 74ff6042..7cdc53e5 100644 --- a/src/libdramsys/DRAMSys/controller/Controller.cpp +++ b/src/libdramsys/DRAMSys/controller/Controller.cpp @@ -34,34 +34,34 @@ #include "Controller.h" +#include "DRAMSys/common/dramExtensions.h" +#include "DRAMSys/configuration/Configuration.h" #include "DRAMSys/controller/checker/CheckerDDR3.h" #include "DRAMSys/controller/checker/CheckerDDR4.h" -#include "DRAMSys/controller/checker/CheckerWideIO.h" -#include "DRAMSys/controller/checker/CheckerLPDDR4.h" -#include "DRAMSys/controller/checker/CheckerWideIO2.h" -#include "DRAMSys/controller/checker/CheckerHBM2.h" #include "DRAMSys/controller/checker/CheckerGDDR5.h" #include "DRAMSys/controller/checker/CheckerGDDR5X.h" #include "DRAMSys/controller/checker/CheckerGDDR6.h" +#include "DRAMSys/controller/checker/CheckerHBM2.h" +#include "DRAMSys/controller/checker/CheckerLPDDR4.h" #include "DRAMSys/controller/checker/CheckerSTTMRAM.h" +#include "DRAMSys/controller/checker/CheckerWideIO.h" +#include "DRAMSys/controller/checker/CheckerWideIO2.h" +#include "DRAMSys/controller/cmdmux/CmdMuxOldest.h" +#include "DRAMSys/controller/cmdmux/CmdMuxStrict.h" +#include "DRAMSys/controller/powerdown/PowerDownManagerDummy.h" +#include "DRAMSys/controller/powerdown/PowerDownManagerStaggered.h" +#include "DRAMSys/controller/refresh/RefreshManagerAllBank.h" +#include "DRAMSys/controller/refresh/RefreshManagerDummy.h" +#include "DRAMSys/controller/refresh/RefreshManagerPer2Bank.h" +#include "DRAMSys/controller/refresh/RefreshManagerPerBank.h" +#include "DRAMSys/controller/refresh/RefreshManagerSameBank.h" +#include "DRAMSys/controller/respqueue/RespQueueFifo.h" +#include "DRAMSys/controller/respqueue/RespQueueReorder.h" #include "DRAMSys/controller/scheduler/SchedulerFifo.h" #include "DRAMSys/controller/scheduler/SchedulerFrFcfs.h" #include "DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.h" #include "DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.h" #include "DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.h" -#include "DRAMSys/controller/cmdmux/CmdMuxStrict.h" -#include "DRAMSys/controller/cmdmux/CmdMuxOldest.h" -#include "DRAMSys/controller/respqueue/RespQueueFifo.h" -#include "DRAMSys/controller/respqueue/RespQueueReorder.h" -#include "DRAMSys/controller/refresh/RefreshManagerDummy.h" -#include "DRAMSys/controller/refresh/RefreshManagerAllBank.h" -#include "DRAMSys/controller/refresh/RefreshManagerPerBank.h" -#include "DRAMSys/controller/refresh/RefreshManagerPer2Bank.h" -#include "DRAMSys/controller/refresh/RefreshManagerSameBank.h" -#include "DRAMSys/controller/powerdown/PowerDownManagerStaggered.h" -#include "DRAMSys/controller/powerdown/PowerDownManagerDummy.h" -#include "DRAMSys/configuration/Configuration.h" -#include "DRAMSys/common/dramExtensions.h" #ifdef DDR5_SIM #include "DRAMSys/controller/checker/CheckerDDR5.h" @@ -79,11 +79,17 @@ using namespace tlm; namespace DRAMSys { -Controller::Controller(const sc_module_name& name, const Configuration& config, const AddressDecoder& addressDecoder) : - ControllerIF(name, config), thinkDelayFw(config.thinkDelayFw), - thinkDelayBw(config.thinkDelayBw), phyDelayFw(config.phyDelayFw), - phyDelayBw(config.phyDelayBw), blockingReadDelay(config.blockingReadDelay), - blockingWriteDelay(config.blockingWriteDelay), addressDecoder(addressDecoder), +Controller::Controller(const sc_module_name& name, + const Configuration& config, + const AddressDecoder& addressDecoder) : + ControllerIF(name, config), + thinkDelayFw(config.thinkDelayFw), + thinkDelayBw(config.thinkDelayBw), + phyDelayFw(config.phyDelayFw), + phyDelayBw(config.phyDelayBw), + blockingReadDelay(config.blockingReadDelay), + blockingWriteDelay(config.blockingWriteDelay), + addressDecoder(addressDecoder), minBytesPerBurst(config.memSpec->defaultBytesPerBurst), maxBytesPerBurst(config.memSpec->maxBytesPerBurst) { @@ -129,7 +135,6 @@ Controller::Controller(const sc_module_name& name, const Configuration& config, checker = std::make_unique(config); #endif - // instantiate scheduler and command mux if (config.scheduler == Configuration::Scheduler::Fifo) scheduler = std::make_unique(config); @@ -166,35 +171,35 @@ Controller::Controller(const sc_module_name& name, const Configuration& config, if (config.pagePolicy == Configuration::PagePolicy::Open) { for (unsigned bankID = 0; bankID < memSpec.banksPerChannel; bankID++) - bankMachines.push_back(std::make_unique - (config, *scheduler, Bank(bankID))); + bankMachines.push_back( + std::make_unique(config, *scheduler, Bank(bankID))); } else if (config.pagePolicy == Configuration::PagePolicy::OpenAdaptive) { for (unsigned bankID = 0; bankID < memSpec.banksPerChannel; bankID++) - bankMachines.push_back(std::make_unique - (config, *scheduler, Bank(bankID))); + bankMachines.push_back( + std::make_unique(config, *scheduler, Bank(bankID))); } else if (config.pagePolicy == Configuration::PagePolicy::Closed) { for (unsigned bankID = 0; bankID < memSpec.banksPerChannel; bankID++) - bankMachines.push_back(std::make_unique - (config, *scheduler, Bank(bankID))); + bankMachines.push_back( + std::make_unique(config, *scheduler, Bank(bankID))); } else if (config.pagePolicy == Configuration::PagePolicy::ClosedAdaptive) { for (unsigned bankID = 0; bankID < memSpec.banksPerChannel; bankID++) - bankMachines.push_back(std::make_unique - (config, *scheduler, Bank(bankID))); + bankMachines.push_back( + std::make_unique(config, *scheduler, Bank(bankID))); } - bankMachinesOnRank = ControllerVector>(memSpec.ranksPerChannel, - ControllerVector(memSpec.banksPerRank)); + bankMachinesOnRank = ControllerVector>( + memSpec.ranksPerChannel, ControllerVector(memSpec.banksPerRank)); for (unsigned rankID = 0; rankID < memSpec.ranksPerChannel; rankID++) { for (unsigned bankID = 0; bankID < memSpec.banksPerRank; bankID++) - bankMachinesOnRank[Rank(rankID)][Bank(bankID)] - = bankMachines[Bank(rankID * memSpec.banksPerRank + bankID)].get(); + bankMachinesOnRank[Rank(rankID)][Bank(bankID)] = + bankMachines[Bank(rankID * memSpec.banksPerRank + bankID)].get(); } // instantiate power-down managers (one per rank) @@ -222,16 +227,22 @@ Controller::Controller(const sc_module_name& name, const Configuration& config, { for (unsigned rankID = 0; rankID < memSpec.ranksPerChannel; rankID++) { - refreshManagers.push_back(std::make_unique - (config, bankMachinesOnRank[Rank(rankID)], *powerDownManagers[Rank(rankID)], Rank(rankID))); + refreshManagers.push_back( + std::make_unique(config, + bankMachinesOnRank[Rank(rankID)], + *powerDownManagers[Rank(rankID)], + Rank(rankID))); } } else if (config.refreshPolicy == Configuration::RefreshPolicy::SameBank) { for (unsigned rankID = 0; rankID < memSpec.ranksPerChannel; rankID++) { - refreshManagers.push_back(std::make_unique - (config, bankMachinesOnRank[Rank(rankID)], *powerDownManagers[Rank(rankID)], Rank(rankID))); + refreshManagers.push_back( + std::make_unique(config, + bankMachinesOnRank[Rank(rankID)], + *powerDownManagers[Rank(rankID)], + Rank(rankID))); } } else if (config.refreshPolicy == Configuration::RefreshPolicy::PerBank) @@ -239,8 +250,11 @@ Controller::Controller(const sc_module_name& name, const Configuration& config, for (unsigned rankID = 0; rankID < memSpec.ranksPerChannel; rankID++) { // TODO: remove bankMachines in constructor - refreshManagers.push_back(std::make_unique - (config, bankMachinesOnRank[Rank(rankID)], *powerDownManagers[Rank(rankID)], Rank(rankID))); + refreshManagers.push_back( + std::make_unique(config, + bankMachinesOnRank[Rank(rankID)], + *powerDownManagers[Rank(rankID)], + Rank(rankID))); } } else if (config.refreshPolicy == Configuration::RefreshPolicy::Per2Bank) @@ -248,8 +262,11 @@ Controller::Controller(const sc_module_name& name, const Configuration& config, for (unsigned rankID = 0; rankID < memSpec.ranksPerChannel; rankID++) { // TODO: remove bankMachines in constructor - refreshManagers.push_back(std::make_unique - (config, bankMachinesOnRank[Rank(rankID)], *powerDownManagers[Rank(rankID)], Rank(rankID))); + refreshManagers.push_back( + std::make_unique(config, + bankMachinesOnRank[Rank(rankID)], + *powerDownManagers[Rank(rankID)], + Rank(rankID))); } } else @@ -310,7 +327,8 @@ void Controller::controllerMethod() { Command command = std::get(it); tlm_generic_payload* trans = std::get(it); - std::get(it) = checker->timeToSatisfyConstraints(command, *trans); + std::get(it) = + checker->timeToSatisfyConstraints(command, *trans); } commandTuple = cmdMux->selectCommand(readyCommands); Command command = std::get(commandTuple); @@ -328,13 +346,15 @@ void Controller::controllerMethod() else if (command.isGroupCommand()) { for (std::size_t bankID = (static_cast(bank) % memSpec.banksPerGroup); - bankID < memSpec.banksPerRank; bankID += memSpec.banksPerGroup) + bankID < memSpec.banksPerRank; + bankID += memSpec.banksPerGroup) bankMachinesOnRank[rank][Bank(bankID)]->update(command); } else if (command.is2BankCommand()) { bankMachines[bank]->update(command); - bankMachines[Bank(static_cast(bank) + memSpec.getPer2BankOffset())]->update(command); + bankMachines[Bank(static_cast(bank) + memSpec.getPer2BankOffset())] + ->update(command); } else // if (isBankCommand(command)) bankMachines[bank]->update(command); @@ -347,10 +367,10 @@ void Controller::controllerMethod() { scheduler->removeRequest(*trans); manageRequests(thinkDelayFw); - respQueue->insertPayload(trans, sc_time_stamp() - + thinkDelayFw + phyDelayFw - + memSpec.getIntervalOnDataStrobe(command, *trans).end - + phyDelayBw + thinkDelayBw); + respQueue->insertPayload(trans, + sc_time_stamp() + thinkDelayFw + phyDelayFw + + memSpec.getIntervalOnDataStrobe(command, *trans).end + + phyDelayBw + thinkDelayBw); sc_time triggerTime = respQueue->getTriggerTime(); if (triggerTime != scMaxTime) @@ -369,7 +389,8 @@ void Controller::controllerMethod() readyCmdBlocked = true; } - // (6) Restart bank machines, refresh managers and power-down managers to issue new requests for the future + // (6) Restart bank machines, refresh managers and power-down managers to issue new requests for + // the future sc_time timeForNextTrigger = scMaxTime; sc_time localTime; for (auto& it : bankMachines) @@ -420,7 +441,8 @@ void Controller::controllerMethod() controllerEvent.notify(timeForNextTrigger - sc_time_stamp()); } -tlm_sync_enum Controller::nb_transport_fw(tlm_generic_payload& trans, tlm_phase& phase, sc_time& delay) +tlm_sync_enum +Controller::nb_transport_fw(tlm_generic_payload& trans, tlm_phase& phase, sc_time& delay) { if (phase == BEGIN_REQ) { @@ -434,17 +456,18 @@ tlm_sync_enum Controller::nb_transport_fw(tlm_generic_payload& trans, tlm_phase& endRespEvent.notify(delay); } else - SC_REPORT_FATAL("Controller", "nb_transport_fw in controller was triggered with unknown phase"); + SC_REPORT_FATAL("Controller", + "nb_transport_fw in controller was triggered with unknown phase"); - PRINTDEBUGMESSAGE(name(), "[fw] " + getPhaseName(phase) + " notification in " + - delay.to_string()); + PRINTDEBUGMESSAGE(name(), + "[fw] " + getPhaseName(phase) + " notification in " + delay.to_string()); return TLM_ACCEPTED; } -tlm_sync_enum Controller::nb_transport_bw([[maybe_unused]] tlm_generic_payload &trans, - [[maybe_unused]] tlm_phase &phase, - [[maybe_unused]] sc_time &delay) +tlm_sync_enum Controller::nb_transport_bw([[maybe_unused]] tlm_generic_payload& trans, + [[maybe_unused]] tlm_phase& phase, + [[maybe_unused]] sc_time& delay) { SC_REPORT_FATAL("Controller", "nb_transport_bw of controller must not be called!"); return TLM_ACCEPTED; @@ -465,30 +488,38 @@ void Controller::manageRequests(const sc_time& delay) { if (transToAcquire.payload != nullptr && transToAcquire.arrival <= sc_time_stamp()) { - // TODO: here we assume that the scheduler always has space not only for a single burst transaction + // TODO: here we assume that the scheduler always has space not only for a single burst + // transaction // but for a maximum size transaction if (scheduler->hasBufferSpace()) { if (totalNumberOfPayloads == 0) idleTimeCollector.end(); - totalNumberOfPayloads++; // seems to be ok + totalNumberOfPayloads++; // seems to be ok transToAcquire.payload->acquire(); // Align address to minimum burst length - uint64_t alignedAddress = transToAcquire.payload->get_address() & ~(minBytesPerBurst - UINT64_C(1)); + uint64_t alignedAddress = + transToAcquire.payload->get_address() & ~(minBytesPerBurst - UINT64_C(1)); transToAcquire.payload->set_address(alignedAddress); // continuous block of data that can be fetched with a single burst - if ((alignedAddress / maxBytesPerBurst) - == ((alignedAddress + transToAcquire.payload->get_data_length() - 1) / maxBytesPerBurst)) + if ((alignedAddress / maxBytesPerBurst) == + ((alignedAddress + transToAcquire.payload->get_data_length() - 1) / + maxBytesPerBurst)) { - DecodedAddress decodedAddress = addressDecoder.decodeAddress(transToAcquire.payload->get_address()); - ControllerExtension::setAutoExtension(*transToAcquire.payload, nextChannelPayloadIDToAppend++, - Rank(decodedAddress.rank), BankGroup(decodedAddress.bankgroup), - Bank(decodedAddress.bank), Row(decodedAddress.row), + DecodedAddress decodedAddress = + addressDecoder.decodeAddress(transToAcquire.payload->get_address()); + ControllerExtension::setAutoExtension(*transToAcquire.payload, + nextChannelPayloadIDToAppend++, + Rank(decodedAddress.rank), + BankGroup(decodedAddress.bankgroup), + Bank(decodedAddress.bank), + Row(decodedAddress.row), Column(decodedAddress.column), - transToAcquire.payload->get_data_length() / memSpec.bytesPerBeat); + transToAcquire.payload->get_data_length() / + memSpec.bytesPerBeat); Rank rank = Rank(decodedAddress.rank); if (ranksNumberOfPayloads[rank] == 0) @@ -503,7 +534,7 @@ void Controller::manageRequests(const sc_time& delay) { createChildTranses(*transToAcquire.payload); const std::vector& childTranses = - transToAcquire.payload->get_extension()->getChildTranses(); + transToAcquire.payload->get_extension()->getChildTranses(); for (auto* childTrans : childTranses) { Rank rank = ControllerExtension::getRank(*childTrans); @@ -559,13 +590,15 @@ void Controller::manageResponses() if (ChildExtension::isChildTrans(*nextTransInRespQueue)) { - tlm_generic_payload& parentTrans = ChildExtension::getParentTrans(*nextTransInRespQueue); + tlm_generic_payload& parentTrans = + ChildExtension::getParentTrans(*nextTransInRespQueue); if (ParentExtension::notifyChildTransCompletion(parentTrans)) { transToRelease.payload = &parentTrans; tlm_phase bwPhase = BEGIN_RESP; sc_time bwDelay; - if (transToRelease.arrival == sc_time_stamp()) // last payload was released in this cycle + if (transToRelease.arrival == + sc_time_stamp()) // last payload was released in this cycle bwDelay = memSpec.tCK; else bwDelay = SC_ZERO_TIME; @@ -585,7 +618,8 @@ void Controller::manageResponses() transToRelease.payload = nextTransInRespQueue; tlm_phase bwPhase = BEGIN_RESP; sc_time bwDelay; - if (transToRelease.arrival == sc_time_stamp()) // last payload was released in this cycle + if (transToRelease.arrival == + sc_time_stamp()) // last payload was released in this cycle bwDelay = memSpec.tCK; else bwDelay = SC_ZERO_TIME; @@ -616,7 +650,6 @@ Controller::MemoryManager::~MemoryManager() trans->reset(); delete trans; } - } tlm::tlm_generic_payload& Controller::MemoryManager::allocate() @@ -626,7 +659,7 @@ tlm::tlm_generic_payload& Controller::MemoryManager::allocate() return *new tlm_generic_payload(this); } - tlm_generic_payload *result = freePayloads.top(); + tlm_generic_payload* result = freePayloads.top(); freePayloads.pop(); return *result; } @@ -675,9 +708,12 @@ void Controller::createChildTranses(tlm::tlm_generic_payload& parentTrans) for (auto* childTrans : childTranses) { DecodedAddress decodedAddress = addressDecoder.decodeAddress(childTrans->get_address()); - ControllerExtension::setAutoExtension(*childTrans, nextChannelPayloadIDToAppend, - Rank(decodedAddress.rank), BankGroup(decodedAddress.bankgroup), - Bank(decodedAddress.bank), Row(decodedAddress.row), + ControllerExtension::setAutoExtension(*childTrans, + nextChannelPayloadIDToAppend, + Rank(decodedAddress.rank), + BankGroup(decodedAddress.bankgroup), + Bank(decodedAddress.bank), + Row(decodedAddress.row), Column(decodedAddress.column), childTrans->get_data_length() / memSpec.bytesPerBeat); } diff --git a/src/libdramsys/DRAMSys/controller/Controller.h b/src/libdramsys/DRAMSys/controller/Controller.h index 0a472d72..3b706896 100644 --- a/src/libdramsys/DRAMSys/controller/Controller.h +++ b/src/libdramsys/DRAMSys/controller/Controller.h @@ -35,20 +35,20 @@ #ifndef CONTROLLER_H #define CONTROLLER_H -#include "DRAMSys/controller/ControllerIF.h" -#include "DRAMSys/controller/Command.h" #include "DRAMSys/controller/BankMachine.h" -#include "DRAMSys/controller/cmdmux/CmdMuxIF.h" +#include "DRAMSys/controller/Command.h" +#include "DRAMSys/controller/ControllerIF.h" #include "DRAMSys/controller/checker/CheckerIF.h" -#include "DRAMSys/controller/refresh/RefreshManagerIF.h" +#include "DRAMSys/controller/cmdmux/CmdMuxIF.h" #include "DRAMSys/controller/powerdown/PowerDownManagerIF.h" +#include "DRAMSys/controller/refresh/RefreshManagerIF.h" #include "DRAMSys/controller/respqueue/RespQueueIF.h" #include "DRAMSys/simulation/AddressDecoder.h" -#include #include #include #include +#include namespace DRAMSys { @@ -56,18 +56,23 @@ namespace DRAMSys class Controller : public ControllerIF { public: - Controller(const sc_core::sc_module_name& name, const Configuration& config, const AddressDecoder& addressDecoder); + Controller(const sc_core::sc_module_name& name, + const Configuration& config, + const AddressDecoder& addressDecoder); SC_HAS_PROCESS(Controller); protected: - tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, + tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& trans, + tlm::tlm_phase& phase, sc_core::sc_time& delay) override; - tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, + tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload& trans, + tlm::tlm_phase& phase, sc_core::sc_time& delay) override; - void b_transport(tlm::tlm_generic_payload& trans, sc_core::sc_time& delay) override; + void b_transport(tlm::tlm_generic_payload& trans, sc_core::sc_time& delay) override; unsigned int transport_dbg(tlm::tlm_generic_payload& trans) override; - virtual void sendToFrontend(tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_core::sc_time& delay); + virtual void + sendToFrontend(tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_core::sc_time& delay); virtual void controllerMethod(); @@ -79,7 +84,7 @@ protected: const sc_core::sc_time phyDelayFw; const sc_core::sc_time phyDelayBw; const sc_core::sc_time blockingReadDelay; - const sc_core::sc_time blockingWriteDelay; + const sc_core::sc_time blockingWriteDelay; private: unsigned totalNumberOfPayloads = 0; @@ -117,10 +122,10 @@ private: { public: MemoryManager() = default; - MemoryManager(const MemoryManager &) = delete; - MemoryManager(MemoryManager &&) = delete; - MemoryManager &operator=(const MemoryManager &) = delete; - MemoryManager &operator=(MemoryManager &&) = delete; + MemoryManager(const MemoryManager&) = delete; + MemoryManager(MemoryManager&&) = delete; + MemoryManager& operator=(const MemoryManager&) = delete; + MemoryManager& operator=(MemoryManager&&) = delete; ~MemoryManager() override; tlm::tlm_generic_payload& allocate(); diff --git a/src/libdramsys/DRAMSys/controller/ControllerIF.h b/src/libdramsys/DRAMSys/controller/ControllerIF.h index 240941e8..c9bb116f 100644 --- a/src/libdramsys/DRAMSys/controller/ControllerIF.h +++ b/src/libdramsys/DRAMSys/controller/ControllerIF.h @@ -37,8 +37,8 @@ #ifndef CONTROLLERIF_H #define CONTROLLERIF_H -#include "DRAMSys/configuration/Configuration.h" #include "DRAMSys/common/DebugManager.h" +#include "DRAMSys/configuration/Configuration.h" #include #include @@ -55,53 +55,45 @@ class ControllerIF : public sc_core::sc_module { public: // Already create and bind sockets to the virtual functions - tlm_utils::simple_target_socket tSocket; // Arbiter side + tlm_utils::simple_target_socket tSocket; // Arbiter side tlm_utils::simple_initiator_socket iSocket; // DRAM side void end_of_simulation() override { idleTimeCollector.end(); - sc_core::sc_time activeTime = static_cast(numberOfBeatsServed) - / memSpec.dataRate - * memSpec.tCK - / memSpec.pseudoChannelsPerChannel; + sc_core::sc_time activeTime = static_cast(numberOfBeatsServed) / memSpec.dataRate * + memSpec.tCK / memSpec.pseudoChannelsPerChannel; double bandwidth = activeTime / sc_core::sc_time_stamp(); - double bandwidthWoIdle = activeTime / (sc_core::sc_time_stamp() - idleTimeCollector.getIdleTime()); + double bandwidthWoIdle = + activeTime / (sc_core::sc_time_stamp() - idleTimeCollector.getIdleTime()); double maxBandwidth = ( - // fCK in GHz e.g. 1 [GHz] (tCK in ps): - (1000 / memSpec.tCK.to_double()) - // DataRate e.g. 2 - * memSpec.dataRate - // BusWidth e.g. 8 or 64 - * memSpec.bitWidth - // Number of devices that form a rank, e.g., 8 on a DDR3 DIMM - * memSpec.devicesPerRank - // HBM specific, one or two pseudo channels per channel - * memSpec.pseudoChannelsPerChannel); + // fCK in GHz e.g. 1 [GHz] (tCK in ps): + (1000 / memSpec.tCK.to_double()) + // DataRate e.g. 2 + * memSpec.dataRate + // BusWidth e.g. 8 or 64 + * memSpec.bitWidth + // Number of devices that form a rank, e.g., 8 on a DDR3 DIMM + * memSpec.devicesPerRank + // HBM specific, one or two pseudo channels per channel + * memSpec.pseudoChannelsPerChannel); std::cout << name() << std::string(" Total Time: ") - << sc_core::sc_time_stamp().to_string() - << std::endl; - std::cout << name() << std::string(" AVG BW: ") - << std::fixed << std::setprecision(2) - << std::setw(6) << (bandwidth * maxBandwidth) << " Gb/s | " - << std::setw(6) << (bandwidth * maxBandwidth / 8) << " GB/s | " - << std::setw(6) << (bandwidth * 100) << " %" - << std::endl; - std::cout << name() << std::string(" AVG BW\\IDLE: ") - << std::fixed << std::setprecision(2) - << std::setw(6) << (bandwidthWoIdle * maxBandwidth) << " Gb/s | " - << std::setw(6) << (bandwidthWoIdle * maxBandwidth / 8) << " GB/s | " - << std::setw(6) << (bandwidthWoIdle * 100) << " %" - << std::endl; - std::cout << name() << std::string(" MAX BW: ") - << std::fixed << std::setprecision(2) - << std::setw(6) << maxBandwidth << " Gb/s | " - << std::setw(6) << maxBandwidth / 8 << " GB/s | " - << std::setw(6) << 100.0 << " %" + << sc_core::sc_time_stamp().to_string() << std::endl; + std::cout << name() << std::string(" AVG BW: ") << std::fixed + << std::setprecision(2) << std::setw(6) << (bandwidth * maxBandwidth) + << " Gb/s | " << std::setw(6) << (bandwidth * maxBandwidth / 8) << " GB/s | " + << std::setw(6) << (bandwidth * 100) << " %" << std::endl; + std::cout << name() << std::string(" AVG BW\\IDLE: ") << std::fixed + << std::setprecision(2) << std::setw(6) << (bandwidthWoIdle * maxBandwidth) + << " Gb/s | " << std::setw(6) << (bandwidthWoIdle * maxBandwidth / 8) + << " GB/s | " << std::setw(6) << (bandwidthWoIdle * 100) << " %" << std::endl; + std::cout << name() << std::string(" MAX BW: ") << std::fixed + << std::setprecision(2) << std::setw(6) << maxBandwidth << " Gb/s | " + << std::setw(6) << maxBandwidth / 8 << " GB/s | " << std::setw(6) << 100.0 << " %" << std::endl; } @@ -109,8 +101,11 @@ protected: const MemSpec& memSpec; // Bind sockets with virtual functions - ControllerIF(const sc_core::sc_module_name& name, const Configuration& config) - : sc_core::sc_module(name), tSocket("tSocket"), iSocket("iSocket"), memSpec(*config.memSpec) + ControllerIF(const sc_core::sc_module_name& name, const Configuration& config) : + sc_core::sc_module(name), + tSocket("tSocket"), + iSocket("iSocket"), + memSpec(*config.memSpec) { tSocket.register_nb_transport_fw(this, &ControllerIF::nb_transport_fw); tSocket.register_transport_dbg(this, &ControllerIF::transport_dbg); @@ -122,9 +117,11 @@ protected: SC_HAS_PROCESS(ControllerIF); // Virtual transport functions - virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, + virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& trans, + tlm::tlm_phase& phase, sc_core::sc_time& delay) = 0; - virtual tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, + virtual tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload& trans, + tlm::tlm_phase& phase, sc_core::sc_time& delay) = 0; virtual void b_transport(tlm::tlm_generic_payload& trans, sc_core::sc_time& delay) = 0; virtual unsigned int transport_dbg(tlm::tlm_generic_payload& trans) = 0; @@ -153,10 +150,7 @@ protected: } } - sc_core::sc_time getIdleTime() - { - return idleTime; - } + sc_core::sc_time getIdleTime() { return idleTime; } private: bool isIdle = false; diff --git a/src/libdramsys/DRAMSys/controller/ControllerRecordable.cpp b/src/libdramsys/DRAMSys/controller/ControllerRecordable.cpp index d82ba70f..c5af3390 100644 --- a/src/libdramsys/DRAMSys/controller/ControllerRecordable.cpp +++ b/src/libdramsys/DRAMSys/controller/ControllerRecordable.cpp @@ -42,10 +42,14 @@ using namespace tlm; namespace DRAMSys { -ControllerRecordable::ControllerRecordable(const sc_module_name& name, const Configuration& config, - const AddressDecoder& addressDecoder, TlmRecorder& tlmRecorder) - : Controller(name, config, addressDecoder), tlmRecorder(tlmRecorder), - windowSizeTime(config.windowSize * memSpec.tCK), activeTimeMultiplier(config.memSpec->tCK / config.memSpec->dataRate), +ControllerRecordable::ControllerRecordable(const sc_module_name& name, + const Configuration& config, + const AddressDecoder& addressDecoder, + TlmRecorder& tlmRecorder) : + Controller(name, config, addressDecoder), + tlmRecorder(tlmRecorder), + windowSizeTime(config.windowSize * memSpec.tCK), + activeTimeMultiplier(config.memSpec->tCK / config.memSpec->dataRate), enableWindowing(config.enableWindowing) { if (enableWindowing) @@ -58,22 +62,24 @@ ControllerRecordable::ControllerRecordable(const sc_module_name& name, const Con } } -tlm_sync_enum ControllerRecordable::nb_transport_fw(tlm_generic_payload& trans, - tlm_phase& phase, sc_time& delay) +tlm_sync_enum +ControllerRecordable::nb_transport_fw(tlm_generic_payload& trans, tlm_phase& phase, sc_time& delay) { tlmRecorder.recordPhase(trans, phase, delay); return Controller::nb_transport_fw(trans, phase, delay); } -tlm_sync_enum ControllerRecordable::nb_transport_bw([[maybe_unused]] tlm_generic_payload &trans, - [[maybe_unused]] tlm_phase &phase, - [[maybe_unused]] sc_time &delay) +tlm_sync_enum ControllerRecordable::nb_transport_bw([[maybe_unused]] tlm_generic_payload& trans, + [[maybe_unused]] tlm_phase& phase, + [[maybe_unused]] sc_time& delay) { SC_REPORT_FATAL("Controller", "nb_transport_bw of controller must not be called"); return TLM_ACCEPTED; } -void ControllerRecordable::sendToFrontend(tlm_generic_payload& payload, tlm_phase& phase, sc_time& delay) +void ControllerRecordable::sendToFrontend(tlm_generic_payload& payload, + tlm_phase& phase, + sc_time& delay) { tlmRecorder.recordPhase(payload, phase, delay); tSocket->nb_transport_bw(payload, phase, delay); @@ -85,7 +91,7 @@ void ControllerRecordable::controllerMethod() { sc_time timeDiff = sc_time_stamp() - lastTimeCalled; lastTimeCalled = sc_time_stamp(); - const std::vector &bufferDepth = scheduler->getBufferDepth(); + const std::vector& bufferDepth = scheduler->getBufferDepth(); for (std::size_t index = 0; index < slidingAverageBufferDepth.size(); index++) slidingAverageBufferDepth[index] += bufferDepth[index] * timeDiff; @@ -107,7 +113,8 @@ void ControllerRecordable::controllerMethod() uint64_t windowNumberOfBeatsServed = numberOfBeatsServed - lastNumberOfBeatsServed; lastNumberOfBeatsServed = numberOfBeatsServed; - sc_time windowActiveTime = activeTimeMultiplier * static_cast(windowNumberOfBeatsServed); + sc_time windowActiveTime = + activeTimeMultiplier * static_cast(windowNumberOfBeatsServed); double windowAverageBandwidth = windowActiveTime / windowSizeTime; tlmRecorder.recordBandwidth(sc_time_stamp().to_seconds(), windowAverageBandwidth); } diff --git a/src/libdramsys/DRAMSys/controller/ControllerRecordable.h b/src/libdramsys/DRAMSys/controller/ControllerRecordable.h index 0445179c..ac21c5b4 100644 --- a/src/libdramsys/DRAMSys/controller/ControllerRecordable.h +++ b/src/libdramsys/DRAMSys/controller/ControllerRecordable.h @@ -35,8 +35,8 @@ #ifndef CONTROLLERRECORDABLE_H #define CONTROLLERRECORDABLE_H -#include "DRAMSys/controller/Controller.h" #include "DRAMSys/common/TlmRecorder.h" +#include "DRAMSys/controller/Controller.h" #include #include @@ -47,17 +47,22 @@ namespace DRAMSys class ControllerRecordable final : public Controller { public: - ControllerRecordable(const sc_core::sc_module_name& name, const Configuration& config, - const AddressDecoder& addressDecoder, TlmRecorder& tlmRecorder); + ControllerRecordable(const sc_core::sc_module_name& name, + const Configuration& config, + const AddressDecoder& addressDecoder, + TlmRecorder& tlmRecorder); protected: - tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, + tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& trans, + tlm::tlm_phase& phase, sc_core::sc_time& delay) override; - tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, + tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload& trans, + tlm::tlm_phase& phase, sc_core::sc_time& delay) override; - void sendToFrontend(tlm::tlm_generic_payload &payload, tlm::tlm_phase &phase, - sc_core::sc_time &delay) override; + void sendToFrontend(tlm::tlm_generic_payload& payload, + tlm::tlm_phase& phase, + sc_core::sc_time& delay) override; void controllerMethod() override; diff --git a/src/libdramsys/DRAMSys/controller/ManagerIF.h b/src/libdramsys/DRAMSys/controller/ManagerIF.h index b4e1c380..cf5bc4e7 100644 --- a/src/libdramsys/DRAMSys/controller/ManagerIF.h +++ b/src/libdramsys/DRAMSys/controller/ManagerIF.h @@ -43,10 +43,10 @@ namespace DRAMSys class ManagerIF { protected: - ManagerIF(const ManagerIF &) = default; - ManagerIF(ManagerIF &&) = default; - ManagerIF &operator=(const ManagerIF &) = default; - ManagerIF &operator=(ManagerIF &&) = default; + ManagerIF(const ManagerIF&) = default; + ManagerIF(ManagerIF&&) = default; + ManagerIF& operator=(const ManagerIF&) = default; + ManagerIF& operator=(ManagerIF&&) = default; public: ManagerIF() = default; diff --git a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxIF.h b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxIF.h index c032a159..e7971ae9 100644 --- a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxIF.h +++ b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxIF.h @@ -43,16 +43,16 @@ namespace DRAMSys class CmdMuxIF { protected: - CmdMuxIF(const CmdMuxIF &) = default; - CmdMuxIF(CmdMuxIF &&) = default; - CmdMuxIF &operator=(const CmdMuxIF &) = default; - CmdMuxIF &operator=(CmdMuxIF &&) = default; + CmdMuxIF(const CmdMuxIF&) = default; + CmdMuxIF(CmdMuxIF&&) = default; + CmdMuxIF& operator=(const CmdMuxIF&) = default; + CmdMuxIF& operator=(CmdMuxIF&&) = default; public: CmdMuxIF() = default; virtual ~CmdMuxIF() = default; - - virtual CommandTuple::Type selectCommand(const ReadyCommands & readyCommands) = 0; + + virtual CommandTuple::Type selectCommand(const ReadyCommands& readyCommands) = 0; }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.cpp b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.cpp index 830e049f..5a1540b7 100644 --- a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.cpp +++ b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.cpp @@ -41,10 +41,12 @@ using namespace sc_core; namespace DRAMSys { -CmdMuxOldest::CmdMuxOldest(const Configuration& config) : memSpec(*config.memSpec) {} +CmdMuxOldest::CmdMuxOldest(const Configuration& config) : memSpec(*config.memSpec) +{ +} -CommandTuple::Type CmdMuxOldest::selectCommand(const ReadyCommands &readyCommands) -{ +CommandTuple::Type CmdMuxOldest::selectCommand(const ReadyCommands& readyCommands) +{ auto result = readyCommands.cend(); uint64_t lastPayloadID = UINT64_MAX; uint64_t newPayloadID = 0; @@ -54,8 +56,9 @@ CommandTuple::Type CmdMuxOldest::selectCommand(const ReadyCommands &readyCommand for (auto it = readyCommands.cbegin(); it != readyCommands.cend(); it++) { newTimestamp = std::get(*it) + - memSpec.getCommandLength(std::get(*it)); - newPayloadID = ControllerExtension::getChannelPayloadID(*std::get(*it)); + memSpec.getCommandLength(std::get(*it)); + newPayloadID = + ControllerExtension::getChannelPayloadID(*std::get(*it)); if (newTimestamp < lastTimestamp) { @@ -71,12 +74,11 @@ CommandTuple::Type CmdMuxOldest::selectCommand(const ReadyCommands &readyCommand } if (result != readyCommands.cend() && - std::get(*result) == sc_time_stamp()) + std::get(*result) == sc_time_stamp()) return *result; return {Command::NOP, nullptr, scMaxTime}; } - CmdMuxOldestRasCas::CmdMuxOldestRasCas(const Configuration& config) : memSpec(*config.memSpec) { readyRasCommands.reserve(memSpec.banksPerChannel); @@ -84,7 +86,7 @@ CmdMuxOldestRasCas::CmdMuxOldestRasCas(const Configuration& config) : memSpec(*c readyRasCasCommands.reserve(2); } -CommandTuple::Type CmdMuxOldestRasCas::selectCommand(const ReadyCommands &readyCommands) +CommandTuple::Type CmdMuxOldestRasCas::selectCommand(const ReadyCommands& readyCommands) { readyRasCommands.clear(); readyCasCommands.clear(); @@ -109,8 +111,9 @@ CommandTuple::Type CmdMuxOldestRasCas::selectCommand(const ReadyCommands &readyC for (auto it = readyRasCommands.cbegin(); it != readyRasCommands.cend(); it++) { newTimestamp = std::get(*it) + - memSpec.getCommandLength(std::get(*it)); - newPayloadID = ControllerExtension::getChannelPayloadID(*std::get(*it)); + memSpec.getCommandLength(std::get(*it)); + newPayloadID = + ControllerExtension::getChannelPayloadID(*std::get(*it)); if (newTimestamp < lastTimestamp) { @@ -131,8 +134,9 @@ CommandTuple::Type CmdMuxOldestRasCas::selectCommand(const ReadyCommands &readyC for (auto it = readyCasCommands.cbegin(); it != readyCasCommands.cend(); it++) { newTimestamp = std::get(*it) + - memSpec.getCommandLength(std::get(*it)); - newPayloadID = ControllerExtension::getChannelPayloadID(*std::get(*it)); + memSpec.getCommandLength(std::get(*it)); + newPayloadID = + ControllerExtension::getChannelPayloadID(*std::get(*it)); if (newTimestamp < lastTimestamp) { @@ -160,7 +164,8 @@ CommandTuple::Type CmdMuxOldestRasCas::selectCommand(const ReadyCommands &readyC for (auto it = readyRasCasCommands.cbegin(); it != readyRasCasCommands.cend(); it++) { newTimestamp = std::get(*it); - newPayloadID = ControllerExtension::getChannelPayloadID(*std::get(*it)); + newPayloadID = + ControllerExtension::getChannelPayloadID(*std::get(*it)); if (newTimestamp < lastTimestamp) { @@ -176,7 +181,7 @@ CommandTuple::Type CmdMuxOldestRasCas::selectCommand(const ReadyCommands &readyC } if (result != readyCommands.cend() && - std::get(*result) == sc_time_stamp()) + std::get(*result) == sc_time_stamp()) return *result; return {Command::NOP, nullptr, scMaxTime}; } diff --git a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.h b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.h index 6ff5772c..a83251c3 100644 --- a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.h +++ b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.h @@ -35,8 +35,8 @@ #ifndef CMDMUXOLDEST_H #define CMDMUXOLDEST_H -#include "DRAMSys/controller/cmdmux/CmdMuxIF.h" #include "DRAMSys/configuration/Configuration.h" +#include "DRAMSys/controller/cmdmux/CmdMuxIF.h" namespace DRAMSys { @@ -45,19 +45,18 @@ class CmdMuxOldest : public CmdMuxIF { public: explicit CmdMuxOldest(const Configuration& config); - CommandTuple::Type selectCommand(const ReadyCommands & readyCommands) override; + CommandTuple::Type selectCommand(const ReadyCommands& readyCommands) override; private: const MemSpec& memSpec; const sc_core::sc_time scMaxTime = sc_core::sc_max_time(); }; - class CmdMuxOldestRasCas : public CmdMuxIF { public: explicit CmdMuxOldestRasCas(const Configuration& config); - CommandTuple::Type selectCommand(const ReadyCommands & readyCommands) override; + CommandTuple::Type selectCommand(const ReadyCommands& readyCommands) override; private: const MemSpec& memSpec; diff --git a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.cpp b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.cpp index 15627c42..d4ae105a 100644 --- a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.cpp +++ b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.cpp @@ -41,9 +41,11 @@ using namespace sc_core; namespace DRAMSys { -CmdMuxStrict::CmdMuxStrict(const Configuration& config) : memSpec(*config.memSpec) {} +CmdMuxStrict::CmdMuxStrict(const Configuration& config) : memSpec(*config.memSpec) +{ +} -CommandTuple::Type CmdMuxStrict::selectCommand(const ReadyCommands &readyCommands) +CommandTuple::Type CmdMuxStrict::selectCommand(const ReadyCommands& readyCommands) { auto result = readyCommands.cend(); uint64_t lastPayloadID = UINT64_MAX; @@ -54,21 +56,24 @@ CommandTuple::Type CmdMuxStrict::selectCommand(const ReadyCommands &readyCommand for (auto it = readyCommands.cbegin(); it != readyCommands.cend(); it++) { newTimestamp = std::get(*it) + - memSpec.getCommandLength(std::get(*it)); - newPayloadID = ControllerExtension::getChannelPayloadID(*std::get(*it)); + memSpec.getCommandLength(std::get(*it)); + newPayloadID = + ControllerExtension::getChannelPayloadID(*std::get(*it)); if (newTimestamp < lastTimestamp) { - if (std::get(*it).isRasCommand() || newPayloadID == nextPayloadID) + if (std::get(*it).isRasCommand() || + newPayloadID == nextPayloadID) { lastTimestamp = newTimestamp; lastPayloadID = newPayloadID; result = it; - } + } } else if ((newTimestamp == lastTimestamp) && (newPayloadID < lastPayloadID)) { - if (std::get(*it).isRasCommand() || newPayloadID == nextPayloadID) + if (std::get(*it).isRasCommand() || + newPayloadID == nextPayloadID) { lastPayloadID = newPayloadID; result = it; @@ -77,7 +82,7 @@ CommandTuple::Type CmdMuxStrict::selectCommand(const ReadyCommands &readyCommand } if (result != readyCommands.cend() && - std::get(*result) == sc_time_stamp()) + std::get(*result) == sc_time_stamp()) { if (std::get(*result).isCasCommand()) nextPayloadID++; @@ -86,7 +91,6 @@ CommandTuple::Type CmdMuxStrict::selectCommand(const ReadyCommands &readyCommand return {Command::NOP, nullptr, scMaxTime}; } - CmdMuxStrictRasCas::CmdMuxStrictRasCas(const Configuration& config) : memSpec(*config.memSpec) { readyRasCommands.reserve(memSpec.banksPerChannel); @@ -94,7 +98,7 @@ CmdMuxStrictRasCas::CmdMuxStrictRasCas(const Configuration& config) : memSpec(*c readyRasCasCommands.reserve(2); } -CommandTuple::Type CmdMuxStrictRasCas::selectCommand(const ReadyCommands &readyCommands) +CommandTuple::Type CmdMuxStrictRasCas::selectCommand(const ReadyCommands& readyCommands) { readyRasCommands.clear(); readyCasCommands.clear(); @@ -119,8 +123,9 @@ CommandTuple::Type CmdMuxStrictRasCas::selectCommand(const ReadyCommands &readyC for (auto it = readyRasCommands.cbegin(); it != readyRasCommands.cend(); it++) { newTimestamp = std::get(*it) + - memSpec.getCommandLength(std::get(*it)); - newPayloadID = ControllerExtension::getChannelPayloadID(*std::get(*it)); + memSpec.getCommandLength(std::get(*it)); + newPayloadID = + ControllerExtension::getChannelPayloadID(*std::get(*it)); if (newTimestamp < lastTimestamp) { @@ -137,7 +142,8 @@ CommandTuple::Type CmdMuxStrictRasCas::selectCommand(const ReadyCommands &readyC for (auto it = readyCasCommands.cbegin(); it != readyCasCommands.cend(); it++) { - newPayloadID = ControllerExtension::getChannelPayloadID(*std::get(*it)); + newPayloadID = + ControllerExtension::getChannelPayloadID(*std::get(*it)); if (newPayloadID == nextPayloadID) { @@ -159,7 +165,8 @@ CommandTuple::Type CmdMuxStrictRasCas::selectCommand(const ReadyCommands &readyC for (auto it = readyRasCasCommands.cbegin(); it != readyRasCasCommands.cend(); it++) { newTimestamp = std::get(*it); - newPayloadID = ControllerExtension::getChannelPayloadID(*std::get(*it)); + newPayloadID = + ControllerExtension::getChannelPayloadID(*std::get(*it)); if (newTimestamp < lastTimestamp) { @@ -175,13 +182,13 @@ CommandTuple::Type CmdMuxStrictRasCas::selectCommand(const ReadyCommands &readyC } if (result != readyCommands.cend() && - std::get(*result) == sc_time_stamp()) - { - if (std::get(*result).isCasCommand()) - nextPayloadID++; - return *result; - } - return {Command::NOP, nullptr, scMaxTime}; + std::get(*result) == sc_time_stamp()) + { + if (std::get(*result).isCasCommand()) + nextPayloadID++; + return *result; + } + return {Command::NOP, nullptr, scMaxTime}; } } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.h b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.h index 2b98bc9e..b0572a3f 100644 --- a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.h +++ b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.h @@ -35,8 +35,8 @@ #ifndef CMDMUXSTRICT_H #define CMDMUXSTRICT_H -#include "DRAMSys/controller/cmdmux/CmdMuxIF.h" #include "DRAMSys/configuration/Configuration.h" +#include "DRAMSys/controller/cmdmux/CmdMuxIF.h" namespace DRAMSys { @@ -45,7 +45,7 @@ class CmdMuxStrict : public CmdMuxIF { public: explicit CmdMuxStrict(const Configuration& config); - CommandTuple::Type selectCommand(const ReadyCommands & readyCommands) override; + CommandTuple::Type selectCommand(const ReadyCommands& readyCommands) override; private: uint64_t nextPayloadID = 1; @@ -57,7 +57,7 @@ class CmdMuxStrictRasCas : public CmdMuxIF { public: explicit CmdMuxStrictRasCas(const Configuration& config); - CommandTuple::Type selectCommand(const ReadyCommands & readyCommands) override; + CommandTuple::Type selectCommand(const ReadyCommands& readyCommands) override; private: uint64_t nextPayloadID = 1; diff --git a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerIF.h b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerIF.h index d3f42802..d065ce17 100644 --- a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerIF.h +++ b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerIF.h @@ -35,8 +35,8 @@ #ifndef POWERDOWNMANAGERIF_H #define POWERDOWNMANAGERIF_H -#include "DRAMSys/controller/ManagerIF.h" #include "DRAMSys/controller/Command.h" +#include "DRAMSys/controller/ManagerIF.h" #include diff --git a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.cpp b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.cpp index f380d508..83eb3524 100644 --- a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.cpp +++ b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.cpp @@ -98,7 +98,7 @@ void PowerDownManagerStaggered::evaluate() else if (entryTriggered) { nextCommand = Command::PDEP; - for (auto *it : bankMachinesOnRank) + for (auto* it : bankMachinesOnRank) { if (it->isActivated()) { @@ -117,47 +117,49 @@ void PowerDownManagerStaggered::update(Command command) { switch (command) { - case Command::PDEA: - state = State::ActivePdn; - entryTriggered = false; - break; - case Command::PDEP: - state = State::PrechargePdn; - entryTriggered = false; - break; - case Command::SREFEN: - state = State::SelfRefresh; - entryTriggered = false; - enterSelfRefresh = false; - break; - case Command::PDXA: + case Command::PDEA: + state = State::ActivePdn; + entryTriggered = false; + break; + case Command::PDEP: + state = State::PrechargePdn; + entryTriggered = false; + break; + case Command::SREFEN: + state = State::SelfRefresh; + entryTriggered = false; + enterSelfRefresh = false; + break; + case Command::PDXA: + state = State::Idle; + exitTriggered = false; + break; + case Command::PDXP: + state = State::Idle; + exitTriggered = false; + if (controllerIdle) + enterSelfRefresh = true; + break; + case Command::SREFEX: + state = State::ExtraRefresh; + break; + case Command::REFAB: + if (state == State::ExtraRefresh) + { state = State::Idle; exitTriggered = false; - break; - case Command::PDXP: - state = State::Idle; - exitTriggered = false; - if (controllerIdle) - enterSelfRefresh = true; - break; - case Command::SREFEX: - state = State::ExtraRefresh; - break; - case Command::REFAB: - if (state == State::ExtraRefresh) - { - state = State::Idle; - exitTriggered = false; - } - else if (controllerIdle) - entryTriggered = true; - break; - case Command::REFPB: case Command::REFP2B: case Command::REFSB: - if (controllerIdle) - entryTriggered = true; - break; - default: - break; + } + else if (controllerIdle) + entryTriggered = true; + break; + case Command::REFPB: + case Command::REFP2B: + case Command::REFSB: + if (controllerIdle) + entryTriggered = true; + break; + default: + break; } } diff --git a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.h b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.h index 687655a4..a3581cac 100644 --- a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.h +++ b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.h @@ -35,9 +35,9 @@ #ifndef POWERDOWNMANAGERSTAGGERED_H #define POWERDOWNMANAGERSTAGGERED_H -#include "DRAMSys/controller/powerdown/PowerDownManagerIF.h" #include "DRAMSys/common/dramExtensions.h" #include "DRAMSys/controller/checker/CheckerIF.h" +#include "DRAMSys/controller/powerdown/PowerDownManagerIF.h" #include @@ -60,7 +60,14 @@ public: void evaluate() override; private: - enum class State {Idle, ActivePdn, PrechargePdn, SelfRefresh, ExtraRefresh} state = State::Idle; + enum class State + { + Idle, + ActivePdn, + PrechargePdn, + SelfRefresh, + ExtraRefresh + } state = State::Idle; tlm::tlm_generic_payload powerDownPayload; ControllerVector& bankMachinesOnRank; Command nextCommand = Command::NOP; diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.cpp b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.cpp index aeeb67c2..4cb4fd25 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.cpp +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.cpp @@ -44,15 +44,20 @@ using namespace tlm; namespace DRAMSys { -RefreshManagerAllBank::RefreshManagerAllBank(const Configuration& config, - ControllerVector& bankMachinesOnRank, - PowerDownManagerIF& powerDownManager, Rank rank) - : memSpec(*config.memSpec), bankMachinesOnRank(bankMachinesOnRank), - powerDownManager(powerDownManager), maxPostponed(static_cast(config.refreshMaxPostponed)), - maxPulledin(-static_cast(config.refreshMaxPulledin)), refreshManagement(config.refreshManagement) +RefreshManagerAllBank::RefreshManagerAllBank( + const Configuration& config, + ControllerVector& bankMachinesOnRank, + PowerDownManagerIF& powerDownManager, + Rank rank) : + memSpec(*config.memSpec), + bankMachinesOnRank(bankMachinesOnRank), + powerDownManager(powerDownManager), + maxPostponed(static_cast(config.refreshMaxPostponed)), + maxPulledin(-static_cast(config.refreshMaxPulledin)), + refreshManagement(config.refreshManagement) { - timeForNextTrigger = getTimeForFirstTrigger(memSpec.tCK, memSpec.getRefreshIntervalAB(), - rank, memSpec.ranksPerChannel); + timeForNextTrigger = getTimeForFirstTrigger( + memSpec.tCK, memSpec.getRefreshIntervalAB(), rank, memSpec.ranksPerChannel); setUpDummy(refreshPayload, 0, rank); } @@ -178,49 +183,54 @@ void RefreshManagerAllBank::update(Command command) { switch (command) { - case Command::ACT: - activatedBanks++; - break; - case Command::PREPB: case Command::RDA: case Command::WRA: case Command::MWRA: - activatedBanks--; - break; - case Command::PREAB: - activatedBanks = 0; - break; - case Command::REFAB: - if (sleeping) - { - // Refresh command after SREFEX - state = State::Regular; // TODO: check if this assignment is necessary - timeForNextTrigger = sc_time_stamp() + memSpec.getRefreshIntervalAB(); - sleeping = false; - } - else - { - if (state == State::Pulledin) - flexibilityCounter--; - else - state = State::Pulledin; - - if (flexibilityCounter == maxPulledin) - { - state = State::Regular; - timeForNextTrigger += memSpec.getRefreshIntervalAB(); - } - } - break; - case Command::PDEA: case Command::PDEP: - sleeping = true; - break; - case Command::SREFEN: - sleeping = true; - timeForNextTrigger = scMaxTime; - break; - case Command::PDXA: case Command::PDXP: + case Command::ACT: + activatedBanks++; + break; + case Command::PREPB: + case Command::RDA: + case Command::WRA: + case Command::MWRA: + activatedBanks--; + break; + case Command::PREAB: + activatedBanks = 0; + break; + case Command::REFAB: + if (sleeping) + { + // Refresh command after SREFEX + state = State::Regular; // TODO: check if this assignment is necessary + timeForNextTrigger = sc_time_stamp() + memSpec.getRefreshIntervalAB(); sleeping = false; - break; - default: - break; + } + else + { + if (state == State::Pulledin) + flexibilityCounter--; + else + state = State::Pulledin; + + if (flexibilityCounter == maxPulledin) + { + state = State::Regular; + timeForNextTrigger += memSpec.getRefreshIntervalAB(); + } + } + break; + case Command::PDEA: + case Command::PDEP: + sleeping = true; + break; + case Command::SREFEN: + sleeping = true; + timeForNextTrigger = scMaxTime; + break; + case Command::PDXA: + case Command::PDXP: + sleeping = false; + break; + default: + break; } } diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.h b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.h index 14776904..ca79af6c 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.h +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.h @@ -35,14 +35,14 @@ #ifndef REFRESHMANAGERALLBANK_H #define REFRESHMANAGERALLBANK_H -#include "DRAMSys/controller/refresh/RefreshManagerIF.h" -#include "DRAMSys/controller/checker/CheckerIF.h" #include "DRAMSys/configuration/Configuration.h" #include "DRAMSys/configuration/memspec/MemSpec.h" +#include "DRAMSys/controller/checker/CheckerIF.h" +#include "DRAMSys/controller/refresh/RefreshManagerIF.h" -#include #include #include +#include namespace DRAMSys { @@ -53,8 +53,10 @@ class PowerDownManagerIF; class RefreshManagerAllBank final : public RefreshManagerIF { public: - RefreshManagerAllBank(const Configuration& config, ControllerVector& bankMachinesOnRank, - PowerDownManagerIF& powerDownManager, Rank rank); + RefreshManagerAllBank(const Configuration& config, + ControllerVector& bankMachinesOnRank, + PowerDownManagerIF& powerDownManager, + Rank rank); CommandTuple::Type getNextCommand() override; void evaluate() override; @@ -62,7 +64,11 @@ public: sc_core::sc_time getTimeForNextTrigger() override; private: - enum class State {Regular, Pulledin} state = State::Regular; + enum class State + { + Regular, + Pulledin + } state = State::Regular; const MemSpec& memSpec; ControllerVector& bankMachinesOnRank; PowerDownManagerIF& powerDownManager; diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerDummy.h b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerDummy.h index 18c92d81..dc17017b 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerDummy.h +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerDummy.h @@ -49,6 +49,7 @@ public: void evaluate() override {} void update([[maybe_unused]] Command command) override {} sc_core::sc_time getTimeForNextTrigger() override; + private: const sc_core::sc_time scMaxTime = sc_core::sc_max_time(); }; diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerIF.h b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerIF.h index 3f8b7d7d..cd0f0e81 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerIF.h +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerIF.h @@ -35,9 +35,9 @@ #ifndef REFRESHMANAGERIF_H #define REFRESHMANAGERIF_H -#include "DRAMSys/controller/ManagerIF.h" -#include "DRAMSys/controller/Command.h" #include "DRAMSys/configuration/Configuration.h" +#include "DRAMSys/controller/Command.h" +#include "DRAMSys/controller/ManagerIF.h" #include #include @@ -51,8 +51,10 @@ public: virtual sc_core::sc_time getTimeForNextTrigger() = 0; protected: - static sc_core::sc_time getTimeForFirstTrigger(const sc_core::sc_time& tCK, const sc_core::sc_time &refreshInterval, - Rank rank, unsigned numberOfRanks) + static sc_core::sc_time getTimeForFirstTrigger(const sc_core::sc_time& tCK, + const sc_core::sc_time& refreshInterval, + Rank rank, + unsigned numberOfRanks) { // Calculate bit-reversal rank ID auto rankID = static_cast(rank); @@ -73,7 +75,8 @@ protected: } // Use bit-reversal order for refreshes on ranks - sc_core::sc_time timeForFirstTrigger = refreshInterval - reverseRankID * (refreshInterval / numberOfRanks); + sc_core::sc_time timeForFirstTrigger = + refreshInterval - reverseRankID * (refreshInterval / numberOfRanks); timeForFirstTrigger = std::ceil(timeForFirstTrigger / tCK) * tCK; return timeForFirstTrigger; diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.cpp b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.cpp index 677f888d..bd37eb2a 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.cpp +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.cpp @@ -43,28 +43,39 @@ using namespace tlm; namespace DRAMSys { -RefreshManagerPer2Bank::RefreshManagerPer2Bank(const Configuration& config, - ControllerVector& bankMachinesOnRank, - PowerDownManagerIF& powerDownManager, Rank rank) - : memSpec(*config.memSpec), powerDownManager(powerDownManager), +RefreshManagerPer2Bank::RefreshManagerPer2Bank( + const Configuration& config, + ControllerVector& bankMachinesOnRank, + PowerDownManagerIF& powerDownManager, + Rank rank) : + memSpec(*config.memSpec), + powerDownManager(powerDownManager), maxPostponed(static_cast(config.refreshMaxPostponed * memSpec.banksPerRank / 2)), maxPulledin(-static_cast(config.refreshMaxPulledin * memSpec.banksPerRank / 2)) { - timeForNextTrigger = getTimeForFirstTrigger(memSpec.tCK, memSpec.getRefreshIntervalP2B(), rank, - memSpec.ranksPerChannel); + timeForNextTrigger = getTimeForFirstTrigger( + memSpec.tCK, memSpec.getRefreshIntervalP2B(), rank, memSpec.ranksPerChannel); // each bank pair has one payload (e.g. 0-8, 1-9, 2-10, 3-11, ...) - for (unsigned outerID = 0; outerID < memSpec.banksPerRank; outerID += (memSpec.getPer2BankOffset() * 2)) + for (unsigned outerID = 0; outerID < memSpec.banksPerRank; + outerID += (memSpec.getPer2BankOffset() * 2)) { for (unsigned bankID = outerID; bankID < (outerID + memSpec.getPer2BankOffset()); bankID++) { Bank firstBank = Bank(bankID); Bank secondBank = Bank(bankID + memSpec.getPer2BankOffset()); - setUpDummy(refreshPayloads[bankMachinesOnRank[firstBank]], 0, rank, - bankMachinesOnRank[firstBank]->getBankGroup(), bankMachinesOnRank[firstBank]->getBank()); - setUpDummy(refreshPayloads[bankMachinesOnRank[secondBank]], 0, rank, - bankMachinesOnRank[secondBank]->getBankGroup(), bankMachinesOnRank[secondBank]->getBank()); - allBankMachines.push_back({bankMachinesOnRank[firstBank], bankMachinesOnRank[secondBank]}); + setUpDummy(refreshPayloads[bankMachinesOnRank[firstBank]], + 0, + rank, + bankMachinesOnRank[firstBank]->getBankGroup(), + bankMachinesOnRank[firstBank]->getBank()); + setUpDummy(refreshPayloads[bankMachinesOnRank[secondBank]], + 0, + rank, + bankMachinesOnRank[secondBank]->getBankGroup(), + bankMachinesOnRank[secondBank]->getBank()); + allBankMachines.push_back( + {bankMachinesOnRank[firstBank], bankMachinesOnRank[secondBank]}); } } @@ -102,7 +113,9 @@ void RefreshManagerPer2Bank::evaluate() if (!skipSelection) { currentIterator = remainingBankMachines.begin(); - for (auto bankIt = remainingBankMachines.begin(); bankIt != remainingBankMachines.end(); bankIt++) + for (auto bankIt = remainingBankMachines.begin(); + bankIt != remainingBankMachines.end(); + bankIt++) { bool pairIsBusy = false; for (const auto* pairIt : *bankIt) @@ -131,7 +144,7 @@ void RefreshManagerPer2Bank::evaluate() nextCommand = Command::REFP2B; currentRefreshPayload = &refreshPayloads.at(currentIterator->front()); - for (auto *it : *currentIterator) + for (auto* it : *currentIterator) { if (it->isActivated()) { @@ -139,18 +152,18 @@ void RefreshManagerPer2Bank::evaluate() currentRefreshPayload = &refreshPayloads.at(it); break; } - } + } - // TODO: banks should already be blocked for precharge and selection should be skipped - if (nextCommand == Command::REFP2B && forcedRefresh) - { - for (auto* it : *currentIterator) - it->block(); - skipSelection = true; - } - return; + // TODO: banks should already be blocked for precharge and selection should be skipped + if (nextCommand == Command::REFP2B && forcedRefresh) + { + for (auto* it : *currentIterator) + it->block(); + skipSelection = true; + } + return; } - + // if (state == RmState::Pulledin) bool allBankPairsBusy = true; @@ -159,7 +172,7 @@ void RefreshManagerPer2Bank::evaluate() bankIt++) { bool pairIsBusy = false; - for (const auto *pairIt : *bankIt) + for (const auto* pairIt : *bankIt) { if (!pairIt->isIdle()) { @@ -184,7 +197,7 @@ void RefreshManagerPer2Bank::evaluate() nextCommand = Command::REFP2B; currentRefreshPayload = &refreshPayloads.at(currentIterator->front()); - for (auto *it : *currentIterator) + for (auto* it : *currentIterator) { if (it->isActivated()) { @@ -201,45 +214,47 @@ void RefreshManagerPer2Bank::update(Command command) { switch (command) { - case Command::REFP2B: - skipSelection = false; - remainingBankMachines.erase(currentIterator); - if (remainingBankMachines.empty()) - remainingBankMachines = allBankMachines; - currentIterator = remainingBankMachines.begin(); - - if (state == State::Pulledin) - flexibilityCounter--; - else - state = State::Pulledin; - - if (flexibilityCounter == maxPulledin) - { - state = State::Regular; - timeForNextTrigger += memSpec.getRefreshIntervalP2B(); - } - break; - case Command::REFAB: - // Refresh command after SREFEX - state = State::Regular; // TODO: check if this assignment is necessary - timeForNextTrigger = sc_time_stamp() + memSpec.getRefreshIntervalP2B(); - sleeping = false; + case Command::REFP2B: + skipSelection = false; + remainingBankMachines.erase(currentIterator); + if (remainingBankMachines.empty()) remainingBankMachines = allBankMachines; - currentIterator = remainingBankMachines.begin(); - skipSelection = false; - break; - case Command::PDEA: case Command::PDEP: - sleeping = true; - break; - case Command::SREFEN: - sleeping = true; - timeForNextTrigger = scMaxTime; - break; - case Command::PDXA: case Command::PDXP: - sleeping = false; - break; - default: - break; + currentIterator = remainingBankMachines.begin(); + + if (state == State::Pulledin) + flexibilityCounter--; + else + state = State::Pulledin; + + if (flexibilityCounter == maxPulledin) + { + state = State::Regular; + timeForNextTrigger += memSpec.getRefreshIntervalP2B(); + } + break; + case Command::REFAB: + // Refresh command after SREFEX + state = State::Regular; // TODO: check if this assignment is necessary + timeForNextTrigger = sc_time_stamp() + memSpec.getRefreshIntervalP2B(); + sleeping = false; + remainingBankMachines = allBankMachines; + currentIterator = remainingBankMachines.begin(); + skipSelection = false; + break; + case Command::PDEA: + case Command::PDEP: + sleeping = true; + break; + case Command::SREFEN: + sleeping = true; + timeForNextTrigger = scMaxTime; + break; + case Command::PDXA: + case Command::PDXP: + sleeping = false; + break; + default: + break; } } diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.h b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.h index 79e5b0f9..4a3c07a3 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.h +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.h @@ -35,16 +35,16 @@ #ifndef REFRESHMANAGERPER2BANK_H #define REFRESHMANAGERPER2BANK_H -#include "DRAMSys/controller/refresh/RefreshManagerIF.h" -#include "DRAMSys/controller/checker/CheckerIF.h" -#include "DRAMSys/configuration/memspec/MemSpec.h" #include "DRAMSys/configuration/Configuration.h" +#include "DRAMSys/configuration/memspec/MemSpec.h" +#include "DRAMSys/controller/checker/CheckerIF.h" +#include "DRAMSys/controller/refresh/RefreshManagerIF.h" -#include #include -#include #include #include +#include +#include namespace DRAMSys { @@ -55,8 +55,10 @@ class PowerDownManagerIF; class RefreshManagerPer2Bank final : public RefreshManagerIF { public: - RefreshManagerPer2Bank(const Configuration& config, ControllerVector& bankMachinesOnRank, - PowerDownManagerIF& powerDownManager, Rank rank); + RefreshManagerPer2Bank(const Configuration& config, + ControllerVector& bankMachinesOnRank, + PowerDownManagerIF& powerDownManager, + Rank rank); CommandTuple::Type getNextCommand() override; void evaluate() override; @@ -64,7 +66,11 @@ public: sc_core::sc_time getTimeForNextTrigger() override; private: - enum class State {Regular, Pulledin} state = State::Regular; + enum class State + { + Regular, + Pulledin + } state = State::Regular; const MemSpec& memSpec; PowerDownManagerIF& powerDownManager; std::unordered_map refreshPayloads; diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.cpp b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.cpp index 9185377c..954bddcb 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.cpp +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.cpp @@ -43,15 +43,18 @@ using namespace tlm; namespace DRAMSys { -RefreshManagerPerBank::RefreshManagerPerBank(const Configuration& config, - ControllerVector& bankMachinesOnRank, - PowerDownManagerIF& powerDownManager, Rank rank) - : memSpec(*config.memSpec), powerDownManager(powerDownManager), +RefreshManagerPerBank::RefreshManagerPerBank( + const Configuration& config, + ControllerVector& bankMachinesOnRank, + PowerDownManagerIF& powerDownManager, + Rank rank) : + memSpec(*config.memSpec), + powerDownManager(powerDownManager), maxPostponed(static_cast(config.refreshMaxPostponed * memSpec.banksPerRank)), maxPulledin(-static_cast(config.refreshMaxPulledin * memSpec.banksPerRank)) { - timeForNextTrigger = getTimeForFirstTrigger(memSpec.tCK, memSpec.getRefreshIntervalPB(), rank, - memSpec.ranksPerChannel); + timeForNextTrigger = getTimeForFirstTrigger( + memSpec.tCK, memSpec.getRefreshIntervalPB(), rank, memSpec.ranksPerChannel); for (auto* it : bankMachinesOnRank) { setUpDummy(refreshPayloads[it], 0, rank, it->getBankGroup(), it->getBank()); @@ -92,7 +95,8 @@ void RefreshManagerPerBank::evaluate() { currentIterator = remainingBankMachines.begin(); - for (auto it = remainingBankMachines.begin(); it != remainingBankMachines.end(); it++) + for (auto it = remainingBankMachines.begin(); it != remainingBankMachines.end(); + it++) { if ((*it)->isIdle()) { @@ -125,7 +129,7 @@ void RefreshManagerPerBank::evaluate() } return; } - + // if (state == RmState::Pulledin) bool allBanksBusy = true; @@ -159,45 +163,47 @@ void RefreshManagerPerBank::update(Command command) { switch (command) { - case Command::REFPB: - skipSelection = false; - remainingBankMachines.erase(currentIterator); - if (remainingBankMachines.empty()) - remainingBankMachines = allBankMachines; - currentIterator = remainingBankMachines.begin(); - - if (state == State::Pulledin) - flexibilityCounter--; - else - state = State::Pulledin; - - if (flexibilityCounter == maxPulledin) - { - state = State::Regular; - timeForNextTrigger += memSpec.getRefreshIntervalPB(); - } - break; - case Command::REFAB: - // Refresh command after SREFEX - state = State::Regular; // TODO: check if this assignment is necessary - timeForNextTrigger = sc_time_stamp() + memSpec.getRefreshIntervalPB(); - sleeping = false; + case Command::REFPB: + skipSelection = false; + remainingBankMachines.erase(currentIterator); + if (remainingBankMachines.empty()) remainingBankMachines = allBankMachines; - currentIterator = remainingBankMachines.begin(); - skipSelection = false; - break; - case Command::PDEA: case Command::PDEP: - sleeping = true; - break; - case Command::SREFEN: - sleeping = true; - timeForNextTrigger = scMaxTime; - break; - case Command::PDXA: case Command::PDXP: - sleeping = false; - break; - default: - break; + currentIterator = remainingBankMachines.begin(); + + if (state == State::Pulledin) + flexibilityCounter--; + else + state = State::Pulledin; + + if (flexibilityCounter == maxPulledin) + { + state = State::Regular; + timeForNextTrigger += memSpec.getRefreshIntervalPB(); + } + break; + case Command::REFAB: + // Refresh command after SREFEX + state = State::Regular; // TODO: check if this assignment is necessary + timeForNextTrigger = sc_time_stamp() + memSpec.getRefreshIntervalPB(); + sleeping = false; + remainingBankMachines = allBankMachines; + currentIterator = remainingBankMachines.begin(); + skipSelection = false; + break; + case Command::PDEA: + case Command::PDEP: + sleeping = true; + break; + case Command::SREFEN: + sleeping = true; + timeForNextTrigger = scMaxTime; + break; + case Command::PDXA: + case Command::PDXP: + sleeping = false; + break; + default: + break; } } diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.h b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.h index 6d0fe7e0..491829f5 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.h +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.h @@ -35,16 +35,16 @@ #ifndef REFRESHMANAGERPERBANK_H #define REFRESHMANAGERPERBANK_H -#include "DRAMSys/controller/refresh/RefreshManagerIF.h" -#include "DRAMSys/controller/checker/CheckerIF.h" -#include "DRAMSys/configuration/memspec/MemSpec.h" #include "DRAMSys/configuration/Configuration.h" +#include "DRAMSys/configuration/memspec/MemSpec.h" +#include "DRAMSys/controller/checker/CheckerIF.h" +#include "DRAMSys/controller/refresh/RefreshManagerIF.h" -#include #include -#include #include #include +#include +#include namespace DRAMSys { @@ -55,8 +55,10 @@ class PowerDownManagerIF; class RefreshManagerPerBank final : public RefreshManagerIF { public: - RefreshManagerPerBank(const Configuration& config, ControllerVector& bankMachinesOnRank, - PowerDownManagerIF& powerDownManager, Rank rank); + RefreshManagerPerBank(const Configuration& config, + ControllerVector& bankMachinesOnRank, + PowerDownManagerIF& powerDownManager, + Rank rank); CommandTuple::Type getNextCommand() override; void evaluate() override; @@ -64,7 +66,11 @@ public: sc_core::sc_time getTimeForNextTrigger() override; private: - enum class State {Regular, Pulledin} state = State::Regular; + enum class State + { + Regular, + Pulledin + } state = State::Regular; const MemSpec& memSpec; PowerDownManagerIF& powerDownManager; std::unordered_map refreshPayloads; diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.cpp b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.cpp index 29721961..6b73ce5f 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.cpp +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.cpp @@ -43,25 +43,31 @@ using namespace tlm; namespace DRAMSys { -RefreshManagerSameBank::RefreshManagerSameBank(const Configuration& config, - ControllerVector& bankMachinesOnRank, - PowerDownManagerIF& powerDownManager, Rank rank) - : memSpec(*config.memSpec), powerDownManager(powerDownManager), +RefreshManagerSameBank::RefreshManagerSameBank( + const Configuration& config, + ControllerVector& bankMachinesOnRank, + PowerDownManagerIF& powerDownManager, + Rank rank) : + memSpec(*config.memSpec), + powerDownManager(powerDownManager), maxPostponed(static_cast(config.refreshMaxPostponed * memSpec.banksPerGroup)), maxPulledin(-static_cast(config.refreshMaxPulledin * memSpec.banksPerGroup)), refreshManagement(config.refreshManagement) { - timeForNextTrigger = getTimeForFirstTrigger(memSpec.tCK, memSpec.getRefreshIntervalSB(), rank, - memSpec.ranksPerChannel); + timeForNextTrigger = getTimeForFirstTrigger( + memSpec.tCK, memSpec.getRefreshIntervalSB(), rank, memSpec.ranksPerChannel); // each same-bank group has one payload (e.g. 0-4-8-12-16-20-24-28) refreshPayloads = std::vector(memSpec.banksPerGroup); for (unsigned bankID = 0; bankID < memSpec.banksPerGroup; bankID++) { // rank 0: bank group 0, bank 0 - 3; rank 1: bank group 8, bank 32 - 35 - setUpDummy(refreshPayloads[bankID], 0, rank, bankMachinesOnRank[Bank(bankID)]->getBankGroup(), + setUpDummy(refreshPayloads[bankID], + 0, + rank, + bankMachinesOnRank[Bank(bankID)]->getBankGroup(), bankMachinesOnRank[Bank(bankID)]->getBank()); - allBankMachines.emplace_back(std::vector(memSpec.groupsPerRank)); + allBankMachines.emplace_back(std::vector(memSpec.groupsPerRank)); } // allBankMachines: ((0-4-8-12-16-20-24-28), (1-5-9-13-17-21-25-29), ...) @@ -80,7 +86,8 @@ RefreshManagerSameBank::RefreshManagerSameBank(const Configuration& config, CommandTuple::Type RefreshManagerSameBank::getNextCommand() { return {nextCommand, - &refreshPayloads[static_cast(currentIterator->front()->getBank()) % memSpec.banksPerGroup], + &refreshPayloads[static_cast(currentIterator->front()->getBank()) % + memSpec.banksPerGroup], SC_ZERO_TIME}; } @@ -108,7 +115,9 @@ void RefreshManagerSameBank::evaluate() if (!skipSelection) { currentIterator = remainingBankMachines.begin(); - for (auto bankIt = remainingBankMachines.begin(); bankIt != remainingBankMachines.end(); bankIt++) + for (auto bankIt = remainingBankMachines.begin(); + bankIt != remainingBankMachines.end(); + bankIt++) { bool groupIsBusy = false; for (const auto* groupIt : *bankIt) @@ -134,7 +143,7 @@ void RefreshManagerSameBank::evaluate() timeForNextTrigger += memSpec.getRefreshIntervalSB(); } else - { + { nextCommand = Command::REFSB; for (const auto* it : *currentIterator) { @@ -145,8 +154,8 @@ void RefreshManagerSameBank::evaluate() } } - // TODO: banks should already be blocked for precharge and selection should be skipped - // only check for forced refresh, also block for PRESB + // TODO: banks should already be blocked for precharge and selection should be + // skipped only check for forced refresh, also block for PRESB if (nextCommand == Command::REFSB && forcedRefresh) { for (auto* it : *currentIterator) @@ -161,7 +170,8 @@ void RefreshManagerSameBank::evaluate() bool allGroupsBusy = true; currentIterator = remainingBankMachines.begin(); - for (auto bankIt = remainingBankMachines.begin(); bankIt != remainingBankMachines.end(); bankIt++) + for (auto bankIt = remainingBankMachines.begin(); bankIt != remainingBankMachines.end(); + bankIt++) { bool groupIsBusy = false; for (const auto* groupIt : *bankIt) @@ -277,45 +287,47 @@ void RefreshManagerSameBank::update(Command command) { switch (command) { - case Command::REFSB: - skipSelection = false; - remainingBankMachines.erase(currentIterator); - if (remainingBankMachines.empty()) - remainingBankMachines = allBankMachines; - currentIterator = remainingBankMachines.begin(); - - if (state == State::Pulledin) - flexibilityCounter--; - else - state = State::Pulledin; - - if (flexibilityCounter == maxPulledin) - { - state = State::Regular; - timeForNextTrigger += memSpec.getRefreshIntervalSB(); - } - break; - case Command::REFAB: - // Refresh command after SREFEX - state = State::Regular; // TODO: check if this assignment is necessary - timeForNextTrigger = sc_time_stamp() + memSpec.getRefreshIntervalSB(); - sleeping = false; + case Command::REFSB: + skipSelection = false; + remainingBankMachines.erase(currentIterator); + if (remainingBankMachines.empty()) remainingBankMachines = allBankMachines; - currentIterator = remainingBankMachines.begin(); - skipSelection = false; - break; - case Command::PDEA: case Command::PDEP: - sleeping = true; - break; - case Command::SREFEN: - sleeping = true; - timeForNextTrigger = scMaxTime; - break; - case Command::PDXA: case Command::PDXP: - sleeping = false; - break; - default: - break; + currentIterator = remainingBankMachines.begin(); + + if (state == State::Pulledin) + flexibilityCounter--; + else + state = State::Pulledin; + + if (flexibilityCounter == maxPulledin) + { + state = State::Regular; + timeForNextTrigger += memSpec.getRefreshIntervalSB(); + } + break; + case Command::REFAB: + // Refresh command after SREFEX + state = State::Regular; // TODO: check if this assignment is necessary + timeForNextTrigger = sc_time_stamp() + memSpec.getRefreshIntervalSB(); + sleeping = false; + remainingBankMachines = allBankMachines; + currentIterator = remainingBankMachines.begin(); + skipSelection = false; + break; + case Command::PDEA: + case Command::PDEP: + sleeping = true; + break; + case Command::SREFEN: + sleeping = true; + timeForNextTrigger = scMaxTime; + break; + case Command::PDXA: + case Command::PDXP: + sleeping = false; + break; + default: + break; } } diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.h b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.h index 04cea387..4f66bce7 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.h +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.h @@ -35,15 +35,15 @@ #ifndef REFRESHMANAGERSAMEBANK_H #define REFRESHMANAGERSAMEBANK_H -#include "DRAMSys/controller/refresh/RefreshManagerIF.h" -#include "DRAMSys/controller/checker/CheckerIF.h" -#include "DRAMSys/configuration/memspec/MemSpec.h" #include "DRAMSys/configuration/Configuration.h" +#include "DRAMSys/configuration/memspec/MemSpec.h" +#include "DRAMSys/controller/checker/CheckerIF.h" +#include "DRAMSys/controller/refresh/RefreshManagerIF.h" -#include #include #include #include +#include namespace DRAMSys { @@ -54,8 +54,10 @@ class PowerDownManagerIF; class RefreshManagerSameBank final : public RefreshManagerIF { public: - RefreshManagerSameBank(const Configuration& config, ControllerVector& bankMachinesOnRank, - PowerDownManagerIF& powerDownManager, Rank rank); + RefreshManagerSameBank(const Configuration& config, + ControllerVector& bankMachinesOnRank, + PowerDownManagerIF& powerDownManager, + Rank rank); CommandTuple::Type getNextCommand() override; void evaluate() override; @@ -63,16 +65,20 @@ public: sc_core::sc_time getTimeForNextTrigger() override; private: - enum class State {Regular, Pulledin} state = State::Regular; + enum class State + { + Regular, + Pulledin + } state = State::Regular; const MemSpec& memSpec; PowerDownManagerIF& powerDownManager; std::vector refreshPayloads; sc_core::sc_time timeForNextTrigger = sc_core::sc_max_time(); Command nextCommand = Command::NOP; - std::list> remainingBankMachines; - std::list> allBankMachines; - std::list>::iterator currentIterator; + std::list> remainingBankMachines; + std::list> allBankMachines; + std::list>::iterator currentIterator; int flexibilityCounter = 0; const int maxPostponed; diff --git a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueFifo.h b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueFifo.h index f6a0f53a..a01a02fa 100644 --- a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueFifo.h +++ b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueFifo.h @@ -37,10 +37,10 @@ #include "DRAMSys/controller/respqueue/RespQueueIF.h" -#include #include #include #include +#include namespace DRAMSys { diff --git a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueIF.h b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueIF.h index dad6725a..6c111930 100644 --- a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueIF.h +++ b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueIF.h @@ -44,10 +44,10 @@ namespace DRAMSys class RespQueueIF { protected: - RespQueueIF(const RespQueueIF &) = default; - RespQueueIF(RespQueueIF &&) = default; - RespQueueIF &operator=(const RespQueueIF &) = default; - RespQueueIF &operator=(RespQueueIF &&) = default; + RespQueueIF(const RespQueueIF&) = default; + RespQueueIF(RespQueueIF&&) = default; + RespQueueIF& operator=(const RespQueueIF&) = default; + RespQueueIF& operator=(RespQueueIF&&) = default; public: RespQueueIF() = default; diff --git a/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterBankwise.cpp b/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterBankwise.cpp index 29b5398a..a807e11e 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterBankwise.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterBankwise.cpp @@ -41,8 +41,8 @@ using namespace tlm; namespace DRAMSys { -BufferCounterBankwise::BufferCounterBankwise(unsigned requestBufferSize, unsigned numberOfBanks) - : requestBufferSize(requestBufferSize) +BufferCounterBankwise::BufferCounterBankwise(unsigned requestBufferSize, unsigned numberOfBanks) : + requestBufferSize(requestBufferSize) { numRequestsOnBank = std::vector(numberOfBanks, 0); } diff --git a/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterBankwise.h b/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterBankwise.h index c335cce3..63d23329 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterBankwise.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterBankwise.h @@ -37,8 +37,8 @@ #include "DRAMSys/controller/scheduler/BufferCounterIF.h" -#include #include +#include namespace DRAMSys { diff --git a/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterIF.h b/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterIF.h index 02357545..c028822f 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterIF.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterIF.h @@ -35,8 +35,8 @@ #ifndef BUFFERCOUNTERIF_H #define BUFFERCOUNTERIF_H -#include #include +#include namespace DRAMSys { @@ -44,10 +44,10 @@ namespace DRAMSys class BufferCounterIF { protected: - BufferCounterIF(const BufferCounterIF &) = default; - BufferCounterIF(BufferCounterIF &&) = default; - BufferCounterIF &operator=(const BufferCounterIF &) = default; - BufferCounterIF &operator=(BufferCounterIF &&) = default; + BufferCounterIF(const BufferCounterIF&) = default; + BufferCounterIF(BufferCounterIF&&) = default; + BufferCounterIF& operator=(const BufferCounterIF&) = default; + BufferCounterIF& operator=(BufferCounterIF&&) = default; public: BufferCounterIF() = default; diff --git a/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterReadWrite.cpp b/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterReadWrite.cpp index 46d4ce64..4cb212f5 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterReadWrite.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterReadWrite.cpp @@ -39,15 +39,16 @@ using namespace tlm; namespace DRAMSys { -BufferCounterReadWrite::BufferCounterReadWrite(unsigned requestBufferSize) - : requestBufferSize(requestBufferSize) +BufferCounterReadWrite::BufferCounterReadWrite(unsigned requestBufferSize) : + requestBufferSize(requestBufferSize) { numReadWriteRequests = std::vector(2); } bool BufferCounterReadWrite::hasBufferSpace() const { - return (numReadWriteRequests[0] < requestBufferSize && numReadWriteRequests[1] < requestBufferSize); + return (numReadWriteRequests[0] < requestBufferSize && + numReadWriteRequests[1] < requestBufferSize); } void BufferCounterReadWrite::storeRequest(const tlm_generic_payload& trans) diff --git a/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterReadWrite.h b/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterReadWrite.h index 362d9723..8202acef 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterReadWrite.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterReadWrite.h @@ -37,8 +37,8 @@ #include "DRAMSys/controller/scheduler/BufferCounterIF.h" -#include #include +#include namespace DRAMSys { diff --git a/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterShared.cpp b/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterShared.cpp index 44f5ed5c..d2d4c937 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterShared.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterShared.cpp @@ -39,8 +39,8 @@ using namespace tlm; namespace DRAMSys { -BufferCounterShared::BufferCounterShared(unsigned requestBufferSize) - : requestBufferSize(requestBufferSize) +BufferCounterShared::BufferCounterShared(unsigned requestBufferSize) : + requestBufferSize(requestBufferSize) { numRequests = std::vector(1); } diff --git a/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterShared.h b/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterShared.h index 9897a769..b5b6f090 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterShared.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterShared.h @@ -37,8 +37,8 @@ #include "DRAMSys/controller/scheduler/BufferCounterIF.h" -#include #include +#include namespace DRAMSys { diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.cpp b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.cpp index 43df9e4d..5f15f14c 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.cpp @@ -45,10 +45,12 @@ namespace DRAMSys SchedulerFifo::SchedulerFifo(const Configuration& config) { - buffer = ControllerVector>(config.memSpec->banksPerChannel); + buffer = + ControllerVector>(config.memSpec->banksPerChannel); if (config.schedulerBuffer == Configuration::SchedulerBuffer::Bankwise) - bufferCounter = std::make_unique(config.requestBufferSize, config.memSpec->banksPerChannel); + bufferCounter = std::make_unique(config.requestBufferSize, + config.memSpec->banksPerChannel); else if (config.schedulerBuffer == Configuration::SchedulerBuffer::ReadWrite) bufferCounter = std::make_unique(config.requestBufferSize); else if (config.schedulerBuffer == Configuration::SchedulerBuffer::Shared) diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.h b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.h index 813442d8..8a2a6df3 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.h @@ -35,15 +35,15 @@ #ifndef SCHEDULERFIFO_H #define SCHEDULERFIFO_H -#include "DRAMSys/controller/scheduler/SchedulerIF.h" #include "DRAMSys/common/dramExtensions.h" #include "DRAMSys/controller/BankMachine.h" #include "DRAMSys/controller/scheduler/BufferCounterIF.h" +#include "DRAMSys/controller/scheduler/SchedulerIF.h" -#include #include #include #include +#include namespace DRAMSys { @@ -55,8 +55,10 @@ public: [[nodiscard]] bool hasBufferSpace() const override; void storeRequest(tlm::tlm_generic_payload& payload) override; void removeRequest(tlm::tlm_generic_payload& payload) override; - [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine& bankMachine) const override; - [[nodiscard]] bool hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command command) const override; + [[nodiscard]] tlm::tlm_generic_payload* + getNextRequest(const BankMachine& bankMachine) const override; + [[nodiscard]] bool + hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command command) const override; [[nodiscard]] bool hasFurtherRequest(Bank bank, tlm::tlm_command command) const override; [[nodiscard]] const std::vector& getBufferDepth() const override; diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.cpp b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.cpp index dfdd566e..27dc0785 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.cpp @@ -45,10 +45,12 @@ namespace DRAMSys SchedulerFrFcfs::SchedulerFrFcfs(const Configuration& config) { - buffer = ControllerVector>(config.memSpec->banksPerChannel); + buffer = + ControllerVector>(config.memSpec->banksPerChannel); if (config.schedulerBuffer == Configuration::SchedulerBuffer::Bankwise) - bufferCounter = std::make_unique(config.requestBufferSize, config.memSpec->banksPerChannel); + bufferCounter = std::make_unique(config.requestBufferSize, + config.memSpec->banksPerChannel); else if (config.schedulerBuffer == Configuration::SchedulerBuffer::ReadWrite) bufferCounter = std::make_unique(config.requestBufferSize); else if (config.schedulerBuffer == Configuration::SchedulerBuffer::Shared) @@ -101,7 +103,9 @@ tlm_generic_payload* SchedulerFrFcfs::getNextRequest(const BankMachine& bankMach return nullptr; } -bool SchedulerFrFcfs::hasFurtherRowHit(Bank bank, Row row, [[maybe_unused]] tlm_command command) const +bool SchedulerFrFcfs::hasFurtherRowHit(Bank bank, + Row row, + [[maybe_unused]] tlm_command command) const { unsigned rowHitCounter = 0; for (auto* it : buffer[bank]) diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.h b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.h index 9f0a9178..e3bdab83 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.h @@ -35,15 +35,15 @@ #ifndef SCHEDULERFRFCFS_H #define SCHEDULERFRFCFS_H -#include "DRAMSys/controller/scheduler/SchedulerIF.h" #include "DRAMSys/common/dramExtensions.h" #include "DRAMSys/controller/BankMachine.h" #include "DRAMSys/controller/scheduler/BufferCounterIF.h" +#include "DRAMSys/controller/scheduler/SchedulerIF.h" -#include #include #include #include +#include namespace DRAMSys { @@ -55,8 +55,10 @@ public: [[nodiscard]] bool hasBufferSpace() const override; void storeRequest(tlm::tlm_generic_payload& payload) override; void removeRequest(tlm::tlm_generic_payload& payload) override; - [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine& bankMachine) const override; - [[nodiscard]] bool hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command command) const override; + [[nodiscard]] tlm::tlm_generic_payload* + getNextRequest(const BankMachine& bankMachine) const override; + [[nodiscard]] bool + hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command command) const override; [[nodiscard]] bool hasFurtherRequest(Bank bank, tlm::tlm_command command) const override; [[nodiscard]] const std::vector& getBufferDepth() const override; diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.cpp b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.cpp index f548f520..a120c662 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.cpp @@ -45,10 +45,12 @@ namespace DRAMSys SchedulerFrFcfsGrp::SchedulerFrFcfsGrp(const Configuration& config) { - buffer = ControllerVector>(config.memSpec->banksPerChannel); + buffer = + ControllerVector>(config.memSpec->banksPerChannel); if (config.schedulerBuffer == Configuration::SchedulerBuffer::Bankwise) - bufferCounter = std::make_unique(config.requestBufferSize, config.memSpec->banksPerChannel); + bufferCounter = std::make_unique(config.requestBufferSize, + config.memSpec->banksPerChannel); else if (config.schedulerBuffer == Configuration::SchedulerBuffer::ReadWrite) bufferCounter = std::make_unique(config.requestBufferSize); else if (config.schedulerBuffer == Configuration::SchedulerBuffer::Shared) @@ -90,8 +92,8 @@ tlm_generic_payload* SchedulerFrFcfsGrp::getNextRequest(const BankMachine& bankM { // Filter all row hits Row openRow = bankMachine.getOpenRow(); - std::list rowHits; - for (auto *it : buffer[bank]) + std::list rowHits; + for (auto* it : buffer[bank]) { if (ControllerExtension::getRow(*it) == openRow) rowHits.push_back(it); @@ -126,10 +128,12 @@ tlm_generic_payload* SchedulerFrFcfsGrp::getNextRequest(const BankMachine& bankM return nullptr; } -bool SchedulerFrFcfsGrp::hasFurtherRowHit(Bank bank, Row row, [[maybe_unused]] tlm_command command) const +bool SchedulerFrFcfsGrp::hasFurtherRowHit(Bank bank, + Row row, + [[maybe_unused]] tlm_command command) const { unsigned rowHitCounter = 0; - for (auto *it : buffer[bank]) + for (auto* it : buffer[bank]) { if (ControllerExtension::getRow(*it) == row) { diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.h b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.h index 19ed2271..f7bd73db 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.h @@ -35,15 +35,15 @@ #ifndef SCHEDULERFRFCFSGRP_H #define SCHEDULERFRFCFSGRP_H -#include "DRAMSys/controller/scheduler/SchedulerIF.h" #include "DRAMSys/common/dramExtensions.h" #include "DRAMSys/controller/BankMachine.h" #include "DRAMSys/controller/scheduler/BufferCounterIF.h" +#include "DRAMSys/controller/scheduler/SchedulerIF.h" -#include #include #include #include +#include namespace DRAMSys { @@ -55,13 +55,15 @@ public: [[nodiscard]] bool hasBufferSpace() const override; void storeRequest(tlm::tlm_generic_payload& payload) override; void removeRequest(tlm::tlm_generic_payload& payload) override; - [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine& bankMachine) const override; - [[nodiscard]] bool hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command command) const override; + [[nodiscard]] tlm::tlm_generic_payload* + getNextRequest(const BankMachine& bankMachine) const override; + [[nodiscard]] bool + hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command command) const override; [[nodiscard]] bool hasFurtherRequest(Bank bank, tlm::tlm_command command) const override; [[nodiscard]] const std::vector& getBufferDepth() const override; private: - ControllerVector> buffer; + ControllerVector> buffer; tlm::tlm_command lastCommand = tlm::TLM_READ_COMMAND; std::unique_ptr bufferCounter; }; diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.cpp b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.cpp index 0fb5091d..e9ca8915 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.cpp @@ -45,11 +45,14 @@ namespace DRAMSys SchedulerGrpFrFcfs::SchedulerGrpFrFcfs(const Configuration& config) { - readBuffer = ControllerVector>(config.memSpec->banksPerChannel); - writeBuffer = ControllerVector>(config.memSpec->banksPerChannel); + readBuffer = + ControllerVector>(config.memSpec->banksPerChannel); + writeBuffer = + ControllerVector>(config.memSpec->banksPerChannel); if (config.schedulerBuffer == Configuration::SchedulerBuffer::Bankwise) - bufferCounter = std::make_unique(config.requestBufferSize, config.memSpec->banksPerChannel); + bufferCounter = std::make_unique(config.requestBufferSize, + config.memSpec->banksPerChannel); else if (config.schedulerBuffer == Configuration::SchedulerBuffer::ReadWrite) bufferCounter = std::make_unique(config.requestBufferSize); else if (config.schedulerBuffer == Configuration::SchedulerBuffer::Shared) @@ -98,7 +101,7 @@ tlm_generic_payload* SchedulerGrpFrFcfs::getNextRequest(const BankMachine& bankM { // Search for read row hit Row openRow = bankMachine.getOpenRow(); - for (auto *it : readBuffer[bank]) + for (auto* it : readBuffer[bank]) { if (ControllerExtension::getRow(*it) == openRow) return it; @@ -113,7 +116,7 @@ tlm_generic_payload* SchedulerGrpFrFcfs::getNextRequest(const BankMachine& bankM { // Search for write row hit Row openRow = bankMachine.getOpenRow(); - for (auto *it : writeBuffer[bank]) + for (auto* it : writeBuffer[bank]) { if (ControllerExtension::getRow(*it) == openRow) return it; @@ -131,7 +134,7 @@ tlm_generic_payload* SchedulerGrpFrFcfs::getNextRequest(const BankMachine& bankM { // Search for write row hit Row openRow = bankMachine.getOpenRow(); - for (auto *it : writeBuffer[bank]) + for (auto* it : writeBuffer[bank]) { if (ControllerExtension::getRow(*it) == openRow) return it; @@ -146,7 +149,7 @@ tlm_generic_payload* SchedulerGrpFrFcfs::getNextRequest(const BankMachine& bankM { // Search for read row hit Row openRow = bankMachine.getOpenRow(); - for (auto *it : readBuffer[bank]) + for (auto* it : readBuffer[bank]) { if (ControllerExtension::getRow(*it) == openRow) return it; @@ -164,7 +167,7 @@ bool SchedulerGrpFrFcfs::hasFurtherRowHit(Bank bank, Row row, tlm_command comman unsigned rowHitCounter = 0; if (command == tlm::TLM_READ_COMMAND) { - for (auto *it : readBuffer[bank]) + for (auto* it : readBuffer[bank]) { if (ControllerExtension::getRow(*it) == row) { @@ -197,7 +200,6 @@ bool SchedulerGrpFrFcfs::hasFurtherRequest(Bank bank, tlm_command command) const } return writeBuffer[bank].size() >= 2; - } const std::vector& SchedulerGrpFrFcfs::getBufferDepth() const diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.h b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.h index a39eea78..bb28d2b9 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.h @@ -35,15 +35,15 @@ #ifndef SCHEDULERGRPFRFCFS_H #define SCHEDULERGRPFRFCFS_H -#include "DRAMSys/controller/scheduler/SchedulerIF.h" #include "DRAMSys/common/dramExtensions.h" #include "DRAMSys/controller/BankMachine.h" #include "DRAMSys/controller/scheduler/BufferCounterIF.h" +#include "DRAMSys/controller/scheduler/SchedulerIF.h" -#include #include #include #include +#include namespace DRAMSys { @@ -55,8 +55,10 @@ public: [[nodiscard]] bool hasBufferSpace() const override; void storeRequest(tlm::tlm_generic_payload& payload) override; void removeRequest(tlm::tlm_generic_payload& payload) override; - [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine& bankMachine) const override; - [[nodiscard]] bool hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command command) const override; + [[nodiscard]] tlm::tlm_generic_payload* + getNextRequest(const BankMachine& bankMachine) const override; + [[nodiscard]] bool + hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command command) const override; [[nodiscard]] bool hasFurtherRequest(Bank bank, tlm::tlm_command command) const override; [[nodiscard]] const std::vector& getBufferDepth() const override; diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.cpp b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.cpp index 1957d020..6e2a5a2e 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.cpp @@ -43,14 +43,18 @@ using namespace tlm; namespace DRAMSys { -SchedulerGrpFrFcfsWm::SchedulerGrpFrFcfsWm(const Configuration& config) - : lowWatermark(config.lowWatermark), highWatermark(config.highWatermark) +SchedulerGrpFrFcfsWm::SchedulerGrpFrFcfsWm(const Configuration& config) : + lowWatermark(config.lowWatermark), + highWatermark(config.highWatermark) { - readBuffer = ControllerVector>(config.memSpec->banksPerChannel); - writeBuffer = ControllerVector>(config.memSpec->banksPerChannel); + readBuffer = + ControllerVector>(config.memSpec->banksPerChannel); + writeBuffer = + ControllerVector>(config.memSpec->banksPerChannel); if (config.schedulerBuffer == Configuration::SchedulerBuffer::Bankwise) - bufferCounter = std::make_unique(config.requestBufferSize, config.memSpec->banksPerChannel); + bufferCounter = std::make_unique(config.requestBufferSize, + config.memSpec->banksPerChannel); else if (config.schedulerBuffer == Configuration::SchedulerBuffer::ReadWrite) bufferCounter = std::make_unique(config.requestBufferSize); else if (config.schedulerBuffer == Configuration::SchedulerBuffer::Shared) @@ -102,7 +106,7 @@ tlm_generic_payload* SchedulerGrpFrFcfsWm::getNextRequest(const BankMachine& ban { // Search for read row hit Row openRow = bankMachine.getOpenRow(); - for (auto *it : readBuffer[bank]) + for (auto* it : readBuffer[bank]) { if (ControllerExtension::getRow(*it) == openRow) return it; @@ -133,7 +137,9 @@ tlm_generic_payload* SchedulerGrpFrFcfsWm::getNextRequest(const BankMachine& ban return nullptr; } -bool SchedulerGrpFrFcfsWm::hasFurtherRowHit(Bank bank, Row row, [[maybe_unused]] tlm::tlm_command command) const +bool SchedulerGrpFrFcfsWm::hasFurtherRowHit(Bank bank, + Row row, + [[maybe_unused]] tlm::tlm_command command) const { unsigned rowHitCounter = 0; if (!writeMode) @@ -163,7 +169,8 @@ bool SchedulerGrpFrFcfsWm::hasFurtherRowHit(Bank bank, Row row, [[maybe_unused]] return false; } -bool SchedulerGrpFrFcfsWm::hasFurtherRequest(Bank bank, [[maybe_unused]] tlm::tlm_command command) const +bool SchedulerGrpFrFcfsWm::hasFurtherRequest(Bank bank, + [[maybe_unused]] tlm::tlm_command command) const { if (!writeMode) { @@ -182,12 +189,14 @@ void SchedulerGrpFrFcfsWm::evaluateWriteMode() { if (writeMode) { - if (bufferCounter->getNumWriteRequests() <= lowWatermark && bufferCounter->getNumReadRequests() != 0) + if (bufferCounter->getNumWriteRequests() <= lowWatermark && + bufferCounter->getNumReadRequests() != 0) writeMode = false; } else { - if (bufferCounter->getNumWriteRequests() > highWatermark || bufferCounter->getNumReadRequests() == 0) + if (bufferCounter->getNumWriteRequests() > highWatermark || + bufferCounter->getNumReadRequests() == 0) writeMode = true; } } diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.h b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.h index f5c31d31..a9bfcba2 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.h @@ -35,16 +35,16 @@ #ifndef SCHEDULERGRPFRFCFSWM_H #define SCHEDULERGRPFRFCFSWM_H -#include "DRAMSys/controller/scheduler/SchedulerIF.h" #include "DRAMSys/common/dramExtensions.h" +#include "DRAMSys/configuration/Configuration.h" #include "DRAMSys/controller/BankMachine.h" #include "DRAMSys/controller/scheduler/BufferCounterIF.h" -#include "DRAMSys/configuration/Configuration.h" +#include "DRAMSys/controller/scheduler/SchedulerIF.h" -#include #include #include #include +#include namespace DRAMSys { @@ -56,8 +56,10 @@ public: [[nodiscard]] bool hasBufferSpace() const override; void storeRequest(tlm::tlm_generic_payload& payload) override; void removeRequest(tlm::tlm_generic_payload& payload) override; - [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine& bankMachine) const override; - [[nodiscard]] bool hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command command) const override; + [[nodiscard]] tlm::tlm_generic_payload* + getNextRequest(const BankMachine& bankMachine) const override; + [[nodiscard]] bool + hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command command) const override; [[nodiscard]] bool hasFurtherRequest(Bank bank, tlm::tlm_command command) const override; [[nodiscard]] const std::vector& getBufferDepth() const override; diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerIF.h b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerIF.h index 0aed1e9e..207b03c5 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerIF.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerIF.h @@ -37,8 +37,8 @@ #include "DRAMSys/common/dramExtensions.h" -#include #include +#include namespace DRAMSys { @@ -48,10 +48,10 @@ class BankMachine; class SchedulerIF { protected: - SchedulerIF(const SchedulerIF &) = default; - SchedulerIF(SchedulerIF &&) = default; - SchedulerIF &operator=(const SchedulerIF &) = default; - SchedulerIF &operator=(SchedulerIF &&) = default; + SchedulerIF(const SchedulerIF&) = default; + SchedulerIF(SchedulerIF&&) = default; + SchedulerIF& operator=(const SchedulerIF&) = default; + SchedulerIF& operator=(SchedulerIF&&) = default; public: SchedulerIF() = default; @@ -60,8 +60,10 @@ public: [[nodiscard]] virtual bool hasBufferSpace() const = 0; virtual void storeRequest(tlm::tlm_generic_payload& payload) = 0; virtual void removeRequest(tlm::tlm_generic_payload& payload) = 0; - [[nodiscard]] virtual tlm::tlm_generic_payload* getNextRequest(const BankMachine& bankMachine) const = 0; - [[nodiscard]] virtual bool hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command command) const = 0; + [[nodiscard]] virtual tlm::tlm_generic_payload* + getNextRequest(const BankMachine& bankMachine) const = 0; + [[nodiscard]] virtual bool + hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command command) const = 0; [[nodiscard]] virtual bool hasFurtherRequest(Bank bank, tlm::tlm_command command) const = 0; [[nodiscard]] virtual const std::vector& getBufferDepth() const = 0; }; diff --git a/src/libdramsys/DRAMSys/simulation/AddressDecoder.cpp b/src/libdramsys/DRAMSys/simulation/AddressDecoder.cpp index 5e5b20d1..8e9ecfef 100644 --- a/src/libdramsys/DRAMSys/simulation/AddressDecoder.cpp +++ b/src/libdramsys/DRAMSys/simulation/AddressDecoder.cpp @@ -39,30 +39,32 @@ #include "AddressDecoder.h" #include "DRAMSys/configuration/Configuration.h" -#include -#include -#include #include +#include +#include +#include namespace DRAMSys { -AddressDecoder::AddressDecoder(const DRAMSys::Config::AddressMapping &addressMapping, const MemSpec &memSpec) +AddressDecoder::AddressDecoder(const DRAMSys::Config::AddressMapping& addressMapping, + const MemSpec& memSpec) { - if (const auto &channelBits = addressMapping.CHANNEL_BIT) + if (const auto& channelBits = addressMapping.CHANNEL_BIT) { std::copy(channelBits->begin(), channelBits->end(), std::back_inserter(vChannelBits)); } - if (const auto &rankBits = addressMapping.RANK_BIT) + if (const auto& rankBits = addressMapping.RANK_BIT) { std::copy(rankBits->begin(), rankBits->end(), std::back_inserter(vRankBits)); } // HBM pseudo channels are internally modelled as ranks - if (const auto &pseudoChannelBits = addressMapping.PSEUDOCHANNEL_BIT) + if (const auto& pseudoChannelBits = addressMapping.PSEUDOCHANNEL_BIT) { - std::copy(pseudoChannelBits->begin(), pseudoChannelBits->end(), std::back_inserter(vRankBits)); + std::copy( + pseudoChannelBits->begin(), pseudoChannelBits->end(), std::back_inserter(vRankBits)); } if (const auto& bankGroupBits = addressMapping.BANKGROUP_BIT) @@ -70,12 +72,12 @@ AddressDecoder::AddressDecoder(const DRAMSys::Config::AddressMapping &addressMap std::copy(bankGroupBits->begin(), bankGroupBits->end(), std::back_inserter(vBankGroupBits)); } - if (const auto &byteBits = addressMapping.BYTE_BIT) + if (const auto& byteBits = addressMapping.BYTE_BIT) { std::copy(byteBits->begin(), byteBits->end(), std::back_inserter(vByteBits)); } - if (const auto &xorBits = addressMapping.XOR) + if (const auto& xorBits = addressMapping.XOR) { for (const auto& xorBit : *xorBits) { @@ -83,17 +85,17 @@ AddressDecoder::AddressDecoder(const DRAMSys::Config::AddressMapping &addressMap } } - if (const auto &bankBits = addressMapping.BANK_BIT) + if (const auto& bankBits = addressMapping.BANK_BIT) { std::copy(bankBits->begin(), bankBits->end(), std::back_inserter(vBankBits)); } - if (const auto &rowBits = addressMapping.ROW_BIT) + if (const auto& rowBits = addressMapping.ROW_BIT) { std::copy(rowBits->begin(), rowBits->end(), std::back_inserter(vRowBits)); } - if (const auto &columnBits = addressMapping.COLUMN_BIT) + if (const auto& columnBits = addressMapping.COLUMN_BIT) { std::copy(columnBits->begin(), columnBits->end(), std::back_inserter(vColumnBits)); } @@ -106,20 +108,20 @@ AddressDecoder::AddressDecoder(const DRAMSys::Config::AddressMapping &addressMap unsigned columns = std::lround(std::pow(2.0, vColumnBits.size())); unsigned bytes = std::lround(std::pow(2.0, vByteBits.size())); - maximumAddress = static_cast(bytes) * columns * rows * banks - * bankGroups * ranks * channels - 1; + maximumAddress = + static_cast(bytes) * columns * rows * banks * bankGroups * ranks * channels - 1; auto totalAddressBits = static_cast(std::log2(maximumAddress)); for (unsigned bitPosition = 0; bitPosition < totalAddressBits; bitPosition++) { - if (std::count(vChannelBits.begin(), vChannelBits.end(), bitPosition) - + std::count(vRankBits.begin(), vRankBits.end(), bitPosition) - + std::count(vBankGroupBits.begin(), vBankGroupBits.end(), bitPosition) - + std::count(vBankBits.begin(), vBankBits.end(), bitPosition) - + std::count(vRowBits.begin(), vRowBits.end(), bitPosition) - + std::count(vColumnBits.begin(), vColumnBits.end(), bitPosition) - + std::count(vByteBits.begin(), vByteBits.end(), bitPosition) - != 1) + if (std::count(vChannelBits.begin(), vChannelBits.end(), bitPosition) + + std::count(vRankBits.begin(), vRankBits.end(), bitPosition) + + std::count(vBankGroupBits.begin(), vBankGroupBits.end(), bitPosition) + + std::count(vBankBits.begin(), vBankBits.end(), bitPosition) + + std::count(vRowBits.begin(), vRowBits.end(), bitPosition) + + std::count(vColumnBits.begin(), vColumnBits.end(), bitPosition) + + std::count(vByteBits.begin(), vByteBits.end(), bitPosition) != + 1) SC_REPORT_FATAL("AddressDecoder", "Not all address bits occur exactly once"); } @@ -133,7 +135,9 @@ AddressDecoder::AddressDecoder(const DRAMSys::Config::AddressMapping &addressMap auto maxBurstLengthBits = static_cast(std::log2(memSpec.maxBurstLength)); - for (unsigned bitPosition = highestByteBit + 1; bitPosition < highestByteBit + 1 + maxBurstLengthBits; bitPosition++) + for (unsigned bitPosition = highestByteBit + 1; + bitPosition < highestByteBit + 1 + maxBurstLengthBits; + bitPosition++) { if (std::find(vColumnBits.begin(), vColumnBits.end(), bitPosition) == vColumnBits.end()) SC_REPORT_FATAL("AddressDecoder", "No continuous column bits for maximum burst length"); @@ -145,24 +149,30 @@ AddressDecoder::AddressDecoder(const DRAMSys::Config::AddressMapping &addressMap banksPerGroup = banks; banks = banksPerGroup * bankGroups; - if (memSpec.numberOfChannels != channels || memSpec.ranksPerChannel != ranks - || memSpec.bankGroupsPerChannel != bankGroups || memSpec.banksPerChannel != banks - || memSpec.rowsPerBank != rows || memSpec.columnsPerRow != columns - || memSpec.devicesPerRank * memSpec.bitWidth != bytes * 8) + if (memSpec.numberOfChannels != channels || memSpec.ranksPerChannel != ranks || + memSpec.bankGroupsPerChannel != bankGroups || memSpec.banksPerChannel != banks || + memSpec.rowsPerBank != rows || memSpec.columnsPerRow != columns || + memSpec.devicesPerRank * memSpec.bitWidth != bytes * 8) SC_REPORT_FATAL("AddressDecoder", "Memspec and address mapping do not match"); } DecodedAddress AddressDecoder::decodeAddress(uint64_t encAddr) const { if (encAddr > maximumAddress) - SC_REPORT_WARNING("AddressDecoder", ("Address " + std::to_string(encAddr) + " out of range (maximum address is " + std::to_string(maximumAddress) + ")").c_str()); + SC_REPORT_WARNING("AddressDecoder", + ("Address " + std::to_string(encAddr) + + " out of range (maximum address is " + std::to_string(maximumAddress) + + ")") + .c_str()); // Apply XOR // For each used xor: - // Get the first bit and second bit. Apply a bitwise xor operator and save it back to the first bit. - for (const auto &it : vXor) + // Get the first bit and second bit. Apply a bitwise xor operator and save it back to the + // first bit. + for (const auto& it : vXor) { - uint64_t xoredBit = (((encAddr >> it.first) & UINT64_C(1)) ^ ((encAddr >> it.second) & UINT64_C(1))); + uint64_t xoredBit = + (((encAddr >> it.first) & UINT64_C(1)) ^ ((encAddr >> it.second) & UINT64_C(1))); encAddr &= ~(UINT64_C(1) << it.first); encAddr |= xoredBit << it.first; } @@ -199,14 +209,20 @@ DecodedAddress AddressDecoder::decodeAddress(uint64_t encAddr) const unsigned AddressDecoder::decodeChannel(uint64_t encAddr) const { if (encAddr > maximumAddress) - SC_REPORT_WARNING("AddressDecoder", ("Address " + std::to_string(encAddr) + " out of range (maximum address is " + std::to_string(maximumAddress) + ")").c_str()); + SC_REPORT_WARNING("AddressDecoder", + ("Address " + std::to_string(encAddr) + + " out of range (maximum address is " + std::to_string(maximumAddress) + + ")") + .c_str()); // Apply XOR // For each used xor: - // Get the first bit and second bit. Apply a bitwise xor operator and save it back to the first bit. - for (const auto &it : vXor) + // Get the first bit and second bit. Apply a bitwise xor operator and save it back to the + // first bit. + for (const auto& it : vXor) { - uint64_t xoredBit = (((encAddr >> it.first) & UINT64_C(1)) ^ ((encAddr >> it.second) & UINT64_C(1))); + uint64_t xoredBit = + (((encAddr >> it.first) & UINT64_C(1)) ^ ((encAddr >> it.second) & UINT64_C(1))); encAddr &= ~(UINT64_C(1) << it.first); encAddr |= xoredBit << it.first; } @@ -253,7 +269,6 @@ uint64_t AddressDecoder::encodeAddress(DecodedAddress decodedAddress) const return address; } - void AddressDecoder::print() const { std::cout << headline << std::endl; @@ -262,79 +277,93 @@ void AddressDecoder::print() const for (int it = static_cast(vChannelBits.size() - 1); it >= 0; it--) { - uint64_t addressBits = (UINT64_C(1) << vChannelBits[static_cast::size_type>(it)]); + uint64_t addressBits = + (UINT64_C(1) << vChannelBits[static_cast::size_type>(it)]); for (auto it2 : vXor) { if (it2.first == vChannelBits[static_cast::size_type>(it)]) addressBits |= (UINT64_C(1) << it2.second); } - std::cout << " Ch " << std::setw(2) << it << ": " << std::bitset<64>(addressBits) << std::endl; + std::cout << " Ch " << std::setw(2) << it << ": " << std::bitset<64>(addressBits) + << std::endl; } for (int it = static_cast(vRankBits.size() - 1); it >= 0; it--) { - uint64_t addressBits = (UINT64_C(1) << vRankBits[static_cast::size_type>(it)]); + uint64_t addressBits = + (UINT64_C(1) << vRankBits[static_cast::size_type>(it)]); for (auto it2 : vXor) { if (it2.first == vRankBits[static_cast::size_type>(it)]) addressBits |= (UINT64_C(1) << it2.second); } - std::cout << " Ra " << std::setw(2) << it << ": " << std::bitset<64>(addressBits) << std::endl; + std::cout << " Ra " << std::setw(2) << it << ": " << std::bitset<64>(addressBits) + << std::endl; } for (int it = static_cast(vBankGroupBits.size() - 1); it >= 0; it--) { - uint64_t addressBits = (UINT64_C(1) << vBankGroupBits[static_cast::size_type>(it)]); + uint64_t addressBits = + (UINT64_C(1) << vBankGroupBits[static_cast::size_type>(it)]); for (auto it2 : vXor) { if (it2.first == vBankGroupBits[static_cast::size_type>(it)]) addressBits |= (UINT64_C(1) << it2.second); } - std::cout << " Bg " << std::setw(2) << it << ": " << std::bitset<64>(addressBits) << std::endl; + std::cout << " Bg " << std::setw(2) << it << ": " << std::bitset<64>(addressBits) + << std::endl; } for (int it = static_cast(vBankBits.size() - 1); it >= 0; it--) { - uint64_t addressBits = (UINT64_C(1) << vBankBits[static_cast::size_type>(it)]); + uint64_t addressBits = + (UINT64_C(1) << vBankBits[static_cast::size_type>(it)]); for (auto it2 : vXor) { if (it2.first == vBankBits[static_cast::size_type>(it)]) addressBits |= (UINT64_C(1) << it2.second); } - std::cout << " Ba " << std::setw(2) << it << ": " << std::bitset<64>(addressBits) << std::endl; + std::cout << " Ba " << std::setw(2) << it << ": " << std::bitset<64>(addressBits) + << std::endl; } for (int it = static_cast(vRowBits.size() - 1); it >= 0; it--) { - uint64_t addressBits = (UINT64_C(1) << vRowBits[static_cast::size_type>(it)]); + uint64_t addressBits = + (UINT64_C(1) << vRowBits[static_cast::size_type>(it)]); for (auto it2 : vXor) { if (it2.first == vRowBits[static_cast::size_type>(it)]) addressBits |= (UINT64_C(1) << it2.second); } - std::cout << " Ro " << std::setw(2) << it << ": " << std::bitset<64>(addressBits) << std::endl; + std::cout << " Ro " << std::setw(2) << it << ": " << std::bitset<64>(addressBits) + << std::endl; } for (int it = static_cast(vColumnBits.size() - 1); it >= 0; it--) { - uint64_t addressBits = (UINT64_C(1) << vColumnBits[static_cast::size_type>(it)]); + uint64_t addressBits = + (UINT64_C(1) << vColumnBits[static_cast::size_type>(it)]); for (auto it2 : vXor) { if (it2.first == vColumnBits[static_cast::size_type>(it)]) addressBits |= (UINT64_C(1) << it2.second); } - std::cout << " Co " << std::setw(2) << it << ": " << std::bitset<64>(addressBits) << std::endl; + std::cout << " Co " << std::setw(2) << it << ": " << std::bitset<64>(addressBits) + << std::endl; } for (int it = static_cast(vByteBits.size() - 1); it >= 0; it--) { - uint64_t addressBits = (UINT64_C(1) << vByteBits[static_cast::size_type>(it)]); + uint64_t addressBits = + (UINT64_C(1) << vByteBits[static_cast::size_type>(it)]); for (auto it2 : vXor) { if (it2.first == vByteBits[static_cast::size_type>(it)]) addressBits |= (UINT64_C(1) << it2.second); } - std::cout << " By " << std::setw(2) << it << ": " << std::bitset<64>(addressBits) << std::endl; + std::cout << " By " << std::setw(2) << it << ": " << std::bitset<64>(addressBits) + << std::endl; } std::cout << std::endl; diff --git a/src/libdramsys/DRAMSys/simulation/AddressDecoder.h b/src/libdramsys/DRAMSys/simulation/AddressDecoder.h index 5e1f6d27..4cb01668 100644 --- a/src/libdramsys/DRAMSys/simulation/AddressDecoder.h +++ b/src/libdramsys/DRAMSys/simulation/AddressDecoder.h @@ -42,20 +42,30 @@ #include "DRAMSys/config/DRAMSysConfiguration.h" #include "DRAMSys/configuration/Configuration.h" -#include #include +#include namespace DRAMSys { struct DecodedAddress { - DecodedAddress(unsigned channel, unsigned rank, - unsigned bankgroup, unsigned bank, - unsigned row, unsigned column, unsigned bytes) - : channel(channel), rank(rank), - bankgroup(bankgroup), bank(bank), - row(row), column(column), byte(bytes) {} + DecodedAddress(unsigned channel, + unsigned rank, + unsigned bankgroup, + unsigned bank, + unsigned row, + unsigned column, + unsigned bytes) : + channel(channel), + rank(rank), + bankgroup(bankgroup), + bank(bank), + row(row), + column(column), + byte(bytes) + { + } DecodedAddress() = default; @@ -71,7 +81,7 @@ struct DecodedAddress class AddressDecoder { public: - AddressDecoder(const DRAMSys::Config::AddressMapping &addressMapping, const MemSpec &memSpec); + AddressDecoder(const DRAMSys::Config::AddressMapping& addressMapping, const MemSpec& memSpec); [[nodiscard]] DecodedAddress decodeAddress(uint64_t encAddr) const; [[nodiscard]] unsigned decodeChannel(uint64_t encAddr) const; [[nodiscard]] uint64_t encodeAddress(DecodedAddress decodedAddress) const; @@ -83,7 +93,8 @@ private: uint64_t maximumAddress; - // This container stores for each used xor gate a pair of address bits, the first bit is overwritten with the result + // This container stores for each used xor gate a pair of address bits, the first bit is + // overwritten with the result std::vector> vXor; std::vector vChannelBits; std::vector vRankBits; diff --git a/src/libdramsys/DRAMSys/simulation/Arbiter.cpp b/src/libdramsys/DRAMSys/simulation/Arbiter.cpp index 41662b4b..a5349142 100644 --- a/src/libdramsys/DRAMSys/simulation/Arbiter.cpp +++ b/src/libdramsys/DRAMSys/simulation/Arbiter.cpp @@ -39,9 +39,9 @@ #include "Arbiter.h" -#include "DRAMSys/simulation/AddressDecoder.h" -#include "DRAMSys/configuration/Configuration.h" #include "DRAMSys/common/DebugManager.h" +#include "DRAMSys/configuration/Configuration.h" +#include "DRAMSys/simulation/AddressDecoder.h" #include "DRAMSys/config/DRAMSysConfiguration.h" @@ -51,9 +51,12 @@ using namespace tlm; namespace DRAMSys { -Arbiter::Arbiter(const sc_module_name& name, const Configuration& config, +Arbiter::Arbiter(const sc_module_name& name, + const Configuration& config, const AddressDecoder& addressDecoder) : - sc_module(name), addressDecoder(addressDecoder), payloadEventQueue(this, &Arbiter::peqCallback), + sc_module(name), + addressDecoder(addressDecoder), + payloadEventQueue(this, &Arbiter::peqCallback), tCK(config.memSpec->tCK), arbitrationDelayFw(config.arbitrationDelayFw), arbitrationDelayBw(config.arbitrationDelayBw), @@ -66,19 +69,28 @@ Arbiter::Arbiter(const sc_module_name& name, const Configuration& config, tSocket.register_transport_dbg(this, &Arbiter::transport_dbg); } -ArbiterSimple::ArbiterSimple(const sc_module_name& name, const Configuration& config, +ArbiterSimple::ArbiterSimple(const sc_module_name& name, + const Configuration& config, const AddressDecoder& addressDecoder) : - Arbiter(name, config, addressDecoder) {} + Arbiter(name, config, addressDecoder) +{ +} -ArbiterFifo::ArbiterFifo(const sc_module_name& name, const Configuration& config, +ArbiterFifo::ArbiterFifo(const sc_module_name& name, + const Configuration& config, const AddressDecoder& addressDecoder) : - Arbiter(name, config, addressDecoder), - maxActiveTransactionsPerThread(config.maxActiveTransactions) {} + Arbiter(name, config, addressDecoder), + maxActiveTransactionsPerThread(config.maxActiveTransactions) +{ +} -ArbiterReorder::ArbiterReorder(const sc_module_name& name, const Configuration& config, +ArbiterReorder::ArbiterReorder(const sc_module_name& name, + const Configuration& config, const AddressDecoder& addressDecoder) : Arbiter(name, config, addressDecoder), - maxActiveTransactions(config.maxActiveTransactions) {} + maxActiveTransactions(config.maxActiveTransactions) +{ +} void Arbiter::end_of_elaboration() { @@ -89,7 +101,7 @@ void Arbiter::end_of_elaboration() // channel side channelIsBusy = ControllerVector(iSocket.size(), false); pendingRequestsOnChannel = ControllerVector>( - iSocket.size(), std::queue()); + iSocket.size(), std::queue()); nextChannelPayloadIDToAppend = ControllerVector(iSocket.size(), 1); } @@ -99,7 +111,7 @@ void ArbiterSimple::end_of_elaboration() // initiator side pendingResponsesOnThread = ControllerVector>( - tSocket.size(), std::queue()); + tSocket.size(), std::queue()); } void ArbiterFifo::end_of_elaboration() @@ -108,9 +120,10 @@ void ArbiterFifo::end_of_elaboration() // initiator side activeTransactionsOnThread = ControllerVector(tSocket.size(), 0); - outstandingEndReqOnThread = ControllerVector(tSocket.size(), nullptr); + outstandingEndReqOnThread = + ControllerVector(tSocket.size(), nullptr); pendingResponsesOnThread = ControllerVector>( - tSocket.size(), std::queue()); + tSocket.size(), std::queue()); lastEndReqOnChannel = ControllerVector(iSocket.size(), sc_max_time()); lastEndRespOnThread = ControllerVector(tSocket.size(), sc_max_time()); @@ -122,17 +135,19 @@ void ArbiterReorder::end_of_elaboration() // initiator side activeTransactionsOnThread = ControllerVector(tSocket.size(), 0); - outstandingEndReqOnThread = ControllerVector(tSocket.size(), nullptr); - pendingResponsesOnThread = ControllerVector> - (tSocket.size(), std::set()); + outstandingEndReqOnThread = + ControllerVector(tSocket.size(), nullptr); + pendingResponsesOnThread = + ControllerVector>( + tSocket.size(), std::set()); nextThreadPayloadIDToReturn = ControllerVector(tSocket.size(), 1); lastEndReqOnChannel = ControllerVector(iSocket.size(), sc_max_time()); lastEndRespOnThread = ControllerVector(tSocket.size(), sc_max_time()); } -tlm_sync_enum Arbiter::nb_transport_fw(int id, tlm_generic_payload& trans, - tlm_phase& phase, sc_time& fwDelay) +tlm_sync_enum +Arbiter::nb_transport_fw(int id, tlm_generic_payload& trans, tlm_phase& phase, sc_time& fwDelay) { sc_time clockOffset = sc_time::from_value((sc_time_stamp() + fwDelay).value() % tCK.value()); sc_time notDelay = (clockOffset == SC_ZERO_TIME) ? fwDelay : (fwDelay + tCK - clockOffset); @@ -145,27 +160,32 @@ tlm_sync_enum Arbiter::nb_transport_fw(int id, tlm_generic_payload& trans, trans.set_address(adjustedAddress); unsigned channel = addressDecoder.decodeChannel(adjustedAddress); - assert(addressDecoder.decodeChannel(adjustedAddress + trans.get_data_length() - 1) == channel); + assert(addressDecoder.decodeChannel(adjustedAddress + trans.get_data_length() - 1) == + channel); ArbiterExtension::setAutoExtension(trans, Thread(id), Channel(channel)); trans.acquire(); } - PRINTDEBUGMESSAGE(name(), "[fw] " + getPhaseName(phase) + " notification in " + - notDelay.to_string()); + PRINTDEBUGMESSAGE(name(), + "[fw] " + getPhaseName(phase) + " notification in " + notDelay.to_string()); payloadEventQueue.notify(trans, phase, notDelay); return TLM_ACCEPTED; } -tlm_sync_enum Arbiter::nb_transport_bw([[maybe_unused]] int id, tlm_generic_payload& payload, - tlm_phase& phase, sc_time& bwDelay) +tlm_sync_enum Arbiter::nb_transport_bw([[maybe_unused]] int id, + tlm_generic_payload& payload, + tlm_phase& phase, + sc_time& bwDelay) { - PRINTDEBUGMESSAGE(name(), "[bw] " + getPhaseName(phase) + " notification in " + - bwDelay.to_string()); + PRINTDEBUGMESSAGE(name(), + "[bw] " + getPhaseName(phase) + " notification in " + bwDelay.to_string()); payloadEventQueue.notify(payload, phase, bwDelay); return TLM_ACCEPTED; } -void Arbiter::b_transport([[maybe_unused]] int id, tlm::tlm_generic_payload& trans, sc_core::sc_time& delay) +void Arbiter::b_transport([[maybe_unused]] int id, + tlm::tlm_generic_payload& trans, + sc_core::sc_time& delay) { trans.set_address(trans.get_address() - addressOffset); @@ -188,7 +208,8 @@ void ArbiterSimple::peqCallback(tlm_generic_payload& cbTrans, const tlm_phase& c if (cbPhase == BEGIN_REQ) // from initiator { - ArbiterExtension::setIDAndTimeOfGeneration(cbTrans, nextThreadPayloadIDToAppend[thread]++, sc_time_stamp()); + ArbiterExtension::setIDAndTimeOfGeneration( + cbTrans, nextThreadPayloadIDToAppend[thread]++, sc_time_stamp()); if (!channelIsBusy[channel]) { @@ -213,7 +234,7 @@ void ArbiterSimple::peqCallback(tlm_generic_payload& cbTrans, const tlm_phase& c if (!pendingRequestsOnChannel[channel].empty()) { - tlm_generic_payload &tPayload = *pendingRequestsOnChannel[channel].front(); + tlm_generic_payload& tPayload = *pendingRequestsOnChannel[channel].front(); pendingRequestsOnChannel[channel].pop(); tlm_phase tPhase = BEGIN_REQ; // do not send two requests in the same cycle @@ -231,7 +252,8 @@ void ArbiterSimple::peqCallback(tlm_generic_payload& cbTrans, const tlm_phase& c tlm_phase tPhase = BEGIN_RESP; sc_time tDelay = arbitrationDelayBw; - tlm_sync_enum returnValue = tSocket[static_cast(thread)]->nb_transport_bw(cbTrans, tPhase, tDelay); + tlm_sync_enum returnValue = + tSocket[static_cast(thread)]->nb_transport_bw(cbTrans, tPhase, tDelay); // Early completion from initiator if (returnValue == TLM_UPDATED) payloadEventQueue.notify(cbTrans, tPhase, tDelay); @@ -252,13 +274,14 @@ void ArbiterSimple::peqCallback(tlm_generic_payload& cbTrans, const tlm_phase& c if (!pendingResponsesOnThread[thread].empty()) { - tlm_generic_payload &tPayload = *pendingResponsesOnThread[thread].front(); + tlm_generic_payload& tPayload = *pendingResponsesOnThread[thread].front(); pendingResponsesOnThread[thread].pop(); tlm_phase tPhase = BEGIN_RESP; // do not send two responses in the same cycle sc_time tDelay = tCK + arbitrationDelayBw; - tlm_sync_enum returnValue = tSocket[static_cast(thread)]->nb_transport_bw(tPayload, tPhase, tDelay); + tlm_sync_enum returnValue = + tSocket[static_cast(thread)]->nb_transport_bw(tPayload, tPhase, tDelay); // Early completion from initiator if (returnValue == TLM_UPDATED) payloadEventQueue.notify(tPayload, tPhase, tDelay); @@ -281,8 +304,8 @@ void ArbiterFifo::peqCallback(tlm_generic_payload& cbTrans, const tlm_phase& cbP { activeTransactionsOnThread[thread]++; - ArbiterExtension::setIDAndTimeOfGeneration(cbTrans, nextThreadPayloadIDToAppend[thread]++, - sc_time_stamp()); + ArbiterExtension::setIDAndTimeOfGeneration( + cbTrans, nextThreadPayloadIDToAppend[thread]++, sc_time_stamp()); tlm_phase tPhase = END_REQ; sc_time tDelay = SC_ZERO_TIME; @@ -300,7 +323,7 @@ void ArbiterFifo::peqCallback(tlm_generic_payload& cbTrans, const tlm_phase& cbP if (!pendingRequestsOnChannel[channel].empty()) { - tlm_generic_payload &tPayload = *pendingRequestsOnChannel[channel].front(); + tlm_generic_payload& tPayload = *pendingRequestsOnChannel[channel].front(); pendingRequestsOnChannel[channel].pop(); tlm_phase tPhase = BEGIN_REQ; sc_time tDelay = tCK; @@ -309,7 +332,7 @@ void ArbiterFifo::peqCallback(tlm_generic_payload& cbTrans, const tlm_phase& cbP } else channelIsBusy[channel] = false; - } + } else if (cbPhase == BEGIN_RESP) // from memory controller { // TODO: use early completion @@ -329,13 +352,13 @@ void ArbiterFifo::peqCallback(tlm_generic_payload& cbTrans, const tlm_phase& cbP if (outstandingEndReqOnThread[thread] != nullptr) { - tlm_generic_payload &tPayload = *outstandingEndReqOnThread[thread]; + tlm_generic_payload& tPayload = *outstandingEndReqOnThread[thread]; outstandingEndReqOnThread[thread] = nullptr; tlm_phase tPhase = END_REQ; sc_time tDelay = SC_ZERO_TIME; - ArbiterExtension::setIDAndTimeOfGeneration(tPayload, nextThreadPayloadIDToAppend[thread]++, - sc_time_stamp()); + ArbiterExtension::setIDAndTimeOfGeneration( + tPayload, nextThreadPayloadIDToAppend[thread]++, sc_time_stamp()); tSocket[static_cast(thread)]->nb_transport_bw(tPayload, tPhase, tDelay); @@ -346,12 +369,13 @@ void ArbiterFifo::peqCallback(tlm_generic_payload& cbTrans, const tlm_phase& cbP if (!pendingResponsesOnThread[thread].empty()) { - tlm_generic_payload &tPayload = *pendingResponsesOnThread[thread].front(); + tlm_generic_payload& tPayload = *pendingResponsesOnThread[thread].front(); pendingResponsesOnThread[thread].pop(); tlm_phase tPhase = BEGIN_RESP; sc_time tDelay = tCK; - tlm_sync_enum returnValue = tSocket[static_cast(thread)]->nb_transport_bw(tPayload, tPhase, tDelay); + tlm_sync_enum returnValue = + tSocket[static_cast(thread)]->nb_transport_bw(tPayload, tPhase, tDelay); // Early completion from initiator if (returnValue == TLM_UPDATED) payloadEventQueue.notify(tPayload, tPhase, tDelay); @@ -367,7 +391,7 @@ void ArbiterFifo::peqCallback(tlm_generic_payload& cbTrans, const tlm_phase& cbP { channelIsBusy[channel] = true; - tlm_generic_payload &tPayload = *pendingRequestsOnChannel[channel].front(); + tlm_generic_payload& tPayload = *pendingRequestsOnChannel[channel].front(); pendingRequestsOnChannel[channel].pop(); tlm_phase tPhase = BEGIN_REQ; sc_time tDelay = lastEndReqOnChannel[channel] == sc_time_stamp() ? tCK : SC_ZERO_TIME; @@ -383,12 +407,13 @@ void ArbiterFifo::peqCallback(tlm_generic_payload& cbTrans, const tlm_phase& cbP { threadIsBusy[thread] = true; - tlm_generic_payload &tPayload = *pendingResponsesOnThread[thread].front(); + tlm_generic_payload& tPayload = *pendingResponsesOnThread[thread].front(); pendingResponsesOnThread[thread].pop(); tlm_phase tPhase = BEGIN_RESP; sc_time tDelay = lastEndRespOnThread[thread] == sc_time_stamp() ? tCK : SC_ZERO_TIME; - tlm_sync_enum returnValue = tSocket[static_cast(thread)]->nb_transport_bw(tPayload, tPhase, tDelay); + tlm_sync_enum returnValue = + tSocket[static_cast(thread)]->nb_transport_bw(tPayload, tPhase, tDelay); // Early completion from initiator if (returnValue == TLM_UPDATED) payloadEventQueue.notify(tPayload, tPhase, tDelay); @@ -409,8 +434,8 @@ void ArbiterReorder::peqCallback(tlm_generic_payload& cbTrans, const tlm_phase& { activeTransactionsOnThread[thread]++; - ArbiterExtension::setIDAndTimeOfGeneration(cbTrans, nextThreadPayloadIDToAppend[thread]++, - sc_time_stamp()); + ArbiterExtension::setIDAndTimeOfGeneration( + cbTrans, nextThreadPayloadIDToAppend[thread]++, sc_time_stamp()); tlm_phase tPhase = END_REQ; sc_time tDelay = SC_ZERO_TIME; @@ -428,7 +453,7 @@ void ArbiterReorder::peqCallback(tlm_generic_payload& cbTrans, const tlm_phase& if (!pendingRequestsOnChannel[channel].empty()) { - tlm_generic_payload &tPayload = *pendingRequestsOnChannel[channel].front(); + tlm_generic_payload& tPayload = *pendingRequestsOnChannel[channel].front(); pendingRequestsOnChannel[channel].pop(); tlm_phase tPhase = BEGIN_REQ; sc_time tDelay = tCK; @@ -456,13 +481,13 @@ void ArbiterReorder::peqCallback(tlm_generic_payload& cbTrans, const tlm_phase& if (outstandingEndReqOnThread[thread] != nullptr) { - tlm_generic_payload &tPayload = *outstandingEndReqOnThread[thread]; + tlm_generic_payload& tPayload = *outstandingEndReqOnThread[thread]; outstandingEndReqOnThread[thread] = nullptr; tlm_phase tPhase = END_REQ; sc_time tDelay = SC_ZERO_TIME; - ArbiterExtension::setIDAndTimeOfGeneration(tPayload, nextThreadPayloadIDToAppend[thread]++, - sc_time_stamp()); + ArbiterExtension::setIDAndTimeOfGeneration( + tPayload, nextThreadPayloadIDToAppend[thread]++, sc_time_stamp()); tSocket[static_cast(thread)]->nb_transport_bw(tPayload, tPhase, tDelay); @@ -471,10 +496,10 @@ void ArbiterReorder::peqCallback(tlm_generic_payload& cbTrans, const tlm_phase& else activeTransactionsOnThread[thread]--; - tlm_generic_payload &tPayload = **pendingResponsesOnThread[thread].begin(); + tlm_generic_payload& tPayload = **pendingResponsesOnThread[thread].begin(); if (!pendingResponsesOnThread[thread].empty() && - ArbiterExtension::getThreadPayloadID(tPayload) == nextThreadPayloadIDToReturn[thread]) + ArbiterExtension::getThreadPayloadID(tPayload) == nextThreadPayloadIDToReturn[thread]) { nextThreadPayloadIDToReturn[thread]++; pendingResponsesOnThread[thread].erase(pendingResponsesOnThread[thread].begin()); @@ -482,7 +507,8 @@ void ArbiterReorder::peqCallback(tlm_generic_payload& cbTrans, const tlm_phase& tlm_phase tPhase = BEGIN_RESP; sc_time tDelay = tCK; - tlm_sync_enum returnValue = tSocket[static_cast(thread)]->nb_transport_bw(tPayload, tPhase, tDelay); + tlm_sync_enum returnValue = + tSocket[static_cast(thread)]->nb_transport_bw(tPayload, tPhase, tDelay); // Early completion from initiator if (returnValue == TLM_UPDATED) payloadEventQueue.notify(tPayload, tPhase, tDelay); @@ -498,7 +524,7 @@ void ArbiterReorder::peqCallback(tlm_generic_payload& cbTrans, const tlm_phase& { channelIsBusy[channel] = true; - tlm_generic_payload &tPayload = *pendingRequestsOnChannel[channel].front(); + tlm_generic_payload& tPayload = *pendingRequestsOnChannel[channel].front(); pendingRequestsOnChannel[channel].pop(); tlm_phase tPhase = BEGIN_REQ; sc_time tDelay = lastEndReqOnChannel[channel] == sc_time_stamp() ? tCK : SC_ZERO_TIME; @@ -512,18 +538,21 @@ void ArbiterReorder::peqCallback(tlm_generic_payload& cbTrans, const tlm_phase& if (!threadIsBusy[thread]) { - tlm_generic_payload &tPayload = **pendingResponsesOnThread[thread].begin(); + tlm_generic_payload& tPayload = **pendingResponsesOnThread[thread].begin(); - if (ArbiterExtension::getThreadPayloadID(tPayload) == nextThreadPayloadIDToReturn[thread]) + if (ArbiterExtension::getThreadPayloadID(tPayload) == + nextThreadPayloadIDToReturn[thread]) { threadIsBusy[thread] = true; nextThreadPayloadIDToReturn[thread]++; pendingResponsesOnThread[thread].erase(pendingResponsesOnThread[thread].begin()); tlm_phase tPhase = BEGIN_RESP; - sc_time tDelay = lastEndRespOnThread[thread] == sc_time_stamp() ? tCK : SC_ZERO_TIME; + sc_time tDelay = + lastEndRespOnThread[thread] == sc_time_stamp() ? tCK : SC_ZERO_TIME; - tlm_sync_enum returnValue = tSocket[static_cast(thread)]->nb_transport_bw(tPayload, tPhase, tDelay); + tlm_sync_enum returnValue = + tSocket[static_cast(thread)]->nb_transport_bw(tPayload, tPhase, tDelay); // Early completion from initiator if (returnValue == TLM_UPDATED) payloadEventQueue.notify(tPayload, tPhase, tDelay); diff --git a/src/libdramsys/DRAMSys/simulation/Arbiter.h b/src/libdramsys/DRAMSys/simulation/Arbiter.h index 442cb55d..d40a7056 100644 --- a/src/libdramsys/DRAMSys/simulation/Arbiter.h +++ b/src/libdramsys/DRAMSys/simulation/Arbiter.h @@ -40,18 +40,18 @@ #ifndef ARBITER_H #define ARBITER_H -#include "DRAMSys/simulation/AddressDecoder.h" #include "DRAMSys/common/dramExtensions.h" +#include "DRAMSys/simulation/AddressDecoder.h" #include -#include #include #include #include #include -#include #include +#include #include +#include namespace DRAMSys { @@ -66,7 +66,8 @@ public: tlm_utils::multi_passthrough_target_socket tSocket; protected: - Arbiter(const sc_core::sc_module_name& name, const Configuration& config, + Arbiter(const sc_core::sc_module_name& name, + const Configuration& config, const AddressDecoder& addressDecoder); SC_HAS_PROCESS(Arbiter); @@ -85,10 +86,14 @@ protected: ControllerVector nextThreadPayloadIDToAppend; ControllerVector nextChannelPayloadIDToAppend; - tlm::tlm_sync_enum nb_transport_fw(int id, tlm::tlm_generic_payload& trans, - tlm::tlm_phase& phase, sc_core::sc_time& fwDelay); - tlm::tlm_sync_enum nb_transport_bw(int id, tlm::tlm_generic_payload &payload, - tlm::tlm_phase &phase, sc_core::sc_time &bwDelay); + tlm::tlm_sync_enum nb_transport_fw(int id, + tlm::tlm_generic_payload& trans, + tlm::tlm_phase& phase, + sc_core::sc_time& fwDelay); + tlm::tlm_sync_enum nb_transport_bw(int id, + tlm::tlm_generic_payload& payload, + tlm::tlm_phase& phase, + sc_core::sc_time& bwDelay); void b_transport(int id, tlm::tlm_generic_payload& trans, sc_core::sc_time& delay); unsigned int transport_dbg(int id, tlm::tlm_generic_payload& trans); @@ -103,7 +108,8 @@ protected: class ArbiterSimple final : public Arbiter { public: - ArbiterSimple(const sc_core::sc_module_name& name, const Configuration& config, + ArbiterSimple(const sc_core::sc_module_name& name, + const Configuration& config, const AddressDecoder& addressDecoder); SC_HAS_PROCESS(ArbiterSimple); @@ -117,7 +123,8 @@ private: class ArbiterFifo final : public Arbiter { public: - ArbiterFifo(const sc_core::sc_module_name& name, const Configuration& config, + ArbiterFifo(const sc_core::sc_module_name& name, + const Configuration& config, const AddressDecoder& addressDecoder); SC_HAS_PROCESS(ArbiterFifo); @@ -138,7 +145,8 @@ private: class ArbiterReorder final : public Arbiter { public: - ArbiterReorder(const sc_core::sc_module_name& name, const Configuration& config, + ArbiterReorder(const sc_core::sc_module_name& name, + const Configuration& config, const AddressDecoder& addressDecoder); SC_HAS_PROCESS(ArbiterReorder); @@ -151,14 +159,17 @@ private: struct ThreadPayloadIDCompare { - bool operator() (const tlm::tlm_generic_payload* lhs, const tlm::tlm_generic_payload* rhs) const + bool operator()(const tlm::tlm_generic_payload* lhs, + const tlm::tlm_generic_payload* rhs) const { - return ArbiterExtension::getThreadPayloadID(*lhs) < ArbiterExtension::getThreadPayloadID(*rhs); + return ArbiterExtension::getThreadPayloadID(*lhs) < + ArbiterExtension::getThreadPayloadID(*rhs); } }; ControllerVector outstandingEndReqOnThread; - ControllerVector> pendingResponsesOnThread; + ControllerVector> + pendingResponsesOnThread; ControllerVector lastEndReqOnChannel; ControllerVector lastEndRespOnThread; diff --git a/src/libdramsys/DRAMSys/simulation/DRAMSys.cpp b/src/libdramsys/DRAMSys/simulation/DRAMSys.cpp index 0cd725ad..98490e6b 100644 --- a/src/libdramsys/DRAMSys/simulation/DRAMSys.cpp +++ b/src/libdramsys/DRAMSys/simulation/DRAMSys.cpp @@ -45,14 +45,14 @@ #include "DRAMSys/controller/Controller.h" #include "DRAMSys/simulation/dram/DramDDR3.h" #include "DRAMSys/simulation/dram/DramDDR4.h" -#include "DRAMSys/simulation/dram/DramWideIO.h" -#include "DRAMSys/simulation/dram/DramLPDDR4.h" -#include "DRAMSys/simulation/dram/DramWideIO2.h" -#include "DRAMSys/simulation/dram/DramHBM2.h" #include "DRAMSys/simulation/dram/DramGDDR5.h" #include "DRAMSys/simulation/dram/DramGDDR5X.h" #include "DRAMSys/simulation/dram/DramGDDR6.h" +#include "DRAMSys/simulation/dram/DramHBM2.h" +#include "DRAMSys/simulation/dram/DramLPDDR4.h" #include "DRAMSys/simulation/dram/DramSTTMRAM.h" +#include "DRAMSys/simulation/dram/DramWideIO.h" +#include "DRAMSys/simulation/dram/DramWideIO2.h" #ifdef DDR5_SIM #include "DRAMSys/simulation/dram/DramDDR5.h" @@ -67,21 +67,23 @@ #include #include #include -#include #include +#include namespace DRAMSys { DRAMSys::DRAMSys(const sc_core::sc_module_name& name, - const ::DRAMSys::Config::Configuration& configLib) - : DRAMSys(name, configLib, true) -{} + const ::DRAMSys::Config::Configuration& configLib) : + DRAMSys(name, configLib, true) +{ +} DRAMSys::DRAMSys(const sc_core::sc_module_name& name, const ::DRAMSys::Config::Configuration& configLib, - bool initAndBind) - : sc_module(name), tSocket("DRAMSys_tSocket") + bool initAndBind) : + sc_module(name), + tSocket("DRAMSys_tSocket") { logo(); @@ -120,21 +122,17 @@ void DRAMSys::end_of_simulation() void DRAMSys::logo() { -#define GREENTXT(s) std::string(("\u001b[38;5;28m"+std::string((s))+"\033[0m")) -#define DGREENTXT(s) std::string(("\u001b[38;5;22m"+std::string((s))+"\033[0m")) -#define LGREENTXT(s) std::string(("\u001b[38;5;82m"+std::string((s))+"\033[0m")) -#define BLACKTXT(s) std::string(("\u001b[38;5;232m"+std::string((s))+"\033[0m")) -#define BOLDTXT(s) std::string(("\033[1;37m"+std::string((s))+"\033[0m")) +#define GREENTXT(s) std::string(("\u001b[38;5;28m" + std::string((s)) + "\033[0m")) +#define DGREENTXT(s) std::string(("\u001b[38;5;22m" + std::string((s)) + "\033[0m")) +#define LGREENTXT(s) std::string(("\u001b[38;5;82m" + std::string((s)) + "\033[0m")) +#define BLACKTXT(s) std::string(("\u001b[38;5;232m" + std::string((s)) + "\033[0m")) +#define BOLDTXT(s) std::string(("\033[1;37m" + std::string((s)) + "\033[0m")) cout << std::endl - << BLACKTXT("■ ■ ")<< DGREENTXT("■ ") - << BOLDTXT("DRAMSys5.0, Copyright (c) 2023") + << BLACKTXT("■ ■ ") << DGREENTXT("■ ") << BOLDTXT("DRAMSys5.0, Copyright (c) 2023") << std::endl - << BLACKTXT("■ ") << DGREENTXT("■ ") << GREENTXT("■ ") - << "RPTU Kaiserslautern-Landau," - << std::endl - << DGREENTXT("■ ") << GREENTXT("■ ") << LGREENTXT("■ " ) - << "Fraunhofer IESE" + << BLACKTXT("■ ") << DGREENTXT("■ ") << GREENTXT("■ ") << "RPTU Kaiserslautern-Landau," << std::endl + << DGREENTXT("■ ") << GREENTXT("■ ") << LGREENTXT("■ ") << "Fraunhofer IESE" << std::endl << std::endl; #undef GREENTXT #undef DGREENTXT @@ -173,45 +171,59 @@ void DRAMSys::instantiateModules(const ::DRAMSys::Config::AddressMapping& addres MemSpec::MemoryType memoryType = config.memSpec->memoryType; for (std::size_t i = 0; i < config.memSpec->numberOfChannels; i++) { - controllers.emplace_back(std::make_unique(("controller" + std::to_string(i)).c_str(), config, - *addressDecoder)); + controllers.emplace_back(std::make_unique( + ("controller" + std::to_string(i)).c_str(), config, *addressDecoder)); if (memoryType == MemSpec::MemoryType::DDR3) - drams.emplace_back(std::make_unique(("dram" + std::to_string(i)).c_str(), config)); + drams.emplace_back( + std::make_unique(("dram" + std::to_string(i)).c_str(), config)); else if (memoryType == MemSpec::MemoryType::DDR4) - drams.emplace_back(std::make_unique(("dram" + std::to_string(i)).c_str(), config)); + drams.emplace_back( + std::make_unique(("dram" + std::to_string(i)).c_str(), config)); else if (memoryType == MemSpec::MemoryType::WideIO) - drams.emplace_back(std::make_unique(("dram" + std::to_string(i)).c_str(), config)); + drams.emplace_back( + std::make_unique(("dram" + std::to_string(i)).c_str(), config)); else if (memoryType == MemSpec::MemoryType::LPDDR4) - drams.emplace_back(std::make_unique(("dram" + std::to_string(i)).c_str(), config)); + drams.emplace_back( + std::make_unique(("dram" + std::to_string(i)).c_str(), config)); else if (memoryType == MemSpec::MemoryType::WideIO2) - drams.emplace_back(std::make_unique(("dram" + std::to_string(i)).c_str(), config)); + drams.emplace_back( + std::make_unique(("dram" + std::to_string(i)).c_str(), config)); else if (memoryType == MemSpec::MemoryType::HBM2) - drams.emplace_back(std::make_unique(("dram" + std::to_string(i)).c_str(), config)); + drams.emplace_back( + std::make_unique(("dram" + std::to_string(i)).c_str(), config)); else if (memoryType == MemSpec::MemoryType::GDDR5) - drams.emplace_back(std::make_unique(("dram" + std::to_string(i)).c_str(), config)); + drams.emplace_back( + std::make_unique(("dram" + std::to_string(i)).c_str(), config)); else if (memoryType == MemSpec::MemoryType::GDDR5X) - drams.emplace_back(std::make_unique(("dram" + std::to_string(i)).c_str(), config)); + drams.emplace_back( + std::make_unique(("dram" + std::to_string(i)).c_str(), config)); else if (memoryType == MemSpec::MemoryType::GDDR6) - drams.emplace_back(std::make_unique(("dram" + std::to_string(i)).c_str(), config)); + drams.emplace_back( + std::make_unique(("dram" + std::to_string(i)).c_str(), config)); else if (memoryType == MemSpec::MemoryType::STTMRAM) - drams.emplace_back(std::make_unique(("dram" + std::to_string(i)).c_str(), config)); + drams.emplace_back( + std::make_unique(("dram" + std::to_string(i)).c_str(), config)); #ifdef DDR5_SIM else if (memoryType == MemSpec::MemoryType::DDR5) - drams.emplace_back(std::make_unique(("dram" + std::to_string(i)).c_str(), config)); + drams.emplace_back( + std::make_unique(("dram" + std::to_string(i)).c_str(), config)); #endif #ifdef LPDDR5_SIM else if (memoryType == MemSpec::MemoryType::LPDDR5) - drams.emplace_back(std::make_unique(("dram" + std::to_string(i)).c_str(), config)); + drams.emplace_back( + std::make_unique(("dram" + std::to_string(i)).c_str(), config)); #endif #ifdef HBM3_SIM else if (memoryType == MemSpec::MemoryType::HBM3) - drams.emplace_back(std::make_unique(("dram" + std::to_string(i)).c_str(), config)); + drams.emplace_back( + std::make_unique(("dram" + std::to_string(i)).c_str(), config)); #endif if (config.checkTLM2Protocol) - controllersTlmCheckers.push_back(std::make_unique> - (("TlmCheckerController" + std::to_string(i)).c_str())); + controllersTlmCheckers.push_back( + std::make_unique>( + ("TlmCheckerController" + std::to_string(i)).c_str())); } } diff --git a/src/libdramsys/DRAMSys/simulation/DRAMSys.h b/src/libdramsys/DRAMSys/simulation/DRAMSys.h index a641ec9c..bc32470d 100644 --- a/src/libdramsys/DRAMSys/simulation/DRAMSys.h +++ b/src/libdramsys/DRAMSys/simulation/DRAMSys.h @@ -41,18 +41,18 @@ #ifndef DRAMSYS_H #define DRAMSYS_H -#include "DRAMSys/simulation/dram/Dram.h" -#include "DRAMSys/simulation/Arbiter.h" -#include "DRAMSys/simulation/ReorderBuffer.h" #include "DRAMSys/common/tlm2_base_protocol_checker.h" #include "DRAMSys/controller/ControllerIF.h" #include "DRAMSys/simulation/AddressDecoder.h" +#include "DRAMSys/simulation/Arbiter.h" +#include "DRAMSys/simulation/ReorderBuffer.h" +#include "DRAMSys/simulation/dram/Dram.h" #include "DRAMSys/config/DRAMSysConfiguration.h" -#include #include #include +#include #include #include #include @@ -67,11 +67,10 @@ public: tlm_utils::multi_passthrough_target_socket tSocket; SC_HAS_PROCESS(DRAMSys); - DRAMSys(const sc_core::sc_module_name& name, - const ::DRAMSys::Config::Configuration& configLib); + DRAMSys(const sc_core::sc_module_name& name, const ::DRAMSys::Config::Configuration& configLib); const Configuration& getConfig() const; - const AddressDecoder &getAddressDecoder() const { return *addressDecoder; } + const AddressDecoder& getAddressDecoder() const { return *addressDecoder; } protected: DRAMSys(const sc_core::sc_module_name& name, @@ -82,7 +81,7 @@ protected: Configuration config; - //TLM 2.0 Protocol Checkers + // TLM 2.0 Protocol Checkers std::vector>> controllersTlmCheckers; // TODO: Each DRAM has a reorder buffer (check this!) diff --git a/src/libdramsys/DRAMSys/simulation/DRAMSysRecordable.cpp b/src/libdramsys/DRAMSys/simulation/DRAMSysRecordable.cpp index 05086da7..afe1cb25 100644 --- a/src/libdramsys/DRAMSys/simulation/DRAMSysRecordable.cpp +++ b/src/libdramsys/DRAMSys/simulation/DRAMSysRecordable.cpp @@ -36,19 +36,19 @@ #include "DRAMSysRecordable.h" -#include "DRAMSys/controller/ControllerRecordable.h" #include "DRAMSys/common/TlmRecorder.h" -#include "DRAMSys/simulation/dram/DramRecordable.h" +#include "DRAMSys/controller/ControllerRecordable.h" #include "DRAMSys/simulation/dram/DramDDR3.h" #include "DRAMSys/simulation/dram/DramDDR4.h" -#include "DRAMSys/simulation/dram/DramWideIO.h" -#include "DRAMSys/simulation/dram/DramLPDDR4.h" -#include "DRAMSys/simulation/dram/DramWideIO2.h" -#include "DRAMSys/simulation/dram/DramHBM2.h" #include "DRAMSys/simulation/dram/DramGDDR5.h" #include "DRAMSys/simulation/dram/DramGDDR5X.h" #include "DRAMSys/simulation/dram/DramGDDR6.h" +#include "DRAMSys/simulation/dram/DramHBM2.h" +#include "DRAMSys/simulation/dram/DramLPDDR4.h" +#include "DRAMSys/simulation/dram/DramRecordable.h" #include "DRAMSys/simulation/dram/DramSTTMRAM.h" +#include "DRAMSys/simulation/dram/DramWideIO.h" +#include "DRAMSys/simulation/dram/DramWideIO2.h" #ifdef DDR5_SIM #include "DRAMSys/simulation/dram/DramDDR5.h" @@ -65,8 +65,9 @@ namespace DRAMSys { -DRAMSysRecordable::DRAMSysRecordable(const sc_core::sc_module_name& name, const ::DRAMSys::Config::Configuration& configLib) - : DRAMSys(name, configLib, false) +DRAMSysRecordable::DRAMSysRecordable(const sc_core::sc_module_name& name, + const ::DRAMSys::Config::Configuration& configLib) : + DRAMSys(name, configLib, false) { // If a simulation file is passed as argument to DRAMSys the simulation ID // is prepended to the simulation name if found. @@ -90,11 +91,11 @@ void DRAMSysRecordable::end_of_simulation() // Report power before TLM recorders are finalized if (config.powerAnalysis) { - for (auto& dram: drams) + for (auto& dram : drams) dram->reportPower(); } - for (auto& tlmRecorder: tlmRecorders) + for (auto& tlmRecorder : tlmRecorders) tlmRecorder.finalize(); } @@ -108,7 +109,8 @@ void DRAMSysRecordable::setupTlmRecorders(const std::string& traceName, tlmRecorders.reserve(config.memSpec->numberOfChannels); for (std::size_t i = 0; i < config.memSpec->numberOfChannels; i++) { - std::string dbName = std::string(name()) + "_" + traceName + "_ch" + std::to_string(i) + ".tdb"; + std::string dbName = + std::string(name()) + "_" + traceName + "_ch" + std::to_string(i) + ".tdb"; std::string recorderName = "tlmRecorder" + std::to_string(i); nlohmann::json mcconfig; @@ -145,58 +147,59 @@ void DRAMSysRecordable::instantiateModules(const std::string& traceName, MemSpec::MemoryType memoryType = config.memSpec->memoryType; for (std::size_t i = 0; i < config.memSpec->numberOfChannels; i++) { - controllers.emplace_back(std::make_unique(("controller" + std::to_string(i)).c_str(), - config, *addressDecoder, tlmRecorders[i])); + controllers.emplace_back(std::make_unique( + ("controller" + std::to_string(i)).c_str(), config, *addressDecoder, tlmRecorders[i])); if (memoryType == MemSpec::MemoryType::DDR3) - drams.emplace_back(std::make_unique>(("dram" + std::to_string(i)).c_str(), - config, tlmRecorders[i])); + drams.emplace_back(std::make_unique>( + ("dram" + std::to_string(i)).c_str(), config, tlmRecorders[i])); else if (memoryType == MemSpec::MemoryType::DDR4) - drams.emplace_back(std::make_unique>(("dram" + std::to_string(i)).c_str(), - config, tlmRecorders[i])); + drams.emplace_back(std::make_unique>( + ("dram" + std::to_string(i)).c_str(), config, tlmRecorders[i])); else if (memoryType == MemSpec::MemoryType::WideIO) - drams.emplace_back(std::make_unique>(("dram" + std::to_string(i)).c_str(), - config, tlmRecorders[i])); + drams.emplace_back(std::make_unique>( + ("dram" + std::to_string(i)).c_str(), config, tlmRecorders[i])); else if (memoryType == MemSpec::MemoryType::LPDDR4) - drams.emplace_back(std::make_unique>(("dram" + std::to_string(i)).c_str(), - config, tlmRecorders[i])); + drams.emplace_back(std::make_unique>( + ("dram" + std::to_string(i)).c_str(), config, tlmRecorders[i])); else if (memoryType == MemSpec::MemoryType::WideIO2) - drams.emplace_back(std::make_unique>(("dram" + std::to_string(i)).c_str(), - config, tlmRecorders[i])); + drams.emplace_back(std::make_unique>( + ("dram" + std::to_string(i)).c_str(), config, tlmRecorders[i])); else if (memoryType == MemSpec::MemoryType::HBM2) - drams.emplace_back(std::make_unique>(("dram" + std::to_string(i)).c_str(), - config, tlmRecorders[i])); + drams.emplace_back(std::make_unique>( + ("dram" + std::to_string(i)).c_str(), config, tlmRecorders[i])); else if (memoryType == MemSpec::MemoryType::GDDR5) - drams.emplace_back(std::make_unique>(("dram" + std::to_string(i)).c_str(), - config, tlmRecorders[i])); + drams.emplace_back(std::make_unique>( + ("dram" + std::to_string(i)).c_str(), config, tlmRecorders[i])); else if (memoryType == MemSpec::MemoryType::GDDR5X) - drams.emplace_back(std::make_unique>(("dram" + std::to_string(i)).c_str(), - config, tlmRecorders[i])); + drams.emplace_back(std::make_unique>( + ("dram" + std::to_string(i)).c_str(), config, tlmRecorders[i])); else if (memoryType == MemSpec::MemoryType::GDDR6) - drams.emplace_back(std::make_unique>(("dram" + std::to_string(i)).c_str(), - config, tlmRecorders[i])); + drams.emplace_back(std::make_unique>( + ("dram" + std::to_string(i)).c_str(), config, tlmRecorders[i])); else if (memoryType == MemSpec::MemoryType::STTMRAM) - drams.emplace_back(std::make_unique>(("dram" + std::to_string(i)).c_str(), - config, tlmRecorders[i])); + drams.emplace_back(std::make_unique>( + ("dram" + std::to_string(i)).c_str(), config, tlmRecorders[i])); #ifdef DDR5_SIM else if (memoryType == MemSpec::MemoryType::DDR5) - drams.emplace_back(std::make_unique>(("dram" + std::to_string(i)).c_str(), - config, tlmRecorders[i])); + drams.emplace_back(std::make_unique>( + ("dram" + std::to_string(i)).c_str(), config, tlmRecorders[i])); #endif #ifdef LPDDR5_SIM else if (memoryType == MemSpec::MemoryType::LPDDR5) - drams.emplace_back(std::make_unique>(("dram" + std::to_string(i)).c_str(), - config, tlmRecorders[i])); + drams.emplace_back(std::make_unique>( + ("dram" + std::to_string(i)).c_str(), config, tlmRecorders[i])); #endif #ifdef HBM3_SIM else if (memoryType == MemSpec::MemoryType::HBM3) - drams.emplace_back(std::make_unique>(("dram" + std::to_string(i)).c_str(), - config, tlmRecorders[i])); + drams.emplace_back(std::make_unique>( + ("dram" + std::to_string(i)).c_str(), config, tlmRecorders[i])); #endif if (config.checkTLM2Protocol) - controllersTlmCheckers.emplace_back(std::make_unique> - (("TLMCheckerController" + std::to_string(i)).c_str())); + controllersTlmCheckers.emplace_back( + std::make_unique>( + ("TLMCheckerController" + std::to_string(i)).c_str())); } } diff --git a/src/libdramsys/DRAMSys/simulation/DRAMSysRecordable.h b/src/libdramsys/DRAMSys/simulation/DRAMSysRecordable.h index 79c36879..69efdda9 100644 --- a/src/libdramsys/DRAMSys/simulation/DRAMSysRecordable.h +++ b/src/libdramsys/DRAMSys/simulation/DRAMSysRecordable.h @@ -37,8 +37,8 @@ #ifndef DRAMSYSRECORDABLE_H #define DRAMSYSRECORDABLE_H -#include "DRAMSys/simulation/DRAMSys.h" #include "DRAMSys/common/TlmRecorder.h" +#include "DRAMSys/simulation/DRAMSys.h" #include "DRAMSys/config/DRAMSysConfiguration.h" @@ -48,7 +48,8 @@ namespace DRAMSys class DRAMSysRecordable : public DRAMSys { public: - DRAMSysRecordable(const sc_core::sc_module_name& name, const ::DRAMSys::Config::Configuration& configLib); + DRAMSysRecordable(const sc_core::sc_module_name& name, + const ::DRAMSys::Config::Configuration& configLib); protected: void end_of_simulation() override; @@ -58,9 +59,11 @@ private: // They generate the output databases. std::vector tlmRecorders; - void setupTlmRecorders(const std::string& traceName, const ::DRAMSys::Config::Configuration& configLib); + void setupTlmRecorders(const std::string& traceName, + const ::DRAMSys::Config::Configuration& configLib); - void instantiateModules(const std::string& traceName, const ::DRAMSys::Config::Configuration& configLib); + void instantiateModules(const std::string& traceName, + const ::DRAMSys::Config::Configuration& configLib); }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/simulation/ReorderBuffer.h b/src/libdramsys/DRAMSys/simulation/ReorderBuffer.h index 8a588d2d..82bd0a5e 100644 --- a/src/libdramsys/DRAMSys/simulation/ReorderBuffer.h +++ b/src/libdramsys/DRAMSys/simulation/ReorderBuffer.h @@ -42,9 +42,9 @@ #include #include #include +#include #include #include -#include namespace DRAMSys { @@ -55,8 +55,7 @@ public: tlm_utils::simple_initiator_socket iSocket; tlm_utils::simple_target_socket tSocket; - SC_CTOR(ReorderBuffer) : - payloadEventQueue(this, &ReorderBuffer::peqCallback) + SC_CTOR(ReorderBuffer) : payloadEventQueue(this, &ReorderBuffer::peqCallback) { iSocket.register_nb_transport_bw(this, &ReorderBuffer::nb_transport_bw); tSocket.register_nb_transport_fw(this, &ReorderBuffer::nb_transport_fw); @@ -65,13 +64,13 @@ public: private: tlm_utils::peq_with_cb_and_phase payloadEventQueue; std::deque pendingRequestsInOrder; - std::set receivedResponses; + std::set receivedResponses; bool responseIsPendingInInitator = false; - // Initiated by dram side - tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, + tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload& trans, + tlm::tlm_phase& phase, sc_core::sc_time& bwDelay) { payloadEventQueue.notify(trans, phase, bwDelay); @@ -79,12 +78,16 @@ private: } // Initiated by initator side (players) - tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, + tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& trans, + tlm::tlm_phase& phase, sc_core::sc_time& fwDelay) { - if (phase == tlm::BEGIN_REQ) { + if (phase == tlm::BEGIN_REQ) + { trans.acquire(); - } else if (phase == tlm::END_RESP) { + } + else if (phase == tlm::END_RESP) + { trans.release(); } @@ -94,49 +97,56 @@ private: void peqCallback(tlm::tlm_generic_payload& trans, const tlm::tlm_phase& phase) { - //Phases initiated by initiator side - if (phase == tlm::BEGIN_REQ) { + // Phases initiated by initiator side + if (phase == tlm::BEGIN_REQ) + { pendingRequestsInOrder.push_back(&trans); sendToTarget(trans, phase, sc_core::SC_ZERO_TIME); } - else if (phase == tlm::END_RESP) { + else if (phase == tlm::END_RESP) + { responseIsPendingInInitator = false; pendingRequestsInOrder.pop_front(); receivedResponses.erase(&trans); sendNextResponse(); } - //Phases initiated by dram side - else if (phase == tlm::END_REQ) { + // Phases initiated by dram side + else if (phase == tlm::END_REQ) + { sendToInitiator(trans, phase, sc_core::SC_ZERO_TIME); - } else if (phase == tlm::BEGIN_RESP) { + } + else if (phase == tlm::BEGIN_RESP) + { sendToTarget(trans, tlm::END_RESP, sc_core::SC_ZERO_TIME); receivedResponses.emplace(&trans); sendNextResponse(); } - - else { - SC_REPORT_FATAL(0, - "Payload event queue in arbiter was triggered with unknown phase"); + else + { + SC_REPORT_FATAL(0, "Payload event queue in arbiter was triggered with unknown phase"); } } - void sendToTarget(tlm::tlm_generic_payload& trans, const tlm::tlm_phase& phase, const sc_core::sc_time& delay) + void sendToTarget(tlm::tlm_generic_payload& trans, + const tlm::tlm_phase& phase, + const sc_core::sc_time& delay) { tlm::tlm_phase TPhase = phase; sc_core::sc_time TDelay = delay; iSocket->nb_transport_fw(trans, TPhase, TDelay); } - void sendToInitiator(tlm::tlm_generic_payload& trans, const tlm::tlm_phase& phase, const sc_core::sc_time& delay) + void sendToInitiator(tlm::tlm_generic_payload& trans, + const tlm::tlm_phase& phase, + const sc_core::sc_time& delay) { - sc_assert(phase == tlm::END_REQ || - (phase == tlm::BEGIN_RESP && pendingRequestsInOrder.front() == &trans - && receivedResponses.count(&trans))); + (phase == tlm::BEGIN_RESP && pendingRequestsInOrder.front() == &trans && + receivedResponses.count(&trans))); tlm::tlm_phase TPhase = phase; sc_core::sc_time TDelay = delay; @@ -145,21 +155,23 @@ private: void sendNextResponse() { - //only send the next response when there response for the oldest pending request (requestsInOrder.front()) - //has been received + // only send the next response when there response for the oldest pending request + // (requestsInOrder.front()) has been received if (!responseIsPendingInInitator && (receivedResponses.count(pendingRequestsInOrder.front()) != 0)) { - tlm::tlm_generic_payload *payloadToSend = pendingRequestsInOrder.front(); + tlm::tlm_generic_payload* payloadToSend = pendingRequestsInOrder.front(); responseIsPendingInInitator = true; sendToInitiator(*payloadToSend, tlm::BEGIN_RESP, sc_core::SC_ZERO_TIME); } -// else if(!responseIsPendingInInitator && receivedResponses.size()>0 && !receivedResponses.count(pendingRequestsInOrder.front())>0) -// { -// cout << "cant send this response, because we are still waiting for response of oldest pending request. Elemts in buffer: " << receivedResponses.size() << endl; -// } + // else if(!responseIsPendingInInitator && receivedResponses.size()>0 && + // !receivedResponses.count(pendingRequestsInOrder.front())>0) + // { + // cout << "cant send this response, because we are still waiting for response of + // oldest pending request. Elemts in buffer: " << receivedResponses.size() << + // endl; + // } } - }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/simulation/dram/Dram.cpp b/src/libdramsys/DRAMSys/simulation/dram/Dram.cpp index 0ca2ecf7..74d714d8 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/Dram.cpp +++ b/src/libdramsys/DRAMSys/simulation/dram/Dram.cpp @@ -51,9 +51,9 @@ #include #ifdef _WIN32 - #include +#include #else - #include +#include #endif using namespace sc_core; @@ -66,30 +66,37 @@ using namespace DRAMPower; namespace DRAMSys { - -Dram::Dram(const sc_module_name& name, const Configuration& config) - : sc_module(name), memSpec(*config.memSpec), storeMode(config.storeMode), powerAnalysis(config.powerAnalysis), - useMalloc(config.useMalloc), tSocket("socket") +Dram::Dram(const sc_module_name& name, const Configuration& config) : + sc_module(name), + memSpec(*config.memSpec), + storeMode(config.storeMode), + powerAnalysis(config.powerAnalysis), + useMalloc(config.useMalloc), + tSocket("socket") { uint64_t channelSize = memSpec.getSimMemSizeInBytes() / memSpec.numberOfChannels; if (storeMode == Configuration::StoreMode::Store) { if (useMalloc) { - memory = (unsigned char *)malloc(channelSize); + memory = (unsigned char*)malloc(channelSize); if (memory == nullptr) SC_REPORT_FATAL(this->name(), "Memory allocation failed"); } else { - // allocate and model storage of one DRAM channel using memory map - #ifdef _WIN32 - SC_REPORT_FATAL("Dram", "On Windows Storage is not yet supported"); - memory = 0; // FIXME - #else - memory = (unsigned char *)mmap(nullptr, channelSize, - PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON | MAP_NORESERVE, -1, 0); - #endif +// allocate and model storage of one DRAM channel using memory map +#ifdef _WIN32 + SC_REPORT_FATAL("Dram", "On Windows Storage is not yet supported"); + memory = 0; // FIXME +#else + memory = (unsigned char*)mmap(nullptr, + channelSize, + PROT_READ | PROT_WRITE, + MAP_PRIVATE | MAP_ANON | MAP_NORESERVE, + -1, + 0); +#endif } } @@ -111,18 +118,13 @@ void Dram::reportPower() // Print the final total energy and the average power for // the simulation: - std::cout << name() << std::string(" Total Energy: ") - << std::fixed << std::setprecision( 2 ) - << DRAMPower->getEnergy().total_energy - * memSpec.devicesPerRank - << std::string(" pJ") - << std::endl; + std::cout << name() << std::string(" Total Energy: ") << std::fixed << std::setprecision(2) + << DRAMPower->getEnergy().total_energy * memSpec.devicesPerRank << std::string(" pJ") + << std::endl; - std::cout << name() << std::string(" Average Power: ") - << std::fixed << std::setprecision( 2 ) - << DRAMPower->getPower().average_power - * memSpec.devicesPerRank - << std::string(" mW") << std::endl; + std::cout << name() << std::string(" Average Power: ") << std::fixed << std::setprecision(2) + << DRAMPower->getPower().average_power * memSpec.devicesPerRank << std::string(" mW") + << std::endl; #endif } @@ -161,7 +163,8 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload& trans, tlm_phase& phase } } } - else if (phase == BEGIN_WR || phase == BEGIN_WRA || phase == BEGIN_MWR || phase == BEGIN_MWRA) + else if (phase == BEGIN_WR || phase == BEGIN_WRA || phase == BEGIN_MWR || + phase == BEGIN_MWRA) { unsigned char* phyAddr = memory + trans.get_address(); @@ -224,7 +227,7 @@ unsigned int Dram::transport_dbg(tlm_generic_payload& trans) } else { - //ememory[bank]->load(trans); + // ememory[bank]->load(trans); SC_REPORT_FATAL("DRAM", "Debug transport not supported with error model yet."); } } @@ -252,7 +255,7 @@ unsigned int Dram::transport_dbg(tlm_generic_payload& trans) } else { - //ememory[bank]->store(trans); + // ememory[bank]->store(trans); SC_REPORT_FATAL("DRAM", "Debug transport not supported with error model yet."); } } diff --git a/src/libdramsys/DRAMSys/simulation/dram/Dram.h b/src/libdramsys/DRAMSys/simulation/dram/Dram.h index acf16459..28d80e9a 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/Dram.h +++ b/src/libdramsys/DRAMSys/simulation/dram/Dram.h @@ -54,7 +54,6 @@ class libDRAMPower; namespace DRAMSys { - class Dram : public sc_core::sc_module { protected: @@ -74,7 +73,8 @@ protected: #endif virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& trans, - tlm::tlm_phase& phase, sc_core::sc_time& delay); + tlm::tlm_phase& phase, + sc_core::sc_time& delay); virtual void b_transport(tlm::tlm_generic_payload& trans, sc_core::sc_time& delay); virtual unsigned int transport_dbg(tlm::tlm_generic_payload& trans); @@ -87,10 +87,10 @@ public: virtual void reportPower(); - Dram(const Dram &) = delete; - Dram(Dram &&) = delete; - Dram &operator=(const Dram &) = delete; - Dram &operator=(Dram &&) = delete; + Dram(const Dram&) = delete; + Dram(Dram&&) = delete; + Dram& operator=(const Dram&) = delete; + Dram& operator=(Dram&&) = delete; ~Dram() override; }; diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramDDR3.cpp b/src/libdramsys/DRAMSys/simulation/dram/DramDDR3.cpp index 1feb025c..1e0e61e2 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramDDR3.cpp +++ b/src/libdramsys/DRAMSys/simulation/dram/DramDDR3.cpp @@ -47,101 +47,100 @@ using namespace sc_core; namespace DRAMSys { -DramDDR3::DramDDR3(const sc_module_name& name, const Configuration& config) - : Dram(name, config) +DramDDR3::DramDDR3(const sc_module_name& name, const Configuration& config) : Dram(name, config) { #ifdef DRAMPOWER if (powerAnalysis) { - const auto *memSpecDDR3 = dynamic_cast(config.memSpec.get()); + const auto* memSpecDDR3 = dynamic_cast(config.memSpec.get()); if (memSpecDDR3 == nullptr) SC_REPORT_FATAL("DramDDR3", "Wrong MemSpec chosen"); MemArchitectureSpec memArchSpec; - memArchSpec.burstLength = memSpecDDR3->defaultBurstLength; - memArchSpec.dataRate = memSpecDDR3->dataRate; - memArchSpec.nbrOfRows = memSpecDDR3->rowsPerBank; - memArchSpec.nbrOfBanks = memSpecDDR3->banksPerChannel; - memArchSpec.nbrOfColumns = memSpecDDR3->columnsPerRow; - memArchSpec.nbrOfRanks = memSpecDDR3->ranksPerChannel; - memArchSpec.width = memSpecDDR3->bitWidth; - memArchSpec.nbrOfBankGroups = memSpecDDR3->bankGroupsPerChannel; + memArchSpec.burstLength = memSpecDDR3->defaultBurstLength; + memArchSpec.dataRate = memSpecDDR3->dataRate; + memArchSpec.nbrOfRows = memSpecDDR3->rowsPerBank; + memArchSpec.nbrOfBanks = memSpecDDR3->banksPerChannel; + memArchSpec.nbrOfColumns = memSpecDDR3->columnsPerRow; + memArchSpec.nbrOfRanks = memSpecDDR3->ranksPerChannel; + memArchSpec.width = memSpecDDR3->bitWidth; + memArchSpec.nbrOfBankGroups = memSpecDDR3->bankGroupsPerChannel; memArchSpec.twoVoltageDomains = false; - memArchSpec.dll = true; + memArchSpec.dll = true; MemTimingSpec memTimingSpec; - //FIXME: memTimingSpec.FAWB = memSpecDDR3->tFAW / memSpecDDR3->tCK; - //FIXME: memTimingSpec.RASB = memSpecDDR3->tRAS / memSpecDDR3->tCK; - //FIXME: memTimingSpec.RCB = memSpecDDR3->tRC / memSpecDDR3->tCK; - //FIXME: memTimingSpec.RPB = memSpecDDR3->tRP / memSpecDDR3->tCK; - //FIXME: memTimingSpec.RRDB = memSpecDDR3->tRRD / memSpecDDR3->tCK; - //FIXME: memTimingSpec.RRDB_L = memSpecDDR3->tRRD / memSpecDDR3->tCK; - //FIXME: memTimingSpec.RRDB_S = memSpecDDR3->tRRD / memSpecDDR3->tCK; - memTimingSpec.AL = memSpecDDR3->tAL / memSpecDDR3->tCK; - memTimingSpec.CCD = memSpecDDR3->tCCD / memSpecDDR3->tCK; - memTimingSpec.CCD_L = memSpecDDR3->tCCD / memSpecDDR3->tCK; - memTimingSpec.CCD_S = memSpecDDR3->tCCD / memSpecDDR3->tCK; - memTimingSpec.CKE = memSpecDDR3->tCKE / memSpecDDR3->tCK; - memTimingSpec.CKESR = memSpecDDR3->tCKESR / memSpecDDR3->tCK; + // FIXME: memTimingSpec.FAWB = memSpecDDR3->tFAW / memSpecDDR3->tCK; + // FIXME: memTimingSpec.RASB = memSpecDDR3->tRAS / memSpecDDR3->tCK; + // FIXME: memTimingSpec.RCB = memSpecDDR3->tRC / memSpecDDR3->tCK; + // FIXME: memTimingSpec.RPB = memSpecDDR3->tRP / memSpecDDR3->tCK; + // FIXME: memTimingSpec.RRDB = memSpecDDR3->tRRD / memSpecDDR3->tCK; + // FIXME: memTimingSpec.RRDB_L = memSpecDDR3->tRRD / memSpecDDR3->tCK; + // FIXME: memTimingSpec.RRDB_S = memSpecDDR3->tRRD / memSpecDDR3->tCK; + memTimingSpec.AL = memSpecDDR3->tAL / memSpecDDR3->tCK; + memTimingSpec.CCD = memSpecDDR3->tCCD / memSpecDDR3->tCK; + memTimingSpec.CCD_L = memSpecDDR3->tCCD / memSpecDDR3->tCK; + memTimingSpec.CCD_S = memSpecDDR3->tCCD / memSpecDDR3->tCK; + memTimingSpec.CKE = memSpecDDR3->tCKE / memSpecDDR3->tCK; + memTimingSpec.CKESR = memSpecDDR3->tCKESR / memSpecDDR3->tCK; memTimingSpec.clkMhz = memSpecDDR3->fCKMHz; // See also MemTimingSpec.cc in DRAMPower memTimingSpec.clkPeriod = 1000.0 / memSpecDDR3->fCKMHz; - memTimingSpec.DQSCK = memSpecDDR3->tDQSCK / memSpecDDR3->tCK; - memTimingSpec.FAW = memSpecDDR3->tFAW / memSpecDDR3->tCK; - memTimingSpec.RAS = memSpecDDR3->tRAS / memSpecDDR3->tCK; - memTimingSpec.RC = memSpecDDR3->tRC / memSpecDDR3->tCK; - memTimingSpec.RCD = memSpecDDR3->tRCD / memSpecDDR3->tCK; - memTimingSpec.REFI = memSpecDDR3->tREFI / memSpecDDR3->tCK; - memTimingSpec.RFC = memSpecDDR3->tRFC / memSpecDDR3->tCK; - memTimingSpec.RL = memSpecDDR3->tRL / memSpecDDR3->tCK; - memTimingSpec.RP = memSpecDDR3->tRP / memSpecDDR3->tCK; - memTimingSpec.RRD = memSpecDDR3->tRRD / memSpecDDR3->tCK; - memTimingSpec.RRD_L = memSpecDDR3->tRRD / memSpecDDR3->tCK; - memTimingSpec.RRD_S = memSpecDDR3->tRRD / memSpecDDR3->tCK; - memTimingSpec.RTP = memSpecDDR3->tRTP / memSpecDDR3->tCK; - memTimingSpec.TAW = memSpecDDR3->tFAW / memSpecDDR3->tCK; - memTimingSpec.WL = memSpecDDR3->tWL / memSpecDDR3->tCK; - memTimingSpec.WR = memSpecDDR3->tWR / memSpecDDR3->tCK; - memTimingSpec.WTR = memSpecDDR3->tWTR / memSpecDDR3->tCK; - memTimingSpec.WTR_L = memSpecDDR3->tWTR / memSpecDDR3->tCK; - memTimingSpec.WTR_S = memSpecDDR3->tWTR / memSpecDDR3->tCK; - memTimingSpec.XP = memSpecDDR3->tXP / memSpecDDR3->tCK; - memTimingSpec.XPDLL = memSpecDDR3->tXPDLL / memSpecDDR3->tCK; - memTimingSpec.XS = memSpecDDR3->tXS / memSpecDDR3->tCK; - memTimingSpec.XSDLL = memSpecDDR3->tXSDLL / memSpecDDR3->tCK; + memTimingSpec.DQSCK = memSpecDDR3->tDQSCK / memSpecDDR3->tCK; + memTimingSpec.FAW = memSpecDDR3->tFAW / memSpecDDR3->tCK; + memTimingSpec.RAS = memSpecDDR3->tRAS / memSpecDDR3->tCK; + memTimingSpec.RC = memSpecDDR3->tRC / memSpecDDR3->tCK; + memTimingSpec.RCD = memSpecDDR3->tRCD / memSpecDDR3->tCK; + memTimingSpec.REFI = memSpecDDR3->tREFI / memSpecDDR3->tCK; + memTimingSpec.RFC = memSpecDDR3->tRFC / memSpecDDR3->tCK; + memTimingSpec.RL = memSpecDDR3->tRL / memSpecDDR3->tCK; + memTimingSpec.RP = memSpecDDR3->tRP / memSpecDDR3->tCK; + memTimingSpec.RRD = memSpecDDR3->tRRD / memSpecDDR3->tCK; + memTimingSpec.RRD_L = memSpecDDR3->tRRD / memSpecDDR3->tCK; + memTimingSpec.RRD_S = memSpecDDR3->tRRD / memSpecDDR3->tCK; + memTimingSpec.RTP = memSpecDDR3->tRTP / memSpecDDR3->tCK; + memTimingSpec.TAW = memSpecDDR3->tFAW / memSpecDDR3->tCK; + memTimingSpec.WL = memSpecDDR3->tWL / memSpecDDR3->tCK; + memTimingSpec.WR = memSpecDDR3->tWR / memSpecDDR3->tCK; + memTimingSpec.WTR = memSpecDDR3->tWTR / memSpecDDR3->tCK; + memTimingSpec.WTR_L = memSpecDDR3->tWTR / memSpecDDR3->tCK; + memTimingSpec.WTR_S = memSpecDDR3->tWTR / memSpecDDR3->tCK; + memTimingSpec.XP = memSpecDDR3->tXP / memSpecDDR3->tCK; + memTimingSpec.XPDLL = memSpecDDR3->tXPDLL / memSpecDDR3->tCK; + memTimingSpec.XS = memSpecDDR3->tXS / memSpecDDR3->tCK; + memTimingSpec.XSDLL = memSpecDDR3->tXSDLL / memSpecDDR3->tCK; - MemPowerSpec memPowerSpec; - memPowerSpec.idd0 = memSpecDDR3->iDD0; - memPowerSpec.idd02 = 0; - memPowerSpec.idd2p0 = memSpecDDR3->iDD2P0; + MemPowerSpec memPowerSpec; + memPowerSpec.idd0 = memSpecDDR3->iDD0; + memPowerSpec.idd02 = 0; + memPowerSpec.idd2p0 = memSpecDDR3->iDD2P0; memPowerSpec.idd2p02 = 0; - memPowerSpec.idd2p1 = memSpecDDR3->iDD2P1; + memPowerSpec.idd2p1 = memSpecDDR3->iDD2P1; memPowerSpec.idd2p12 = 0; - memPowerSpec.idd2n = memSpecDDR3->iDD2N; - memPowerSpec.idd2n2 = 0; - memPowerSpec.idd3p0 = memSpecDDR3->iDD3P0; + memPowerSpec.idd2n = memSpecDDR3->iDD2N; + memPowerSpec.idd2n2 = 0; + memPowerSpec.idd3p0 = memSpecDDR3->iDD3P0; memPowerSpec.idd3p02 = 0; - memPowerSpec.idd3p1 = memSpecDDR3->iDD3P1; + memPowerSpec.idd3p1 = memSpecDDR3->iDD3P1; memPowerSpec.idd3p12 = 0; - memPowerSpec.idd3n = memSpecDDR3->iDD3N; - memPowerSpec.idd3n2 = 0; - memPowerSpec.idd4r = memSpecDDR3->iDD4R; - memPowerSpec.idd4r2 = 0; - memPowerSpec.idd4w = memSpecDDR3->iDD4W; - memPowerSpec.idd4w2 = 0; - memPowerSpec.idd5 = memSpecDDR3->iDD5; - memPowerSpec.idd52 = 0; - memPowerSpec.idd6 = memSpecDDR3->iDD6; - memPowerSpec.idd62 = 0; - memPowerSpec.vdd = memSpecDDR3->vDD; - memPowerSpec.vdd2 = 0; + memPowerSpec.idd3n = memSpecDDR3->iDD3N; + memPowerSpec.idd3n2 = 0; + memPowerSpec.idd4r = memSpecDDR3->iDD4R; + memPowerSpec.idd4r2 = 0; + memPowerSpec.idd4w = memSpecDDR3->iDD4W; + memPowerSpec.idd4w2 = 0; + memPowerSpec.idd5 = memSpecDDR3->iDD5; + memPowerSpec.idd52 = 0; + memPowerSpec.idd6 = memSpecDDR3->iDD6; + memPowerSpec.idd62 = 0; + memPowerSpec.vdd = memSpecDDR3->vDD; + memPowerSpec.vdd2 = 0; MemorySpecification powerSpec; powerSpec.id = memSpecDDR3->memoryId; powerSpec.memoryType = MemoryType::DDR3; powerSpec.memTimingSpec = memTimingSpec; - powerSpec.memPowerSpec = memPowerSpec; - powerSpec.memArchSpec = memArchSpec; + powerSpec.memPowerSpec = memPowerSpec; + powerSpec.memArchSpec = memArchSpec; DRAMPower = std::make_unique(powerSpec, false); } diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramDDR4.cpp b/src/libdramsys/DRAMSys/simulation/dram/DramDDR4.cpp index e7dc97da..deac705b 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramDDR4.cpp +++ b/src/libdramsys/DRAMSys/simulation/dram/DramDDR4.cpp @@ -47,101 +47,100 @@ using namespace sc_core; namespace DRAMSys { -DramDDR4::DramDDR4(const sc_module_name& name, const Configuration& config) - : Dram(name, config) +DramDDR4::DramDDR4(const sc_module_name& name, const Configuration& config) : Dram(name, config) { #ifdef DRAMPOWER if (powerAnalysis) { - const auto *memSpecDDR4 = dynamic_cast(config.memSpec.get()); + const auto* memSpecDDR4 = dynamic_cast(config.memSpec.get()); if (memSpecDDR4 == nullptr) SC_REPORT_FATAL("DramDDR4", "Wrong MemSpec chosen"); MemArchitectureSpec memArchSpec; - memArchSpec.burstLength = memSpecDDR4->defaultBurstLength; - memArchSpec.dataRate = memSpecDDR4->dataRate; - memArchSpec.nbrOfRows = memSpecDDR4->rowsPerBank; - memArchSpec.nbrOfBanks = memSpecDDR4->banksPerChannel; - memArchSpec.nbrOfColumns = memSpecDDR4->columnsPerRow; - memArchSpec.nbrOfRanks = memSpecDDR4->ranksPerChannel; - memArchSpec.width = memSpecDDR4->bitWidth; - memArchSpec.nbrOfBankGroups = memSpecDDR4->bankGroupsPerChannel; + memArchSpec.burstLength = memSpecDDR4->defaultBurstLength; + memArchSpec.dataRate = memSpecDDR4->dataRate; + memArchSpec.nbrOfRows = memSpecDDR4->rowsPerBank; + memArchSpec.nbrOfBanks = memSpecDDR4->banksPerChannel; + memArchSpec.nbrOfColumns = memSpecDDR4->columnsPerRow; + memArchSpec.nbrOfRanks = memSpecDDR4->ranksPerChannel; + memArchSpec.width = memSpecDDR4->bitWidth; + memArchSpec.nbrOfBankGroups = memSpecDDR4->bankGroupsPerChannel; memArchSpec.twoVoltageDomains = true; - memArchSpec.dll = true; + memArchSpec.dll = true; MemTimingSpec memTimingSpec; - //FIXME: memTimingSpec.FAWB = memSpecDDR4->tFAW / memSpecDDR4->tCK; - //FIXME: memTimingSpec.RASB = memSpecDDR4->tRAS / memSpecDDR4->tCK; - //FIXME: memTimingSpec.RCB = memSpecDDR4->tRC / memSpecDDR4->tCK; - //FIXME: memTimingSpec.RPB = memSpecDDR4->tRP / memSpecDDR4->tCK; - //FIXME: memTimingSpec.RRDB = memSpecDDR4->tRRD_S / memSpecDDR4->tCK; - //FIXME: memTimingSpec.RRDB_L = memSpecDDR4->tRRD_L / memSpecDDR4->tCK; - //FIXME: memTimingSpec.RRDB_S = memSpecDDR4->tRRD_S / memSpecDDR4->tCK; - memTimingSpec.AL = memSpecDDR4->tAL / memSpecDDR4->tCK; - memTimingSpec.CCD = memSpecDDR4->tCCD_S / memSpecDDR4->tCK; - memTimingSpec.CCD_L = memSpecDDR4->tCCD_L / memSpecDDR4->tCK; - memTimingSpec.CCD_S = memSpecDDR4->tCCD_S / memSpecDDR4->tCK; - memTimingSpec.CKE = memSpecDDR4->tCKE / memSpecDDR4->tCK; - memTimingSpec.CKESR = memSpecDDR4->tCKESR / memSpecDDR4->tCK; + // FIXME: memTimingSpec.FAWB = memSpecDDR4->tFAW / memSpecDDR4->tCK; + // FIXME: memTimingSpec.RASB = memSpecDDR4->tRAS / memSpecDDR4->tCK; + // FIXME: memTimingSpec.RCB = memSpecDDR4->tRC / memSpecDDR4->tCK; + // FIXME: memTimingSpec.RPB = memSpecDDR4->tRP / memSpecDDR4->tCK; + // FIXME: memTimingSpec.RRDB = memSpecDDR4->tRRD_S / memSpecDDR4->tCK; + // FIXME: memTimingSpec.RRDB_L = memSpecDDR4->tRRD_L / memSpecDDR4->tCK; + // FIXME: memTimingSpec.RRDB_S = memSpecDDR4->tRRD_S / memSpecDDR4->tCK; + memTimingSpec.AL = memSpecDDR4->tAL / memSpecDDR4->tCK; + memTimingSpec.CCD = memSpecDDR4->tCCD_S / memSpecDDR4->tCK; + memTimingSpec.CCD_L = memSpecDDR4->tCCD_L / memSpecDDR4->tCK; + memTimingSpec.CCD_S = memSpecDDR4->tCCD_S / memSpecDDR4->tCK; + memTimingSpec.CKE = memSpecDDR4->tCKE / memSpecDDR4->tCK; + memTimingSpec.CKESR = memSpecDDR4->tCKESR / memSpecDDR4->tCK; memTimingSpec.clkMhz = memSpecDDR4->fCKMHz; // See also MemTimingSpec.cc in DRAMPower memTimingSpec.clkPeriod = 1000.0 / memSpecDDR4->fCKMHz; - memTimingSpec.DQSCK = memSpecDDR4->tDQSCK / memSpecDDR4->tCK; - memTimingSpec.FAW = memSpecDDR4->tFAW / memSpecDDR4->tCK; - memTimingSpec.RAS = memSpecDDR4->tRAS / memSpecDDR4->tCK; - memTimingSpec.RC = memSpecDDR4->tRC / memSpecDDR4->tCK; - memTimingSpec.RCD = memSpecDDR4->tRCD / memSpecDDR4->tCK; - memTimingSpec.REFI = memSpecDDR4->tREFI / memSpecDDR4->tCK; - memTimingSpec.RFC = memSpecDDR4->tRFC / memSpecDDR4->tCK; - memTimingSpec.RL = memSpecDDR4->tRL / memSpecDDR4->tCK; - memTimingSpec.RP = memSpecDDR4->tRP / memSpecDDR4->tCK; - memTimingSpec.RRD = memSpecDDR4->tRRD_S / memSpecDDR4->tCK; - memTimingSpec.RRD_L = memSpecDDR4->tRRD_L / memSpecDDR4->tCK; - memTimingSpec.RRD_S = memSpecDDR4->tRRD_S / memSpecDDR4->tCK; - memTimingSpec.RTP = memSpecDDR4->tRTP / memSpecDDR4->tCK; - memTimingSpec.TAW = memSpecDDR4->tFAW / memSpecDDR4->tCK; - memTimingSpec.WL = memSpecDDR4->tWL / memSpecDDR4->tCK; - memTimingSpec.WR = memSpecDDR4->tWR / memSpecDDR4->tCK; - memTimingSpec.WTR = memSpecDDR4->tWTR_S / memSpecDDR4->tCK; - memTimingSpec.WTR_L = memSpecDDR4->tWTR_L / memSpecDDR4->tCK; - memTimingSpec.WTR_S = memSpecDDR4->tWTR_S / memSpecDDR4->tCK; - memTimingSpec.XP = memSpecDDR4->tXP / memSpecDDR4->tCK; - memTimingSpec.XPDLL = memSpecDDR4->tXPDLL / memSpecDDR4->tCK; - memTimingSpec.XS = memSpecDDR4->tXS / memSpecDDR4->tCK; - memTimingSpec.XSDLL = memSpecDDR4->tXSDLL / memSpecDDR4->tCK; + memTimingSpec.DQSCK = memSpecDDR4->tDQSCK / memSpecDDR4->tCK; + memTimingSpec.FAW = memSpecDDR4->tFAW / memSpecDDR4->tCK; + memTimingSpec.RAS = memSpecDDR4->tRAS / memSpecDDR4->tCK; + memTimingSpec.RC = memSpecDDR4->tRC / memSpecDDR4->tCK; + memTimingSpec.RCD = memSpecDDR4->tRCD / memSpecDDR4->tCK; + memTimingSpec.REFI = memSpecDDR4->tREFI / memSpecDDR4->tCK; + memTimingSpec.RFC = memSpecDDR4->tRFC / memSpecDDR4->tCK; + memTimingSpec.RL = memSpecDDR4->tRL / memSpecDDR4->tCK; + memTimingSpec.RP = memSpecDDR4->tRP / memSpecDDR4->tCK; + memTimingSpec.RRD = memSpecDDR4->tRRD_S / memSpecDDR4->tCK; + memTimingSpec.RRD_L = memSpecDDR4->tRRD_L / memSpecDDR4->tCK; + memTimingSpec.RRD_S = memSpecDDR4->tRRD_S / memSpecDDR4->tCK; + memTimingSpec.RTP = memSpecDDR4->tRTP / memSpecDDR4->tCK; + memTimingSpec.TAW = memSpecDDR4->tFAW / memSpecDDR4->tCK; + memTimingSpec.WL = memSpecDDR4->tWL / memSpecDDR4->tCK; + memTimingSpec.WR = memSpecDDR4->tWR / memSpecDDR4->tCK; + memTimingSpec.WTR = memSpecDDR4->tWTR_S / memSpecDDR4->tCK; + memTimingSpec.WTR_L = memSpecDDR4->tWTR_L / memSpecDDR4->tCK; + memTimingSpec.WTR_S = memSpecDDR4->tWTR_S / memSpecDDR4->tCK; + memTimingSpec.XP = memSpecDDR4->tXP / memSpecDDR4->tCK; + memTimingSpec.XPDLL = memSpecDDR4->tXPDLL / memSpecDDR4->tCK; + memTimingSpec.XS = memSpecDDR4->tXS / memSpecDDR4->tCK; + memTimingSpec.XSDLL = memSpecDDR4->tXSDLL / memSpecDDR4->tCK; - MemPowerSpec memPowerSpec; - memPowerSpec.idd0 = memSpecDDR4->iDD0; - memPowerSpec.idd02 = memSpecDDR4->iDD02; - memPowerSpec.idd2p0 = memSpecDDR4->iDD2P0; + MemPowerSpec memPowerSpec; + memPowerSpec.idd0 = memSpecDDR4->iDD0; + memPowerSpec.idd02 = memSpecDDR4->iDD02; + memPowerSpec.idd2p0 = memSpecDDR4->iDD2P0; memPowerSpec.idd2p02 = 0; - memPowerSpec.idd2p1 = memSpecDDR4->iDD2P1; + memPowerSpec.idd2p1 = memSpecDDR4->iDD2P1; memPowerSpec.idd2p12 = 0; - memPowerSpec.idd2n = memSpecDDR4->iDD2N; - memPowerSpec.idd2n2 = 0; - memPowerSpec.idd3p0 = memSpecDDR4->iDD3P0; + memPowerSpec.idd2n = memSpecDDR4->iDD2N; + memPowerSpec.idd2n2 = 0; + memPowerSpec.idd3p0 = memSpecDDR4->iDD3P0; memPowerSpec.idd3p02 = 0; - memPowerSpec.idd3p1 = memSpecDDR4->iDD3P1; + memPowerSpec.idd3p1 = memSpecDDR4->iDD3P1; memPowerSpec.idd3p12 = 0; - memPowerSpec.idd3n = memSpecDDR4->iDD3N; - memPowerSpec.idd3n2 = 0; - memPowerSpec.idd4r = memSpecDDR4->iDD4R; - memPowerSpec.idd4r2 = 0; - memPowerSpec.idd4w = memSpecDDR4->iDD4W; - memPowerSpec.idd4w2 = 0; - memPowerSpec.idd5 = memSpecDDR4->iDD5; - memPowerSpec.idd52 = 0; - memPowerSpec.idd6 = memSpecDDR4->iDD6; - memPowerSpec.idd62 = memSpecDDR4->iDD62; - memPowerSpec.vdd = memSpecDDR4->vDD; - memPowerSpec.vdd2 = memSpecDDR4->vDD2; + memPowerSpec.idd3n = memSpecDDR4->iDD3N; + memPowerSpec.idd3n2 = 0; + memPowerSpec.idd4r = memSpecDDR4->iDD4R; + memPowerSpec.idd4r2 = 0; + memPowerSpec.idd4w = memSpecDDR4->iDD4W; + memPowerSpec.idd4w2 = 0; + memPowerSpec.idd5 = memSpecDDR4->iDD5; + memPowerSpec.idd52 = 0; + memPowerSpec.idd6 = memSpecDDR4->iDD6; + memPowerSpec.idd62 = memSpecDDR4->iDD62; + memPowerSpec.vdd = memSpecDDR4->vDD; + memPowerSpec.vdd2 = memSpecDDR4->vDD2; MemorySpecification powerSpec; powerSpec.id = memSpecDDR4->memoryId; powerSpec.memoryType = MemoryType::DDR4; powerSpec.memTimingSpec = memTimingSpec; - powerSpec.memPowerSpec = memPowerSpec; - powerSpec.memArchSpec = memArchSpec; + powerSpec.memPowerSpec = memPowerSpec; + powerSpec.memArchSpec = memArchSpec; DRAMPower = std::make_unique(powerSpec, false); } diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramGDDR5.cpp b/src/libdramsys/DRAMSys/simulation/dram/DramGDDR5.cpp index 82c1e8ba..376b10f4 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramGDDR5.cpp +++ b/src/libdramsys/DRAMSys/simulation/dram/DramGDDR5.cpp @@ -40,8 +40,7 @@ using namespace sc_core; namespace DRAMSys { -DramGDDR5::DramGDDR5(const sc_module_name& name, const Configuration& config) - : Dram(name, config) +DramGDDR5::DramGDDR5(const sc_module_name& name, const Configuration& config) : Dram(name, config) { #ifdef DRAMPOWER if (powerAnalysis) diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramGDDR5X.cpp b/src/libdramsys/DRAMSys/simulation/dram/DramGDDR5X.cpp index f70d5d1f..ef7a7ea1 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramGDDR5X.cpp +++ b/src/libdramsys/DRAMSys/simulation/dram/DramGDDR5X.cpp @@ -40,8 +40,7 @@ using namespace sc_core; namespace DRAMSys { -DramGDDR5X::DramGDDR5X(const sc_module_name& name, const Configuration& config) - : Dram(name, config) +DramGDDR5X::DramGDDR5X(const sc_module_name& name, const Configuration& config) : Dram(name, config) { #ifdef DRAMPOWER if (powerAnalysis) diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramGDDR6.cpp b/src/libdramsys/DRAMSys/simulation/dram/DramGDDR6.cpp index 17748162..658c1e43 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramGDDR6.cpp +++ b/src/libdramsys/DRAMSys/simulation/dram/DramGDDR6.cpp @@ -40,8 +40,7 @@ using namespace sc_core; namespace DRAMSys { -DramGDDR6::DramGDDR6(const sc_module_name& name, const Configuration& config) - : Dram(name, config) +DramGDDR6::DramGDDR6(const sc_module_name& name, const Configuration& config) : Dram(name, config) { #ifdef DRAMPOWER if (powerAnalysis) diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramHBM2.cpp b/src/libdramsys/DRAMSys/simulation/dram/DramHBM2.cpp index 89cbcfb1..7978642b 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramHBM2.cpp +++ b/src/libdramsys/DRAMSys/simulation/dram/DramHBM2.cpp @@ -40,8 +40,7 @@ using namespace sc_core; namespace DRAMSys { -DramHBM2::DramHBM2(const sc_module_name& name, const Configuration& config) - : Dram(name, config) +DramHBM2::DramHBM2(const sc_module_name& name, const Configuration& config) : Dram(name, config) { #ifdef DRAMPOWER if (powerAnalysis) diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramHBM2.h b/src/libdramsys/DRAMSys/simulation/dram/DramHBM2.h index 2a3c870d..9ce170f9 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramHBM2.h +++ b/src/libdramsys/DRAMSys/simulation/dram/DramHBM2.h @@ -45,7 +45,7 @@ namespace DRAMSys class DramHBM2 : public Dram { public: - DramHBM2(const sc_core::sc_module_name &name, const Configuration& config); + DramHBM2(const sc_core::sc_module_name& name, const Configuration& config); SC_HAS_PROCESS(DramHBM2); }; diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramLPDDR4.cpp b/src/libdramsys/DRAMSys/simulation/dram/DramLPDDR4.cpp index f6e45325..d94dc622 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramLPDDR4.cpp +++ b/src/libdramsys/DRAMSys/simulation/dram/DramLPDDR4.cpp @@ -40,8 +40,7 @@ using namespace sc_core; namespace DRAMSys { -DramLPDDR4::DramLPDDR4(const sc_module_name& name, const Configuration& config) - : Dram(name, config) +DramLPDDR4::DramLPDDR4(const sc_module_name& name, const Configuration& config) : Dram(name, config) { #ifdef DRAMPOWER if (powerAnalysis) diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramRecordable.cpp b/src/libdramsys/DRAMSys/simulation/dram/DramRecordable.cpp index 0538b909..5fe61f63 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramRecordable.cpp +++ b/src/libdramsys/DRAMSys/simulation/dram/DramRecordable.cpp @@ -35,19 +35,19 @@ #include "DramRecordable.h" +#include "DRAMSys/common/DebugManager.h" #include "DRAMSys/common/TlmRecorder.h" #include "DRAMSys/common/utils.h" -#include "DRAMSys/common/DebugManager.h" #include "DRAMSys/simulation/dram/DramDDR3.h" #include "DRAMSys/simulation/dram/DramDDR4.h" -#include "DRAMSys/simulation/dram/DramWideIO.h" -#include "DRAMSys/simulation/dram/DramLPDDR4.h" -#include "DRAMSys/simulation/dram/DramWideIO2.h" -#include "DRAMSys/simulation/dram/DramHBM2.h" #include "DRAMSys/simulation/dram/DramGDDR5.h" #include "DRAMSys/simulation/dram/DramGDDR5X.h" #include "DRAMSys/simulation/dram/DramGDDR6.h" +#include "DRAMSys/simulation/dram/DramHBM2.h" +#include "DRAMSys/simulation/dram/DramLPDDR4.h" #include "DRAMSys/simulation/dram/DramSTTMRAM.h" +#include "DRAMSys/simulation/dram/DramWideIO.h" +#include "DRAMSys/simulation/dram/DramWideIO2.h" #ifdef DDR5_SIM #include "DRAMSys/simulation/dram/DramDDR5.h" @@ -65,10 +65,12 @@ using namespace tlm; namespace DRAMSys { -template -DramRecordable::DramRecordable(const sc_module_name& name, const Configuration& config, - TlmRecorder& tlmRecorder) - : BaseDram(name, config), tlmRecorder(tlmRecorder), +template +DramRecordable::DramRecordable(const sc_module_name& name, + const Configuration& config, + TlmRecorder& tlmRecorder) : + BaseDram(name, config), + tlmRecorder(tlmRecorder), powerWindowSize(config.memSpec->tCK * config.windowSize) { #ifdef DRAMPOWER @@ -79,20 +81,20 @@ DramRecordable::DramRecordable(const sc_module_name& name, const Confi #endif } -template -void DramRecordable::reportPower() +template void DramRecordable::reportPower() { BaseDram::reportPower(); #ifdef DRAMPOWER tlmRecorder.recordPower(sc_time_stamp().to_seconds(), - this->DRAMPower->getPower().window_average_power - * this->memSpec.devicesPerRank); -#endif + this->DRAMPower->getPower().window_average_power * + this->memSpec.devicesPerRank); +#endif } -template +template tlm_sync_enum DramRecordable::nb_transport_fw(tlm_generic_payload& trans, - tlm_phase &phase, sc_time &delay) + tlm_phase& phase, + sc_time& delay) { tlmRecorder.recordPhase(trans, phase, delay); return BaseDram::nb_transport_fw(trans, phase, delay); @@ -100,9 +102,9 @@ tlm_sync_enum DramRecordable::nb_transport_fw(tlm_generic_payload& tra #ifdef DRAMPOWER // This Thread is only triggered when Power Simulation is enabled. -// It estimates the current average power which will be stored in the trace database for visualization purposes. -template -void DramRecordable::powerWindow() +// It estimates the current average power which will be stored in the trace database for +// visualization purposes. +template void DramRecordable::powerWindow() { int64_t clkCycles = 0; @@ -120,17 +122,20 @@ void DramRecordable::powerWindow() // Store the time (in seconds) and the current average power (in mW) into the database tlmRecorder.recordPower(sc_time_stamp().to_seconds(), - this->DRAMPower->getPower().window_average_power - * this->memSpec.devicesPerRank); + this->DRAMPower->getPower().window_average_power * + this->memSpec.devicesPerRank); // Here considering that DRAMPower provides the energy in pJ and the power in mW - PRINTDEBUGMESSAGE(this->name(), std::string("\tWindow Energy: \t") + std::to_string( - this->DRAMPower->getEnergy().window_energy * - this->memSpec.devicesPerRank) + std::string("\t[pJ]")); - PRINTDEBUGMESSAGE(this->name(), std::string("\tWindow Average Power: \t") + std::to_string( - this->DRAMPower->getPower().window_average_power * - this->memSpec.devicesPerRank) + std::string("\t[mW]")); - + PRINTDEBUGMESSAGE(this->name(), + std::string("\tWindow Energy: \t") + + std::to_string(this->DRAMPower->getEnergy().window_energy * + this->memSpec.devicesPerRank) + + std::string("\t[pJ]")); + PRINTDEBUGMESSAGE(this->name(), + std::string("\tWindow Average Power: \t") + + std::to_string(this->DRAMPower->getPower().window_average_power * + this->memSpec.devicesPerRank) + + std::string("\t[mW]")); } } #endif diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramRecordable.h b/src/libdramsys/DRAMSys/simulation/dram/DramRecordable.h index 9cc0ef5a..6d0e8711 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramRecordable.h +++ b/src/libdramsys/DRAMSys/simulation/dram/DramRecordable.h @@ -49,18 +49,20 @@ namespace DRAMSys { -template -class DramRecordable final : public BaseDram +template class DramRecordable final : public BaseDram { public: - DramRecordable(const sc_core::sc_module_name& name, const Configuration& config, TlmRecorder& tlmRecorder); + DramRecordable(const sc_core::sc_module_name& name, + const Configuration& config, + TlmRecorder& tlmRecorder); SC_HAS_PROCESS(DramRecordable); void reportPower() override; private: tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& trans, - tlm::tlm_phase& phase, sc_core::sc_time& delay) override; + tlm::tlm_phase& phase, + sc_core::sc_time& delay) override; TlmRecorder& tlmRecorder; @@ -76,7 +78,8 @@ private: #ifdef DRAMPOWER // This Thread is only triggered when Power Simulation is enabled. - // It estimates the current average power which will be stored in the trace database for visualization purposes. + // It estimates the current average power which will be stored in the trace database for + // visualization purposes. void powerWindow(); #endif }; diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramSTTMRAM.cpp b/src/libdramsys/DRAMSys/simulation/dram/DramSTTMRAM.cpp index f0711688..27acfb34 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramSTTMRAM.cpp +++ b/src/libdramsys/DRAMSys/simulation/dram/DramSTTMRAM.cpp @@ -40,8 +40,8 @@ using namespace sc_core; namespace DRAMSys { -DramSTTMRAM::DramSTTMRAM(const sc_module_name& name, const Configuration& config) - : Dram(name, config) +DramSTTMRAM::DramSTTMRAM(const sc_module_name& name, const Configuration& config) : + Dram(name, config) { #ifdef DRAMPOWER if (powerAnalysis) diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramWideIO.cpp b/src/libdramsys/DRAMSys/simulation/dram/DramWideIO.cpp index c7af9a45..94e8d17d 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramWideIO.cpp +++ b/src/libdramsys/DRAMSys/simulation/dram/DramWideIO.cpp @@ -49,101 +49,100 @@ using namespace tlm; namespace DRAMSys { -DramWideIO::DramWideIO(const sc_module_name& name, const Configuration& config) - : Dram(name, config) +DramWideIO::DramWideIO(const sc_module_name& name, const Configuration& config) : Dram(name, config) { #ifdef DRAMPOWER if (powerAnalysis) { - const auto* memSpecWideIO = dynamic_cast(config.memSpec.get()); + const auto* memSpecWideIO = dynamic_cast(config.memSpec.get()); if (memSpecWideIO == nullptr) SC_REPORT_FATAL("DramWideIO", "Wrong MemSpec chosen"); MemArchitectureSpec memArchSpec; - memArchSpec.burstLength = memSpecWideIO->defaultBurstLength; - memArchSpec.dataRate = memSpecWideIO->dataRate; - memArchSpec.nbrOfRows = memSpecWideIO->rowsPerBank; - memArchSpec.nbrOfBanks = memSpecWideIO->banksPerChannel; - memArchSpec.nbrOfColumns = memSpecWideIO->columnsPerRow; - memArchSpec.nbrOfRanks = memSpecWideIO->ranksPerChannel; - memArchSpec.width = memSpecWideIO->bitWidth; - memArchSpec.nbrOfBankGroups = memSpecWideIO->bankGroupsPerChannel; + memArchSpec.burstLength = memSpecWideIO->defaultBurstLength; + memArchSpec.dataRate = memSpecWideIO->dataRate; + memArchSpec.nbrOfRows = memSpecWideIO->rowsPerBank; + memArchSpec.nbrOfBanks = memSpecWideIO->banksPerChannel; + memArchSpec.nbrOfColumns = memSpecWideIO->columnsPerRow; + memArchSpec.nbrOfRanks = memSpecWideIO->ranksPerChannel; + memArchSpec.width = memSpecWideIO->bitWidth; + memArchSpec.nbrOfBankGroups = memSpecWideIO->bankGroupsPerChannel; memArchSpec.twoVoltageDomains = true; - memArchSpec.dll = false; + memArchSpec.dll = false; MemTimingSpec memTimingSpec; - //FIXME: memTimingSpec.FAWB = memSpecWideIO->tTAW / memSpecWideIO->tCK; - //FIXME: memTimingSpec.RASB = memSpecWideIO->tRAS / memSpecWideIO->tCK; - //FIXME: memTimingSpec.RCB = memSpecWideIO->tRC / memSpecWideIO->tCK; - //FIXME: memTimingSpec.RPB = memSpecWideIO->tRP / memSpecWideIO->tCK; - //FIXME: memTimingSpec.RRDB = memSpecWideIO->tRRD / memSpecWideIO->tCK; - //FIXME: memTimingSpec.RRDB_L = memSpecWideIO->tRRD / memSpecWideIO->tCK; - //FIXME: memTimingSpec.RRDB_S = memSpecWideIO->tRRD / memSpecWideIO->tCK; - memTimingSpec.AL = 0; - memTimingSpec.CCD = memSpecWideIO->defaultBurstLength; - memTimingSpec.CCD_L = memSpecWideIO->defaultBurstLength; - memTimingSpec.CCD_S = memSpecWideIO->defaultBurstLength; - memTimingSpec.CKE = memSpecWideIO->tCKE / memSpecWideIO->tCK; - memTimingSpec.CKESR = memSpecWideIO->tCKESR / memSpecWideIO->tCK; + // FIXME: memTimingSpec.FAWB = memSpecWideIO->tTAW / memSpecWideIO->tCK; + // FIXME: memTimingSpec.RASB = memSpecWideIO->tRAS / memSpecWideIO->tCK; + // FIXME: memTimingSpec.RCB = memSpecWideIO->tRC / memSpecWideIO->tCK; + // FIXME: memTimingSpec.RPB = memSpecWideIO->tRP / memSpecWideIO->tCK; + // FIXME: memTimingSpec.RRDB = memSpecWideIO->tRRD / memSpecWideIO->tCK; + // FIXME: memTimingSpec.RRDB_L = memSpecWideIO->tRRD / memSpecWideIO->tCK; + // FIXME: memTimingSpec.RRDB_S = memSpecWideIO->tRRD / memSpecWideIO->tCK; + memTimingSpec.AL = 0; + memTimingSpec.CCD = memSpecWideIO->defaultBurstLength; + memTimingSpec.CCD_L = memSpecWideIO->defaultBurstLength; + memTimingSpec.CCD_S = memSpecWideIO->defaultBurstLength; + memTimingSpec.CKE = memSpecWideIO->tCKE / memSpecWideIO->tCK; + memTimingSpec.CKESR = memSpecWideIO->tCKESR / memSpecWideIO->tCK; memTimingSpec.clkMhz = memSpecWideIO->fCKMHz; // See also MemTimingSpec.cc in DRAMPower memTimingSpec.clkPeriod = 1000.0 / memSpecWideIO->fCKMHz; - memTimingSpec.DQSCK = memSpecWideIO->tDQSCK / memSpecWideIO->tCK; - memTimingSpec.FAW = memSpecWideIO->tTAW / memSpecWideIO->tCK; - memTimingSpec.RAS = memSpecWideIO->tRAS / memSpecWideIO->tCK; - memTimingSpec.RC = memSpecWideIO->tRC / memSpecWideIO->tCK; - memTimingSpec.RCD = memSpecWideIO->tRCD / memSpecWideIO->tCK; - memTimingSpec.REFI = memSpecWideIO->tREFI / memSpecWideIO->tCK; - memTimingSpec.RFC = memSpecWideIO->tRFC / memSpecWideIO->tCK; - memTimingSpec.RL = memSpecWideIO->tRL / memSpecWideIO->tCK; - memTimingSpec.RP = memSpecWideIO->tRP / memSpecWideIO->tCK; - memTimingSpec.RRD = memSpecWideIO->tRRD / memSpecWideIO->tCK; - memTimingSpec.RRD_L = memSpecWideIO->tRRD / memSpecWideIO->tCK; - memTimingSpec.RRD_S = memSpecWideIO->tRRD / memSpecWideIO->tCK; - memTimingSpec.RTP = memSpecWideIO->defaultBurstLength; - memTimingSpec.TAW = memSpecWideIO->tTAW / memSpecWideIO->tCK; - memTimingSpec.WL = memSpecWideIO->tWL / memSpecWideIO->tCK; - memTimingSpec.WR = memSpecWideIO->tWR / memSpecWideIO->tCK; - memTimingSpec.WTR = memSpecWideIO->tWTR / memSpecWideIO->tCK; - memTimingSpec.WTR_L = memSpecWideIO->tWTR / memSpecWideIO->tCK; - memTimingSpec.WTR_S = memSpecWideIO->tWTR / memSpecWideIO->tCK; - memTimingSpec.XP = memSpecWideIO->tXP / memSpecWideIO->tCK; - memTimingSpec.XPDLL = memSpecWideIO->tXP / memSpecWideIO->tCK; - memTimingSpec.XS = memSpecWideIO->tXSR / memSpecWideIO->tCK; - memTimingSpec.XSDLL = memSpecWideIO->tXSR / memSpecWideIO->tCK; + memTimingSpec.DQSCK = memSpecWideIO->tDQSCK / memSpecWideIO->tCK; + memTimingSpec.FAW = memSpecWideIO->tTAW / memSpecWideIO->tCK; + memTimingSpec.RAS = memSpecWideIO->tRAS / memSpecWideIO->tCK; + memTimingSpec.RC = memSpecWideIO->tRC / memSpecWideIO->tCK; + memTimingSpec.RCD = memSpecWideIO->tRCD / memSpecWideIO->tCK; + memTimingSpec.REFI = memSpecWideIO->tREFI / memSpecWideIO->tCK; + memTimingSpec.RFC = memSpecWideIO->tRFC / memSpecWideIO->tCK; + memTimingSpec.RL = memSpecWideIO->tRL / memSpecWideIO->tCK; + memTimingSpec.RP = memSpecWideIO->tRP / memSpecWideIO->tCK; + memTimingSpec.RRD = memSpecWideIO->tRRD / memSpecWideIO->tCK; + memTimingSpec.RRD_L = memSpecWideIO->tRRD / memSpecWideIO->tCK; + memTimingSpec.RRD_S = memSpecWideIO->tRRD / memSpecWideIO->tCK; + memTimingSpec.RTP = memSpecWideIO->defaultBurstLength; + memTimingSpec.TAW = memSpecWideIO->tTAW / memSpecWideIO->tCK; + memTimingSpec.WL = memSpecWideIO->tWL / memSpecWideIO->tCK; + memTimingSpec.WR = memSpecWideIO->tWR / memSpecWideIO->tCK; + memTimingSpec.WTR = memSpecWideIO->tWTR / memSpecWideIO->tCK; + memTimingSpec.WTR_L = memSpecWideIO->tWTR / memSpecWideIO->tCK; + memTimingSpec.WTR_S = memSpecWideIO->tWTR / memSpecWideIO->tCK; + memTimingSpec.XP = memSpecWideIO->tXP / memSpecWideIO->tCK; + memTimingSpec.XPDLL = memSpecWideIO->tXP / memSpecWideIO->tCK; + memTimingSpec.XS = memSpecWideIO->tXSR / memSpecWideIO->tCK; + memTimingSpec.XSDLL = memSpecWideIO->tXSR / memSpecWideIO->tCK; - MemPowerSpec memPowerSpec; - memPowerSpec.idd0 = memSpecWideIO->iDD0; - memPowerSpec.idd02 = memSpecWideIO->iDD02; - memPowerSpec.idd2p0 = memSpecWideIO->iDD2P0; + MemPowerSpec memPowerSpec; + memPowerSpec.idd0 = memSpecWideIO->iDD0; + memPowerSpec.idd02 = memSpecWideIO->iDD02; + memPowerSpec.idd2p0 = memSpecWideIO->iDD2P0; memPowerSpec.idd2p02 = memSpecWideIO->iDD2P02; - memPowerSpec.idd2p1 = memSpecWideIO->iDD2P1; + memPowerSpec.idd2p1 = memSpecWideIO->iDD2P1; memPowerSpec.idd2p12 = memSpecWideIO->iDD2P12; - memPowerSpec.idd2n = memSpecWideIO->iDD2N; - memPowerSpec.idd2n2 = memSpecWideIO->iDD2N2; - memPowerSpec.idd3p0 = memSpecWideIO->iDD3P0; + memPowerSpec.idd2n = memSpecWideIO->iDD2N; + memPowerSpec.idd2n2 = memSpecWideIO->iDD2N2; + memPowerSpec.idd3p0 = memSpecWideIO->iDD3P0; memPowerSpec.idd3p02 = memSpecWideIO->iDD3P02; - memPowerSpec.idd3p1 = memSpecWideIO->iDD3P1; + memPowerSpec.idd3p1 = memSpecWideIO->iDD3P1; memPowerSpec.idd3p12 = memSpecWideIO->iDD3P12; - memPowerSpec.idd3n = memSpecWideIO->iDD3N; - memPowerSpec.idd3n2 = memSpecWideIO->iDD3N2; - memPowerSpec.idd4r = memSpecWideIO->iDD4R; - memPowerSpec.idd4r2 = memSpecWideIO->iDD4R2; - memPowerSpec.idd4w = memSpecWideIO->iDD4W; - memPowerSpec.idd4w2 = memSpecWideIO->iDD4W2; - memPowerSpec.idd5 = memSpecWideIO->iDD5; - memPowerSpec.idd52 = memSpecWideIO->iDD52; - memPowerSpec.idd6 = memSpecWideIO->iDD6; - memPowerSpec.idd62 = memSpecWideIO->iDD62; - memPowerSpec.vdd = memSpecWideIO->vDD; - memPowerSpec.vdd2 = memSpecWideIO->vDD2; + memPowerSpec.idd3n = memSpecWideIO->iDD3N; + memPowerSpec.idd3n2 = memSpecWideIO->iDD3N2; + memPowerSpec.idd4r = memSpecWideIO->iDD4R; + memPowerSpec.idd4r2 = memSpecWideIO->iDD4R2; + memPowerSpec.idd4w = memSpecWideIO->iDD4W; + memPowerSpec.idd4w2 = memSpecWideIO->iDD4W2; + memPowerSpec.idd5 = memSpecWideIO->iDD5; + memPowerSpec.idd52 = memSpecWideIO->iDD52; + memPowerSpec.idd6 = memSpecWideIO->iDD6; + memPowerSpec.idd62 = memSpecWideIO->iDD62; + memPowerSpec.vdd = memSpecWideIO->vDD; + memPowerSpec.vdd2 = memSpecWideIO->vDD2; MemorySpecification powerSpec; powerSpec.id = memSpecWideIO->memoryId; powerSpec.memoryType = MemoryType::WIDEIO_SDR; powerSpec.memTimingSpec = memTimingSpec; - powerSpec.memPowerSpec = memPowerSpec; - powerSpec.memArchSpec = memArchSpec; + powerSpec.memPowerSpec = memPowerSpec; + powerSpec.memArchSpec = memArchSpec; DRAMPower = std::make_unique(powerSpec, false); } diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramWideIO2.cpp b/src/libdramsys/DRAMSys/simulation/dram/DramWideIO2.cpp index eaac0f36..ca76890e 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramWideIO2.cpp +++ b/src/libdramsys/DRAMSys/simulation/dram/DramWideIO2.cpp @@ -40,8 +40,8 @@ using namespace sc_core; namespace DRAMSys { -DramWideIO2::DramWideIO2(const sc_module_name& name, const Configuration& config) - : Dram(name, config) +DramWideIO2::DramWideIO2(const sc_module_name& name, const Configuration& config) : + Dram(name, config) { #ifdef DRAMPOWER if (config.powerAnalysis) diff --git a/src/simulator/simulator/Cache.cpp b/src/simulator/simulator/Cache.cpp index a5ed222c..d3319e33 100644 --- a/src/simulator/simulator/Cache.cpp +++ b/src/simulator/simulator/Cache.cpp @@ -45,7 +45,7 @@ using namespace sc_core; DECLARE_EXTENDED_PHASE(HIT_HANDLING); DECLARE_EXTENDED_PHASE(MISS_HANDLING); -Cache::Cache(const sc_module_name &name, +Cache::Cache(const sc_module_name& name, std::size_t size, std::size_t associativity, std::size_t lineSize, @@ -55,7 +55,7 @@ Cache::Cache(const sc_module_name &name, bool storageEnabled, sc_core::sc_time cycleTime, std::size_t hitCycles, - MemoryManager &memoryManager) : + MemoryManager& memoryManager) : sc_module(name), payloadEventQueue(this, &Cache::peqCallback), storageEnabled(storageEnabled), @@ -76,7 +76,8 @@ Cache::Cache(const sc_module_name &name, iSocket.register_nb_transport_bw(this, &Cache::nb_transport_bw); tSocket.register_nb_transport_fw(this, &Cache::nb_transport_fw); - lineTable = std::vector>(numberOfSets, std::vector(associativity)); + lineTable = + std::vector>(numberOfSets, std::vector(associativity)); if (storageEnabled) { @@ -85,18 +86,22 @@ Cache::Cache(const sc_module_name &name, for (std::size_t set = 0; set < lineTable.size(); set++) { for (std::size_t way = 0; way < lineTable[set].size(); way++) - lineTable[set][way].dataPtr = dataMemory.data() + set * associativity * lineSize + way * lineSize; + lineTable[set][way].dataPtr = + dataMemory.data() + set * associativity * lineSize + way * lineSize; } } } -tlm_sync_enum Cache::nb_transport_fw(tlm_generic_payload &trans, tlm_phase &phase, sc_time &delay) // core side ---> +tlm_sync_enum Cache::nb_transport_fw(tlm_generic_payload& trans, + tlm_phase& phase, + sc_time& delay) // core side ---> { if (phase == BEGIN_REQ) { if (trans.get_data_length() > lineSize) { - SC_REPORT_FATAL(name(), "Accesses larger than line size in non-blocking mode not supported!"); + SC_REPORT_FATAL(name(), + "Accesses larger than line size in non-blocking mode not supported!"); } trans.acquire(); @@ -108,7 +113,9 @@ tlm_sync_enum Cache::nb_transport_fw(tlm_generic_payload &trans, tlm_phase &phas return TLM_ACCEPTED; } -tlm_sync_enum Cache::nb_transport_bw(tlm_generic_payload &trans, tlm_phase &phase, sc_time &bwDelay) // DRAM side <--- +tlm_sync_enum Cache::nb_transport_bw(tlm_generic_payload& trans, + tlm_phase& phase, + sc_time& bwDelay) // DRAM side <--- { // TODO: early completion would be possible payloadEventQueue.notify(trans, phase, ceilDelay(bwDelay)); @@ -116,7 +123,7 @@ tlm_sync_enum Cache::nb_transport_bw(tlm_generic_payload &trans, tlm_phase &phas return TLM_ACCEPTED; } -void Cache::peqCallback(tlm_generic_payload &trans, const tlm_phase &phase) +void Cache::peqCallback(tlm_generic_payload& trans, const tlm_phase& phase) { if (phase == BEGIN_REQ) // core side ---> { @@ -151,7 +158,7 @@ void Cache::peqCallback(tlm_generic_payload &trans, const tlm_phase &phase) clearTargetBackpressureAndProcessLines(trans); return; } - + if (phase == HIT_HANDLING) // direct hit, account for the hit delay { index_t index = 0; @@ -169,8 +176,10 @@ void Cache::peqCallback(tlm_generic_payload &trans, const tlm_phase &phase) tag_t tag = 0; std::tie(index, tag, std::ignore) = decodeAddress(trans.get_address()); - auto mshrIt = std::find_if(mshrQueue.begin(), mshrQueue.end(), - [index, tag](const Mshr &mshr) { return mshr.index == index && mshr.tag == tag; }); + auto mshrIt = std::find_if(mshrQueue.begin(), + mshrQueue.end(), + [index, tag](const Mshr& mshr) + { return mshr.index == index && mshr.tag == tag; }); assert(mshrIt != mshrQueue.end()); mshrIt->hitDelayAccounted = true; @@ -193,7 +202,7 @@ void Cache::peqCallback(tlm_generic_payload &trans, const tlm_phase &phase) } /// Handler for begin request from core side. -void Cache::fetchLineAndSendEndRequest(tlm_generic_payload &trans) +void Cache::fetchLineAndSendEndRequest(tlm_generic_payload& trans) { if (hasBufferSpace()) { @@ -201,9 +210,10 @@ void Cache::fetchLineAndSendEndRequest(tlm_generic_payload &trans) tag_t tag = 0; std::tie(index, tag, std::ignore) = decodeAddress(trans.get_address()); - auto mshrEntry = - std::find_if(mshrQueue.begin(), mshrQueue.end(), - [index, tag](const Mshr &entry) { return (index == entry.index) && (tag == entry.tag); }); + auto mshrEntry = std::find_if(mshrQueue.begin(), + mshrQueue.end(), + [index, tag](const Mshr& entry) + { return (index == entry.index) && (tag == entry.tag); }); if (isHit(index, tag)) { @@ -237,7 +247,7 @@ void Cache::fetchLineAndSendEndRequest(tlm_generic_payload &trans) // Cache miss and no fetch in progress. // So evict line and allocate empty line. - auto *evictedLine = evictLine(index); + auto* evictedLine = evictLine(index); if (evictedLine == nullptr) { // Line eviction not possible. @@ -272,7 +282,7 @@ void Cache::clearInitiatorBackpressureAndProcessBuffers() } /// Handler for begin response from DRAM side. -void Cache::sendEndResponseAndFillLine(tlm_generic_payload &trans) +void Cache::sendEndResponseAndFillLine(tlm_generic_payload& trans) { tlm_phase fwPhase = END_RESP; sc_time fwDelay = SC_ZERO_TIME; @@ -288,7 +298,7 @@ void Cache::sendEndResponseAndFillLine(tlm_generic_payload &trans) } /// Handler for end response from core side. -void Cache::clearTargetBackpressureAndProcessLines(tlm_generic_payload &trans) +void Cache::clearTargetBackpressureAndProcessLines(tlm_generic_payload& trans) { trans.release(); tSocketBackpressure = false; @@ -307,16 +317,18 @@ void Cache::clearTargetBackpressureAndProcessLines(tlm_generic_payload &trans) } } -unsigned int Cache::transport_dbg(tlm_generic_payload &trans) +unsigned int Cache::transport_dbg(tlm_generic_payload& trans) { return iSocket->transport_dbg(trans); } bool Cache::isHit(index_t index, tag_t tag) const { - return std::find_if(lineTable[index].begin(), lineTable[index].end(), - [tag](const CacheLine &cacheLine) - { return (cacheLine.tag == tag) && cacheLine.valid; }) != lineTable[index].end(); + return std::find_if(lineTable[index].begin(), + lineTable[index].end(), + [tag](const CacheLine& cacheLine) { + return (cacheLine.tag == tag) && cacheLine.valid; + }) != lineTable[index].end(); } bool Cache::isHit(uint64_t address) const @@ -328,24 +340,31 @@ bool Cache::isHit(uint64_t address) const return isHit(index, tag); } -std::tuple Cache::decodeAddress(uint64_t address) const +std::tuple +Cache::decodeAddress(uint64_t address) const { return {(address >> indexShifts) & indexMask, address >> tagShifts, address % lineSize}; } -uint64_t Cache::encodeAddress(Cache::index_t index, Cache::tag_t tag, Cache::lineOffset_t lineOffset) const +uint64_t +Cache::encodeAddress(Cache::index_t index, Cache::tag_t tag, Cache::lineOffset_t lineOffset) const { return static_cast(tag << tagShifts) | index << indexShifts | lineOffset; } /// Write data to an available cache line, update flags -void Cache::writeLine( - index_t index, tag_t tag, lineOffset_t lineOffset, unsigned int dataLength, const unsigned char *dataPtr) +void Cache::writeLine(index_t index, + tag_t tag, + lineOffset_t lineOffset, + unsigned int dataLength, + const unsigned char* dataPtr) { // SC_REPORT_ERROR("cache", "Write to Cache not allowed!"); - CacheLine ¤tLine = *std::find_if(lineTable[index].begin(), lineTable[index].end(), - [tag](const CacheLine &cacheLine) { return cacheLine.tag == tag; }); + CacheLine& currentLine = + *std::find_if(lineTable[index].begin(), + lineTable[index].end(), + [tag](const CacheLine& cacheLine) { return cacheLine.tag == tag; }); assert(currentLine.valid); currentLine.lastAccessTime = sc_time_stamp(); @@ -356,24 +375,33 @@ void Cache::writeLine( } /// Read data from an available cache line, update flags -void Cache::readLine(index_t index, tag_t tag, lineOffset_t lineOffset, unsigned int dataLength, unsigned char *dataPtr) +void Cache::readLine(index_t index, + tag_t tag, + lineOffset_t lineOffset, + unsigned int dataLength, + unsigned char* dataPtr) { - CacheLine ¤tLine = *std::find_if(lineTable[index].begin(), lineTable[index].end(), - [tag](const CacheLine &cacheLine) { return cacheLine.tag == tag; }); + CacheLine& currentLine = + *std::find_if(lineTable[index].begin(), + lineTable[index].end(), + [tag](const CacheLine& cacheLine) { return cacheLine.tag == tag; }); assert(currentLine.valid); currentLine.lastAccessTime = sc_time_stamp(); if (storageEnabled) - std::copy(currentLine.dataPtr + lineOffset, currentLine.dataPtr + lineOffset + dataLength, dataPtr); + std::copy(currentLine.dataPtr + lineOffset, + currentLine.dataPtr + lineOffset + dataLength, + dataPtr); } /// Tries to evict oldest line (insert into write memory) /// Returns the line or a nullptr if not possible -Cache::CacheLine *Cache::evictLine(Cache::index_t index) +Cache::CacheLine* Cache::evictLine(Cache::index_t index) { - CacheLine &oldestLine = *std::min_element(lineTable[index].begin(), lineTable[index].end(), - [](const CacheLine &lhs, const CacheLine &rhs) + CacheLine& oldestLine = *std::min_element(lineTable[index].begin(), + lineTable[index].end(), + [](const CacheLine& lhs, const CacheLine& rhs) { return lhs.lastAccessTime < rhs.lastAccessTime; }); if (oldestLine.allocated && !oldestLine.valid) @@ -383,7 +411,7 @@ Cache::CacheLine *Cache::evictLine(Cache::index_t index) } if (std::find_if(mshrQueue.begin(), mshrQueue.end(), - [index, oldestLine](const Mshr &entry) { + [index, oldestLine](const Mshr& entry) { return (index == entry.index) && (oldestLine.tag == entry.tag); }) != mshrQueue.end()) { @@ -391,9 +419,11 @@ Cache::CacheLine *Cache::evictLine(Cache::index_t index) // There are still entries in mshrQueue to the oldest line -> do not evict it return nullptr; } - if (std::find_if(hitQueue.begin(), hitQueue.end(), - [index, oldestLine](const BufferEntry &entry) - { return (index == entry.index) && (oldestLine.tag == entry.tag); }) != hitQueue.end()) + if (std::find_if(hitQueue.begin(), + hitQueue.end(), + [index, oldestLine](const BufferEntry& entry) { + return (index == entry.index) && (oldestLine.tag == entry.tag); + }) != hitQueue.end()) { // TODO: solve this in a more clever way // There are still hits in hitQueue to the oldest line -> do not evict it @@ -402,7 +432,7 @@ Cache::CacheLine *Cache::evictLine(Cache::index_t index) if (oldestLine.valid && oldestLine.dirty) { - auto &wbTrans = memoryManager.allocate(lineSize); + auto& wbTrans = memoryManager.allocate(lineSize); wbTrans.acquire(); wbTrans.set_address(encodeAddress(index, oldestLine.tag)); wbTrans.set_write(); @@ -434,7 +464,8 @@ void Cache::processMshrQueue() if ((requestInProgress == nullptr) && !mshrQueue.empty()) { // Get the first entry that wasn't already issued to the target - auto mshrIt = std::find_if(mshrQueue.begin(), mshrQueue.end(), [](const Mshr &entry) { return !entry.issued; }); + auto mshrIt = std::find_if( + mshrQueue.begin(), mshrQueue.end(), [](const Mshr& entry) { return !entry.issued; }); if (mshrIt == mshrQueue.end()) return; @@ -447,9 +478,11 @@ void Cache::processMshrQueue() std::tie(index, tag, std::ignore) = decodeAddress(alignedAddress); // Search through the writeBuffer in reverse order to get the most recent entry. - auto writeBufferEntry = std::find_if(writeBuffer.rbegin(), writeBuffer.rbegin(), - [index, tag](const BufferEntry &entry) - { return (index == entry.index) && (tag == entry.tag); }); + auto writeBufferEntry = + std::find_if(writeBuffer.rbegin(), + writeBuffer.rbegin(), + [index, tag](const BufferEntry& entry) + { return (index == entry.index) && (tag == entry.tag); }); if (writeBufferEntry != writeBuffer.rbegin()) { @@ -467,7 +500,7 @@ void Cache::processMshrQueue() // Prevents that the cache line will get fetched multiple times from the target mshrIt->issued = true; - auto &fetchTrans = memoryManager.allocate(lineSize); + auto& fetchTrans = memoryManager.allocate(lineSize); fetchTrans.acquire(); fetchTrans.set_read(); fetchTrans.set_data_length(lineSize); @@ -512,7 +545,7 @@ void Cache::processWriteBuffer() { if ((requestInProgress == nullptr) && !writeBuffer.empty()) { - tlm_generic_payload &wbTrans = *writeBuffer.front().trans; + tlm_generic_payload& wbTrans = *writeBuffer.front().trans; tlm_phase fwPhase = BEGIN_REQ; sc_time fwDelay = (lastEndReq == sc_time_stamp()) ? cycleTime : SC_ZERO_TIME; @@ -542,15 +575,16 @@ void Cache::processWriteBuffer() } /// Fill allocated cache line with data from memory -void Cache::fillLine(tlm_generic_payload &trans) +void Cache::fillLine(tlm_generic_payload& trans) { index_t index = 0; tag_t tag = 0; std::tie(index, tag, std::ignore) = decodeAddress(trans.get_address()); - CacheLine &allocatedLine = - *std::find_if(lineTable[index].begin(), lineTable[index].end(), - [tag](const CacheLine &cacheLine) { return cacheLine.allocated && cacheLine.tag == tag; }); + CacheLine& allocatedLine = *std::find_if( + lineTable[index].begin(), + lineTable[index].end(), + [tag](const CacheLine& cacheLine) { return cacheLine.allocated && cacheLine.tag == tag; }); allocatedLine.valid = true; allocatedLine.dirty = false; @@ -572,7 +606,7 @@ void Cache::processHitQueue() } /// Access the available cache line and send the response -void Cache::accessCacheAndSendResponse(tlm_generic_payload &trans) +void Cache::accessCacheAndSendResponse(tlm_generic_payload& trans) { assert(!tSocketBackpressure); assert(isHit(trans.get_address())); @@ -597,28 +631,34 @@ void Cache::accessCacheAndSendResponse(tlm_generic_payload &trans) } /// Allocates an empty line for later filling (lastAccessTime = sc_max_time()) -void Cache::allocateLine(CacheLine *line, tag_t tag) +void Cache::allocateLine(CacheLine* line, tag_t tag) { line->allocated = true; line->tag = tag; line->lastAccessTime = sc_max_time(); } -/// Checks whether a line with the corresponding tag is already allocated (fetch in progress or already valid) +/// Checks whether a line with the corresponding tag is already allocated (fetch in progress or +/// already valid) bool Cache::isAllocated(Cache::index_t index, Cache::tag_t tag) const { - return std::find_if(lineTable[index].begin(), lineTable[index].end(), - [tag](const CacheLine &cacheLine) - { return (cacheLine.tag == tag) && cacheLine.allocated; }) != lineTable[index].end(); + return std::find_if(lineTable[index].begin(), + lineTable[index].end(), + [tag](const CacheLine& cacheLine) { + return (cacheLine.tag == tag) && cacheLine.allocated; + }) != lineTable[index].end(); } /// Process oldest hit in mshrQueue, accept pending request from initiator void Cache::processMshrResponse() { - if (!tSocketBackpressure) // TODO: Bedingung eigentlich zu streng, wenn man Hit delay berücksichtigt. + if (!tSocketBackpressure) // TODO: Bedingung eigentlich zu streng, wenn man Hit delay + // berücksichtigt. { - const auto hitIt = std::find_if(mshrQueue.begin(), mshrQueue.end(), - [this](const Mshr &entry) { return isHit(entry.index, entry.tag); }); + const auto hitIt = + std::find_if(mshrQueue.begin(), + mshrQueue.end(), + [this](const Mshr& entry) { return isHit(entry.index, entry.tag); }); // In case there are hits in mshrActive, handle them. Otherwise try again later. if (hitIt == mshrQueue.end()) @@ -630,7 +670,7 @@ void Cache::processMshrResponse() return; // Get the first request in the list and respond to it - tlm_generic_payload &returnTrans = *hitIt->requestList.front(); + tlm_generic_payload& returnTrans = *hitIt->requestList.front(); hitIt->requestList.pop_front(); if (hitIt->hitDelayAccounted) @@ -661,12 +701,12 @@ bool Cache::hasBufferSpace() const return mshrQueue.size() < mshrDepth && writeBuffer.size() < writeBufferDepth; } -sc_time Cache::ceilTime(const sc_time &inTime) const +sc_time Cache::ceilTime(const sc_time& inTime) const { return std::ceil(inTime / cycleTime) * cycleTime; } -sc_time Cache::ceilDelay(const sc_time &inDelay) const +sc_time Cache::ceilDelay(const sc_time& inDelay) const { sc_time inTime = sc_time_stamp() + inDelay; sc_time outTime = ceilTime(inTime); diff --git a/src/simulator/simulator/Cache.h b/src/simulator/simulator/Cache.h index f714bd09..504b76db 100644 --- a/src/simulator/simulator/Cache.h +++ b/src/simulator/simulator/Cache.h @@ -53,7 +53,7 @@ public: tlm_utils::simple_initiator_socket iSocket; tlm_utils::simple_target_socket tSocket; - Cache(const sc_core::sc_module_name &name, + Cache(const sc_core::sc_module_name& name, std::size_t size, std::size_t associativity, std::size_t lineSize, @@ -63,24 +63,24 @@ public: bool storageEnabled, sc_core::sc_time cycleTime, std::size_t hitCycles, - MemoryManager &memoryManager); + MemoryManager& memoryManager); SC_HAS_PROCESS(Cache); private: - void peqCallback(tlm::tlm_generic_payload &trans, const tlm::tlm_phase &phase); + void peqCallback(tlm::tlm_generic_payload& trans, const tlm::tlm_phase& phase); - tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &trans, - tlm::tlm_phase &phase, - sc_core::sc_time &fwDelay); - tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &trans, - tlm::tlm_phase &phase, - sc_core::sc_time &bwDelay); - unsigned int transport_dbg(tlm::tlm_generic_payload &trans); + tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& trans, + tlm::tlm_phase& phase, + sc_core::sc_time& fwDelay); + tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload& trans, + tlm::tlm_phase& phase, + sc_core::sc_time& bwDelay); + unsigned int transport_dbg(tlm::tlm_generic_payload& trans); - void fetchLineAndSendEndRequest(tlm::tlm_generic_payload &trans); + void fetchLineAndSendEndRequest(tlm::tlm_generic_payload& trans); void clearInitiatorBackpressureAndProcessBuffers(); - void sendEndResponseAndFillLine(tlm::tlm_generic_payload &trans); - void clearTargetBackpressureAndProcessLines(tlm::tlm_generic_payload &trans); + void sendEndResponseAndFillLine(tlm::tlm_generic_payload& trans); + void clearTargetBackpressureAndProcessLines(tlm::tlm_generic_payload& trans); tlm_utils::peq_with_cb_and_phase payloadEventQueue; @@ -109,7 +109,7 @@ private: struct CacheLine { tag_t tag = 0; - unsigned char *dataPtr = nullptr; + unsigned char* dataPtr = nullptr; bool allocated = false; bool valid = false; bool dirty = false; @@ -126,15 +126,15 @@ private: tag_t tag, lineOffset_t lineOffset, unsigned int dataLength, - const unsigned char *dataPtr); - + const unsigned char* dataPtr); + void readLine(index_t index, tag_t tag, lineOffset_t lineOffset, unsigned int dataLength, - unsigned char *dataPtr); + unsigned char* dataPtr); - CacheLine *evictLine(index_t index); + CacheLine* evictLine(index_t index); std::tuple decodeAddress(std::uint64_t address) const; std::uint64_t encodeAddress(index_t index, tag_t tag, lineOffset_t lineOffset = 0) const; @@ -143,10 +143,12 @@ private: { index_t index; tag_t tag; - tlm::tlm_generic_payload *trans; + tlm::tlm_generic_payload* trans; - BufferEntry(index_t index, tag_t tag, tlm::tlm_generic_payload *trans) - : index(index), tag(tag), trans(trans) + BufferEntry(index_t index, tag_t tag, tlm::tlm_generic_payload* trans) : + index(index), + tag(tag), + trans(trans) { } }; @@ -155,7 +157,7 @@ private: { index_t index; tag_t tag; - std::list requestList; + std::list requestList; /// Whether the Mshr entry was already issued to the target. bool issued = false; @@ -170,8 +172,10 @@ private: /// delay when it is already being waited on. bool hitDelayStarted = false; - Mshr(index_t index, tag_t tag, tlm::tlm_generic_payload *request) - : index(index), tag(tag), requestList{request} + Mshr(index_t index, tag_t tag, tlm::tlm_generic_payload* request) : + index(index), + tag(tag), + requestList{request} { } }; @@ -196,22 +200,22 @@ private: bool tSocketBackpressure = false; // Request to the target - tlm::tlm_generic_payload *requestInProgress = nullptr; + tlm::tlm_generic_payload* requestInProgress = nullptr; // Backpressure on initiator - tlm::tlm_generic_payload *endRequestPending = nullptr; + tlm::tlm_generic_payload* endRequestPending = nullptr; sc_core::sc_time lastEndReq = sc_core::sc_max_time(); - void fillLine(tlm::tlm_generic_payload &trans); - void accessCacheAndSendResponse(tlm::tlm_generic_payload &trans); - static void allocateLine(CacheLine *line, tag_t tag); + void fillLine(tlm::tlm_generic_payload& trans); + void accessCacheAndSendResponse(tlm::tlm_generic_payload& trans); + static void allocateLine(CacheLine* line, tag_t tag); bool isAllocated(index_t index, tag_t tag) const; bool hasBufferSpace() const; - sc_core::sc_time ceilTime(const sc_core::sc_time &inTime) const; - sc_core::sc_time ceilDelay(const sc_core::sc_time &inDelay) const; + sc_core::sc_time ceilTime(const sc_core::sc_time& inTime) const; + sc_core::sc_time ceilDelay(const sc_core::sc_time& inDelay) const; - MemoryManager &memoryManager; + MemoryManager& memoryManager; }; diff --git a/src/simulator/simulator/EccModule.cpp b/src/simulator/simulator/EccModule.cpp index 5933d969..363cf4c3 100644 --- a/src/simulator/simulator/EccModule.cpp +++ b/src/simulator/simulator/EccModule.cpp @@ -43,7 +43,7 @@ using namespace sc_core; using namespace tlm; -EccModule::EccModule(sc_module_name name, DRAMSys::AddressDecoder const &addressDecoder) : +EccModule::EccModule(sc_module_name name, DRAMSys::AddressDecoder const& addressDecoder) : sc_core::sc_module(name), payloadEventQueue(this, &EccModule::peqCallback), memoryManager(false), @@ -53,9 +53,9 @@ EccModule::EccModule(sc_module_name name, DRAMSys::AddressDecoder const &address tSocket.register_nb_transport_fw(this, &EccModule::nb_transport_fw); } -tlm::tlm_sync_enum EccModule::nb_transport_fw(tlm::tlm_generic_payload &payload, - tlm::tlm_phase &phase, - sc_core::sc_time &fwDelay) +tlm::tlm_sync_enum EccModule::nb_transport_fw(tlm::tlm_generic_payload& payload, + tlm::tlm_phase& phase, + sc_core::sc_time& fwDelay) { if (phase == BEGIN_REQ) { @@ -66,15 +66,15 @@ tlm::tlm_sync_enum EccModule::nb_transport_fw(tlm::tlm_generic_payload &payload, return TLM_ACCEPTED; } -tlm::tlm_sync_enum EccModule::nb_transport_bw(tlm::tlm_generic_payload &payload, - tlm::tlm_phase &phase, - sc_core::sc_time &bwDelay) +tlm::tlm_sync_enum EccModule::nb_transport_bw(tlm::tlm_generic_payload& payload, + tlm::tlm_phase& phase, + sc_core::sc_time& bwDelay) { payloadEventQueue.notify(payload, phase, bwDelay); return TLM_ACCEPTED; } -void EccModule::peqCallback(tlm::tlm_generic_payload &cbPayload, const tlm::tlm_phase &cbPhase) +void EccModule::peqCallback(tlm::tlm_generic_payload& cbPayload, const tlm::tlm_phase& cbPhase) { if (cbPhase == BEGIN_REQ) // from initiator { @@ -88,7 +88,8 @@ void EccModule::peqCallback(tlm::tlm_generic_payload &cbPayload, const tlm::tlm_ tlm_phase tPhase = BEGIN_REQ; sc_time tDelay = SC_ZERO_TIME; - DRAMSys::DecodedAddress decodedAddress = addressDecoder.decodeAddress(cbPayload.get_address()); + DRAMSys::DecodedAddress decodedAddress = + addressDecoder.decodeAddress(cbPayload.get_address()); decodedAddress = calculateOffsetAddress(decodedAddress); // Update the original address to account for the offsets @@ -103,14 +104,14 @@ void EccModule::peqCallback(tlm::tlm_generic_payload &cbPayload, const tlm::tlm_ { blockedRequest = &cbPayload; - auto &eccFifo = activeEccBlocks[decodedAddress.bank]; + auto& eccFifo = activeEccBlocks[decodedAddress.bank]; eccFifo.push_back({currentBlock, decodedAddress.row}); // Only hold 4 elements at max. if (eccFifo.size() >= 4) eccFifo.pop_front(); - tlm::tlm_generic_payload *eccPayload = generateEccPayload(decodedAddress); + tlm::tlm_generic_payload* eccPayload = generateEccPayload(decodedAddress); iSocket->nb_transport_fw(*eccPayload, tPhase, tDelay); } @@ -138,7 +139,7 @@ void EccModule::peqCallback(tlm::tlm_generic_payload &cbPayload, const tlm::tlm_ if (blockedRequest != nullptr) { - tlm_generic_payload &tPayload = *blockedRequest; + tlm_generic_payload& tPayload = *blockedRequest; blockedRequest = nullptr; tlm_phase tPhase = BEGIN_REQ; @@ -152,12 +153,13 @@ void EccModule::peqCallback(tlm::tlm_generic_payload &cbPayload, const tlm::tlm_ if (pendingRequest != nullptr) { - tlm_generic_payload &tPayload = *pendingRequest; + tlm_generic_payload& tPayload = *pendingRequest; tlm_phase tPhase = BEGIN_REQ; sc_time tDelay = SC_ZERO_TIME; - DRAMSys::DecodedAddress decodedAddress = addressDecoder.decodeAddress(tPayload.get_address()); + DRAMSys::DecodedAddress decodedAddress = + addressDecoder.decodeAddress(tPayload.get_address()); decodedAddress = calculateOffsetAddress(decodedAddress); #ifdef ECC_ENABLE @@ -168,14 +170,14 @@ void EccModule::peqCallback(tlm::tlm_generic_payload &cbPayload, const tlm::tlm_ blockedRequest = pendingRequest; pendingRequest = nullptr; - auto &eccFifo = activeEccBlocks[decodedAddress.bank]; + auto& eccFifo = activeEccBlocks[decodedAddress.bank]; eccFifo.push_back({currentBlock, decodedAddress.row}); // Only hold 4 elements at max. if (eccFifo.size() >= 4) eccFifo.pop_front(); - tlm::tlm_generic_payload *eccPayload = generateEccPayload(decodedAddress); + tlm::tlm_generic_payload* eccPayload = generateEccPayload(decodedAddress); iSocket->nb_transport_fw(*eccPayload, tPhase, tDelay); } @@ -242,7 +244,7 @@ void EccModule::peqCallback(tlm::tlm_generic_payload &cbPayload, const tlm::tlm_ } } -tlm::tlm_generic_payload *EccModule::generateEccPayload(DRAMSys::DecodedAddress decodedAddress) +tlm::tlm_generic_payload* EccModule::generateEccPayload(DRAMSys::DecodedAddress decodedAddress) { unsigned int eccAtom = decodedAddress.column / 512; uint64_t eccColumn = 1792 + eccAtom * 32; @@ -250,7 +252,7 @@ tlm::tlm_generic_payload *EccModule::generateEccPayload(DRAMSys::DecodedAddress decodedAddress.column = eccColumn; uint64_t eccAddress = addressDecoder.encodeAddress(decodedAddress); - tlm_generic_payload &payload = memoryManager.allocate(32); + tlm_generic_payload& payload = memoryManager.allocate(32); payload.acquire(); payload.set_address(eccAddress); payload.set_response_status(tlm::TLM_INCOMPLETE_RESPONSE); @@ -286,13 +288,14 @@ void EccModule::end_of_simulation() uint64_t latencies = 0; uint64_t numberOfLatencies = 0; - for (auto const &[latency, occurences] : latencyMap) + for (auto const& [latency, occurences] : latencyMap) { latencies += (latency.to_double() / 1000.0) * occurences; numberOfLatencies += occurences; } - std::cout << "Average latency: " << static_cast(latencies) / numberOfLatencies << std::endl; + std::cout << "Average latency: " << static_cast(latencies) / numberOfLatencies + << std::endl; } sc_time EccModule::roundLatency(sc_time latency) @@ -305,7 +308,8 @@ sc_time EccModule::roundLatency(sc_time latency) bool EccModule::activeEccBlock(Bank bank, Row row, Block block) const { - auto eccIt = std::find_if(activeEccBlocks.at(bank).cbegin(), activeEccBlocks.at(bank).cend(), + auto eccIt = std::find_if(activeEccBlocks.at(bank).cbegin(), + activeEccBlocks.at(bank).cend(), [block, row](EccIdentifier identifier) { return (identifier.first == block) && (identifier.second == row); }); diff --git a/src/simulator/simulator/EccModule.h b/src/simulator/simulator/EccModule.h index 6b384354..34fcdf82 100644 --- a/src/simulator/simulator/EccModule.h +++ b/src/simulator/simulator/EccModule.h @@ -41,13 +41,13 @@ #include +#include +#include #include #include #include #include #include -#include -#include class EccModule : public sc_core::sc_module { @@ -55,7 +55,7 @@ public: tlm_utils::simple_initiator_socket iSocket; tlm_utils::simple_target_socket tSocket; - EccModule(sc_core::sc_module_name name, DRAMSys::AddressDecoder const &addressDecoder); + EccModule(sc_core::sc_module_name name, DRAMSys::AddressDecoder const& addressDecoder); SC_HAS_PROCESS(EccModule); private: @@ -71,32 +71,32 @@ private: void end_of_simulation() override; - void peqCallback(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase); + void peqCallback(tlm::tlm_generic_payload& payload, const tlm::tlm_phase& phase); - tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload, - tlm::tlm_phase &phase, - sc_core::sc_time &fwDelay); - tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &payload, - tlm::tlm_phase &phase, - sc_core::sc_time &bwDelay); + tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& payload, + tlm::tlm_phase& phase, + sc_core::sc_time& fwDelay); + tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload& payload, + tlm::tlm_phase& phase, + sc_core::sc_time& bwDelay); - tlm::tlm_generic_payload *generateEccPayload(DRAMSys::DecodedAddress decodedAddress); + tlm::tlm_generic_payload* generateEccPayload(DRAMSys::DecodedAddress decodedAddress); static unsigned int alignToBlock(unsigned int column); - + tlm_utils::peq_with_cb_and_phase payloadEventQueue; - tlm::tlm_generic_payload *pendingRequest = nullptr; - tlm::tlm_generic_payload *blockedRequest = nullptr; + tlm::tlm_generic_payload* pendingRequest = nullptr; + tlm::tlm_generic_payload* blockedRequest = nullptr; bool targetBusy = false; const sc_core::sc_time tCK; MemoryManager memoryManager; - DRAMSys::AddressDecoder const &addressDecoder; + DRAMSys::AddressDecoder const& addressDecoder; std::unordered_map activeEccBlocks; - using EccPayload = tlm::tlm_generic_payload *; + using EccPayload = tlm::tlm_generic_payload*; using StartTime = sc_core::sc_time; std::unordered_map payloadMap; diff --git a/src/simulator/simulator/Initiator.h b/src/simulator/simulator/Initiator.h index 8cc14675..eeb99b3b 100644 --- a/src/simulator/simulator/Initiator.h +++ b/src/simulator/simulator/Initiator.h @@ -40,15 +40,15 @@ class Initiator { protected: - Initiator(const Initiator &) = default; - Initiator(Initiator &&) = default; - Initiator &operator=(const Initiator &) = default; - Initiator &operator=(Initiator &&) = default; + Initiator(const Initiator&) = default; + Initiator(Initiator&&) = default; + Initiator& operator=(const Initiator&) = default; + Initiator& operator=(Initiator&&) = default; public: Initiator() = default; virtual ~Initiator() = default; - virtual void bind(tlm_utils::multi_target_base<> &target) = 0; + virtual void bind(tlm_utils::multi_target_base<>& target) = 0; virtual uint64_t totalRequests() = 0; }; diff --git a/src/simulator/simulator/MemoryManager.cpp b/src/simulator/simulator/MemoryManager.cpp index 38f17100..44d65023 100644 --- a/src/simulator/simulator/MemoryManager.cpp +++ b/src/simulator/simulator/MemoryManager.cpp @@ -40,9 +40,9 @@ using namespace tlm; -MemoryManager::MemoryManager(bool storageEnabled) - : storageEnabled(storageEnabled) -{} +MemoryManager::MemoryManager(bool storageEnabled) : storageEnabled(storageEnabled) +{ +} MemoryManager::~MemoryManager() { @@ -61,8 +61,9 @@ MemoryManager::~MemoryManager() } // Comment in if you are suspecting a memory leak in the manager - //PRINTDEBUGMESSAGE("MemoryManager","Number of allocated payloads: " + to_string(numberOfAllocations)); - //PRINTDEBUGMESSAGE("MemoryManager","Number of freed payloads: " + to_string(numberOfFrees)); + // PRINTDEBUGMESSAGE("MemoryManager","Number of allocated payloads: " + + // to_string(numberOfAllocations)); PRINTDEBUGMESSAGE("MemoryManager","Number of freed payloads: + // " + to_string(numberOfFrees)); } tlm_generic_payload& MemoryManager::allocate(unsigned dataLength) @@ -83,7 +84,7 @@ tlm_generic_payload& MemoryManager::allocate(unsigned dataLength) return *payload; } - tlm_generic_payload *result = freePayloads[dataLength].top(); + tlm_generic_payload* result = freePayloads[dataLength].top(); freePayloads[dataLength].pop(); return *result; } diff --git a/src/simulator/simulator/MemoryManager.h b/src/simulator/simulator/MemoryManager.h index 7cbe33f1..ebd2ca86 100644 --- a/src/simulator/simulator/MemoryManager.h +++ b/src/simulator/simulator/MemoryManager.h @@ -38,18 +38,18 @@ #ifndef MEMORYMANAGER_H #define MEMORYMANAGER_H -#include #include #include +#include class MemoryManager : public tlm::tlm_mm_interface { public: explicit MemoryManager(bool storageEnabled); - MemoryManager(const MemoryManager &) = delete; - MemoryManager(MemoryManager &&) = delete; - MemoryManager &operator=(const MemoryManager &) = delete; - MemoryManager &operator=(MemoryManager &&) = delete; + MemoryManager(const MemoryManager&) = delete; + MemoryManager(MemoryManager&&) = delete; + MemoryManager& operator=(const MemoryManager&) = delete; + MemoryManager& operator=(MemoryManager&&) = delete; ~MemoryManager() override; tlm::tlm_generic_payload& allocate(unsigned dataLength); diff --git a/src/simulator/simulator/SimpleInitiator.h b/src/simulator/simulator/SimpleInitiator.h index 3c0a0064..410588d4 100644 --- a/src/simulator/simulator/SimpleInitiator.h +++ b/src/simulator/simulator/SimpleInitiator.h @@ -38,32 +38,31 @@ #include "Initiator.h" #include "request/RequestIssuer.h" -template -class SimpleInitiator : public Initiator +template class SimpleInitiator : public Initiator { public: - SimpleInitiator(sc_core::sc_module_name const &name, - MemoryManager &memoryManager, + SimpleInitiator(sc_core::sc_module_name const& name, + MemoryManager& memoryManager, unsigned int clkMhz, std::optional maxPendingReadRequests, std::optional maxPendingWriteRequests, std::function transactionFinished, std::function terminate, - Producer &&producer) - : producer(std::forward(producer)), - issuer( - name, - memoryManager, - clkMhz, - maxPendingReadRequests, - maxPendingWriteRequests, - [this] { return this->producer.nextRequest(); }, - std::move(transactionFinished), - std::move(terminate)) + Producer&& producer) : + producer(std::forward(producer)), + issuer( + name, + memoryManager, + clkMhz, + maxPendingReadRequests, + maxPendingWriteRequests, + [this] { return this->producer.nextRequest(); }, + std::move(transactionFinished), + std::move(terminate)) { } - void bind(tlm_utils::multi_target_base<> &target) override { issuer.iSocket.bind(target); } + void bind(tlm_utils::multi_target_base<>& target) override { issuer.iSocket.bind(target); } uint64_t totalRequests() override { return producer.totalRequests(); }; private: diff --git a/src/simulator/simulator/generator/RandomProducer.cpp b/src/simulator/simulator/generator/RandomProducer.cpp index 36a3b693..3cc18299 100644 --- a/src/simulator/simulator/generator/RandomProducer.cpp +++ b/src/simulator/simulator/generator/RandomProducer.cpp @@ -43,15 +43,15 @@ RandomProducer::RandomProducer(uint64_t numRequests, std::optional maxAddress, uint64_t memorySize, unsigned int dataLength, - unsigned int dataAlignment) - : numberOfRequests(numRequests), - seed(seed.value_or(DEFAULT_SEED)), - rwRatio(rwRatio), - dataLength(dataLength), - dataAlignment(dataAlignment), - randomGenerator(this->seed), - randomAddressDistribution(minAddress.value_or(DEFAULT_MIN_ADDRESS), - maxAddress.value_or((memorySize) - dataLength)) + unsigned int dataAlignment) : + numberOfRequests(numRequests), + seed(seed.value_or(DEFAULT_SEED)), + rwRatio(rwRatio), + dataLength(dataLength), + dataAlignment(dataAlignment), + randomGenerator(this->seed), + randomAddressDistribution(minAddress.value_or(DEFAULT_MIN_ADDRESS), + maxAddress.value_or((memorySize)-dataLength)) { if (minAddress > memorySize - 1) SC_REPORT_FATAL("TrafficGenerator", "minAddress is out of range."); diff --git a/src/simulator/simulator/generator/SequentialProducer.cpp b/src/simulator/simulator/generator/SequentialProducer.cpp index 2a1aad9c..9c0d552e 100644 --- a/src/simulator/simulator/generator/SequentialProducer.cpp +++ b/src/simulator/simulator/generator/SequentialProducer.cpp @@ -43,15 +43,15 @@ SequentialProducer::SequentialProducer(uint64_t numRequests, std::optional minAddress, std::optional maxAddress, uint64_t memorySize, - unsigned int dataLength) - : numberOfRequests(numRequests), - addressIncrement(addressIncrement.value_or(dataLength)), - minAddress(minAddress.value_or(DEFAULT_MIN_ADDRESS)), - maxAddress(maxAddress.value_or(memorySize - 1)), - seed(seed.value_or(DEFAULT_SEED)), - rwRatio(rwRatio), - dataLength(dataLength), - randomGenerator(this->seed) + unsigned int dataLength) : + numberOfRequests(numRequests), + addressIncrement(addressIncrement.value_or(dataLength)), + minAddress(minAddress.value_or(DEFAULT_MIN_ADDRESS)), + maxAddress(maxAddress.value_or(memorySize - 1)), + seed(seed.value_or(DEFAULT_SEED)), + rwRatio(rwRatio), + dataLength(dataLength), + randomGenerator(this->seed) { if (minAddress > memorySize - 1) SC_REPORT_FATAL("TrafficGenerator", "minAddress is out of range."); diff --git a/src/simulator/simulator/generator/TrafficGenerator.h b/src/simulator/simulator/generator/TrafficGenerator.h index 3636cc7b..8892494c 100644 --- a/src/simulator/simulator/generator/TrafficGenerator.h +++ b/src/simulator/simulator/generator/TrafficGenerator.h @@ -46,21 +46,21 @@ class TrafficGenerator : public Initiator { public: - TrafficGenerator(DRAMSys::Config::TrafficGenerator const &config, - MemoryManager &memoryManager, + TrafficGenerator(DRAMSys::Config::TrafficGenerator const& config, + MemoryManager& memoryManager, uint64_t memorySize, unsigned int defaultDataLength, std::function transactionFinished, std::function terminateInitiator); - TrafficGenerator(DRAMSys::Config::TrafficGeneratorStateMachine const &config, - MemoryManager &memoryManager, + TrafficGenerator(DRAMSys::Config::TrafficGeneratorStateMachine const& config, + MemoryManager& memoryManager, uint64_t memorySize, unsigned int defaultDataLength, std::function transactionFinished, std::function terminateInitiator); - void bind(tlm_utils::multi_target_base<> &target) override { issuer.iSocket.bind(target); } + void bind(tlm_utils::multi_target_base<>& target) override { issuer.iSocket.bind(target); } uint64_t totalRequests() override; Request nextRequest(); diff --git a/src/simulator/simulator/hammer/RowHammer.cpp b/src/simulator/simulator/hammer/RowHammer.cpp index c671f151..7da74d8a 100644 --- a/src/simulator/simulator/hammer/RowHammer.cpp +++ b/src/simulator/simulator/hammer/RowHammer.cpp @@ -35,12 +35,10 @@ #include "RowHammer.h" -RowHammer::RowHammer(uint64_t numRequests, - uint64_t rowIncrement, - unsigned int dataLength) - : numberOfRequests(numRequests), - dataLength(dataLength), - rowIncrement(rowIncrement) +RowHammer::RowHammer(uint64_t numRequests, uint64_t rowIncrement, unsigned int dataLength) : + numberOfRequests(numRequests), + dataLength(dataLength), + rowIncrement(rowIncrement) { } @@ -48,7 +46,7 @@ Request RowHammer::nextRequest() { if (generatedRequests >= numberOfRequests) return Request{Request::Command::Stop}; - + generatedRequests++; if (currentAddress == 0x00) diff --git a/src/simulator/simulator/hammer/RowHammer.h b/src/simulator/simulator/hammer/RowHammer.h index 75996299..82c6d547 100644 --- a/src/simulator/simulator/hammer/RowHammer.h +++ b/src/simulator/simulator/hammer/RowHammer.h @@ -42,9 +42,7 @@ class RowHammer : public RequestProducer { public: - RowHammer(uint64_t numRequests, - uint64_t rowIncrement, - unsigned int dataLength); + RowHammer(uint64_t numRequests, uint64_t rowIncrement, unsigned int dataLength); Request nextRequest() override; uint64_t totalRequests() override { return numberOfRequests; } diff --git a/src/simulator/simulator/player/StlPlayer.cpp b/src/simulator/simulator/player/StlPlayer.cpp index 9f1e0944..4eb0c9ac 100644 --- a/src/simulator/simulator/player/StlPlayer.cpp +++ b/src/simulator/simulator/player/StlPlayer.cpp @@ -46,16 +46,16 @@ StlPlayer::StlPlayer(std::string_view tracePath, unsigned int clkMhz, unsigned int defaultDataLength, TraceType traceType, - bool storageEnabled) - : traceType(traceType), - storageEnabled(storageEnabled), - playerPeriod(sc_core::sc_time(1.0 / static_cast(clkMhz), sc_core::SC_US)), - defaultDataLength(defaultDataLength), - traceFile(tracePath.data()), - lineBuffers( - {std::make_shared>(), std::make_shared>()}), - parseBuffer(lineBuffers.at(1)), - readoutBuffer(lineBuffers.at(0)) + bool storageEnabled) : + traceType(traceType), + storageEnabled(storageEnabled), + playerPeriod(sc_core::sc_time(1.0 / static_cast(clkMhz), sc_core::SC_US)), + defaultDataLength(defaultDataLength), + traceFile(tracePath.data()), + lineBuffers( + {std::make_shared>(), std::make_shared>()}), + parseBuffer(lineBuffers.at(1)), + readoutBuffer(lineBuffers.at(0)) { readoutBuffer->reserve(LINE_BUFFER_SIZE); parseBuffer->reserve(LINE_BUFFER_SIZE); @@ -72,8 +72,7 @@ StlPlayer::StlPlayer(std::string_view tracePath, numberOfLines++; } if (numberOfLines == 0) - SC_REPORT_FATAL("StlPlayer", - (std::string("Empty trace ") + tracePath.data()).c_str()); + SC_REPORT_FATAL("StlPlayer", (std::string("Empty trace ") + tracePath.data()).c_str()); traceFile.clear(); traceFile.seekg(0); } @@ -101,7 +100,8 @@ Request StlPlayer::nextRequest() if (traceType == TraceType::Absolute) { bool behindSchedule = sc_core::sc_time_stamp() > readoutIt->delay; - delay = behindSchedule ? sc_core::SC_ZERO_TIME : readoutIt->delay - sc_core::sc_time_stamp(); + delay = + behindSchedule ? sc_core::SC_ZERO_TIME : readoutIt->delay - sc_core::sc_time_stamp(); } else // if (traceType == TraceType::Relative) { @@ -134,7 +134,7 @@ void StlPlayer::parseTraceFile() parsedLines++; parseBuffer->emplace_back(); - Request &content = parseBuffer->back(); + Request& content = parseBuffer->back(); // Trace files MUST provide timestamp, command and address for every // transaction. The data information depends on the storage mode @@ -150,8 +150,8 @@ void StlPlayer::parseTraceFile() iss >> element; if (element.empty()) SC_REPORT_FATAL( - "StlPlayer", - ("Malformed trace file line " + std::to_string(currentLine) + ".").c_str()); + "StlPlayer", + ("Malformed trace file line " + std::to_string(currentLine) + ".").c_str()); content.delay = playerPeriod * static_cast(std::stoull(element)); @@ -159,8 +159,8 @@ void StlPlayer::parseTraceFile() iss >> element; if (element.empty()) SC_REPORT_FATAL( - "StlPlayer", - ("Malformed trace file line " + std::to_string(currentLine) + ".").c_str()); + "StlPlayer", + ("Malformed trace file line " + std::to_string(currentLine) + ".").c_str()); if (element.at(0) == '(') { @@ -169,8 +169,8 @@ void StlPlayer::parseTraceFile() iss >> element; if (element.empty()) SC_REPORT_FATAL( - "StlPlayer", - ("Malformed trace file line " + std::to_string(currentLine) + ".").c_str()); + "StlPlayer", + ("Malformed trace file line " + std::to_string(currentLine) + ".").c_str()); } else content.length = defaultDataLength; @@ -181,15 +181,15 @@ void StlPlayer::parseTraceFile() content.command = Request::Command::Write; else SC_REPORT_FATAL( - "StlPlayer", - ("Malformed trace file line " + std::to_string(currentLine) + ".").c_str()); + "StlPlayer", + ("Malformed trace file line " + std::to_string(currentLine) + ".").c_str()); // Get the address. iss >> element; if (element.empty()) SC_REPORT_FATAL( - "StlPlayer", - ("Malformed trace file line " + std::to_string(currentLine) + ".").c_str()); + "StlPlayer", + ("Malformed trace file line " + std::to_string(currentLine) + ".").c_str()); content.address = std::stoull(element, nullptr, 16); // Get the data if necessary. @@ -202,20 +202,20 @@ void StlPlayer::parseTraceFile() // We need two characters to represent 1 byte in hexadecimal. Offset for 0x prefix. if (element.length() != (content.length * 2 + 2)) SC_REPORT_FATAL( - "StlPlayer", - ("Malformed trace file line " + std::to_string(currentLine) + ".").c_str()); + "StlPlayer", + ("Malformed trace file line " + std::to_string(currentLine) + ".").c_str()); // Set data for (unsigned i = 0; i < content.length; i++) content.data.emplace_back(static_cast( - std::stoi(element.substr(i * 2 + 2, 2), nullptr, 16))); + std::stoi(element.substr(i * 2 + 2, 2), nullptr, 16))); } } catch (...) { SC_REPORT_FATAL( - "StlPlayer", - ("Malformed trace file line " + std::to_string(currentLine) + ".").c_str()); + "StlPlayer", + ("Malformed trace file line " + std::to_string(currentLine) + ".").c_str()); } } } diff --git a/src/simulator/simulator/request/RequestIssuer.cpp b/src/simulator/simulator/request/RequestIssuer.cpp index fe1a8fa0..d759570a 100644 --- a/src/simulator/simulator/request/RequestIssuer.cpp +++ b/src/simulator/simulator/request/RequestIssuer.cpp @@ -35,23 +35,23 @@ #include "RequestIssuer.h" -RequestIssuer::RequestIssuer(sc_core::sc_module_name const &name, - MemoryManager &memoryManager, +RequestIssuer::RequestIssuer(sc_core::sc_module_name const& name, + MemoryManager& memoryManager, unsigned int clkMhz, std::optional maxPendingReadRequests, std::optional maxPendingWriteRequests, std::function nextRequest, std::function transactionFinished, - std::function terminate) - : sc_module(name), - payloadEventQueue(this, &RequestIssuer::peqCallback), - memoryManager(memoryManager), - clkPeriod(sc_core::sc_time(1.0 / static_cast(clkMhz), sc_core::SC_US)), - maxPendingReadRequests(maxPendingReadRequests), - maxPendingWriteRequests(maxPendingWriteRequests), - transactionFinished(std::move(transactionFinished)), - terminate(std::move(terminate)), - nextRequest(std::move(nextRequest)) + std::function terminate) : + sc_module(name), + payloadEventQueue(this, &RequestIssuer::peqCallback), + memoryManager(memoryManager), + clkPeriod(sc_core::sc_time(1.0 / static_cast(clkMhz), sc_core::SC_US)), + maxPendingReadRequests(maxPendingReadRequests), + maxPendingWriteRequests(maxPendingWriteRequests), + transactionFinished(std::move(transactionFinished)), + terminate(std::move(terminate)), + nextRequest(std::move(nextRequest)) { SC_THREAD(sendNextRequest); iSocket.register_nb_transport_bw(this, &RequestIssuer::nb_transport_bw); @@ -67,7 +67,7 @@ void RequestIssuer::sendNextRequest() return; } - tlm::tlm_generic_payload &payload = memoryManager.allocate(request.length); + tlm::tlm_generic_payload& payload = memoryManager.allocate(request.length); payload.acquire(); payload.set_address(request.address); payload.set_response_status(tlm::TLM_INCOMPLETE_RESPONSE); @@ -120,7 +120,7 @@ bool RequestIssuer::nextRequestSendable() const return true; } -void RequestIssuer::peqCallback(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase) +void RequestIssuer::peqCallback(tlm::tlm_generic_payload& payload, const tlm::tlm_phase& phase) { if (phase == tlm::END_REQ) { diff --git a/src/simulator/simulator/request/RequestIssuer.h b/src/simulator/simulator/request/RequestIssuer.h index 77af12ba..2d21c38b 100644 --- a/src/simulator/simulator/request/RequestIssuer.h +++ b/src/simulator/simulator/request/RequestIssuer.h @@ -50,8 +50,8 @@ class RequestIssuer : sc_core::sc_module public: tlm_utils::simple_initiator_socket iSocket; - RequestIssuer(sc_core::sc_module_name const &name, - MemoryManager &memoryManager, + RequestIssuer(sc_core::sc_module_name const& name, + MemoryManager& memoryManager, unsigned int clkMhz, std::optional maxPendingReadRequests, std::optional maxPendingWriteRequests, @@ -62,7 +62,7 @@ public: private: tlm_utils::peq_with_cb_and_phase payloadEventQueue; - MemoryManager &memoryManager; + MemoryManager& memoryManager; const sc_core::sc_time clkPeriod; @@ -85,13 +85,13 @@ private: void sendNextRequest(); bool nextRequestSendable() const; - tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &payload, - tlm::tlm_phase &phase, - sc_core::sc_time &bwDelay) + tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload& payload, + tlm::tlm_phase& phase, + sc_core::sc_time& bwDelay) { payloadEventQueue.notify(payload, phase, bwDelay); return tlm::TLM_ACCEPTED; } - void peqCallback(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase); + void peqCallback(tlm::tlm_generic_payload& payload, const tlm::tlm_phase& phase); }; diff --git a/src/simulator/simulator/request/RequestProducer.h b/src/simulator/simulator/request/RequestProducer.h index b41f9ed2..ad4a01bb 100644 --- a/src/simulator/simulator/request/RequestProducer.h +++ b/src/simulator/simulator/request/RequestProducer.h @@ -40,10 +40,10 @@ class RequestProducer { protected: - RequestProducer(const RequestProducer &) = default; - RequestProducer(RequestProducer &&) = default; - RequestProducer &operator=(const RequestProducer &) = default; - RequestProducer &operator=(RequestProducer &&) = default; + RequestProducer(const RequestProducer&) = default; + RequestProducer(RequestProducer&&) = default; + RequestProducer& operator=(const RequestProducer&) = default; + RequestProducer& operator=(RequestProducer&&) = default; public: RequestProducer() = default; diff --git a/src/util/DRAMSys/util/json.h b/src/util/DRAMSys/util/json.h index 5d34a4b2..282dee98 100644 --- a/src/util/DRAMSys/util/json.h +++ b/src/util/DRAMSys/util/json.h @@ -34,7 +34,6 @@ * Derek Christ */ - #ifndef DRAMSYS_UTIL_JSON_H #define DRAMSYS_UTIL_JSON_H @@ -46,27 +45,31 @@ using json_t = nlohmann::json; -namespace DRAMSys::util { +namespace DRAMSys::util +{ // See https://www.kdab.com/jsonify-with-nlohmann-json/ // Try to set the value of type T into the variant data if it fails, do nothing template -void variant_from_json(const nlohmann::json &j, std::variant &data) +void variant_from_json(const nlohmann::json& j, std::variant& data) { - try { + try + { data = j.get(); - } catch (...) { + } + catch (...) + { } } template -void optional_to_json(nlohmann::json &j, std::string_view name, const std::optional &value) +void optional_to_json(nlohmann::json& j, std::string_view name, const std::optional& value) { if (value) j[name] = *value; } template -void optional_from_json(const nlohmann::json &j, std::string_view name, std::optional &value) +void optional_from_json(const nlohmann::json& j, std::string_view name, std::optional& value) { const auto it = j.find(name); @@ -76,13 +79,10 @@ void optional_from_json(const nlohmann::json &j, std::string_view name, std::opt value = std::nullopt; } -template -constexpr bool is_optional = false; -template -constexpr bool is_optional> = true; +template constexpr bool is_optional = false; +template constexpr bool is_optional> = true; -template -void extended_to_json(const char *key, nlohmann::json &j, const T &value) +template void extended_to_json(const char* key, nlohmann::json& j, const T& value) { if constexpr (is_optional) optional_to_json(j, key, value); @@ -90,8 +90,7 @@ void extended_to_json(const char *key, nlohmann::json &j, const T &value) j[key] = value; } -template -void extended_from_json(const char *key, const nlohmann::json &j, T &value) +template void extended_from_json(const char* key, const nlohmann::json& j, T& value) { if constexpr (is_optional) optional_from_json(j, key, value); @@ -103,57 +102,65 @@ void extended_from_json(const char *key, const nlohmann::json &j, T &value) NLOHMANN_JSON_NAMESPACE_BEGIN -template -struct adl_serializer> +template struct adl_serializer> { - static void to_json(nlohmann::json &j, const std::variant &data) + static void to_json(nlohmann::json& j, const std::variant& data) { - std::visit([&j](const auto &v) { j = v; }, data); + std::visit([&j](const auto& v) { j = v; }, data); } - static void from_json(const nlohmann::json &j, std::variant &data) + static void from_json(const nlohmann::json& j, std::variant& data) { // Call variant_from_json for all types, only one will succeed (DRAMSys::util::variant_from_json(j, data), ...); } }; -template -struct adl_serializer> { - static void to_json(json_t& j, const std::optional& opt) { - if (opt == std::nullopt) { +template struct adl_serializer> +{ + static void to_json(json_t& j, const std::optional& opt) + { + if (opt == std::nullopt) + { j = nullptr; } - else { + else + { j = *opt; } } - static void from_json(const json_t& j, std::optional& opt) { - if (j.is_null()) { + static void from_json(const json_t& j, std::optional& opt) + { + if (j.is_null()) + { opt = std::nullopt; } - else { + else + { opt = j.get(); } } }; - NLOHMANN_JSON_NAMESPACE_END // NOLINTBEGIN(cppcoreguidelines-macro-usage) -#define EXTEND_JSON_TO(v1) DRAMSys::util::extended_to_json(#v1, nlohmann_json_j, nlohmann_json_t.v1); -#define EXTEND_JSON_FROM(v1) DRAMSys::util::extended_from_json(#v1, nlohmann_json_j, nlohmann_json_t.v1); - -#define NLOHMANN_JSONIFY_ALL_THINGS(Type, ...) \ - inline void to_json(nlohmann::json &nlohmann_json_j, const Type &nlohmann_json_t) { \ - NLOHMANN_JSON_EXPAND(NLOHMANN_JSON_PASTE(EXTEND_JSON_TO, __VA_ARGS__)) \ - } \ - inline void from_json(const nlohmann::json &nlohmann_json_j, Type &nlohmann_json_t) { \ - NLOHMANN_JSON_EXPAND(NLOHMANN_JSON_PASTE(EXTEND_JSON_FROM, __VA_ARGS__)) \ - } +#define EXTEND_JSON_TO(v1) \ + DRAMSys::util::extended_to_json(#v1, nlohmann_json_j, nlohmann_json_t.v1); +#define EXTEND_JSON_FROM(v1) \ + DRAMSys::util::extended_from_json(#v1, nlohmann_json_j, nlohmann_json_t.v1); + +#define NLOHMANN_JSONIFY_ALL_THINGS(Type, ...) \ + inline void to_json(nlohmann::json& nlohmann_json_j, const Type& nlohmann_json_t) \ + { \ + NLOHMANN_JSON_EXPAND(NLOHMANN_JSON_PASTE(EXTEND_JSON_TO, __VA_ARGS__)) \ + } \ + inline void from_json(const nlohmann::json& nlohmann_json_j, Type& nlohmann_json_t) \ + { \ + NLOHMANN_JSON_EXPAND(NLOHMANN_JSON_PASTE(EXTEND_JSON_FROM, __VA_ARGS__)) \ + } // NOLINTEND(cppcoreguidelines-macro-usage) diff --git a/src/util/DRAMSys/util/util.cpp b/src/util/DRAMSys/util/util.cpp index 93f828b0..8341fcd7 100644 --- a/src/util/DRAMSys/util/util.cpp +++ b/src/util/DRAMSys/util/util.cpp @@ -35,6 +35,7 @@ #include "util.h" -namespace DRAMSys::util { +namespace DRAMSys::util +{ } diff --git a/src/util/DRAMSys/util/util.h b/src/util/DRAMSys/util/util.h index 416b3ade..8a000398 100644 --- a/src/util/DRAMSys/util/util.h +++ b/src/util/DRAMSys/util/util.h @@ -36,8 +36,9 @@ #ifndef DRAMSYS_UTIL_UTIL_H #define DRAMSYS_UTIL_UTIL_H -namespace DRAMSys::util { +namespace DRAMSys::util +{ } -#endif +#endif