From d56f62fd6d0fd96978fdc08f0ac5fcef3d016792 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Wed, 20 Apr 2022 16:36:02 +0200 Subject: [PATCH 01/29] Give controller access to address decoder. --- DRAMSys/library/src/common/dramExtensions.cpp | 151 ++++-------------- DRAMSys/library/src/common/dramExtensions.h | 25 +-- .../library/src/controller/BankMachine.cpp | 16 +- DRAMSys/library/src/controller/Controller.cpp | 19 +-- DRAMSys/library/src/controller/Controller.h | 5 +- .../src/controller/ControllerRecordable.cpp | 4 +- .../src/controller/ControllerRecordable.h | 3 +- .../src/controller/cmdmux/CmdMuxOldest.cpp | 8 +- .../src/controller/cmdmux/CmdMuxStrict.cpp | 8 +- .../controller/respqueue/RespQueueReorder.cpp | 2 +- .../controller/scheduler/SchedulerFifo.cpp | 2 +- .../controller/scheduler/SchedulerFrFcfs.cpp | 4 +- .../scheduler/SchedulerFrFcfsGrp.cpp | 4 +- .../scheduler/SchedulerGrpFrFcfs.cpp | 12 +- .../scheduler/SchedulerGrpFrFcfsWm.cpp | 8 +- .../library/src/simulation/AddressDecoder.cpp | 28 +++- .../library/src/simulation/AddressDecoder.h | 5 +- DRAMSys/library/src/simulation/Arbiter.cpp | 18 +-- DRAMSys/library/src/simulation/Arbiter.h | 12 +- DRAMSys/library/src/simulation/DRAMSys.cpp | 14 +- DRAMSys/library/src/simulation/DRAMSys.h | 3 + .../src/simulation/DRAMSysRecordable.cpp | 8 +- 22 files changed, 144 insertions(+), 215 deletions(-) diff --git a/DRAMSys/library/src/common/dramExtensions.cpp b/DRAMSys/library/src/common/dramExtensions.cpp index 286c25ad..4843ec67 100644 --- a/DRAMSys/library/src/common/dramExtensions.cpp +++ b/DRAMSys/library/src/common/dramExtensions.cpp @@ -54,14 +54,14 @@ DramExtension::DramExtension(Thread thread, Channel channel, Rank rank, row(row), column(column), burstLength(burstLength), threadPayloadID(threadPayloadID), channelPayloadID(channelPayloadID) {} -void DramExtension::setExtension(tlm_generic_payload *payload, +void DramExtension::setExtension(tlm_generic_payload& payload, Thread thread, Channel channel, Rank rank, BankGroup bankGroup, Bank bank, Row row, Column column, unsigned int burstLength, uint64_t threadPayloadID, uint64_t channelPayloadID) { - DramExtension *extension = nullptr; - payload->get_extension(extension); + DramExtension* extension = nullptr; + payload.get_extension(extension); if (extension != nullptr) { @@ -81,148 +81,78 @@ void DramExtension::setExtension(tlm_generic_payload *payload, extension = new DramExtension(thread, channel, rank, bankGroup, bank, row, column, burstLength, threadPayloadID, channelPayloadID); - payload->set_auto_extension(extension); + payload.set_auto_extension(extension); } } -void DramExtension::setExtension(tlm_generic_payload &payload, - Thread thread, Channel channel, Rank rank, - BankGroup bankGroup, Bank bank, Row row, - Column column, unsigned int burstLength, - uint64_t threadPayloadID, uint64_t channelPayloadID) +void DramExtension::setPayloadIDs(tlm_generic_payload& payload, uint64_t threadPayloadID, uint64_t channelPayloadID) { - setExtension(&payload, thread, channel, rank, bankGroup, - bank, row, column, burstLength, - threadPayloadID, channelPayloadID); -} - -void DramExtension::setPayloadIDs(tlm_generic_payload *payload, uint64_t threadPayloadID, uint64_t channelPayloadID) -{ - DramExtension *extension; - payload->get_extension(extension); + DramExtension* extension = nullptr; + payload.get_extension(extension); + assert(extension != nullptr); extension->threadPayloadID = threadPayloadID; extension->channelPayloadID = channelPayloadID; } -void DramExtension::setPayloadIDs(tlm_generic_payload &payload, uint64_t threadPayloadID, uint64_t channelPayloadID) +DramExtension& DramExtension::getExtension(const tlm_generic_payload& payload) { - DramExtension::setPayloadIDs(&payload, threadPayloadID, channelPayloadID); -} - -DramExtension &DramExtension::getExtension(const tlm_generic_payload *payload) -{ - DramExtension *result = nullptr; - payload->get_extension(result); - sc_assert(result != nullptr); + DramExtension* result = nullptr; + payload.get_extension(result); + assert(result != nullptr); return *result; } -DramExtension &DramExtension::getExtension(const tlm_generic_payload &payload) -{ - return DramExtension::getExtension(&payload); -} - -Thread DramExtension::getThread(const tlm_generic_payload *payload) +Thread DramExtension::getThread(const tlm_generic_payload& payload) { return DramExtension::getExtension(payload).getThread(); } -Thread DramExtension::getThread(const tlm_generic_payload &payload) -{ - return DramExtension::getThread(&payload); -} - -Channel DramExtension::getChannel(const tlm_generic_payload *payload) +Channel DramExtension::getChannel(const tlm_generic_payload& payload) { return DramExtension::getExtension(payload).getChannel(); } -Channel DramExtension::getChannel(const tlm_generic_payload &payload) -{ - return DramExtension::getChannel(&payload); -} - -Rank DramExtension::getRank(const tlm_generic_payload *payload) +Rank DramExtension::getRank(const tlm_generic_payload& payload) { return DramExtension::getExtension(payload).getRank(); } -Rank DramExtension::getRank(const tlm_generic_payload &payload) -{ - return DramExtension::getRank(&payload); -} - -BankGroup DramExtension::getBankGroup(const tlm_generic_payload *payload) +BankGroup DramExtension::getBankGroup(const tlm_generic_payload& payload) { return DramExtension::getExtension(payload).getBankGroup(); } -BankGroup DramExtension::getBankGroup(const tlm_generic_payload &payload) -{ - return DramExtension::getBankGroup(&payload); -} - -Bank DramExtension::getBank(const tlm_generic_payload *payload) +Bank DramExtension::getBank(const tlm_generic_payload& payload) { return DramExtension::getExtension(payload).getBank(); } -Bank DramExtension::getBank(const tlm_generic_payload &payload) -{ - return DramExtension::getBank(&payload); -} - -Row DramExtension::getRow(const tlm_generic_payload *payload) +Row DramExtension::getRow(const tlm_generic_payload& payload) { return DramExtension::getExtension(payload).getRow(); } -Row DramExtension::getRow(const tlm_generic_payload &payload) -{ - return DramExtension::getRow(&payload); -} - -Column DramExtension::getColumn(const tlm_generic_payload *payload) +Column DramExtension::getColumn(const tlm_generic_payload& payload) { return DramExtension::getExtension(payload).getColumn(); } -Column DramExtension::getColumn(const tlm_generic_payload &payload) -{ - return DramExtension::getColumn(&payload); -} - -unsigned DramExtension::getBurstLength(const tlm_generic_payload *payload) +unsigned DramExtension::getBurstLength(const tlm_generic_payload& payload) { return DramExtension::getExtension(payload).getBurstLength(); } -unsigned DramExtension::getBurstLength(const tlm_generic_payload &payload) -{ - return DramExtension::getBurstLength(&payload); -} - -uint64_t DramExtension::getThreadPayloadID(const tlm_generic_payload *payload) +uint64_t DramExtension::getThreadPayloadID(const tlm_generic_payload& payload) { return DramExtension::getExtension(payload).getThreadPayloadID(); } -uint64_t DramExtension::getThreadPayloadID(const tlm_generic_payload &payload) -{ - return DramExtension::getThreadPayloadID(&payload); -} - -uint64_t DramExtension::getChannelPayloadID(const tlm_generic_payload *payload) +uint64_t DramExtension::getChannelPayloadID(const tlm_generic_payload& payload) { return DramExtension::getExtension(payload).getChannelPayloadID(); } -uint64_t DramExtension::getChannelPayloadID(const tlm_generic_payload &payload) -{ - return DramExtension::getChannelPayloadID(&payload); -} - tlm_extension_base *DramExtension::clone() const { return new DramExtension(thread, channel, rank, bankGroup, bank, row, column, @@ -304,50 +234,35 @@ void GenerationExtension::copy_from(const tlm_extension_base &ext) } -void GenerationExtension::setExtension(tlm_generic_payload *payload, const sc_time &timeOfGeneration) +void GenerationExtension::setExtension(tlm_generic_payload& payload, const sc_time& _timeOfGeneration) { - GenerationExtension *extension = nullptr; - payload->get_extension(extension); + GenerationExtension* extension = nullptr; + payload.get_extension(extension); if (extension != nullptr) { - extension->timeOfGeneration = timeOfGeneration; + extension->timeOfGeneration = _timeOfGeneration; } else { - extension = new GenerationExtension(timeOfGeneration); - payload->set_auto_extension(extension); + extension = new GenerationExtension(_timeOfGeneration); + payload.set_auto_extension(extension); } } -void GenerationExtension::setExtension(tlm_generic_payload &payload, const sc_time &timeOfGeneration) +GenerationExtension& GenerationExtension::getExtension(const tlm_generic_payload& payload) { - GenerationExtension::setExtension(&payload, timeOfGeneration); -} - -GenerationExtension &GenerationExtension::getExtension(const tlm_generic_payload *payload) -{ - GenerationExtension *result = nullptr; - payload->get_extension(result); - sc_assert(result != nullptr); + GenerationExtension* result = nullptr; + payload.get_extension(result); + assert(result != nullptr); return *result; } -GenerationExtension &GenerationExtension::getExtension(const tlm_generic_payload &payload) -{ - return GenerationExtension::getExtension(&payload); -} - -sc_time GenerationExtension::getTimeOfGeneration(const tlm_generic_payload *payload) +sc_time GenerationExtension::getTimeOfGeneration(const tlm_generic_payload& payload) { return GenerationExtension::getExtension(payload).timeOfGeneration; } -sc_time GenerationExtension::getTimeOfGeneration(const tlm_generic_payload &payload) -{ - return GenerationExtension::getTimeOfGeneration(&payload); -} - //THREAD bool operator ==(const Thread &lhs, const Thread &rhs) { diff --git a/DRAMSys/library/src/common/dramExtensions.h b/DRAMSys/library/src/common/dramExtensions.h index 76c9f1d8..cfd9cb9a 100644 --- a/DRAMSys/library/src/common/dramExtensions.h +++ b/DRAMSys/library/src/common/dramExtensions.h @@ -166,45 +166,27 @@ public: tlm::tlm_extension_base *clone() const override; void copy_from(const tlm::tlm_extension_base &ext) override; - static void setExtension(tlm::tlm_generic_payload *payload, - Thread thread, Channel channel, Rank rank, - BankGroup bankGroup, Bank bank, Row row, - Column column, unsigned int burstLength, - uint64_t threadPayloadID, uint64_t channelPayloadID); static void setExtension(tlm::tlm_generic_payload &payload, Thread thread, Channel channel, Rank rank, BankGroup bankGroup, Bank bank, Row row, Column column, unsigned int burstLength, uint64_t threadPayloadID, uint64_t channelPayloadID); - static DramExtension &getExtension(const tlm::tlm_generic_payload *payload); static DramExtension &getExtension(const tlm::tlm_generic_payload &payload); - static void setPayloadIDs(tlm::tlm_generic_payload *payload, - uint64_t threadPayloadID, uint64_t channelPayloadID); static void setPayloadIDs(tlm::tlm_generic_payload &payload, uint64_t threadPayloadID, uint64_t channelPayloadID); - // Used for convience, caller could also use getExtension(..) to access these field - static Thread getThread(const tlm::tlm_generic_payload *payload); + // Used for convenience, caller could also use getExtension(..) to access these field static Thread getThread(const tlm::tlm_generic_payload &payload); - static Channel getChannel(const tlm::tlm_generic_payload *payload); static Channel getChannel(const tlm::tlm_generic_payload &payload); - static Rank getRank(const tlm::tlm_generic_payload *payload); static Rank getRank(const tlm::tlm_generic_payload &payload); - static BankGroup getBankGroup(const tlm::tlm_generic_payload *payload); static BankGroup getBankGroup(const tlm::tlm_generic_payload &payload); - static Bank getBank(const tlm::tlm_generic_payload *payload); static Bank getBank(const tlm::tlm_generic_payload &payload); - static Row getRow(const tlm::tlm_generic_payload *payload); static Row getRow(const tlm::tlm_generic_payload &payload); - static Column getColumn(const tlm::tlm_generic_payload *payload); static Column getColumn(const tlm::tlm_generic_payload &payload); - static unsigned getBurstLength(const tlm::tlm_generic_payload *payload); static unsigned getBurstLength(const tlm::tlm_generic_payload &payload); - static uint64_t getThreadPayloadID(const tlm::tlm_generic_payload *payload); static uint64_t getThreadPayloadID(const tlm::tlm_generic_payload &payload); - static uint64_t getChannelPayloadID(const tlm::tlm_generic_payload *payload); static uint64_t getChannelPayloadID(const tlm::tlm_generic_payload &payload); Thread getThread() const; @@ -243,11 +225,8 @@ public: : timeOfGeneration(timeOfGeneration) {} tlm::tlm_extension_base *clone() const override; void copy_from(const tlm::tlm_extension_base &ext) override; - static void setExtension(tlm::tlm_generic_payload *payload, const sc_core::sc_time &timeOfGeneration); - static void setExtension(tlm::tlm_generic_payload &payload, const sc_core::sc_time &timeOfGeneration); - static GenerationExtension &getExtension(const tlm::tlm_generic_payload *payload); + static void setExtension(tlm::tlm_generic_payload &payload, const sc_core::sc_time &_timeOfGeneration); static GenerationExtension &getExtension(const tlm::tlm_generic_payload &payload); - static sc_core::sc_time getTimeOfGeneration(const tlm::tlm_generic_payload *payload); static sc_core::sc_time getTimeOfGeneration(const tlm::tlm_generic_payload &payload); private: diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index 6c34a6b2..10b29206 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -57,7 +57,7 @@ void BankMachine::updateState(Command command) { case Command::ACT: state = State::Activated; - openRow = DramExtension::getRow(currentPayload); + openRow = DramExtension::getRow(*currentPayload); keepTrans = true; refreshManagementCounter++; break; @@ -180,7 +180,7 @@ sc_time BankMachineOpen::start() assert(!keepTrans || currentPayload != nullptr); if (keepTrans) { - if (DramExtension::getRow(newPayload) == openRow) + if (DramExtension::getRow(*newPayload) == openRow) currentPayload = newPayload; } else @@ -192,7 +192,7 @@ sc_time BankMachineOpen::start() nextCommand = Command::ACT; else if (state == State::Activated) { - if (DramExtension::getRow(currentPayload) == openRow) // row hit + if (DramExtension::getRow(*currentPayload) == openRow) // row hit { assert(currentPayload->is_read() || currentPayload->is_write()); if (currentPayload->is_read()) @@ -232,7 +232,7 @@ sc_time BankMachineClosed::start() assert(!keepTrans || currentPayload != nullptr); if (keepTrans) { - if (DramExtension::getRow(newPayload) == openRow) + if (DramExtension::getRow(*newPayload) == openRow) currentPayload = newPayload; } else @@ -279,7 +279,7 @@ sc_time BankMachineOpenAdaptive::start() assert(!keepTrans || currentPayload != nullptr); if (keepTrans) { - if (DramExtension::getRow(newPayload) == openRow) + if (DramExtension::getRow(*newPayload) == openRow) currentPayload = newPayload; } else @@ -291,7 +291,7 @@ sc_time BankMachineOpenAdaptive::start() nextCommand = Command::ACT; else if (state == State::Activated) { - if (DramExtension::getRow(currentPayload) == openRow) // row hit + if (DramExtension::getRow(*currentPayload) == openRow) // row hit { if (scheduler.hasFurtherRequest(bank, currentPayload->get_command()) && !scheduler.hasFurtherRowHit(bank, openRow, currentPayload->get_command())) @@ -343,7 +343,7 @@ sc_time BankMachineClosedAdaptive::start() assert(!keepTrans || currentPayload != nullptr); if (keepTrans) { - if (DramExtension::getRow(newPayload) == openRow) + if (DramExtension::getRow(*newPayload) == openRow) currentPayload = newPayload; } else @@ -355,7 +355,7 @@ sc_time BankMachineClosedAdaptive::start() nextCommand = Command::ACT; else if (state == State::Activated) { - if (DramExtension::getRow(currentPayload) == openRow) // row hit + if (DramExtension::getRow(*currentPayload) == openRow) // row hit { if (scheduler.hasFurtherRowHit(bank, openRow, currentPayload->get_command())) { diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index b1afbdee..08d9116e 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -69,8 +69,9 @@ using namespace sc_core; using namespace tlm; -Controller::Controller(const sc_module_name& name, const Configuration& config) : - ControllerIF(name, config), thinkDelayFw(config.thinkDelayFw), thinkDelayBw(config.thinkDelayBw), +Controller::Controller(const sc_module_name& name, const Configuration& config, const AddressDecoder& addressDecoder) : + ControllerIF(name, config), addressDecoder(addressDecoder), + thinkDelayFw(config.thinkDelayFw), thinkDelayBw(config.thinkDelayBw), phyDelayFw(config.phyDelayFw), phyDelayBw(config.phyDelayBw) { SC_METHOD(controllerMethod); @@ -283,8 +284,8 @@ void Controller::controllerMethod() tlm_generic_payload *payload = std::get(commandTuple); if (command != Command::NOP) // can happen with FIFO strict { - Rank rank = DramExtension::getRank(payload); - Bank bank = DramExtension::getBank(payload); + Rank rank = DramExtension::getRank(*payload); + Bank bank = DramExtension::getBank(*payload); if (command.isRankCommand()) { @@ -401,14 +402,14 @@ void Controller::manageRequests(const sc_time &delay) { if (scheduler->hasBufferSpace()) { - NDEBUG_UNUSED(uint64_t id) = DramExtension::getChannelPayloadID(transToAcquire.payload); + NDEBUG_UNUSED(uint64_t id) = DramExtension::getChannelPayloadID(*transToAcquire.payload); PRINTDEBUGMESSAGE(name(), "Payload " + std::to_string(id) + " entered system."); if (totalNumberOfPayloads == 0) idleTimeCollector.end(); totalNumberOfPayloads++; - Rank rank = DramExtension::getRank(transToAcquire.payload); + Rank rank = DramExtension::getRank(*transToAcquire.payload); if (ranksNumberOfPayloads[rank.ID()] == 0) powerDownManagers[rank.ID()]->triggerExit(); @@ -417,7 +418,7 @@ void Controller::manageRequests(const sc_time &delay) scheduler->storeRequest(*transToAcquire.payload); transToAcquire.payload->acquire(); - Bank bank = DramExtension::getBank(transToAcquire.payload); + Bank bank = DramExtension::getBank(*transToAcquire.payload); bankMachines[bank.ID()]->start(); transToAcquire.payload->set_response_status(TLM_OK_RESPONSE); @@ -440,10 +441,10 @@ void Controller::manageResponses() assert(transToRelease.time >= sc_time_stamp()); if (transToRelease.time == sc_time_stamp()) { - NDEBUG_UNUSED(uint64_t id) = DramExtension::getChannelPayloadID(transToRelease.payload); + NDEBUG_UNUSED(uint64_t id) = DramExtension::getChannelPayloadID(*transToRelease.payload); PRINTDEBUGMESSAGE(name(), "Payload " + std::to_string(id) + " left system."); - numberOfBeatsServed += DramExtension::getBurstLength(transToRelease.payload); + numberOfBeatsServed += DramExtension::getBurstLength(*transToRelease.payload); transToRelease.payload->release(); transToRelease.payload = nullptr; totalNumberOfPayloads--; diff --git a/DRAMSys/library/src/controller/Controller.h b/DRAMSys/library/src/controller/Controller.h index 12a9a879..4852f549 100644 --- a/DRAMSys/library/src/controller/Controller.h +++ b/DRAMSys/library/src/controller/Controller.h @@ -48,11 +48,12 @@ #include "refresh/RefreshManagerIF.h" #include "powerdown/PowerDownManagerIF.h" #include "respqueue/RespQueueIF.h" +#include "../simulation/AddressDecoder.h" class Controller : public ControllerIF { public: - Controller(const sc_core::sc_module_name& name, const Configuration& config); + Controller(const sc_core::sc_module_name& name, const Configuration& config, const AddressDecoder& addressDecoder); SC_HAS_PROCESS(Controller); protected: @@ -87,6 +88,8 @@ private: std::vector> refreshManagers; std::vector> powerDownManagers; + const AddressDecoder& addressDecoder; + struct Transaction { tlm::tlm_generic_payload *payload = nullptr; diff --git a/DRAMSys/library/src/controller/ControllerRecordable.cpp b/DRAMSys/library/src/controller/ControllerRecordable.cpp index 5ef3fbe7..f7aa782a 100644 --- a/DRAMSys/library/src/controller/ControllerRecordable.cpp +++ b/DRAMSys/library/src/controller/ControllerRecordable.cpp @@ -40,8 +40,8 @@ using namespace sc_core; using namespace tlm; ControllerRecordable::ControllerRecordable(const sc_module_name &name, const Configuration& config, - TlmRecorder& tlmRecorder) - : Controller(name, config), tlmRecorder(tlmRecorder), + const AddressDecoder& addressDecoder, TlmRecorder& tlmRecorder) + : Controller(name, config, addressDecoder), tlmRecorder(tlmRecorder), activeTimeMultiplier(config.memSpec->tCK / config.memSpec->dataRate), enableWindowing(config.enableWindowing), windowSizeTime(config.windowSize * memSpec.tCK) { diff --git a/DRAMSys/library/src/controller/ControllerRecordable.h b/DRAMSys/library/src/controller/ControllerRecordable.h index c02fab6a..ef4d69fd 100644 --- a/DRAMSys/library/src/controller/ControllerRecordable.h +++ b/DRAMSys/library/src/controller/ControllerRecordable.h @@ -43,7 +43,8 @@ class ControllerRecordable final : public Controller { public: - ControllerRecordable(const sc_core::sc_module_name &name, const Configuration& config, TlmRecorder& tlmRecorder); + ControllerRecordable(const sc_core::sc_module_name &name, const Configuration& config, + const AddressDecoder& addressDecoder, TlmRecorder& tlmRecorder); ~ControllerRecordable() override = default; protected: diff --git a/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.cpp b/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.cpp index 3426c142..7ff7181c 100644 --- a/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.cpp +++ b/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.cpp @@ -52,7 +52,7 @@ CommandTuple::Type CmdMuxOldest::selectCommand(const ReadyCommands &readyCommand { newTimestamp = std::get(*it) + memSpec.getCommandLength(std::get(*it)); - newPayloadID = DramExtension::getChannelPayloadID(std::get(*it)); + newPayloadID = DramExtension::getChannelPayloadID(*std::get(*it)); if (newTimestamp < lastTimestamp) { @@ -108,7 +108,7 @@ CommandTuple::Type CmdMuxOldestRasCas::selectCommand(const ReadyCommands &readyC { newTimestamp = std::get(*it) + memSpec.getCommandLength(std::get(*it)); - newPayloadID = DramExtension::getChannelPayloadID(std::get(*it)); + newPayloadID = DramExtension::getChannelPayloadID(*std::get(*it)); if (newTimestamp < lastTimestamp) { @@ -130,7 +130,7 @@ CommandTuple::Type CmdMuxOldestRasCas::selectCommand(const ReadyCommands &readyC { newTimestamp = std::get(*it) + memSpec.getCommandLength(std::get(*it)); - newPayloadID = DramExtension::getChannelPayloadID(std::get(*it)); + newPayloadID = DramExtension::getChannelPayloadID(*std::get(*it)); if (newTimestamp < lastTimestamp) { @@ -158,7 +158,7 @@ CommandTuple::Type CmdMuxOldestRasCas::selectCommand(const ReadyCommands &readyC for (auto it = readyRasCasCommands.cbegin(); it != readyRasCasCommands.cend(); it++) { newTimestamp = std::get(*it); - newPayloadID = DramExtension::getChannelPayloadID(std::get(*it)); + newPayloadID = DramExtension::getChannelPayloadID(*std::get(*it)); if (newTimestamp < lastTimestamp) { diff --git a/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp b/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp index 3bd7baba..d046b161 100644 --- a/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp +++ b/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp @@ -52,7 +52,7 @@ CommandTuple::Type CmdMuxStrict::selectCommand(const ReadyCommands &readyCommand { newTimestamp = std::get(*it) + memSpec.getCommandLength(std::get(*it)); - newPayloadID = DramExtension::getChannelPayloadID(std::get(*it)); + newPayloadID = DramExtension::getChannelPayloadID(*std::get(*it)); if (newTimestamp < lastTimestamp) { @@ -118,7 +118,7 @@ CommandTuple::Type CmdMuxStrictRasCas::selectCommand(const ReadyCommands &readyC { newTimestamp = std::get(*it) + memSpec.getCommandLength(std::get(*it)); - newPayloadID = DramExtension::getChannelPayloadID(std::get(*it)); + newPayloadID = DramExtension::getChannelPayloadID(*std::get(*it)); if (newTimestamp < lastTimestamp) { @@ -135,7 +135,7 @@ CommandTuple::Type CmdMuxStrictRasCas::selectCommand(const ReadyCommands &readyC for (auto it = readyCasCommands.cbegin(); it != readyCasCommands.cend(); it++) { - newPayloadID = DramExtension::getChannelPayloadID(std::get(*it)); + newPayloadID = DramExtension::getChannelPayloadID(*std::get(*it)); if (newPayloadID == nextPayloadID) { @@ -157,7 +157,7 @@ CommandTuple::Type CmdMuxStrictRasCas::selectCommand(const ReadyCommands &readyC for (auto it = readyRasCasCommands.cbegin(); it != readyRasCasCommands.cend(); it++) { newTimestamp = std::get(*it); - newPayloadID = DramExtension::getChannelPayloadID(std::get(*it)); + newPayloadID = DramExtension::getChannelPayloadID(*std::get(*it)); if (newTimestamp < lastTimestamp) { diff --git a/DRAMSys/library/src/controller/respqueue/RespQueueReorder.cpp b/DRAMSys/library/src/controller/respqueue/RespQueueReorder.cpp index a1214ac6..32793a6e 100644 --- a/DRAMSys/library/src/controller/respqueue/RespQueueReorder.cpp +++ b/DRAMSys/library/src/controller/respqueue/RespQueueReorder.cpp @@ -40,7 +40,7 @@ using namespace tlm; void RespQueueReorder::insertPayload(tlm_generic_payload *payload, sc_time strobeEnd) { - buffer[DramExtension::getChannelPayloadID(payload)] = {payload, strobeEnd}; + buffer[DramExtension::getChannelPayloadID(*payload)] = {payload, strobeEnd}; } tlm_generic_payload *RespQueueReorder::nextPayload() diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp b/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp index 674bf7e8..52cd08ed 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp @@ -82,7 +82,7 @@ bool SchedulerFifo::hasFurtherRowHit(Bank bank, Row row, tlm_command command) co { if (buffer[bank.ID()].size() >= 2) { - tlm_generic_payload *nextRequest = buffer[bank.ID()][1]; + tlm_generic_payload& nextRequest = *buffer[bank.ID()][1]; if (DramExtension::getRow(nextRequest) == row) return true; } diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp index 63487b10..3c5d4587 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp @@ -88,7 +88,7 @@ tlm_generic_payload *SchedulerFrFcfs::getNextRequest(const BankMachine& bankMach Row openRow = bankMachine.getOpenRow(); for (auto it : buffer[bankID]) { - if (DramExtension::getRow(it) == openRow) + if (DramExtension::getRow(*it) == openRow) return it; } } @@ -103,7 +103,7 @@ bool SchedulerFrFcfs::hasFurtherRowHit(Bank bank, Row row, tlm_command command) unsigned rowHitCounter = 0; for (auto it : buffer[bank.ID()]) { - if (DramExtension::getRow(it) == row) + if (DramExtension::getRow(*it) == row) { rowHitCounter++; if (rowHitCounter == 2) diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.cpp b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.cpp index f616ceff..b4b6320b 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.cpp +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.cpp @@ -90,7 +90,7 @@ tlm_generic_payload *SchedulerFrFcfsGrp::getNextRequest(const BankMachine& bankM std::list rowHits; for (auto it : buffer[bankID]) { - if (DramExtension::getRow(it) == openRow) + if (DramExtension::getRow(*it) == openRow) rowHits.push_back(it); } @@ -128,7 +128,7 @@ bool SchedulerFrFcfsGrp::hasFurtherRowHit(Bank bank, Row row, tlm_command comman unsigned rowHitCounter = 0; for (auto it : buffer[bank.ID()]) { - if (DramExtension::getRow(it) == row) + if (DramExtension::getRow(*it) == row) { rowHitCounter++; if (rowHitCounter == 2) diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerGrpFrFcfs.cpp b/DRAMSys/library/src/controller/scheduler/SchedulerGrpFrFcfs.cpp index da79cf7b..cd9f697c 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerGrpFrFcfs.cpp +++ b/DRAMSys/library/src/controller/scheduler/SchedulerGrpFrFcfs.cpp @@ -97,7 +97,7 @@ tlm_generic_payload *SchedulerGrpFrFcfs::getNextRequest(const BankMachine& bankM Row openRow = bankMachine.getOpenRow(); for (auto it : readBuffer[bankID]) { - if (DramExtension::getRow(it) == openRow) + if (DramExtension::getRow(*it) == openRow) return it; } } @@ -112,7 +112,7 @@ tlm_generic_payload *SchedulerGrpFrFcfs::getNextRequest(const BankMachine& bankM Row openRow = bankMachine.getOpenRow(); for (auto it : writeBuffer[bankID]) { - if (DramExtension::getRow(it) == openRow) + if (DramExtension::getRow(*it) == openRow) return it; } } @@ -132,7 +132,7 @@ tlm_generic_payload *SchedulerGrpFrFcfs::getNextRequest(const BankMachine& bankM Row openRow = bankMachine.getOpenRow(); for (auto it : writeBuffer[bankID]) { - if (DramExtension::getRow(it) == openRow) + if (DramExtension::getRow(*it) == openRow) return it; } } @@ -147,7 +147,7 @@ tlm_generic_payload *SchedulerGrpFrFcfs::getNextRequest(const BankMachine& bankM Row openRow = bankMachine.getOpenRow(); for (auto it : readBuffer[bankID]) { - if (DramExtension::getRow(it) == openRow) + if (DramExtension::getRow(*it) == openRow) return it; } } @@ -167,7 +167,7 @@ bool SchedulerGrpFrFcfs::hasFurtherRowHit(Bank bank, Row row, tlm_command comman { for (auto it : readBuffer[bank.ID()]) { - if (DramExtension::getRow(it) == row) + if (DramExtension::getRow(*it) == row) { rowHitCounter++; if (rowHitCounter == 2) @@ -180,7 +180,7 @@ bool SchedulerGrpFrFcfs::hasFurtherRowHit(Bank bank, Row row, tlm_command comman { for (auto it : writeBuffer[bank.ID()]) { - if (DramExtension::getRow(it) == row) + if (DramExtension::getRow(*it) == row) { rowHitCounter++; if (rowHitCounter == 2) diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerGrpFrFcfsWm.cpp b/DRAMSys/library/src/controller/scheduler/SchedulerGrpFrFcfsWm.cpp index 63de3575..c6adda13 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerGrpFrFcfsWm.cpp +++ b/DRAMSys/library/src/controller/scheduler/SchedulerGrpFrFcfsWm.cpp @@ -101,7 +101,7 @@ tlm_generic_payload *SchedulerGrpFrFcfsWm::getNextRequest(const BankMachine& ban Row openRow = bankMachine.getOpenRow(); for (auto it : readBuffer[bankID]) { - if (DramExtension::getRow(it) == openRow) + if (DramExtension::getRow(*it) == openRow) return it; } } @@ -121,7 +121,7 @@ tlm_generic_payload *SchedulerGrpFrFcfsWm::getNextRequest(const BankMachine& ban Row openRow = bankMachine.getOpenRow(); for (auto it : writeBuffer[bankID]) { - if (DramExtension::getRow(it) == openRow) + if (DramExtension::getRow(*it) == openRow) return it; } } @@ -140,7 +140,7 @@ bool SchedulerGrpFrFcfsWm::hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command { for (const auto* it : readBuffer[bank.ID()]) { - if (DramExtension::getRow(it) == row) + if (DramExtension::getRow(*it) == row) { rowHitCounter++; if (rowHitCounter == 2) @@ -153,7 +153,7 @@ bool SchedulerGrpFrFcfsWm::hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command { for (auto it : writeBuffer[bank.ID()]) { - if (DramExtension::getRow(it) == row) + if (DramExtension::getRow(*it) == row) { rowHitCounter++; if (rowHitCounter == 2) diff --git a/DRAMSys/library/src/simulation/AddressDecoder.cpp b/DRAMSys/library/src/simulation/AddressDecoder.cpp index a6d7c390..cd9321de 100644 --- a/DRAMSys/library/src/simulation/AddressDecoder.cpp +++ b/DRAMSys/library/src/simulation/AddressDecoder.cpp @@ -116,7 +116,7 @@ AddressDecoder::AddressDecoder(const Configuration& config, const DRAMSysConfigu SC_REPORT_FATAL("AddressDecoder", "Memspec and address mapping do not match"); } -DecodedAddress AddressDecoder::decodeAddress(uint64_t encAddr) +DecodedAddress AddressDecoder::decodeAddress(uint64_t encAddr) const { if (encAddr > maximumAddress) SC_REPORT_WARNING("AddressDecoder", ("Address " + std::to_string(encAddr) + " out of range (maximum address is " + std::to_string(maximumAddress) + ")").c_str()); @@ -161,7 +161,31 @@ DecodedAddress AddressDecoder::decodeAddress(uint64_t encAddr) return decAddr; } -void AddressDecoder::print() +unsigned AddressDecoder::decodeChannel(uint64_t encAddr) const +{ + if (encAddr > maximumAddress) + SC_REPORT_WARNING("AddressDecoder", ("Address " + std::to_string(encAddr) + " out of range (maximum address is " + std::to_string(maximumAddress) + ")").c_str()); + + // Apply XOR + // For each used xor: + // Get the first bit and second bit. Apply a bitwise xor operator and save it back to the first bit. + for (auto &it : vXor) + { + uint64_t xoredBit; + xoredBit = (((encAddr >> it.first) & UINT64_C(1)) ^ ((encAddr >> it.second) & UINT64_C(1))); + encAddr &= ~(UINT64_C(1) << it.first); + encAddr |= xoredBit << it.first; + } + + unsigned channel = 0; + + for (unsigned it = 0; it < vChannelBits.size(); it++) + channel |= ((encAddr >> vChannelBits[it]) & UINT64_C(1)) << it; + + return channel; +} + +void AddressDecoder::print() const { std::cout << headline << std::endl; std::cout << "Used Address Mapping:" << std::endl; diff --git a/DRAMSys/library/src/simulation/AddressDecoder.h b/DRAMSys/library/src/simulation/AddressDecoder.h index 8989190d..74b34679 100644 --- a/DRAMSys/library/src/simulation/AddressDecoder.h +++ b/DRAMSys/library/src/simulation/AddressDecoder.h @@ -68,8 +68,9 @@ class AddressDecoder { public: AddressDecoder(const Configuration& config, const DRAMSysConfiguration::AddressMapping &addressMapping); - DecodedAddress decodeAddress(uint64_t addr); - void print(); + DecodedAddress decodeAddress(uint64_t encAddr) const; + unsigned decodeChannel(uint64_t encAddr) const; + void print() const; private: unsigned banksPerGroup; diff --git a/DRAMSys/library/src/simulation/Arbiter.cpp b/DRAMSys/library/src/simulation/Arbiter.cpp index 2a1620f4..9bbf1992 100644 --- a/DRAMSys/library/src/simulation/Arbiter.cpp +++ b/DRAMSys/library/src/simulation/Arbiter.cpp @@ -47,8 +47,8 @@ using namespace sc_core; using namespace tlm; Arbiter::Arbiter(const sc_module_name &name, const Configuration& config, - const DRAMSysConfiguration::AddressMapping& addressMapping) : - sc_module(name), addressDecoder(config, addressMapping), payloadEventQueue(this, &Arbiter::peqCallback), + const AddressDecoder& addressDecoder) : + sc_module(name), addressDecoder(addressDecoder), payloadEventQueue(this, &Arbiter::peqCallback), tCK(config.memSpec->tCK), arbitrationDelayFw(config.arbitrationDelayFw), arbitrationDelayBw(config.arbitrationDelayBw), @@ -58,22 +58,20 @@ Arbiter::Arbiter(const sc_module_name &name, const Configuration& config, iSocket.register_nb_transport_bw(this, &Arbiter::nb_transport_bw); tSocket.register_nb_transport_fw(this, &Arbiter::nb_transport_fw); tSocket.register_transport_dbg(this, &Arbiter::transport_dbg); - - addressDecoder.print(); } ArbiterSimple::ArbiterSimple(const sc_module_name& name, const Configuration& config, - const DRAMSysConfiguration::AddressMapping &addressMapping) : - Arbiter(name, config, addressMapping) {} + const AddressDecoder& addressDecoder) : + Arbiter(name, config, addressDecoder) {} ArbiterFifo::ArbiterFifo(const sc_module_name &name, const Configuration& config, - const DRAMSysConfiguration::AddressMapping &addressMapping) : - Arbiter(name, config, addressMapping), + const AddressDecoder& addressDecoder) : + Arbiter(name, config, addressDecoder), maxActiveTransactions(config.maxActiveTransactions) {} ArbiterReorder::ArbiterReorder(const sc_module_name &name, const Configuration& config, - const DRAMSysConfiguration::AddressMapping &addressMapping) : - Arbiter(name, config, addressMapping), + const AddressDecoder& addressDecoder) : + Arbiter(name, config, addressDecoder), maxActiveTransactions(config.maxActiveTransactions) {} void Arbiter::end_of_elaboration() diff --git a/DRAMSys/library/src/simulation/Arbiter.h b/DRAMSys/library/src/simulation/Arbiter.h index dcc96a75..799ab27c 100644 --- a/DRAMSys/library/src/simulation/Arbiter.h +++ b/DRAMSys/library/src/simulation/Arbiter.h @@ -64,12 +64,12 @@ public: protected: Arbiter(const sc_core::sc_module_name &name, const Configuration& config, - const DRAMSysConfiguration::AddressMapping &addressMapping); + const AddressDecoder& addressDecoder); SC_HAS_PROCESS(Arbiter); void end_of_elaboration() override; - AddressDecoder addressDecoder; + const AddressDecoder& addressDecoder; tlm_utils::peq_with_cb_and_phase payloadEventQueue; virtual void peqCallback(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase) = 0; @@ -100,7 +100,7 @@ class ArbiterSimple final : public Arbiter { public: ArbiterSimple(const sc_core::sc_module_name &name, const Configuration& config, - const DRAMSysConfiguration::AddressMapping &addressMapping); + const AddressDecoder& addressDecoder); SC_HAS_PROCESS(ArbiterSimple); private: @@ -114,7 +114,7 @@ class ArbiterFifo final : public Arbiter { public: ArbiterFifo(const sc_core::sc_module_name &name, const Configuration& config, - const DRAMSysConfiguration::AddressMapping &addressMapping); + const AddressDecoder& addressDecoder); SC_HAS_PROCESS(ArbiterFifo); private: @@ -135,7 +135,7 @@ class ArbiterReorder final : public Arbiter { public: ArbiterReorder(const sc_core::sc_module_name &name, const Configuration& config, - const DRAMSysConfiguration::AddressMapping &addressMapping); + const AddressDecoder& addressDecoder); SC_HAS_PROCESS(ArbiterReorder); private: @@ -149,7 +149,7 @@ private: { bool operator() (const tlm::tlm_generic_payload *lhs, const tlm::tlm_generic_payload *rhs) const { - return DramExtension::getThreadPayloadID(lhs) < DramExtension::getThreadPayloadID(rhs); + return DramExtension::getThreadPayloadID(*lhs) < DramExtension::getThreadPayloadID(*rhs); } }; diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index dcdf9f5b..9582b765 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -149,23 +149,27 @@ void DRAMSys::setupDebugManager(NDEBUG_UNUSED(const std::string &traceName)) #endif } -void DRAMSys::instantiateModules(const DRAMSysConfiguration::AddressMapping &addressMapping) +void DRAMSys::instantiateModules(const DRAMSysConfiguration::AddressMapping& addressMapping) { temperatureController = std::make_unique("TemperatureController", config); + addressDecoder = std::make_unique(config, addressMapping); + addressDecoder->print(); + // Create arbiter if (config.arbiter == Configuration::Arbiter::Simple) - arbiter = std::make_unique("arbiter", config, addressMapping); + arbiter = std::make_unique("arbiter", config, *addressDecoder); else if (config.arbiter == Configuration::Arbiter::Fifo) - arbiter = std::make_unique("arbiter", config, addressMapping); + arbiter = std::make_unique("arbiter", config, *addressDecoder); else if (config.arbiter == Configuration::Arbiter::Reorder) - arbiter = std::make_unique("arbiter", config, addressMapping); + arbiter = std::make_unique("arbiter", config, *addressDecoder); // Create controllers and DRAMs MemSpec::MemoryType memoryType = config.memSpec->memoryType; for (std::size_t i = 0; i < config.memSpec->numberOfChannels; i++) { - controllers.emplace_back(std::make_unique(("controller" + std::to_string(i)).c_str(), config)); + controllers.emplace_back(std::make_unique(("controller" + std::to_string(i)).c_str(), config, + *addressDecoder)); if (memoryType == MemSpec::MemoryType::DDR3) drams.emplace_back(std::make_unique(("dram" + std::to_string(i)).c_str(), config, diff --git a/DRAMSys/library/src/simulation/DRAMSys.h b/DRAMSys/library/src/simulation/DRAMSys.h index d0c8ec74..33cdba50 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.h +++ b/DRAMSys/library/src/simulation/DRAMSys.h @@ -48,6 +48,7 @@ #include "../error/eccbaseclass.h" #include "../controller/ControllerIF.h" #include "TemperatureController.h" +#include "AddressDecoder.h" #include #include @@ -94,6 +95,8 @@ protected: // DRAM units std::vector> drams; + std::unique_ptr addressDecoder; + void report(const std::string &message); void bindSockets(); diff --git a/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp b/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp index 77bd94e7..e2110b48 100644 --- a/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp +++ b/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp @@ -116,18 +116,18 @@ void DRAMSysRecordable::instantiateModules(const std::string &traceName, // Create arbiter if (config.arbiter == Configuration::Arbiter::Simple) - arbiter = std::make_unique("arbiter", config, configLib.addressMapping); + arbiter = std::make_unique("arbiter", config, *addressDecoder); else if (config.arbiter == Configuration::Arbiter::Fifo) - arbiter = std::make_unique("arbiter", config, configLib.addressMapping); + arbiter = std::make_unique("arbiter", config, *addressDecoder); else if (config.arbiter == Configuration::Arbiter::Reorder) - arbiter = std::make_unique("arbiter", config, configLib.addressMapping); + arbiter = std::make_unique("arbiter", config, *addressDecoder); // Create controllers and DRAMs MemSpec::MemoryType memoryType = config.memSpec->memoryType; for (std::size_t i = 0; i < config.memSpec->numberOfChannels; i++) { controllers.emplace_back(std::make_unique(("controller" + std::to_string(i)).c_str(), - config, tlmRecorders[i])); + config, *addressDecoder, tlmRecorders[i])); if (memoryType == MemSpec::MemoryType::DDR3) drams.emplace_back(std::make_unique>(("dram" + std::to_string(i)).c_str(), From ef29af81e39a87967786a1bf9a18b921a6b96d87 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Wed, 20 Apr 2022 16:57:23 +0200 Subject: [PATCH 02/29] Bugfix, instantiate address decoder. --- DRAMSys/library/src/simulation/DRAMSysRecordable.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp b/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp index e2110b48..24e9a2a9 100644 --- a/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp +++ b/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp @@ -110,6 +110,9 @@ void DRAMSysRecordable::instantiateModules(const std::string &traceName, { temperatureController = std::make_unique("TemperatureController", config); + addressDecoder = std::make_unique(config, configLib.addressMapping); + addressDecoder->print(); + // Create and properly initialize TLM recorders. // They need to be ready before creating some modules. setupTlmRecorders(traceName, configLib); From 7c1642bc58a2699231c8f3f80d15e4731c7fbb0d Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Tue, 26 Apr 2022 11:10:30 +0200 Subject: [PATCH 03/29] Add new dram extensions. --- DRAMSys/library/src/common/dramExtensions.cpp | 147 ++++++++++++++++++ DRAMSys/library/src/common/dramExtensions.h | 54 +++++++ 2 files changed, 201 insertions(+) diff --git a/DRAMSys/library/src/common/dramExtensions.cpp b/DRAMSys/library/src/common/dramExtensions.cpp index 4843ec67..bc4e45b2 100644 --- a/DRAMSys/library/src/common/dramExtensions.cpp +++ b/DRAMSys/library/src/common/dramExtensions.cpp @@ -41,6 +41,153 @@ using namespace sc_core; using namespace tlm; +ArbiterExtension::ArbiterExtension(Thread thread, Channel channel, uint64_t threadPayloadID, + const sc_core::sc_time& timeOfGeneration) : + thread(thread), channel(channel), threadPayloadID(threadPayloadID), timeOfGeneration(timeOfGeneration) +{} + +void ArbiterExtension::setExtension(tlm::tlm_generic_payload& trans, Thread thread, Channel channel) +{ + auto* extension = trans.get_extension(); + + if (extension != nullptr) + { + extension->thread = thread; + extension->channel = channel; + extension->threadPayloadID = 0; + extension->timeOfGeneration = SC_ZERO_TIME; + } + else + { + extension = new ArbiterExtension(thread, channel, 0, SC_ZERO_TIME); + trans.set_auto_extension(extension); + } +} + +void ArbiterExtension::setIDAndTimeOfGeneration(tlm::tlm_generic_payload& trans, uint64_t threadPayloadID, + const sc_core::sc_time& timeOfGeneration) +{ + assert(trans.get_extension() != nullptr); + + auto* extension = trans.get_extension(); + extension->threadPayloadID = threadPayloadID; + extension->timeOfGeneration = timeOfGeneration; +} + +tlm_extension_base* ArbiterExtension::clone() const +{ + return new ArbiterExtension(thread, channel, threadPayloadID, timeOfGeneration); +} + +void ArbiterExtension::copy_from(const tlm_extension_base& ext) +{ + const auto& cpyFrom = dynamic_cast(ext); + thread = cpyFrom.thread; + channel = cpyFrom.channel; + threadPayloadID = cpyFrom.threadPayloadID; + timeOfGeneration = cpyFrom.timeOfGeneration; +} + +Thread ArbiterExtension::getThread(const tlm::tlm_generic_payload& trans) +{ + return trans.get_extension()->thread; +} + +Channel ArbiterExtension::getChannel(const tlm::tlm_generic_payload& trans) +{ + return trans.get_extension()->channel; +} + +uint64_t ArbiterExtension::getThreadPayloadID(const tlm::tlm_generic_payload& trans) +{ + return trans.get_extension()->threadPayloadID; +} + +sc_time ArbiterExtension::getTimeOfGeneration(const tlm::tlm_generic_payload& trans) +{ + return trans.get_extension()->timeOfGeneration; +} + +ControllerExtension::ControllerExtension(uint64_t channelPayloadID, Rank rank, BankGroup bankGroup, Bank bank, Row row, + Column column, unsigned int burstLength) : + channelPayloadID(channelPayloadID), rank(rank), bankGroup(bankGroup), bank(bank), row(row), column(column), + burstLength(burstLength) +{} + +void ControllerExtension::setExtension(tlm::tlm_generic_payload& trans, uint64_t channelPayloadID, Rank rank, + BankGroup bankGroup, Bank bank, Row row, Column column, unsigned int burstLength) +{ + auto* extension = trans.get_extension(); + + if (extension != nullptr) + { + extension->channelPayloadID = channelPayloadID; + extension->rank = rank; + extension->bankGroup = bankGroup; + extension->bank = bank; + extension->row = row; + extension->column = column; + extension->burstLength = burstLength; + } + else + { + extension = new ControllerExtension(channelPayloadID, rank, bankGroup, bank, row, column, burstLength); + trans.set_auto_extension(extension); + } +} + +tlm_extension_base* ControllerExtension::clone() const +{ + return new ControllerExtension(channelPayloadID, rank, bankGroup, bank, row, column, burstLength); +} + +void ControllerExtension::copy_from(const tlm_extension_base& ext) +{ + const auto& cpyFrom = dynamic_cast(ext); + channelPayloadID = cpyFrom.channelPayloadID; + rank = cpyFrom.rank; + bankGroup = cpyFrom.bankGroup; + bank = cpyFrom.bank; + row = cpyFrom.row; + column = cpyFrom.column; + burstLength = cpyFrom.burstLength; +} + +uint64_t ControllerExtension::getChannelPayloadID(const tlm::tlm_generic_payload& trans) +{ + return trans.get_extension()->channelPayloadID; +} + +Rank ControllerExtension::getRank(const tlm::tlm_generic_payload& trans) +{ + return trans.get_extension()->rank; +} + +BankGroup ControllerExtension::getBankGroup(const tlm::tlm_generic_payload& trans) +{ + return trans.get_extension()->bankGroup; +} + +Bank ControllerExtension::getBank(const tlm::tlm_generic_payload& trans) +{ + return trans.get_extension()->bank; +} + +Row ControllerExtension::getRow(const tlm::tlm_generic_payload& trans) +{ + return trans.get_extension()->row; +} + +Column ControllerExtension::getColumn(const tlm::tlm_generic_payload& trans) +{ + return trans.get_extension()->column; +} + +unsigned ControllerExtension::getBurstLength(const tlm::tlm_generic_payload& trans) +{ + return trans.get_extension()->burstLength; +} + DramExtension::DramExtension() : thread(0), channel(0), rank(0), bankGroup(0), bank(0), row(0), column(0), burstLength(0), diff --git a/DRAMSys/library/src/common/dramExtensions.h b/DRAMSys/library/src/common/dramExtensions.h index cfd9cb9a..27726bb7 100644 --- a/DRAMSys/library/src/common/dramExtensions.h +++ b/DRAMSys/library/src/common/dramExtensions.h @@ -154,6 +154,60 @@ private: unsigned int id; }; +class ArbiterExtension : public tlm::tlm_extension +{ +public: + static void setExtension(tlm::tlm_generic_payload& trans, Thread thread, Channel channel); + static void setIDAndTimeOfGeneration(tlm::tlm_generic_payload& trans, uint64_t threadPayloadID, + const sc_core::sc_time& timeOfGeneration); + + tlm::tlm_extension_base* clone() const override; + void copy_from(const tlm::tlm_extension_base& ext) override; + + static Thread getThread(const tlm::tlm_generic_payload& trans); + static Channel getChannel(const tlm::tlm_generic_payload& trans); + static uint64_t getThreadPayloadID(const tlm::tlm_generic_payload& trans); + static sc_core::sc_time getTimeOfGeneration(const tlm::tlm_generic_payload& trans); + +private: + ArbiterExtension(Thread thread, Channel channel, uint64_t threadPayloadID, const sc_core::sc_time& timeOfGeneration); + Thread thread; + Channel channel; + uint64_t threadPayloadID; + sc_core::sc_time timeOfGeneration; +}; + +class ControllerExtension : public tlm::tlm_extension +{ +public: + static void setExtension(tlm::tlm_generic_payload& trans, uint64_t channelPayloadID, Rank rank, BankGroup bankGroup, + Bank bank, Row row, Column column, unsigned burstLength); + + //static ControllerExtension& getExtension(const tlm::tlm_generic_payload& trans); + + tlm::tlm_extension_base* clone() const override; + void copy_from(const tlm::tlm_extension_base& ext) override; + + static uint64_t getChannelPayloadID(const tlm::tlm_generic_payload& trans); + static Rank getRank(const tlm::tlm_generic_payload& trans); + static BankGroup getBankGroup(const tlm::tlm_generic_payload& trans); + static Bank getBank(const tlm::tlm_generic_payload& trans); + static Row getRow(const tlm::tlm_generic_payload& trans); + static Column getColumn(const tlm::tlm_generic_payload& trans); + static unsigned getBurstLength(const tlm::tlm_generic_payload& trans); + +private: + ControllerExtension(uint64_t channelPayloadID, Rank rank, BankGroup bankGroup, Bank bank, Row row, Column column, + unsigned burstLength); + uint64_t channelPayloadID; + Rank rank; + BankGroup bankGroup; + Bank bank; + Row row; + Column column; + unsigned burstLength; +}; + class DramExtension : public tlm::tlm_extension { From 844eaa390a8e98518e10318cdb0ddfb949426fd5 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Wed, 27 Apr 2022 11:13:35 +0200 Subject: [PATCH 04/29] Integrate new extensions. --- DRAMSys/library/src/common/TlmRecorder.cpp | 50 +-- DRAMSys/library/src/common/TlmRecorder.h | 10 +- DRAMSys/library/src/common/dramExtensions.cpp | 307 +++++------------- DRAMSys/library/src/common/dramExtensions.h | 103 ++---- DRAMSys/library/src/common/utils.cpp | 5 +- .../src/configuration/memspec/MemSpec.cpp | 1 + .../src/configuration/memspec/MemSpec.h | 1 + .../src/configuration/memspec/MemSpecDDR5.cpp | 10 +- .../library/src/controller/BankMachine.cpp | 16 +- DRAMSys/library/src/controller/Controller.cpp | 29 +- DRAMSys/library/src/controller/Controller.h | 1 + .../src/controller/ControllerRecordable.cpp | 18 +- .../src/controller/checker/CheckerDDR3.cpp | 12 +- .../src/controller/checker/CheckerDDR4.cpp | 16 +- .../src/controller/checker/CheckerDDR5.cpp | 18 +- .../src/controller/checker/CheckerGDDR5.cpp | 16 +- .../src/controller/checker/CheckerGDDR5X.cpp | 16 +- .../src/controller/checker/CheckerGDDR6.cpp | 16 +- .../src/controller/checker/CheckerHBM2.cpp | 16 +- .../src/controller/checker/CheckerLPDDR4.cpp | 12 +- .../src/controller/checker/CheckerLPDDR5.cpp | 18 +- .../src/controller/checker/CheckerSTTMRAM.cpp | 12 +- .../src/controller/checker/CheckerWideIO.cpp | 12 +- .../src/controller/checker/CheckerWideIO2.cpp | 12 +- .../src/controller/cmdmux/CmdMuxOldest.cpp | 8 +- .../src/controller/cmdmux/CmdMuxStrict.cpp | 8 +- .../controller/respqueue/RespQueueReorder.cpp | 2 +- .../scheduler/BufferCounterBankwise.cpp | 4 +- .../controller/scheduler/SchedulerFifo.cpp | 6 +- .../controller/scheduler/SchedulerFrFcfs.cpp | 8 +- .../scheduler/SchedulerFrFcfsGrp.cpp | 8 +- .../scheduler/SchedulerGrpFrFcfs.cpp | 18 +- .../scheduler/SchedulerGrpFrFcfsWm.cpp | 14 +- DRAMSys/library/src/error/errormodel.cpp | 23 +- DRAMSys/library/src/simulation/Arbiter.cpp | 50 ++- DRAMSys/library/src/simulation/Arbiter.h | 2 +- DRAMSys/library/src/simulation/dram/Dram.cpp | 2 +- .../src/simulation/dram/DramRecordable.cpp | 12 +- .../src/simulation/dram/DramWideIO.cpp | 8 +- 39 files changed, 358 insertions(+), 542 deletions(-) diff --git a/DRAMSys/library/src/common/TlmRecorder.cpp b/DRAMSys/library/src/common/TlmRecorder.cpp index dd22ec4a..15ffc4da 100644 --- a/DRAMSys/library/src/common/TlmRecorder.cpp +++ b/DRAMSys/library/src/common/TlmRecorder.cpp @@ -123,16 +123,16 @@ void TlmRecorder::recordPhase(tlm_generic_payload &trans, if (phase == END_REQ || phase == END_RESP || phase >= END_PDNA) { - assert(getPhaseName(phase).substr(4) == currentTransactionsInSystem[&trans].recordedPhases.back().name); - currentTransactionsInSystem[&trans].recordedPhases.back().interval.end = time; + assert(getPhaseName(phase).substr(4) == currentTransactionsInSystem.at(&trans).recordedPhases.back().name); + currentTransactionsInSystem.at(&trans).recordedPhases.back().interval.end = time; } else { std::string phaseName = getPhaseName(phase).substr(6); // remove "BEGIN_" - currentTransactionsInSystem[&trans].recordedPhases.emplace_back(phaseName, time); + currentTransactionsInSystem.at(&trans).recordedPhases.emplace_back(phaseName, time); } - if (currentTransactionsInSystem[&trans].cmd == 'X') + if (currentTransactionsInSystem.at(&trans).cmd == 'X') { if (phase == END_REFAB || phase == END_RFMAB @@ -161,8 +161,8 @@ void TlmRecorder::updateDataStrobe(const sc_time &begin, const sc_time &end, tlm_generic_payload &trans) { assert(currentTransactionsInSystem.count(&trans) != 0); - currentTransactionsInSystem[&trans].timeOnDataStrobe.start = begin; - currentTransactionsInSystem[&trans].timeOnDataStrobe.end = end; + currentTransactionsInSystem.at(&trans).timeOnDataStrobe.start = begin; + currentTransactionsInSystem.at(&trans).timeOnDataStrobe.end = end; } @@ -177,21 +177,23 @@ void TlmRecorder::recordDebugMessage(const std::string &message, const sc_time & void TlmRecorder::introduceTransactionSystem(tlm_generic_payload &trans) { totalNumTransactions++; - currentTransactionsInSystem[&trans].id = totalNumTransactions; + currentTransactionsInSystem.insert({&trans, Transaction(totalNumTransactions, + ArbiterExtension::getExtension(trans), ControllerExtension::getExtension(trans))}); + currentTransactionsInSystem.at(&trans).id = totalNumTransactions; tlm_command command = trans.get_command(); if (command == TLM_READ_COMMAND) - currentTransactionsInSystem[&trans].cmd = 'R'; + currentTransactionsInSystem.at(&trans).cmd = 'R'; else if (command == TLM_WRITE_COMMAND) - currentTransactionsInSystem[&trans].cmd = 'W'; + currentTransactionsInSystem.at(&trans).cmd = 'W'; else - currentTransactionsInSystem[&trans].cmd = 'X'; - currentTransactionsInSystem[&trans].address = trans.get_address(); - currentTransactionsInSystem[&trans].burstLength = DramExtension::getBurstLength(trans); - currentTransactionsInSystem[&trans].dramExtension = DramExtension::getExtension(trans); - currentTransactionsInSystem[&trans].timeOfGeneration = GenerationExtension::getTimeOfGeneration(trans); + currentTransactionsInSystem.at(&trans).cmd = 'X'; + currentTransactionsInSystem.at(&trans).address = trans.get_address(); + currentTransactionsInSystem.at(&trans).burstLength = ControllerExtension::getBurstLength(trans); + currentTransactionsInSystem.at(&trans).controllerExtension = ControllerExtension::getExtension(trans); + currentTransactionsInSystem.at(&trans).timeOfGeneration = ArbiterExtension::getTimeOfGeneration(trans); PRINTDEBUGMESSAGE(name, "New transaction #" + std::to_string(totalNumTransactions) + " generation time " + - currentTransactionsInSystem[&trans].timeOfGeneration.to_string()); + currentTransactionsInSystem.at(&trans).timeOfGeneration.to_string()); } void TlmRecorder::removeTransactionFromSystem(tlm_generic_payload &trans) @@ -199,9 +201,9 @@ void TlmRecorder::removeTransactionFromSystem(tlm_generic_payload &trans) assert(currentTransactionsInSystem.count(&trans) != 0); PRINTDEBUGMESSAGE(name, "Removing transaction #" + - std::to_string(currentTransactionsInSystem[&trans].id)); + std::to_string(currentTransactionsInSystem.at(&trans).id)); - Transaction &recordingData = currentTransactionsInSystem[&trans]; + Transaction &recordingData = currentTransactionsInSystem.at(&trans); currentDataBuffer->push_back(recordingData); currentTransactionsInSystem.erase(&trans); @@ -413,19 +415,19 @@ void TlmRecorder::insertTransactionInDB(Transaction &recordingData) sqlite3_bind_int64(insertTransactionStatement, 3, static_cast(recordingData.address)); sqlite3_bind_int(insertTransactionStatement, 4, static_cast(recordingData.burstLength)); sqlite3_bind_int(insertTransactionStatement, 5, - static_cast(recordingData.dramExtension.getThread().ID())); + static_cast(recordingData.arbiterExtension.getThread().ID())); sqlite3_bind_int(insertTransactionStatement, 6, - static_cast(recordingData.dramExtension.getChannel().ID())); + static_cast(recordingData.arbiterExtension.getChannel().ID())); sqlite3_bind_int(insertTransactionStatement, 7, - static_cast(recordingData.dramExtension.getRank().ID())); + static_cast(recordingData.controllerExtension.getRank().ID())); sqlite3_bind_int(insertTransactionStatement, 8, - static_cast(recordingData.dramExtension.getBankGroup().ID())); + static_cast(recordingData.controllerExtension.getBankGroup().ID())); sqlite3_bind_int(insertTransactionStatement, 9, - static_cast(recordingData.dramExtension.getBank().ID())); + static_cast(recordingData.controllerExtension.getBank().ID())); sqlite3_bind_int(insertTransactionStatement, 10, - static_cast(recordingData.dramExtension.getRow().ID())); + static_cast(recordingData.controllerExtension.getRow().ID())); sqlite3_bind_int(insertTransactionStatement, 11, - static_cast(recordingData.dramExtension.getColumn().ID())); + static_cast(recordingData.controllerExtension.getColumn().ID())); sqlite3_bind_int64(insertTransactionStatement, 12, static_cast(recordingData.timeOnDataStrobe.start.value())); sqlite3_bind_int64(insertTransactionStatement, 13, diff --git a/DRAMSys/library/src/common/TlmRecorder.h b/DRAMSys/library/src/common/TlmRecorder.h index 1b63b41d..f531efd5 100644 --- a/DRAMSys/library/src/common/TlmRecorder.h +++ b/DRAMSys/library/src/common/TlmRecorder.h @@ -43,6 +43,7 @@ #include #include +#include #include #include @@ -89,14 +90,17 @@ private: struct Transaction { - Transaction() = default; - explicit Transaction(uint64_t id) : id(id) {} + //Transaction() = default; + Transaction(uint64_t id, ArbiterExtension arbiterExtension, ControllerExtension controllerExtension) : + id(id), arbiterExtension(std::move(arbiterExtension)), + controllerExtension(std::move(controllerExtension)) {} uint64_t id = 0; uint64_t address = 0; unsigned int burstLength = 0; char cmd = 'X'; - DramExtension dramExtension; + ArbiterExtension arbiterExtension; + ControllerExtension controllerExtension; sc_core::sc_time timeOfGeneration; TimeInterval timeOnDataStrobe; diff --git a/DRAMSys/library/src/common/dramExtensions.cpp b/DRAMSys/library/src/common/dramExtensions.cpp index bc4e45b2..3c486087 100644 --- a/DRAMSys/library/src/common/dramExtensions.cpp +++ b/DRAMSys/library/src/common/dramExtensions.cpp @@ -46,7 +46,7 @@ ArbiterExtension::ArbiterExtension(Thread thread, Channel channel, uint64_t thre thread(thread), channel(channel), threadPayloadID(threadPayloadID), timeOfGeneration(timeOfGeneration) {} -void ArbiterExtension::setExtension(tlm::tlm_generic_payload& trans, Thread thread, Channel channel) +void ArbiterExtension::setAutoExtension(tlm::tlm_generic_payload& trans, Thread thread, Channel channel) { auto* extension = trans.get_extension(); @@ -64,6 +64,14 @@ void ArbiterExtension::setExtension(tlm::tlm_generic_payload& trans, Thread thre } } +void ArbiterExtension::setExtension(tlm::tlm_generic_payload& trans, Thread thread, Channel channel, + uint64_t threadPayloadID, const sc_core::sc_time& timeOfGeneration) +{ + assert(trans.get_extension() == nullptr); + auto* extension = new ArbiterExtension(thread, channel, threadPayloadID, timeOfGeneration); + trans.set_extension(extension); +} + void ArbiterExtension::setIDAndTimeOfGeneration(tlm::tlm_generic_payload& trans, uint64_t threadPayloadID, const sc_core::sc_time& timeOfGeneration) { @@ -88,6 +96,31 @@ void ArbiterExtension::copy_from(const tlm_extension_base& ext) timeOfGeneration = cpyFrom.timeOfGeneration; } +Thread ArbiterExtension::getThread() const +{ + return thread; +} + +Channel ArbiterExtension::getChannel() const +{ + return channel; +} + +uint64_t ArbiterExtension::getThreadPayloadID() const +{ + return threadPayloadID; +} + +sc_core::sc_time ArbiterExtension::getTimeOfGeneration() const +{ + return timeOfGeneration; +} + +const ArbiterExtension& ArbiterExtension::getExtension(const tlm::tlm_generic_payload& trans) +{ + return *trans.get_extension(); +} + Thread ArbiterExtension::getThread(const tlm::tlm_generic_payload& trans) { return trans.get_extension()->thread; @@ -114,7 +147,7 @@ ControllerExtension::ControllerExtension(uint64_t channelPayloadID, Rank rank, B burstLength(burstLength) {} -void ControllerExtension::setExtension(tlm::tlm_generic_payload& trans, uint64_t channelPayloadID, Rank rank, +void ControllerExtension::setAutoExtension(tlm::tlm_generic_payload& trans, uint64_t channelPayloadID, Rank rank, BankGroup bankGroup, Bank bank, Row row, Column column, unsigned int burstLength) { auto* extension = trans.get_extension(); @@ -136,6 +169,14 @@ void ControllerExtension::setExtension(tlm::tlm_generic_payload& trans, uint64_t } } +void ControllerExtension::setExtension(tlm::tlm_generic_payload& trans, uint64_t channelPayloadID, Rank rank, + BankGroup bankGroup, Bank bank, Row row, Column column, unsigned int burstLength) +{ + assert(trans.get_extension() == nullptr); + auto* extension = new ControllerExtension(channelPayloadID, rank, bankGroup, bank, row, column, burstLength); + trans.set_extension(extension); +} + tlm_extension_base* ControllerExtension::clone() const { return new ControllerExtension(channelPayloadID, rank, bankGroup, bank, row, column, burstLength); @@ -153,6 +194,46 @@ void ControllerExtension::copy_from(const tlm_extension_base& ext) burstLength = cpyFrom.burstLength; } +uint64_t ControllerExtension::getChannelPayloadID() const +{ + return channelPayloadID; +} + +Rank ControllerExtension::getRank() const +{ + return rank; +} + +BankGroup ControllerExtension::getBankGroup() const +{ + return bankGroup; +} + +Bank ControllerExtension::getBank() const +{ + return bank; +} + +Row ControllerExtension::getRow() const +{ + return row; +} + +Column ControllerExtension::getColumn() const +{ + return column; +} + +unsigned ControllerExtension::getBurstLength() const +{ + return burstLength; +} + +const ControllerExtension& ControllerExtension::getExtension(const tlm::tlm_generic_payload& trans) +{ + return *trans.get_extension(); +} + uint64_t ControllerExtension::getChannelPayloadID(const tlm::tlm_generic_payload& trans) { return trans.get_extension()->channelPayloadID; @@ -188,228 +269,6 @@ unsigned ControllerExtension::getBurstLength(const tlm::tlm_generic_payload& tra return trans.get_extension()->burstLength; } -DramExtension::DramExtension() : - thread(0), channel(0), rank(0), bankGroup(0), bank(0), - row(0), column(0), burstLength(0), - threadPayloadID(0), channelPayloadID(0) {} - -DramExtension::DramExtension(Thread thread, Channel channel, Rank rank, - BankGroup bankGroup, Bank bank, Row row, - Column column, unsigned int burstLength, - uint64_t threadPayloadID, uint64_t channelPayloadID) : - thread(thread), channel(channel), rank(rank), bankGroup(bankGroup), bank(bank), - row(row), column(column), burstLength(burstLength), - threadPayloadID(threadPayloadID), channelPayloadID(channelPayloadID) {} - -void DramExtension::setExtension(tlm_generic_payload& payload, - Thread thread, Channel channel, Rank rank, - BankGroup bankGroup, Bank bank, Row row, - Column column, unsigned int burstLength, - uint64_t threadPayloadID, uint64_t channelPayloadID) -{ - DramExtension* extension = nullptr; - payload.get_extension(extension); - - if (extension != nullptr) - { - extension->thread = thread; - extension->channel = channel; - extension->rank = rank; - extension->bankGroup = bankGroup; - extension->bank = bank; - extension->row = row; - extension->column = column; - extension->burstLength = burstLength; - extension->threadPayloadID = threadPayloadID; - extension->channelPayloadID = channelPayloadID; - } - else - { - extension = new DramExtension(thread, channel, rank, bankGroup, - bank, row, column, burstLength, - threadPayloadID, channelPayloadID); - payload.set_auto_extension(extension); - } -} - -void DramExtension::setPayloadIDs(tlm_generic_payload& payload, uint64_t threadPayloadID, uint64_t channelPayloadID) -{ - DramExtension* extension = nullptr; - payload.get_extension(extension); - assert(extension != nullptr); - extension->threadPayloadID = threadPayloadID; - extension->channelPayloadID = channelPayloadID; -} - -DramExtension& DramExtension::getExtension(const tlm_generic_payload& payload) -{ - DramExtension* result = nullptr; - payload.get_extension(result); - assert(result != nullptr); - - return *result; -} - -Thread DramExtension::getThread(const tlm_generic_payload& payload) -{ - return DramExtension::getExtension(payload).getThread(); -} - -Channel DramExtension::getChannel(const tlm_generic_payload& payload) -{ - return DramExtension::getExtension(payload).getChannel(); -} - -Rank DramExtension::getRank(const tlm_generic_payload& payload) -{ - return DramExtension::getExtension(payload).getRank(); -} - -BankGroup DramExtension::getBankGroup(const tlm_generic_payload& payload) -{ - return DramExtension::getExtension(payload).getBankGroup(); -} - -Bank DramExtension::getBank(const tlm_generic_payload& payload) -{ - return DramExtension::getExtension(payload).getBank(); -} - -Row DramExtension::getRow(const tlm_generic_payload& payload) -{ - return DramExtension::getExtension(payload).getRow(); -} - -Column DramExtension::getColumn(const tlm_generic_payload& payload) -{ - return DramExtension::getExtension(payload).getColumn(); -} - -unsigned DramExtension::getBurstLength(const tlm_generic_payload& payload) -{ - return DramExtension::getExtension(payload).getBurstLength(); -} - -uint64_t DramExtension::getThreadPayloadID(const tlm_generic_payload& payload) -{ - return DramExtension::getExtension(payload).getThreadPayloadID(); -} - -uint64_t DramExtension::getChannelPayloadID(const tlm_generic_payload& payload) -{ - return DramExtension::getExtension(payload).getChannelPayloadID(); -} - -tlm_extension_base *DramExtension::clone() const -{ - return new DramExtension(thread, channel, rank, bankGroup, bank, row, column, - burstLength, threadPayloadID, channelPayloadID); -} - -void DramExtension::copy_from(const tlm_extension_base &ext) -{ - const auto &cpyFrom = dynamic_cast(ext); - thread = cpyFrom.thread; - channel = cpyFrom.channel; - rank = cpyFrom.rank; - bankGroup = cpyFrom.bankGroup; - bank = cpyFrom.bank; - row = cpyFrom.row; - column = cpyFrom.column; - burstLength = cpyFrom.burstLength; -} - -Thread DramExtension::getThread() const -{ - return thread; -} - -Channel DramExtension::getChannel() const -{ - return channel; -} - -Rank DramExtension::getRank() const -{ - return rank; -} - -BankGroup DramExtension::getBankGroup() const -{ - return bankGroup; -} - -Bank DramExtension::getBank() const -{ - return bank; -} - -Row DramExtension::getRow() const -{ - return row; -} - -Column DramExtension::getColumn() const -{ - return column; -} - -unsigned int DramExtension::getBurstLength() const -{ - return burstLength; -} - -uint64_t DramExtension::getThreadPayloadID() const -{ - return threadPayloadID; -} - -uint64_t DramExtension::getChannelPayloadID() const -{ - return channelPayloadID; -} - -tlm_extension_base *GenerationExtension::clone() const -{ - return new GenerationExtension(timeOfGeneration); -} - -void GenerationExtension::copy_from(const tlm_extension_base &ext) -{ - const auto &cpyFrom = dynamic_cast(ext); - timeOfGeneration = cpyFrom.timeOfGeneration; - -} - -void GenerationExtension::setExtension(tlm_generic_payload& payload, const sc_time& _timeOfGeneration) -{ - GenerationExtension* extension = nullptr; - payload.get_extension(extension); - - if (extension != nullptr) - { - extension->timeOfGeneration = _timeOfGeneration; - } - else - { - extension = new GenerationExtension(_timeOfGeneration); - payload.set_auto_extension(extension); - } -} - -GenerationExtension& GenerationExtension::getExtension(const tlm_generic_payload& payload) -{ - GenerationExtension* result = nullptr; - payload.get_extension(result); - assert(result != nullptr); - return *result; -} - -sc_time GenerationExtension::getTimeOfGeneration(const tlm_generic_payload& payload) -{ - return GenerationExtension::getExtension(payload).timeOfGeneration; -} - //THREAD bool operator ==(const Thread &lhs, const Thread &rhs) { diff --git a/DRAMSys/library/src/common/dramExtensions.h b/DRAMSys/library/src/common/dramExtensions.h index 27726bb7..7f164186 100644 --- a/DRAMSys/library/src/common/dramExtensions.h +++ b/DRAMSys/library/src/common/dramExtensions.h @@ -157,13 +157,21 @@ private: class ArbiterExtension : public tlm::tlm_extension { public: - static void setExtension(tlm::tlm_generic_payload& trans, Thread thread, Channel channel); + static void setAutoExtension(tlm::tlm_generic_payload& trans, Thread thread, Channel channel); + static void setExtension(tlm::tlm_generic_payload& trans, Thread thread, Channel channel, + uint64_t threadPayloadID, const sc_core::sc_time& timeOfGeneration); static void setIDAndTimeOfGeneration(tlm::tlm_generic_payload& trans, uint64_t threadPayloadID, const sc_core::sc_time& timeOfGeneration); tlm::tlm_extension_base* clone() const override; void copy_from(const tlm::tlm_extension_base& ext) override; + Thread getThread() const; + Channel getChannel() const; + uint64_t getThreadPayloadID() const; + sc_core::sc_time getTimeOfGeneration() const; + + static const ArbiterExtension& getExtension(const tlm::tlm_generic_payload& trans); static Thread getThread(const tlm::tlm_generic_payload& trans); static Channel getChannel(const tlm::tlm_generic_payload& trans); static uint64_t getThreadPayloadID(const tlm::tlm_generic_payload& trans); @@ -180,14 +188,26 @@ private: class ControllerExtension : public tlm::tlm_extension { public: - static void setExtension(tlm::tlm_generic_payload& trans, uint64_t channelPayloadID, Rank rank, BankGroup bankGroup, + static void setAutoExtension(tlm::tlm_generic_payload& trans, uint64_t channelPayloadID, Rank rank, BankGroup bankGroup, Bank bank, Row row, Column column, unsigned burstLength); + static void setExtension(tlm::tlm_generic_payload& trans, uint64_t channelPayloadID, Rank rank, BankGroup bankGroup, + Bank bank, Row row, Column column, unsigned burstLength); + //static ControllerExtension& getExtension(const tlm::tlm_generic_payload& trans); tlm::tlm_extension_base* clone() const override; void copy_from(const tlm::tlm_extension_base& ext) override; + uint64_t getChannelPayloadID() const; + Rank getRank() const; + BankGroup getBankGroup() const; + Bank getBank() const; + Row getRow() const; + Column getColumn() const; + unsigned getBurstLength() const; + + static const ControllerExtension& getExtension(const tlm::tlm_generic_payload& trans); static uint64_t getChannelPayloadID(const tlm::tlm_generic_payload& trans); static Rank getRank(const tlm::tlm_generic_payload& trans); static BankGroup getBankGroup(const tlm::tlm_generic_payload& trans); @@ -209,85 +229,6 @@ private: }; -class DramExtension : public tlm::tlm_extension -{ -public: - DramExtension(); - DramExtension(Thread thread, Channel channel, Rank rank, - BankGroup bankGroup, Bank bank, Row row, - Column column, unsigned int burstLength, - uint64_t threadPayloadID, uint64_t channelPayloadID); - tlm::tlm_extension_base *clone() const override; - void copy_from(const tlm::tlm_extension_base &ext) override; - - static void setExtension(tlm::tlm_generic_payload &payload, - Thread thread, Channel channel, Rank rank, - BankGroup bankGroup, Bank bank, Row row, - Column column, unsigned int burstLength, - uint64_t threadPayloadID, uint64_t channelPayloadID); - - static DramExtension &getExtension(const tlm::tlm_generic_payload &payload); - - static void setPayloadIDs(tlm::tlm_generic_payload &payload, - uint64_t threadPayloadID, uint64_t channelPayloadID); - - // Used for convenience, caller could also use getExtension(..) to access these field - static Thread getThread(const tlm::tlm_generic_payload &payload); - static Channel getChannel(const tlm::tlm_generic_payload &payload); - static Rank getRank(const tlm::tlm_generic_payload &payload); - static BankGroup getBankGroup(const tlm::tlm_generic_payload &payload); - static Bank getBank(const tlm::tlm_generic_payload &payload); - static Row getRow(const tlm::tlm_generic_payload &payload); - static Column getColumn(const tlm::tlm_generic_payload &payload); - static unsigned getBurstLength(const tlm::tlm_generic_payload &payload); - static uint64_t getThreadPayloadID(const tlm::tlm_generic_payload &payload); - static uint64_t getChannelPayloadID(const tlm::tlm_generic_payload &payload); - - Thread getThread() const; - Channel getChannel() const; - Rank getRank() const; - BankGroup getBankGroup() const; - Bank getBank() const; - Row getRow() const; - Column getColumn() const; - - unsigned int getBurstLength() const; - uint64_t getThreadPayloadID() const; - uint64_t getChannelPayloadID() const; - -private: - Thread thread; - Channel channel; - Rank rank; - BankGroup bankGroup; - Bank bank; - Row row; - Column column; - unsigned int burstLength; - uint64_t threadPayloadID; - uint64_t channelPayloadID; -}; - - -// Used to indicate the time when a payload is created (in a traceplayer or in a core) -// Note that this time can be different from the time the payload enters the DRAM system -//(at that time the phase BEGIN_REQ is recorded), so timeOfGeneration =< time(BEGIN_REQ) -class GenerationExtension : public tlm::tlm_extension -{ -public: - explicit GenerationExtension(const sc_core::sc_time &timeOfGeneration) - : timeOfGeneration(timeOfGeneration) {} - tlm::tlm_extension_base *clone() const override; - void copy_from(const tlm::tlm_extension_base &ext) override; - static void setExtension(tlm::tlm_generic_payload &payload, const sc_core::sc_time &_timeOfGeneration); - static GenerationExtension &getExtension(const tlm::tlm_generic_payload &payload); - static sc_core::sc_time getTimeOfGeneration(const tlm::tlm_generic_payload &payload); - -private: - sc_core::sc_time timeOfGeneration; -}; - - bool operator==(const Thread &lhs, const Thread &rhs); bool operator!=(const Thread &lhs, const Thread &rhs); bool operator<(const Thread &lhs, const Thread &rhs); diff --git a/DRAMSys/library/src/common/utils.cpp b/DRAMSys/library/src/common/utils.cpp index 81f7a565..9784289d 100644 --- a/DRAMSys/library/src/common/utils.cpp +++ b/DRAMSys/library/src/common/utils.cpp @@ -80,7 +80,6 @@ void setUpDummy(tlm_generic_payload &payload, uint64_t channelPayloadID, Rank ra payload.set_dmi_allowed(false); payload.set_byte_enable_length(0); payload.set_streaming_width(0); - payload.set_extension(new DramExtension(Thread(UINT_MAX), Channel(0), rank, - bankGroup, bank, Row(0), Column(0), 0, 0, channelPayloadID)); - payload.set_extension(new GenerationExtension(SC_ZERO_TIME)); + ControllerExtension::setExtension(payload, channelPayloadID, rank, bankGroup, bank, Row(0), Column(0), 0); + ArbiterExtension::setExtension(payload, Thread(UINT_MAX), Channel(0), 0, SC_ZERO_TIME); } diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp index 1b9f86f6..ffa85023 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp @@ -65,6 +65,7 @@ MemSpec::MemSpec(const DRAMSysConfiguration::MemSpec &memSpec, dataRate(memSpec.memArchitectureSpec.entries.at("dataRate")), bitWidth(memSpec.memArchitectureSpec.entries.at("width")), dataBusWidth(bitWidth * devicesPerRank), + bytesPerBeat(dataBusWidth / 8), defaultBytesPerBurst((defaultBurstLength * dataBusWidth) / 8), maxBytesPerBurst((maxBurstLength * dataBusWidth) / 8), fCKMHz(memSpec.memTimingSpec.entries.at("clkMhz")), diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.h b/DRAMSys/library/src/configuration/memspec/MemSpec.h index ac6fca08..bdf23cac 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.h @@ -66,6 +66,7 @@ public: const unsigned dataRate; const unsigned bitWidth; const unsigned dataBusWidth; + const unsigned bytesPerBeat; const unsigned defaultBytesPerBurst; const unsigned maxBytesPerBurst; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp index 259d8c7d..c8ff40ba 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp @@ -216,7 +216,7 @@ sc_time MemSpecDDR5::getExecutionTime(Command command, const tlm_generic_payload return tRCD + longCmdOffset; else if (command == Command::RD) { - if (DramExtension::getBurstLength(payload) == 32) + if (ControllerExtension::getBurstLength(payload) == 32) return tRL + tBURST32 + longCmdOffset; else return tRL + tBURST16 + longCmdOffset; @@ -225,14 +225,14 @@ sc_time MemSpecDDR5::getExecutionTime(Command command, const tlm_generic_payload return tRTP + tRP + longCmdOffset; else if (command == Command::WR) { - if (DramExtension::getBurstLength(payload) == 32) + if (ControllerExtension::getBurstLength(payload) == 32) return tWL + tBURST32 + longCmdOffset; else return tWL + tBURST16 + longCmdOffset; } else if (command == Command::WRA) { - if (DramExtension::getBurstLength(payload) == 32) + if (ControllerExtension::getBurstLength(payload) == 32) return tWL + tBURST32 + tWR + tRP + longCmdOffset; else return tWL + tBURST16 + tWR + tRP + longCmdOffset; @@ -253,14 +253,14 @@ TimeInterval MemSpecDDR5::getIntervalOnDataStrobe(Command command, const tlm_gen { if (command == Command::RD || command == Command::RDA) { - if (DramExtension::getBurstLength(payload) == 32) + if (ControllerExtension::getBurstLength(payload) == 32) return {tRL + longCmdOffset, tRL + tBURST32 + longCmdOffset}; else return {tRL + longCmdOffset, tRL + tBURST16 + longCmdOffset}; } else if (command == Command::WR || command == Command::WRA) { - if (DramExtension::getBurstLength(payload) == 32) + if (ControllerExtension::getBurstLength(payload) == 32) return {tWL + longCmdOffset, tWL + tBURST32 + longCmdOffset}; else return {tWL + longCmdOffset, tWL + tBURST16 + longCmdOffset}; diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index 10b29206..6316280a 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -57,7 +57,7 @@ void BankMachine::updateState(Command command) { case Command::ACT: state = State::Activated; - openRow = DramExtension::getRow(*currentPayload); + openRow = ControllerExtension::getRow(*currentPayload); keepTrans = true; refreshManagementCounter++; break; @@ -180,7 +180,7 @@ sc_time BankMachineOpen::start() assert(!keepTrans || currentPayload != nullptr); if (keepTrans) { - if (DramExtension::getRow(*newPayload) == openRow) + if (ControllerExtension::getRow(*newPayload) == openRow) currentPayload = newPayload; } else @@ -192,7 +192,7 @@ sc_time BankMachineOpen::start() nextCommand = Command::ACT; else if (state == State::Activated) { - if (DramExtension::getRow(*currentPayload) == openRow) // row hit + if (ControllerExtension::getRow(*currentPayload) == openRow) // row hit { assert(currentPayload->is_read() || currentPayload->is_write()); if (currentPayload->is_read()) @@ -232,7 +232,7 @@ sc_time BankMachineClosed::start() assert(!keepTrans || currentPayload != nullptr); if (keepTrans) { - if (DramExtension::getRow(*newPayload) == openRow) + if (ControllerExtension::getRow(*newPayload) == openRow) currentPayload = newPayload; } else @@ -279,7 +279,7 @@ sc_time BankMachineOpenAdaptive::start() assert(!keepTrans || currentPayload != nullptr); if (keepTrans) { - if (DramExtension::getRow(*newPayload) == openRow) + if (ControllerExtension::getRow(*newPayload) == openRow) currentPayload = newPayload; } else @@ -291,7 +291,7 @@ sc_time BankMachineOpenAdaptive::start() nextCommand = Command::ACT; else if (state == State::Activated) { - if (DramExtension::getRow(*currentPayload) == openRow) // row hit + if (ControllerExtension::getRow(*currentPayload) == openRow) // row hit { if (scheduler.hasFurtherRequest(bank, currentPayload->get_command()) && !scheduler.hasFurtherRowHit(bank, openRow, currentPayload->get_command())) @@ -343,7 +343,7 @@ sc_time BankMachineClosedAdaptive::start() assert(!keepTrans || currentPayload != nullptr); if (keepTrans) { - if (DramExtension::getRow(*newPayload) == openRow) + if (ControllerExtension::getRow(*newPayload) == openRow) currentPayload = newPayload; } else @@ -355,7 +355,7 @@ sc_time BankMachineClosedAdaptive::start() nextCommand = Command::ACT; else if (state == State::Activated) { - if (DramExtension::getRow(*currentPayload) == openRow) // row hit + if (ControllerExtension::getRow(*currentPayload) == openRow) // row hit { if (scheduler.hasFurtherRowHit(bank, openRow, currentPayload->get_command())) { diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index 08d9116e..4a410ebd 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -284,8 +284,8 @@ void Controller::controllerMethod() tlm_generic_payload *payload = std::get(commandTuple); if (command != Command::NOP) // can happen with FIFO strict { - Rank rank = DramExtension::getRank(*payload); - Bank bank = DramExtension::getBank(*payload); + Rank rank = ControllerExtension::getRank(*payload); + Bank bank = ControllerExtension::getBank(*payload); if (command.isRankCommand()) { @@ -369,6 +369,13 @@ tlm_sync_enum Controller::nb_transport_fw(tlm_generic_payload &trans, transToAcquire.payload = &trans; transToAcquire.time = sc_time_stamp() + delay; beginReqEvent.notify(delay); + + DecodedAddress decodedAddress = addressDecoder.decodeAddress(transToAcquire.payload->get_address()); + ControllerExtension::setAutoExtension(*transToAcquire.payload, nextChannelPayloadIDToAppend++, + Rank(decodedAddress.rank), BankGroup(decodedAddress.bankgroup), + Bank(decodedAddress.bank), Row(decodedAddress.row), + Column(decodedAddress.column), + transToAcquire.payload->get_data_length() / memSpec.bytesPerBeat); } else if (phase == END_RESP) { @@ -400,16 +407,24 @@ void Controller::manageRequests(const sc_time &delay) { if (transToAcquire.payload != nullptr && transToAcquire.time <= sc_time_stamp()) { + // Check size of transaction +// unsigned numSubTrans = transToAcquire.payload->get_data_length() / memSpec.maxBytesPerBurst; +// if (numSubTrans > 1) +// { +// // Split create child transactions +// // Address decoding!!! +// } + if (scheduler->hasBufferSpace()) { - NDEBUG_UNUSED(uint64_t id) = DramExtension::getChannelPayloadID(*transToAcquire.payload); + NDEBUG_UNUSED(uint64_t id) = ControllerExtension::getChannelPayloadID(*transToAcquire.payload); PRINTDEBUGMESSAGE(name(), "Payload " + std::to_string(id) + " entered system."); if (totalNumberOfPayloads == 0) idleTimeCollector.end(); totalNumberOfPayloads++; - Rank rank = DramExtension::getRank(*transToAcquire.payload); + Rank rank = ControllerExtension::getRank(*transToAcquire.payload); if (ranksNumberOfPayloads[rank.ID()] == 0) powerDownManagers[rank.ID()]->triggerExit(); @@ -418,7 +433,7 @@ void Controller::manageRequests(const sc_time &delay) scheduler->storeRequest(*transToAcquire.payload); transToAcquire.payload->acquire(); - Bank bank = DramExtension::getBank(*transToAcquire.payload); + Bank bank = ControllerExtension::getBank(*transToAcquire.payload); bankMachines[bank.ID()]->start(); transToAcquire.payload->set_response_status(TLM_OK_RESPONSE); @@ -441,10 +456,10 @@ void Controller::manageResponses() assert(transToRelease.time >= sc_time_stamp()); if (transToRelease.time == sc_time_stamp()) { - NDEBUG_UNUSED(uint64_t id) = DramExtension::getChannelPayloadID(*transToRelease.payload); + NDEBUG_UNUSED(uint64_t id) = ControllerExtension::getChannelPayloadID(*transToRelease.payload); PRINTDEBUGMESSAGE(name(), "Payload " + std::to_string(id) + " left system."); - numberOfBeatsServed += DramExtension::getBurstLength(*transToRelease.payload); + numberOfBeatsServed += ControllerExtension::getBurstLength(*transToRelease.payload); transToRelease.payload->release(); transToRelease.payload = nullptr; totalNumberOfPayloads--; diff --git a/DRAMSys/library/src/controller/Controller.h b/DRAMSys/library/src/controller/Controller.h index 4852f549..16e3d521 100644 --- a/DRAMSys/library/src/controller/Controller.h +++ b/DRAMSys/library/src/controller/Controller.h @@ -89,6 +89,7 @@ private: std::vector> powerDownManagers; const AddressDecoder& addressDecoder; + uint64_t nextChannelPayloadIDToAppend = 1; struct Transaction { diff --git a/DRAMSys/library/src/controller/ControllerRecordable.cpp b/DRAMSys/library/src/controller/ControllerRecordable.cpp index f7aa782a..6c188b71 100644 --- a/DRAMSys/library/src/controller/ControllerRecordable.cpp +++ b/DRAMSys/library/src/controller/ControllerRecordable.cpp @@ -58,8 +58,10 @@ ControllerRecordable::ControllerRecordable(const sc_module_name &name, const Con tlm_sync_enum ControllerRecordable::nb_transport_fw(tlm_generic_payload &trans, tlm_phase &phase, sc_time &delay) { + // Important: delay must not be increased by nb_transport_fw + tlm_sync_enum returnValue = Controller::nb_transport_fw(trans, phase, delay); recordPhase(trans, phase, delay); - return Controller::nb_transport_fw(trans, phase, delay); + return returnValue; } tlm_sync_enum ControllerRecordable::nb_transport_bw(tlm_generic_payload &, @@ -92,13 +94,13 @@ void ControllerRecordable::recordPhase(tlm_generic_payload &trans, const tlm_pha { sc_time recTime = delay + sc_time_stamp(); - NDEBUG_UNUSED(unsigned thr) = DramExtension::getExtension(trans).getThread().ID(); - NDEBUG_UNUSED(unsigned ch) = DramExtension::getExtension(trans).getChannel().ID(); - NDEBUG_UNUSED(unsigned bg) = DramExtension::getExtension(trans).getBankGroup().ID(); - NDEBUG_UNUSED(unsigned bank) = DramExtension::getExtension(trans).getBank().ID(); - NDEBUG_UNUSED(unsigned row) = DramExtension::getExtension(trans).getRow().ID(); - NDEBUG_UNUSED(unsigned col) = DramExtension::getExtension(trans).getColumn().ID(); - NDEBUG_UNUSED(uint64_t id) = DramExtension::getExtension(trans).getChannelPayloadID(); + NDEBUG_UNUSED(unsigned thr) = ArbiterExtension::getExtension(trans).getThread().ID(); + NDEBUG_UNUSED(unsigned ch) = ArbiterExtension::getExtension(trans).getChannel().ID(); + NDEBUG_UNUSED(unsigned bg) = ControllerExtension::getExtension(trans).getBankGroup().ID(); + NDEBUG_UNUSED(unsigned bank) = ControllerExtension::getExtension(trans).getBank().ID(); + NDEBUG_UNUSED(unsigned row) = ControllerExtension::getExtension(trans).getRow().ID(); + NDEBUG_UNUSED(unsigned col) = ControllerExtension::getExtension(trans).getColumn().ID(); + NDEBUG_UNUSED(uint64_t id) = ControllerExtension::getExtension(trans).getChannelPayloadID(); PRINTDEBUGMESSAGE(name(), "Recording " + getPhaseName(phase) + " thread " + std::to_string(thr) + " channel " + std::to_string(ch) + " bank group " + std::to_string( diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp index c440f244..4743ceb4 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp @@ -66,15 +66,15 @@ CheckerDDR3::CheckerDDR3(const Configuration& config) sc_time CheckerDDR3::timeToSatisfyConstraints(Command command, const tlm_generic_payload& payload) const { - Rank rank = DramExtension::getRank(payload); - Bank bank = DramExtension::getBank(payload); + Rank rank = ControllerExtension::getRank(payload); + Bank bank = ControllerExtension::getBank(payload); sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); if (command == Command::RD || command == Command::RDA) { - assert(DramExtension::getBurstLength(payload) == 8); + assert(ControllerExtension::getBurstLength(payload) == 8); lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != sc_max_time()) @@ -129,7 +129,7 @@ sc_time CheckerDDR3::timeToSatisfyConstraints(Command command, const tlm_generic } else if (command == Command::WR || command == Command::WRA) { - assert(DramExtension::getBurstLength(payload) == 8); + assert(ControllerExtension::getBurstLength(payload) == 8); lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != sc_max_time()) @@ -425,8 +425,8 @@ sc_time CheckerDDR3::timeToSatisfyConstraints(Command command, const tlm_generic void CheckerDDR3::insert(Command command, const tlm_generic_payload& payload) { - Rank rank = DramExtension::getRank(payload); - Bank bank = DramExtension::getBank(payload); + Rank rank = ControllerExtension::getRank(payload); + Bank bank = ControllerExtension::getBank(payload); PRINTDEBUGMESSAGE("CheckerDDR3", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + command.toString()); diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp index 421cac01..a15b8dfa 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp @@ -69,16 +69,16 @@ CheckerDDR4::CheckerDDR4(const Configuration& config) sc_time CheckerDDR4::timeToSatisfyConstraints(Command command, const tlm_generic_payload& payload) const { - Rank rank = DramExtension::getRank(payload); - BankGroup bankGroup = DramExtension::getBankGroup(payload); - Bank bank = DramExtension::getBank(payload); + Rank rank = ControllerExtension::getRank(payload); + BankGroup bankGroup = ControllerExtension::getBankGroup(payload); + Bank bank = ControllerExtension::getBank(payload); sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); if (command == Command::RD || command == Command::RDA) { - assert(DramExtension::getBurstLength(payload) == 8); + assert(ControllerExtension::getBurstLength(payload) == 8); lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != sc_max_time()) @@ -149,7 +149,7 @@ sc_time CheckerDDR4::timeToSatisfyConstraints(Command command, const tlm_generic } else if (command == Command::WR || command == Command::WRA) { - assert(DramExtension::getBurstLength(payload) == 8); + assert(ControllerExtension::getBurstLength(payload) == 8); lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != sc_max_time()) @@ -457,9 +457,9 @@ sc_time CheckerDDR4::timeToSatisfyConstraints(Command command, const tlm_generic void CheckerDDR4::insert(Command command, const tlm_generic_payload& payload) { - Rank rank = DramExtension::getRank(payload); - BankGroup bankGroup = DramExtension::getBankGroup(payload); - Bank bank = DramExtension::getBank(payload); + Rank rank = ControllerExtension::getRank(payload); + BankGroup bankGroup = ControllerExtension::getBankGroup(payload); + Bank bank = ControllerExtension::getBank(payload); PRINTDEBUGMESSAGE("CheckerDDR4", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + command.toString()); diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR5.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR5.cpp index 795c8857..5a6d92ef 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR5.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR5.cpp @@ -117,11 +117,11 @@ CheckerDDR5::CheckerDDR5(const Configuration& config) sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, const tlm_generic_payload& payload) const { - Rank logicalRank = DramExtension::getRank(payload); + Rank logicalRank = ControllerExtension::getRank(payload); Rank physicalRank = Rank(logicalRank.ID() / memSpec->logicalRanksPerPhysicalRank); Rank dimmRank = Rank(physicalRank.ID() / memSpec->physicalRanksPerDimmRank); - BankGroup bankGroup = DramExtension::getBankGroup(payload); - Bank bank = DramExtension::getBank(payload); + BankGroup bankGroup = ControllerExtension::getBankGroup(payload); + Bank bank = ControllerExtension::getBank(payload); Bank bankInGroup = Bank(logicalRank.ID() * memSpec->banksPerGroup + bank.ID() % memSpec->banksPerGroup); sc_time lastCommandStart; @@ -129,7 +129,7 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, const tlm_generic if (command == Command::RD || command == Command::RDA) { - unsigned burstLength = DramExtension::getBurstLength(payload); + unsigned burstLength = ControllerExtension::getBurstLength(payload); assert((burstLength == 16) || (burstLength == 32)); assert(!(burstLength == 32) || (memSpec->bitWidth == 4)); assert(burstLength <= memSpec->maxBurstLength); @@ -316,7 +316,7 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, const tlm_generic } else if (command == Command::WR || command == Command::WRA) { - unsigned burstLength = DramExtension::getBurstLength(payload); + unsigned burstLength = ControllerExtension::getBurstLength(payload); assert((burstLength == 16) || (burstLength == 32)); assert(!(burstLength == 32) || (memSpec->bitWidth == 4)); assert(burstLength <= memSpec->maxBurstLength); @@ -879,13 +879,13 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, const tlm_generic void CheckerDDR5::insert(Command command, const tlm_generic_payload& payload) { - Rank logicalRank = DramExtension::getRank(payload); + Rank logicalRank = ControllerExtension::getRank(payload); Rank physicalRank = Rank(logicalRank.ID() / memSpec->logicalRanksPerPhysicalRank); Rank dimmRank = Rank(physicalRank.ID() / memSpec->physicalRanksPerDimmRank); - BankGroup bankGroup = DramExtension::getBankGroup(payload); - Bank bank = DramExtension::getBank(payload); + BankGroup bankGroup = ControllerExtension::getBankGroup(payload); + Bank bank = ControllerExtension::getBank(payload); Bank bankInGroup = Bank(logicalRank.ID() * memSpec->banksPerGroup + bank.ID() % memSpec->banksPerGroup); - unsigned burstLength = DramExtension::getBurstLength(payload); + unsigned burstLength = ControllerExtension::getBurstLength(payload); PRINTDEBUGMESSAGE("CheckerDDR5", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + command.toString()); diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp b/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp index 9c9635b4..8ed0bf46 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp @@ -70,16 +70,16 @@ CheckerGDDR5::CheckerGDDR5(const Configuration& config) sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, const tlm_generic_payload& payload) const { - Rank rank = DramExtension::getRank(payload); - BankGroup bankGroup = DramExtension::getBankGroup(payload); - Bank bank = DramExtension::getBank(payload); + Rank rank = ControllerExtension::getRank(payload); + BankGroup bankGroup = ControllerExtension::getBankGroup(payload); + Bank bank = ControllerExtension::getBank(payload); sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); if (command == Command::RD || command == Command::RDA) { - assert(DramExtension::getBurstLength(payload) == 8); + assert(ControllerExtension::getBurstLength(payload) == 8); lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != sc_max_time()) @@ -150,7 +150,7 @@ sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, const tlm_generi } else if (command == Command::WR || command == Command::WRA) { - assert(DramExtension::getBurstLength(payload) == 8); + assert(ControllerExtension::getBurstLength(payload) == 8); lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != sc_max_time()) @@ -539,9 +539,9 @@ sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, const tlm_generi void CheckerGDDR5::insert(Command command, const tlm_generic_payload& payload) { - Rank rank = DramExtension::getRank(payload); - BankGroup bankGroup = DramExtension::getBankGroup(payload); - Bank bank = DramExtension::getBank(payload); + Rank rank = ControllerExtension::getRank(payload); + BankGroup bankGroup = ControllerExtension::getBankGroup(payload); + Bank bank = ControllerExtension::getBank(payload); PRINTDEBUGMESSAGE("CheckerGDDR5", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + command.toString()); diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp b/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp index 2c203b13..beb43e2f 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp @@ -70,16 +70,16 @@ CheckerGDDR5X::CheckerGDDR5X(const Configuration& config) sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, const tlm_generic_payload& payload) const { - Rank rank = DramExtension::getRank(payload); - BankGroup bankGroup = DramExtension::getBankGroup(payload); - Bank bank = DramExtension::getBank(payload); + Rank rank = ControllerExtension::getRank(payload); + BankGroup bankGroup = ControllerExtension::getBankGroup(payload); + Bank bank = ControllerExtension::getBank(payload); sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); if (command == Command::RD || command == Command::RDA) { - unsigned burstLength = DramExtension::getBurstLength(payload); + unsigned burstLength = ControllerExtension::getBurstLength(payload); assert(!(memSpec->dataRate == 4) || (burstLength == 8)); // DDR mode (QDR wrt CK) assert(!(memSpec->dataRate == 8) || (burstLength == 16)); // QDR mode (ODR wrt CK) @@ -152,7 +152,7 @@ sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, const tlm_gener } else if (command == Command::WR || command == Command::WRA) { - unsigned burstLength = DramExtension::getBurstLength(payload); + unsigned burstLength = ControllerExtension::getBurstLength(payload); assert(!(memSpec->dataRate == 4) || (burstLength == 8)); // DDR mode (QDR wrt CK) assert(!(memSpec->dataRate == 8) || (burstLength == 16)); // QDR mode (ODR wrt CK) @@ -543,9 +543,9 @@ sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, const tlm_gener void CheckerGDDR5X::insert(Command command, const tlm_generic_payload& payload) { - Rank rank = DramExtension::getRank(payload); - BankGroup bankGroup = DramExtension::getBankGroup(payload); - Bank bank = DramExtension::getBank(payload); + Rank rank = ControllerExtension::getRank(payload); + BankGroup bankGroup = ControllerExtension::getBankGroup(payload); + Bank bank = ControllerExtension::getBank(payload); PRINTDEBUGMESSAGE("CheckerGDDR5X", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + command.toString()); diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp b/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp index 2aaaa651..681f251d 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp @@ -69,16 +69,16 @@ CheckerGDDR6::CheckerGDDR6(const Configuration& config) sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, const tlm_generic_payload& payload) const { - Rank rank = DramExtension::getRank(payload); - BankGroup bankGroup = DramExtension::getBankGroup(payload); - Bank bank = DramExtension::getBank(payload); + Rank rank = ControllerExtension::getRank(payload); + BankGroup bankGroup = ControllerExtension::getBankGroup(payload); + Bank bank = ControllerExtension::getBank(payload); sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); if (command == Command::RD || command == Command::RDA) { - assert(DramExtension::getBurstLength(payload) == 16); + assert(ControllerExtension::getBurstLength(payload) == 16); lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != sc_max_time()) @@ -149,7 +149,7 @@ sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, const tlm_generi } else if (command == Command::WR || command == Command::WRA) { - assert(DramExtension::getBurstLength(payload) == 16); + assert(ControllerExtension::getBurstLength(payload) == 16); lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != sc_max_time()) @@ -560,9 +560,9 @@ sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, const tlm_generi void CheckerGDDR6::insert(Command command, const tlm_generic_payload& payload) { - Rank rank = DramExtension::getRank(payload); - BankGroup bankGroup = DramExtension::getBankGroup(payload); - Bank bank = DramExtension::getBank(payload); + Rank rank = ControllerExtension::getRank(payload); + BankGroup bankGroup = ControllerExtension::getBankGroup(payload); + Bank bank = ControllerExtension::getBank(payload); PRINTDEBUGMESSAGE("CheckerGDDR6", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + command.toString()); diff --git a/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp b/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp index 26b096a8..671dcb07 100644 --- a/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp @@ -70,16 +70,16 @@ CheckerHBM2::CheckerHBM2(const Configuration& config) sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, const tlm_generic_payload& payload) const { - Rank rank = DramExtension::getRank(payload); - BankGroup bankGroup = DramExtension::getBankGroup(payload); - Bank bank = DramExtension::getBank(payload); + Rank rank = ControllerExtension::getRank(payload); + BankGroup bankGroup = ControllerExtension::getBankGroup(payload); + Bank bank = ControllerExtension::getBank(payload); sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); if (command == Command::RD || command == Command::RDA) { - unsigned burstLength = DramExtension::getBurstLength(payload); + unsigned burstLength = ControllerExtension::getBurstLength(payload); assert(!(memSpec->ranksPerChannel == 1) || (burstLength == 2 || burstLength == 4)); // Legacy mode assert(!(memSpec->ranksPerChannel == 2) || (burstLength == 4)); // Pseudo-channel mode @@ -134,7 +134,7 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, const tlm_generic } else if (command == Command::WR || command == Command::WRA) { - unsigned burstLength = DramExtension::getBurstLength(payload); + unsigned burstLength = ControllerExtension::getBurstLength(payload); assert(!(memSpec->ranksPerChannel == 1) || (burstLength == 2)); // Legacy mode assert(!(memSpec->ranksPerChannel == 2) || (burstLength == 4)); // Pseudo-channel mode @@ -518,9 +518,9 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, const tlm_generic void CheckerHBM2::insert(Command command, const tlm_generic_payload& payload) { - Rank rank = DramExtension::getRank(payload); - BankGroup bankGroup = DramExtension::getBankGroup(payload); - Bank bank = DramExtension::getBank(payload); + Rank rank = ControllerExtension::getRank(payload); + BankGroup bankGroup = ControllerExtension::getBankGroup(payload); + Bank bank = ControllerExtension::getBank(payload); PRINTDEBUGMESSAGE("CheckerHBM2", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + command.toString()); diff --git a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp index cecfa592..eaa26001 100644 --- a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp @@ -72,15 +72,15 @@ CheckerLPDDR4::CheckerLPDDR4(const Configuration& config) sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, const tlm_generic_payload& payload) const { - Rank rank = DramExtension::getRank(payload); - Bank bank = DramExtension::getBank(payload); + Rank rank = ControllerExtension::getRank(payload); + Bank bank = ControllerExtension::getBank(payload); sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); if (command == Command::RD || command == Command::RDA) { - unsigned burstLength = DramExtension::getBurstLength(payload); + unsigned burstLength = ControllerExtension::getBurstLength(payload); assert((burstLength == 16) || (burstLength == 32)); // TODO: BL16/32 OTF assert(burstLength <= memSpec->maxBurstLength); @@ -133,7 +133,7 @@ sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, const tlm_gener } else if (command == Command::WR || command == Command::WRA) { - unsigned burstLength = DramExtension::getBurstLength(payload); + unsigned burstLength = ControllerExtension::getBurstLength(payload); assert((burstLength == 16) || (burstLength == 32)); assert(burstLength <= memSpec->maxBurstLength); @@ -513,8 +513,8 @@ sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, const tlm_gener void CheckerLPDDR4::insert(Command command, const tlm_generic_payload& payload) { - Rank rank = DramExtension::getRank(payload); - Bank bank = DramExtension::getBank(payload); + Rank rank = ControllerExtension::getRank(payload); + Bank bank = ControllerExtension::getBank(payload); PRINTDEBUGMESSAGE("CheckerLPDDR4", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + command.toString()); diff --git a/DRAMSys/library/src/controller/checker/CheckerLPDDR5.cpp b/DRAMSys/library/src/controller/checker/CheckerLPDDR5.cpp index 6b65980a..790a2d5a 100644 --- a/DRAMSys/library/src/controller/checker/CheckerLPDDR5.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerLPDDR5.cpp @@ -72,16 +72,16 @@ CheckerLPDDR5::CheckerLPDDR5(const Configuration& config) sc_time CheckerLPDDR5::timeToSatisfyConstraints(Command command, const tlm_generic_payload& payload) const { - Rank rank = DramExtension::getRank(payload); - BankGroup bankGroup = DramExtension::getBankGroup(payload); - Bank bank = DramExtension::getBank(payload); + Rank rank = ControllerExtension::getRank(payload); + BankGroup bankGroup = ControllerExtension::getBankGroup(payload); + Bank bank = ControllerExtension::getBank(payload); sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); if (command == Command::RD || command == Command::RDA) { - unsigned burstLength = DramExtension::getBurstLength(payload); + unsigned burstLength = ControllerExtension::getBurstLength(payload); assert(!(memSpec->bitWidth == 8) || (burstLength == 32)); // x8 device -> BL32 assert(!(memSpec->groupsPerRank > 1) || (burstLength == 16)); // BG mode -> BL16 (TODO: BL32) assert(burstLength <= memSpec->maxBurstLength); @@ -193,7 +193,7 @@ sc_time CheckerLPDDR5::timeToSatisfyConstraints(Command command, const tlm_gener } else if (command == Command::WR || command == Command::WRA) { - unsigned burstLength = DramExtension::getBurstLength(payload); + unsigned burstLength = ControllerExtension::getBurstLength(payload); assert(!(memSpec->bitWidth == 8) || (burstLength == 32)); // x8 device -> BL32 assert(!(memSpec->groupsPerRank > 1) || (burstLength == 16)); // BG mode -> BL16 (TODO: BL32) assert(burstLength <= memSpec->maxBurstLength); @@ -638,10 +638,10 @@ sc_time CheckerLPDDR5::timeToSatisfyConstraints(Command command, const tlm_gener void CheckerLPDDR5::insert(Command command, const tlm_generic_payload& payload) { - Rank rank = DramExtension::getRank(payload); - BankGroup bankGroup = DramExtension::getBankGroup(payload); - Bank bank = DramExtension::getBank(payload); - unsigned burstLength = DramExtension::getBurstLength(payload); + Rank rank = ControllerExtension::getRank(payload); + BankGroup bankGroup = ControllerExtension::getBankGroup(payload); + Bank bank = ControllerExtension::getBank(payload); + unsigned burstLength = ControllerExtension::getBurstLength(payload); PRINTDEBUGMESSAGE("CheckerLPDDR5", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + command.toString()); diff --git a/DRAMSys/library/src/controller/checker/CheckerSTTMRAM.cpp b/DRAMSys/library/src/controller/checker/CheckerSTTMRAM.cpp index 16f59a26..887c59a3 100644 --- a/DRAMSys/library/src/controller/checker/CheckerSTTMRAM.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerSTTMRAM.cpp @@ -66,15 +66,15 @@ CheckerSTTMRAM::CheckerSTTMRAM(const Configuration& config) sc_time CheckerSTTMRAM::timeToSatisfyConstraints(Command command, const tlm_generic_payload& payload) const { - Rank rank = DramExtension::getRank(payload); - Bank bank = DramExtension::getBank(payload); + Rank rank = ControllerExtension::getRank(payload); + Bank bank = ControllerExtension::getBank(payload); sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); if (command == Command::RD || command == Command::RDA) { - assert(DramExtension::getBurstLength(payload) == 8); + assert(ControllerExtension::getBurstLength(payload) == 8); lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != sc_max_time()) @@ -131,7 +131,7 @@ sc_time CheckerSTTMRAM::timeToSatisfyConstraints(Command command, const tlm_gene } else if (command == Command::WR || command == Command::WRA) { - assert(DramExtension::getBurstLength(payload) == 8); + assert(ControllerExtension::getBurstLength(payload) == 8); lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != sc_max_time()) @@ -381,8 +381,8 @@ sc_time CheckerSTTMRAM::timeToSatisfyConstraints(Command command, const tlm_gene void CheckerSTTMRAM::insert(Command command, const tlm_generic_payload& payload) { - Rank rank = DramExtension::getRank(payload); - Bank bank = DramExtension::getBank(payload); + Rank rank = ControllerExtension::getRank(payload); + Bank bank = ControllerExtension::getBank(payload); PRINTDEBUGMESSAGE("CheckerSTTMRAM", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + command.toString()); diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp b/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp index b6ce278e..76c0abbb 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp @@ -66,15 +66,15 @@ CheckerWideIO::CheckerWideIO(const Configuration& config) sc_time CheckerWideIO::timeToSatisfyConstraints(Command command, const tlm_generic_payload& payload) const { - Rank rank = DramExtension::getRank(payload); - Bank bank = DramExtension::getBank(payload); + Rank rank = ControllerExtension::getRank(payload); + Bank bank = ControllerExtension::getBank(payload); sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); if (command == Command::RD || command == Command::RDA) { - unsigned burstLength = DramExtension::getBurstLength(payload); + unsigned burstLength = ControllerExtension::getBurstLength(payload); assert((burstLength == 2) || (burstLength == 4)); assert(burstLength <= memSpec->maxBurstLength); @@ -127,7 +127,7 @@ sc_time CheckerWideIO::timeToSatisfyConstraints(Command command, const tlm_gener } else if (command == Command::WR || command == Command::WRA) { - unsigned burstLength = DramExtension::getBurstLength(payload); + unsigned burstLength = ControllerExtension::getBurstLength(payload); assert((burstLength == 2) || (burstLength == 4)); assert(burstLength <= memSpec->maxBurstLength); @@ -402,8 +402,8 @@ sc_time CheckerWideIO::timeToSatisfyConstraints(Command command, const tlm_gener void CheckerWideIO::insert(Command command, const tlm_generic_payload& payload) { - Rank rank = DramExtension::getRank(payload); - Bank bank = DramExtension::getBank(payload); + Rank rank = ControllerExtension::getRank(payload); + Bank bank = ControllerExtension::getBank(payload); PRINTDEBUGMESSAGE("CheckerWideIO", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + command.toString()); diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp b/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp index ab73abfb..ca42f0fd 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp @@ -67,15 +67,15 @@ CheckerWideIO2::CheckerWideIO2(const Configuration& config) sc_time CheckerWideIO2::timeToSatisfyConstraints(Command command, const tlm_generic_payload& payload) const { - Rank rank = DramExtension::getRank(payload); - Bank bank = DramExtension::getBank(payload); + Rank rank = ControllerExtension::getRank(payload); + Bank bank = ControllerExtension::getBank(payload); sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); if (command == Command::RD || command == Command::RDA) { - unsigned burstLength = DramExtension::getBurstLength(payload); + unsigned burstLength = ControllerExtension::getBurstLength(payload); assert((burstLength == 4) || (burstLength == 8)); // TODO: BL4/8 OTF assert(burstLength <= memSpec->maxBurstLength); @@ -128,7 +128,7 @@ sc_time CheckerWideIO2::timeToSatisfyConstraints(Command command, const tlm_gene } else if (command == Command::WR || command == Command::WRA) { - unsigned burstLength = DramExtension::getBurstLength(payload); + unsigned burstLength = ControllerExtension::getBurstLength(payload); assert((burstLength == 4) || (burstLength == 8)); assert(burstLength <= memSpec->maxBurstLength); @@ -480,8 +480,8 @@ sc_time CheckerWideIO2::timeToSatisfyConstraints(Command command, const tlm_gene void CheckerWideIO2::insert(Command command, const tlm_generic_payload& payload) { - Rank rank = DramExtension::getRank(payload); - Bank bank = DramExtension::getBank(payload); + Rank rank = ControllerExtension::getRank(payload); + Bank bank = ControllerExtension::getBank(payload); PRINTDEBUGMESSAGE("CheckerWideIO2", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + command.toString()); diff --git a/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.cpp b/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.cpp index 7ff7181c..151b34dc 100644 --- a/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.cpp +++ b/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.cpp @@ -52,7 +52,7 @@ CommandTuple::Type CmdMuxOldest::selectCommand(const ReadyCommands &readyCommand { newTimestamp = std::get(*it) + memSpec.getCommandLength(std::get(*it)); - newPayloadID = DramExtension::getChannelPayloadID(*std::get(*it)); + newPayloadID = ControllerExtension::getChannelPayloadID(*std::get(*it)); if (newTimestamp < lastTimestamp) { @@ -108,7 +108,7 @@ CommandTuple::Type CmdMuxOldestRasCas::selectCommand(const ReadyCommands &readyC { newTimestamp = std::get(*it) + memSpec.getCommandLength(std::get(*it)); - newPayloadID = DramExtension::getChannelPayloadID(*std::get(*it)); + newPayloadID = ControllerExtension::getChannelPayloadID(*std::get(*it)); if (newTimestamp < lastTimestamp) { @@ -130,7 +130,7 @@ CommandTuple::Type CmdMuxOldestRasCas::selectCommand(const ReadyCommands &readyC { newTimestamp = std::get(*it) + memSpec.getCommandLength(std::get(*it)); - newPayloadID = DramExtension::getChannelPayloadID(*std::get(*it)); + newPayloadID = ControllerExtension::getChannelPayloadID(*std::get(*it)); if (newTimestamp < lastTimestamp) { @@ -158,7 +158,7 @@ CommandTuple::Type CmdMuxOldestRasCas::selectCommand(const ReadyCommands &readyC for (auto it = readyRasCasCommands.cbegin(); it != readyRasCasCommands.cend(); it++) { newTimestamp = std::get(*it); - newPayloadID = DramExtension::getChannelPayloadID(*std::get(*it)); + newPayloadID = ControllerExtension::getChannelPayloadID(*std::get(*it)); if (newTimestamp < lastTimestamp) { diff --git a/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp b/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp index d046b161..9f3dd176 100644 --- a/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp +++ b/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp @@ -52,7 +52,7 @@ CommandTuple::Type CmdMuxStrict::selectCommand(const ReadyCommands &readyCommand { newTimestamp = std::get(*it) + memSpec.getCommandLength(std::get(*it)); - newPayloadID = DramExtension::getChannelPayloadID(*std::get(*it)); + newPayloadID = ControllerExtension::getChannelPayloadID(*std::get(*it)); if (newTimestamp < lastTimestamp) { @@ -118,7 +118,7 @@ CommandTuple::Type CmdMuxStrictRasCas::selectCommand(const ReadyCommands &readyC { newTimestamp = std::get(*it) + memSpec.getCommandLength(std::get(*it)); - newPayloadID = DramExtension::getChannelPayloadID(*std::get(*it)); + newPayloadID = ControllerExtension::getChannelPayloadID(*std::get(*it)); if (newTimestamp < lastTimestamp) { @@ -135,7 +135,7 @@ CommandTuple::Type CmdMuxStrictRasCas::selectCommand(const ReadyCommands &readyC for (auto it = readyCasCommands.cbegin(); it != readyCasCommands.cend(); it++) { - newPayloadID = DramExtension::getChannelPayloadID(*std::get(*it)); + newPayloadID = ControllerExtension::getChannelPayloadID(*std::get(*it)); if (newPayloadID == nextPayloadID) { @@ -157,7 +157,7 @@ CommandTuple::Type CmdMuxStrictRasCas::selectCommand(const ReadyCommands &readyC for (auto it = readyRasCasCommands.cbegin(); it != readyRasCasCommands.cend(); it++) { newTimestamp = std::get(*it); - newPayloadID = DramExtension::getChannelPayloadID(*std::get(*it)); + newPayloadID = ControllerExtension::getChannelPayloadID(*std::get(*it)); if (newTimestamp < lastTimestamp) { diff --git a/DRAMSys/library/src/controller/respqueue/RespQueueReorder.cpp b/DRAMSys/library/src/controller/respqueue/RespQueueReorder.cpp index 32793a6e..2ce372ad 100644 --- a/DRAMSys/library/src/controller/respqueue/RespQueueReorder.cpp +++ b/DRAMSys/library/src/controller/respqueue/RespQueueReorder.cpp @@ -40,7 +40,7 @@ using namespace tlm; void RespQueueReorder::insertPayload(tlm_generic_payload *payload, sc_time strobeEnd) { - buffer[DramExtension::getChannelPayloadID(*payload)] = {payload, strobeEnd}; + buffer[ControllerExtension::getChannelPayloadID(*payload)] = {payload, strobeEnd}; } tlm_generic_payload *RespQueueReorder::nextPayload() diff --git a/DRAMSys/library/src/controller/scheduler/BufferCounterBankwise.cpp b/DRAMSys/library/src/controller/scheduler/BufferCounterBankwise.cpp index a45baede..d31db7e6 100644 --- a/DRAMSys/library/src/controller/scheduler/BufferCounterBankwise.cpp +++ b/DRAMSys/library/src/controller/scheduler/BufferCounterBankwise.cpp @@ -50,7 +50,7 @@ bool BufferCounterBankwise::hasBufferSpace() const void BufferCounterBankwise::storeRequest(const tlm_generic_payload& trans) { - lastBankID = DramExtension::getBank(trans).ID(); + lastBankID = ControllerExtension::getBank(trans).ID(); numRequestsOnBank[lastBankID]++; if (trans.is_read()) numReadRequests++; @@ -60,7 +60,7 @@ void BufferCounterBankwise::storeRequest(const tlm_generic_payload& trans) void BufferCounterBankwise::removeRequest(const tlm_generic_payload& trans) { - numRequestsOnBank[DramExtension::getBank(trans).ID()]--; + numRequestsOnBank[ControllerExtension::getBank(trans).ID()]--; if (trans.is_read()) numReadRequests--; else diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp b/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp index 52cd08ed..9e1f9ede 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp @@ -59,13 +59,13 @@ bool SchedulerFifo::hasBufferSpace() const void SchedulerFifo::storeRequest(tlm_generic_payload& payload) { - buffer[DramExtension::getBank(payload).ID()].push_back(&payload); + buffer[ControllerExtension::getBank(payload).ID()].push_back(&payload); bufferCounter->storeRequest(payload); } void SchedulerFifo::removeRequest(tlm_generic_payload& payload) { - buffer[DramExtension::getBank(payload).ID()].pop_front(); + buffer[ControllerExtension::getBank(payload).ID()].pop_front(); bufferCounter->removeRequest(payload); } @@ -83,7 +83,7 @@ bool SchedulerFifo::hasFurtherRowHit(Bank bank, Row row, tlm_command command) co if (buffer[bank.ID()].size() >= 2) { tlm_generic_payload& nextRequest = *buffer[bank.ID()][1]; - if (DramExtension::getRow(nextRequest) == row) + if (ControllerExtension::getRow(nextRequest) == row) return true; } return false; diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp index 3c5d4587..dffdd224 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp @@ -59,14 +59,14 @@ bool SchedulerFrFcfs::hasBufferSpace() const void SchedulerFrFcfs::storeRequest(tlm_generic_payload& trans) { - buffer[DramExtension::getBank(trans).ID()].push_back(&trans); + buffer[ControllerExtension::getBank(trans).ID()].push_back(&trans); bufferCounter->storeRequest(trans); } void SchedulerFrFcfs::removeRequest(tlm_generic_payload& trans) { bufferCounter->removeRequest(trans); - unsigned bankID = DramExtension::getBank(trans).ID(); + unsigned bankID = ControllerExtension::getBank(trans).ID(); for (auto it = buffer[bankID].begin(); it != buffer[bankID].end(); it++) { if (*it == &trans) @@ -88,7 +88,7 @@ tlm_generic_payload *SchedulerFrFcfs::getNextRequest(const BankMachine& bankMach Row openRow = bankMachine.getOpenRow(); for (auto it : buffer[bankID]) { - if (DramExtension::getRow(*it) == openRow) + if (ControllerExtension::getRow(*it) == openRow) return it; } } @@ -103,7 +103,7 @@ bool SchedulerFrFcfs::hasFurtherRowHit(Bank bank, Row row, tlm_command command) unsigned rowHitCounter = 0; for (auto it : buffer[bank.ID()]) { - if (DramExtension::getRow(*it) == row) + if (ControllerExtension::getRow(*it) == row) { rowHitCounter++; if (rowHitCounter == 2) diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.cpp b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.cpp index b4b6320b..5d3a2b8e 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.cpp +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.cpp @@ -59,7 +59,7 @@ bool SchedulerFrFcfsGrp::hasBufferSpace() const void SchedulerFrFcfsGrp::storeRequest(tlm_generic_payload& trans) { - buffer[DramExtension::getBank(trans).ID()].push_back(&trans); + buffer[ControllerExtension::getBank(trans).ID()].push_back(&trans); bufferCounter->storeRequest(trans); } @@ -67,7 +67,7 @@ void SchedulerFrFcfsGrp::removeRequest(tlm_generic_payload& trans) { bufferCounter->removeRequest(trans); lastCommand = trans.get_command(); - unsigned bankID = DramExtension::getBank(trans).ID(); + unsigned bankID = ControllerExtension::getBank(trans).ID(); for (auto it = buffer[bankID].begin(); it != buffer[bankID].end(); it++) { if (*it == &trans) @@ -90,7 +90,7 @@ tlm_generic_payload *SchedulerFrFcfsGrp::getNextRequest(const BankMachine& bankM std::list rowHits; for (auto it : buffer[bankID]) { - if (DramExtension::getRow(*it) == openRow) + if (ControllerExtension::getRow(*it) == openRow) rowHits.push_back(it); } @@ -128,7 +128,7 @@ bool SchedulerFrFcfsGrp::hasFurtherRowHit(Bank bank, Row row, tlm_command comman unsigned rowHitCounter = 0; for (auto it : buffer[bank.ID()]) { - if (DramExtension::getRow(*it) == row) + if (ControllerExtension::getRow(*it) == row) { rowHitCounter++; if (rowHitCounter == 2) diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerGrpFrFcfs.cpp b/DRAMSys/library/src/controller/scheduler/SchedulerGrpFrFcfs.cpp index cd9f697c..35b7fa48 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerGrpFrFcfs.cpp +++ b/DRAMSys/library/src/controller/scheduler/SchedulerGrpFrFcfs.cpp @@ -63,9 +63,9 @@ bool SchedulerGrpFrFcfs::hasBufferSpace() const void SchedulerGrpFrFcfs::storeRequest(tlm_generic_payload& trans) { if (trans.is_read()) - readBuffer[DramExtension::getBank(trans).ID()].push_back(&trans); + readBuffer[ControllerExtension::getBank(trans).ID()].push_back(&trans); else - writeBuffer[DramExtension::getBank(trans).ID()].push_back(&trans); + writeBuffer[ControllerExtension::getBank(trans).ID()].push_back(&trans); bufferCounter->storeRequest(trans); } @@ -73,7 +73,7 @@ void SchedulerGrpFrFcfs::removeRequest(tlm_generic_payload& trans) { bufferCounter->removeRequest(trans); lastCommand = trans.get_command(); - unsigned bankID = DramExtension::getBank(trans).ID(); + unsigned bankID = ControllerExtension::getBank(trans).ID(); if (trans.is_read()) readBuffer[bankID].remove(&trans); @@ -97,7 +97,7 @@ tlm_generic_payload *SchedulerGrpFrFcfs::getNextRequest(const BankMachine& bankM Row openRow = bankMachine.getOpenRow(); for (auto it : readBuffer[bankID]) { - if (DramExtension::getRow(*it) == openRow) + if (ControllerExtension::getRow(*it) == openRow) return it; } } @@ -112,7 +112,7 @@ tlm_generic_payload *SchedulerGrpFrFcfs::getNextRequest(const BankMachine& bankM Row openRow = bankMachine.getOpenRow(); for (auto it : writeBuffer[bankID]) { - if (DramExtension::getRow(*it) == openRow) + if (ControllerExtension::getRow(*it) == openRow) return it; } } @@ -132,7 +132,7 @@ tlm_generic_payload *SchedulerGrpFrFcfs::getNextRequest(const BankMachine& bankM Row openRow = bankMachine.getOpenRow(); for (auto it : writeBuffer[bankID]) { - if (DramExtension::getRow(*it) == openRow) + if (ControllerExtension::getRow(*it) == openRow) return it; } } @@ -147,7 +147,7 @@ tlm_generic_payload *SchedulerGrpFrFcfs::getNextRequest(const BankMachine& bankM Row openRow = bankMachine.getOpenRow(); for (auto it : readBuffer[bankID]) { - if (DramExtension::getRow(*it) == openRow) + if (ControllerExtension::getRow(*it) == openRow) return it; } } @@ -167,7 +167,7 @@ bool SchedulerGrpFrFcfs::hasFurtherRowHit(Bank bank, Row row, tlm_command comman { for (auto it : readBuffer[bank.ID()]) { - if (DramExtension::getRow(*it) == row) + if (ControllerExtension::getRow(*it) == row) { rowHitCounter++; if (rowHitCounter == 2) @@ -180,7 +180,7 @@ bool SchedulerGrpFrFcfs::hasFurtherRowHit(Bank bank, Row row, tlm_command comman { for (auto it : writeBuffer[bank.ID()]) { - if (DramExtension::getRow(*it) == row) + if (ControllerExtension::getRow(*it) == row) { rowHitCounter++; if (rowHitCounter == 2) diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerGrpFrFcfsWm.cpp b/DRAMSys/library/src/controller/scheduler/SchedulerGrpFrFcfsWm.cpp index c6adda13..6a4a8971 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerGrpFrFcfsWm.cpp +++ b/DRAMSys/library/src/controller/scheduler/SchedulerGrpFrFcfsWm.cpp @@ -67,9 +67,9 @@ bool SchedulerGrpFrFcfsWm::hasBufferSpace() const void SchedulerGrpFrFcfsWm::storeRequest(tlm_generic_payload& trans) { if (trans.is_read()) - readBuffer[DramExtension::getBank(trans).ID()].push_back(&trans); + readBuffer[ControllerExtension::getBank(trans).ID()].push_back(&trans); else - writeBuffer[DramExtension::getBank(trans).ID()].push_back(&trans); + writeBuffer[ControllerExtension::getBank(trans).ID()].push_back(&trans); bufferCounter->storeRequest(trans); evaluateWriteMode(); } @@ -77,7 +77,7 @@ void SchedulerGrpFrFcfsWm::storeRequest(tlm_generic_payload& trans) void SchedulerGrpFrFcfsWm::removeRequest(tlm_generic_payload& trans) { bufferCounter->removeRequest(trans); - unsigned bankID = DramExtension::getBank(trans).ID(); + unsigned bankID = ControllerExtension::getBank(trans).ID(); if (trans.is_read()) readBuffer[bankID].remove(&trans); @@ -101,7 +101,7 @@ tlm_generic_payload *SchedulerGrpFrFcfsWm::getNextRequest(const BankMachine& ban Row openRow = bankMachine.getOpenRow(); for (auto it : readBuffer[bankID]) { - if (DramExtension::getRow(*it) == openRow) + if (ControllerExtension::getRow(*it) == openRow) return it; } } @@ -121,7 +121,7 @@ tlm_generic_payload *SchedulerGrpFrFcfsWm::getNextRequest(const BankMachine& ban Row openRow = bankMachine.getOpenRow(); for (auto it : writeBuffer[bankID]) { - if (DramExtension::getRow(*it) == openRow) + if (ControllerExtension::getRow(*it) == openRow) return it; } } @@ -140,7 +140,7 @@ bool SchedulerGrpFrFcfsWm::hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command { for (const auto* it : readBuffer[bank.ID()]) { - if (DramExtension::getRow(*it) == row) + if (ControllerExtension::getRow(*it) == row) { rowHitCounter++; if (rowHitCounter == 2) @@ -153,7 +153,7 @@ bool SchedulerGrpFrFcfsWm::hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command { for (auto it : writeBuffer[bank.ID()]) { - if (DramExtension::getRow(*it) == row) + if (ControllerExtension::getRow(*it) == row) { rowHitCounter++; if (rowHitCounter == 2) diff --git a/DRAMSys/library/src/error/errormodel.cpp b/DRAMSys/library/src/error/errormodel.cpp index ccbfde86..e9a6782f 100644 --- a/DRAMSys/library/src/error/errormodel.cpp +++ b/DRAMSys/library/src/error/errormodel.cpp @@ -158,11 +158,13 @@ void errorModel::store(tlm::tlm_generic_payload &trans) markBitFlips(); // Get the key for the dataMap from the transaction's dram extension: - DramExtension &ext = DramExtension::getExtension(trans); - DecodedAddress key = DecodedAddress(ext.getChannel().ID(), ext.getRank().ID(), - ext.getBankGroup().ID(), ext.getBank().ID(), - ext.getRow().ID(), ext.getColumn().ID(), 0); - // Set context: + // FIXME +// ControllerExtension &ext = ControllerExtension::getExtension(trans); +// DecodedAddress key = DecodedAddress(ext.getChannel().ID(), ext.getRank().ID(), +// ext.getBankGroup().ID(), ext.getBank().ID(), +// ext.getRow().ID(), ext.getColumn().ID(), 0); + DecodedAddress key; +// Set context: setContext(key); std::stringstream msg; @@ -226,11 +228,12 @@ void errorModel::load(tlm::tlm_generic_payload &trans) markBitFlips(); // Get the key for the dataMap from the transaction's dram extension: - DramExtension &ext = DramExtension::getExtension(trans); - DecodedAddress key = DecodedAddress(ext.getChannel().ID(), ext.getRank().ID(), - ext.getBankGroup().ID(), ext.getBank().ID(), - ext.getRow().ID(), ext.getColumn().ID(), 0); - + // FIXME +// DramExtension &ext = DramExtension::getExtension(trans); +// DecodedAddress key = DecodedAddress(ext.getChannel().ID(), ext.getRank().ID(), +// ext.getBankGroup().ID(), ext.getBank().ID(), +// ext.getRow().ID(), ext.getColumn().ID(), 0); + DecodedAddress key; // Set context: setContext(key); diff --git a/DRAMSys/library/src/simulation/Arbiter.cpp b/DRAMSys/library/src/simulation/Arbiter.cpp index 9bbf1992..57c545bf 100644 --- a/DRAMSys/library/src/simulation/Arbiter.cpp +++ b/DRAMSys/library/src/simulation/Arbiter.cpp @@ -138,12 +138,8 @@ tlm_sync_enum Arbiter::nb_transport_fw(int id, tlm_generic_payload &payload, uint64_t adjustedAddress = payload.get_address() - addressOffset; payload.set_address(adjustedAddress); - DecodedAddress decodedAddress = addressDecoder.decodeAddress(adjustedAddress); - DramExtension::setExtension(payload, Thread(static_cast(id)), Channel(decodedAddress.channel), - Rank(decodedAddress.rank), - BankGroup(decodedAddress.bankgroup), Bank(decodedAddress.bank), - Row(decodedAddress.row), Column(decodedAddress.column), - payload.get_data_length() / bytesPerBeat, 0, 0); + unsigned channel = addressDecoder.decodeChannel(adjustedAddress); + ArbiterExtension::setAutoExtension(payload, Thread(id), Channel(channel)); payload.acquire(); } @@ -172,14 +168,12 @@ unsigned int Arbiter::transport_dbg(int /*id*/, tlm::tlm_generic_payload &trans) void ArbiterSimple::peqCallback(tlm_generic_payload &cbPayload, const tlm_phase &cbPhase) { - unsigned int threadId = DramExtension::getExtension(cbPayload).getThread().ID(); - unsigned int channelId = DramExtension::getExtension(cbPayload).getChannel().ID(); + unsigned int threadId = ArbiterExtension::getThread(cbPayload).ID(); + unsigned int channelId = ArbiterExtension::getChannel(cbPayload).ID(); if (cbPhase == BEGIN_REQ) // from initiator { - GenerationExtension::setExtension(cbPayload, sc_time_stamp()); - DramExtension::setPayloadIDs(cbPayload, - nextThreadPayloadIDToAppend[threadId]++, nextChannelPayloadIDToAppend[channelId]++); + ArbiterExtension::setIDAndTimeOfGeneration(cbPayload, nextThreadPayloadIDToAppend[threadId]++, sc_time_stamp()); if (!channelIsBusy[channelId]) { @@ -263,8 +257,8 @@ void ArbiterSimple::peqCallback(tlm_generic_payload &cbPayload, const tlm_phase void ArbiterFifo::peqCallback(tlm_generic_payload &cbPayload, const tlm_phase &cbPhase) { - unsigned int threadId = DramExtension::getExtension(cbPayload).getThread().ID(); - unsigned int channelId = DramExtension::getExtension(cbPayload).getChannel().ID(); + unsigned int threadId = ArbiterExtension::getThread(cbPayload).ID(); + unsigned int channelId = ArbiterExtension::getChannel(cbPayload).ID(); if (cbPhase == BEGIN_REQ) // from initiator { @@ -272,9 +266,8 @@ void ArbiterFifo::peqCallback(tlm_generic_payload &cbPayload, const tlm_phase &c { activeTransactions[threadId]++; - GenerationExtension::setExtension(cbPayload, sc_time_stamp()); - DramExtension::setPayloadIDs(cbPayload, - nextThreadPayloadIDToAppend[threadId]++, nextChannelPayloadIDToAppend[channelId]++); + ArbiterExtension::setIDAndTimeOfGeneration(cbPayload, nextThreadPayloadIDToAppend[threadId]++, + sc_time_stamp()); tlm_phase tPhase = END_REQ; sc_time tDelay = SC_ZERO_TIME; @@ -325,11 +318,9 @@ void ArbiterFifo::peqCallback(tlm_generic_payload &cbPayload, const tlm_phase &c outstandingEndReq[threadId] = nullptr; tlm_phase tPhase = END_REQ; sc_time tDelay = SC_ZERO_TIME; - unsigned int tChannelId = DramExtension::getExtension(tPayload).getChannel().ID(); - GenerationExtension::setExtension(tPayload, sc_time_stamp()); - DramExtension::setPayloadIDs(tPayload, - nextThreadPayloadIDToAppend[threadId]++, nextChannelPayloadIDToAppend[tChannelId]++); + ArbiterExtension::setIDAndTimeOfGeneration(tPayload, nextThreadPayloadIDToAppend[threadId]++, + sc_time_stamp()); tSocket[static_cast(threadId)]->nb_transport_bw(tPayload, tPhase, tDelay); @@ -394,8 +385,8 @@ void ArbiterFifo::peqCallback(tlm_generic_payload &cbPayload, const tlm_phase &c void ArbiterReorder::peqCallback(tlm_generic_payload &cbPayload, const tlm_phase &cbPhase) { - unsigned int threadId = DramExtension::getExtension(cbPayload).getThread().ID(); - unsigned int channelId = DramExtension::getExtension(cbPayload).getChannel().ID(); + unsigned int threadId = ArbiterExtension::getThread(cbPayload).ID(); + unsigned int channelId = ArbiterExtension::getChannel(cbPayload).ID(); if (cbPhase == BEGIN_REQ) // from initiator { @@ -403,9 +394,8 @@ void ArbiterReorder::peqCallback(tlm_generic_payload &cbPayload, const tlm_phase { activeTransactions[threadId]++; - GenerationExtension::setExtension(cbPayload, sc_time_stamp()); - DramExtension::setPayloadIDs(cbPayload, - nextThreadPayloadIDToAppend[threadId]++, nextChannelPayloadIDToAppend[channelId]++); + ArbiterExtension::setIDAndTimeOfGeneration(cbPayload, nextThreadPayloadIDToAppend[threadId]++, + sc_time_stamp()); tlm_phase tPhase = END_REQ; sc_time tDelay = SC_ZERO_TIME; @@ -455,11 +445,9 @@ void ArbiterReorder::peqCallback(tlm_generic_payload &cbPayload, const tlm_phase outstandingEndReq[threadId] = nullptr; tlm_phase tPhase = END_REQ; sc_time tDelay = SC_ZERO_TIME; - unsigned int tChannelId = DramExtension::getExtension(tPayload).getChannel().ID(); - GenerationExtension::setExtension(tPayload, sc_time_stamp()); - DramExtension::setPayloadIDs(tPayload, - nextThreadPayloadIDToAppend[threadId]++, nextChannelPayloadIDToAppend[tChannelId]++); + ArbiterExtension::setIDAndTimeOfGeneration(tPayload, nextThreadPayloadIDToAppend[threadId]++, + sc_time_stamp()); tSocket[static_cast(threadId)]->nb_transport_bw(tPayload, tPhase, tDelay); @@ -471,7 +459,7 @@ void ArbiterReorder::peqCallback(tlm_generic_payload &cbPayload, const tlm_phase tlm_generic_payload &tPayload = **pendingResponses[threadId].begin(); if (!pendingResponses[threadId].empty() && - DramExtension::getThreadPayloadID(tPayload) == nextThreadPayloadIDToReturn[threadId]) + ArbiterExtension::getThreadPayloadID(tPayload) == nextThreadPayloadIDToReturn[threadId]) { nextThreadPayloadIDToReturn[threadId]++; pendingResponses[threadId].erase(pendingResponses[threadId].begin()); @@ -511,7 +499,7 @@ void ArbiterReorder::peqCallback(tlm_generic_payload &cbPayload, const tlm_phase { tlm_generic_payload &tPayload = **pendingResponses[threadId].begin(); - if (DramExtension::getThreadPayloadID(tPayload) == nextThreadPayloadIDToReturn[threadId]) + if (ArbiterExtension::getThreadPayloadID(tPayload) == nextThreadPayloadIDToReturn[threadId]) { threadIsBusy[threadId] = true; diff --git a/DRAMSys/library/src/simulation/Arbiter.h b/DRAMSys/library/src/simulation/Arbiter.h index 799ab27c..f99e997e 100644 --- a/DRAMSys/library/src/simulation/Arbiter.h +++ b/DRAMSys/library/src/simulation/Arbiter.h @@ -149,7 +149,7 @@ private: { bool operator() (const tlm::tlm_generic_payload *lhs, const tlm::tlm_generic_payload *rhs) const { - return DramExtension::getThreadPayloadID(*lhs) < DramExtension::getThreadPayloadID(*rhs); + return ArbiterExtension::getThreadPayloadID(*lhs) < ArbiterExtension::getThreadPayloadID(*rhs); } }; diff --git a/DRAMSys/library/src/simulation/dram/Dram.cpp b/DRAMSys/library/src/simulation/dram/Dram.cpp index e75096d8..d90fd06d 100644 --- a/DRAMSys/library/src/simulation/dram/Dram.cpp +++ b/DRAMSys/library/src/simulation/dram/Dram.cpp @@ -124,7 +124,7 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload, if (powerAnalysis) { - int bank = static_cast(DramExtension::getExtension(payload).getBank().ID()); + int bank = static_cast(ControllerExtension::getBank(payload).ID()); int64_t cycle = std::lround((sc_time_stamp() + delay) / memSpec.tCK); DRAMPower->doCommand(phaseToDRAMPowerCommand(phase), bank, cycle); } diff --git a/DRAMSys/library/src/simulation/dram/DramRecordable.cpp b/DRAMSys/library/src/simulation/dram/DramRecordable.cpp index 90c75dd2..a64e71c4 100644 --- a/DRAMSys/library/src/simulation/dram/DramRecordable.cpp +++ b/DRAMSys/library/src/simulation/dram/DramRecordable.cpp @@ -93,12 +93,12 @@ void DramRecordable::recordPhase(tlm_generic_payload &trans, const tlm if (phase == END_PDNA || phase == END_PDNP || phase == END_SREF) recTime += this->memSpec.getCommandLength(Command(phase)); - NDEBUG_UNUSED(unsigned thr) = DramExtension::getExtension(trans).getThread().ID(); - NDEBUG_UNUSED(unsigned ch) = DramExtension::getExtension(trans).getChannel().ID(); - NDEBUG_UNUSED(unsigned bg) = DramExtension::getExtension(trans).getBankGroup().ID(); - NDEBUG_UNUSED(unsigned bank) = DramExtension::getExtension(trans).getBank().ID(); - NDEBUG_UNUSED(unsigned row) = DramExtension::getExtension(trans).getRow().ID(); - NDEBUG_UNUSED(unsigned col) = DramExtension::getExtension(trans).getColumn().ID(); + NDEBUG_UNUSED(unsigned thr) = ArbiterExtension::getExtension(trans).getThread().ID(); + NDEBUG_UNUSED(unsigned ch) = ArbiterExtension::getExtension(trans).getChannel().ID(); + NDEBUG_UNUSED(unsigned bg) = ControllerExtension::getExtension(trans).getBankGroup().ID(); + NDEBUG_UNUSED(unsigned bank) = ControllerExtension::getExtension(trans).getBank().ID(); + NDEBUG_UNUSED(unsigned row) = ControllerExtension::getExtension(trans).getRow().ID(); + NDEBUG_UNUSED(unsigned col) = ControllerExtension::getExtension(trans).getColumn().ID(); PRINTDEBUGMESSAGE(this->name(), "Recording " + getPhaseName(phase) + " thread " + std::to_string(thr) + " channel " + std::to_string(ch) + " bank group " + std::to_string( diff --git a/DRAMSys/library/src/simulation/dram/DramWideIO.cpp b/DRAMSys/library/src/simulation/dram/DramWideIO.cpp index eb3b6f4e..e96e4760 100644 --- a/DRAMSys/library/src/simulation/dram/DramWideIO.cpp +++ b/DRAMSys/library/src/simulation/dram/DramWideIO.cpp @@ -176,7 +176,7 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, if (powerAnalysis) { - int bank = static_cast(DramExtension::getExtension(payload).getBank().ID()); + int bank = static_cast(ControllerExtension::getBank(payload).ID()); int64_t cycle = std::lround((sc_time_stamp() + delay) / memSpec.tCK); DRAMPower->doCommand(phaseToDRAMPowerCommand(phase), bank, cycle); } @@ -197,16 +197,16 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, else if (storeMode == Configuration::StoreMode::ErrorModel) { // TODO: delay should be considered here! - unsigned bank = DramExtension::getExtension(payload).getBank().ID(); + unsigned bank = ControllerExtension::getBank(payload).ID(); if (phase == BEGIN_ACT) - ememory[bank]->activate(DramExtension::getExtension(payload).getRow().ID()); + ememory[bank]->activate(ControllerExtension::getRow(payload).ID()); else if (phase == BEGIN_RD || phase == BEGIN_RDA) ememory[bank]->load(payload); else if (phase == BEGIN_WR || phase == BEGIN_WRA) ememory[bank]->store(payload); else if (phase == BEGIN_REFAB) - ememory[bank]->refresh(DramExtension::getExtension(payload).getRow().ID()); + ememory[bank]->refresh(ControllerExtension::getRow(payload).ID()); } return TLM_ACCEPTED; From f16878236195ff7f9ad2a59e230a233716920bf0 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Thu, 28 Apr 2022 17:35:40 +0200 Subject: [PATCH 05/29] Change database format 1. --- DRAMSys/library/src/common/TlmRecorder.cpp | 104 +++++++++++---------- DRAMSys/library/src/common/TlmRecorder.h | 52 +++++++---- 2 files changed, 86 insertions(+), 70 deletions(-) diff --git a/DRAMSys/library/src/common/TlmRecorder.cpp b/DRAMSys/library/src/common/TlmRecorder.cpp index 15ffc4da..358886cb 100644 --- a/DRAMSys/library/src/common/TlmRecorder.cpp +++ b/DRAMSys/library/src/common/TlmRecorder.cpp @@ -124,12 +124,20 @@ void TlmRecorder::recordPhase(tlm_generic_payload &trans, if (phase == END_REQ || phase == END_RESP || phase >= END_PDNA) { assert(getPhaseName(phase).substr(4) == currentTransactionsInSystem.at(&trans).recordedPhases.back().name); + // TODO: this assumes that the controller does not start with a transaction until END_REQ has been sent, which is not true any more for big transactions currentTransactionsInSystem.at(&trans).recordedPhases.back().interval.end = time; } + else if (phase == BEGIN_REQ || phase == BEGIN_RESP) + { + std::string phaseName = getPhaseName(phase).substr(6); + currentTransactionsInSystem.at(&trans).recordedPhases.emplace_back(phaseName, time); + } else { std::string phaseName = getPhaseName(phase).substr(6); // remove "BEGIN_" - currentTransactionsInSystem.at(&trans).recordedPhases.emplace_back(phaseName, time); + const ControllerExtension& extension = ControllerExtension::getExtension(trans); + currentTransactionsInSystem.at(&trans).recordedPhases.emplace_back(phaseName, time, extension.getRank(), + extension.getBankGroup(), extension.getBank(), extension.getRow(), extension.getColumn()); } if (currentTransactionsInSystem.at(&trans).cmd == 'X') @@ -174,23 +182,24 @@ void TlmRecorder::recordDebugMessage(const std::string &message, const sc_time & // ------------- internal ----------------------- -void TlmRecorder::introduceTransactionSystem(tlm_generic_payload &trans) +void TlmRecorder::introduceTransactionSystem(tlm_generic_payload& trans) { totalNumTransactions++; - currentTransactionsInSystem.insert({&trans, Transaction(totalNumTransactions, - ArbiterExtension::getExtension(trans), ControllerExtension::getExtension(trans))}); - currentTransactionsInSystem.at(&trans).id = totalNumTransactions; + + char commandChar; tlm_command command = trans.get_command(); if (command == TLM_READ_COMMAND) - currentTransactionsInSystem.at(&trans).cmd = 'R'; + commandChar = 'R'; else if (command == TLM_WRITE_COMMAND) - currentTransactionsInSystem.at(&trans).cmd = 'W'; + commandChar = 'W'; else - currentTransactionsInSystem.at(&trans).cmd = 'X'; - currentTransactionsInSystem.at(&trans).address = trans.get_address(); - currentTransactionsInSystem.at(&trans).burstLength = ControllerExtension::getBurstLength(trans); - currentTransactionsInSystem.at(&trans).controllerExtension = ControllerExtension::getExtension(trans); - currentTransactionsInSystem.at(&trans).timeOfGeneration = ArbiterExtension::getTimeOfGeneration(trans); + commandChar = 'X'; + + const ArbiterExtension& extension = ArbiterExtension::getExtension(trans); + + currentTransactionsInSystem.insert({&trans, Transaction(totalNumTransactions, trans.get_address(), + trans.get_data_length(), commandChar, extension.getTimeOfGeneration(), extension.getThread(), + extension.getChannel())}); PRINTDEBUGMESSAGE(name, "New transaction #" + std::to_string(totalNumTransactions) + " generation time " + currentTransactionsInSystem.at(&trans).timeOfGeneration.to_string()); @@ -247,23 +256,22 @@ void TlmRecorder::terminateRemainingTransactions() void TlmRecorder::commitRecordedDataToDB() { sqlite3_exec(db, "BEGIN;", nullptr, nullptr, nullptr); - for (Transaction &recordingData : *storageDataBuffer) + for (const Transaction& transaction : *storageDataBuffer) { - assert(!recordingData.recordedPhases.empty()); - insertTransactionInDB(recordingData); - for (Transaction::Phase &phaseData : recordingData.recordedPhases) + assert(!transaction.recordedPhases.empty()); + insertTransactionInDB(transaction); + for (const Transaction::Phase& phase : transaction.recordedPhases) { - insertPhaseInDB(phaseData.name, phaseData.interval.start, - phaseData.interval.end, recordingData.id); + insertPhaseInDB(phase, transaction.id); } - sc_time rangeBegin = recordingData.recordedPhases.front().interval.start; + sc_time rangeBegin = transaction.recordedPhases.front().interval.start; sc_time rangeEnd = rangeBegin; - for (auto &it : recordingData.recordedPhases) + for (const Transaction::Phase& phase : transaction.recordedPhases) { - rangeEnd = std::max(rangeEnd, it.interval.end); + rangeEnd = std::max(rangeEnd, phase.interval.end); } - insertRangeInDB(recordingData.id, rangeBegin, rangeEnd); + insertRangeInDB(transaction.id, rangeBegin, rangeEnd); } sqlite3_exec(db, "COMMIT;", nullptr, nullptr, nullptr); @@ -290,8 +298,8 @@ void TlmRecorder::openDB(const std::string &dbName) void TlmRecorder::prepareSqlStatements() { insertTransactionString = - "INSERT INTO Transactions VALUES (:id,:rangeID,:address,:burstlength,:thread,:channel,:rank," - ":bankgroup,:bank,:row,:column,:dataStrobeBegin,:dataStrobeEnd, :timeOfGeneration,:command)"; + "INSERT INTO Transactions VALUES (:id,:rangeID,:address,:dataLength,:thread,:channel," + ":dataStrobeBegin,:dataStrobeEnd,:timeOfGeneration,:command)"; insertRangeString = "INSERT INTO Ranges VALUES (:id,:begin,:end)"; @@ -301,7 +309,8 @@ void TlmRecorder::prepareSqlStatements() "UPDATE Transactions SET DataStrobeBegin = :begin, DataStrobeEnd = :end WHERE ID = :id"; insertPhaseString = - "INSERT INTO Phases (PhaseName,PhaseBegin,PhaseEnd,Transact) VALUES (:name,:begin,:end,:transaction)"; + "INSERT INTO Phases (PhaseName,PhaseBegin,PhaseEnd,Rank,BankGroup,Bank,Row,Column,BurstLength,Transact) " + "VALUES (:name,:begin,:end,:rank,:bankGroup,:bank,:row,:column,:burstLength,:transaction)"; updatePhaseString = "UPDATE Phases SET PhaseEnd = :end WHERE Transact = :trans AND PhaseName = :name"; @@ -408,33 +417,23 @@ void TlmRecorder::insertCommandLengths() insertCommandLength(static_cast(command)); } -void TlmRecorder::insertTransactionInDB(Transaction &recordingData) +void TlmRecorder::insertTransactionInDB(const Transaction &recordingData) { sqlite3_bind_int(insertTransactionStatement, 1, static_cast(recordingData.id)); sqlite3_bind_int(insertTransactionStatement, 2, static_cast(recordingData.id)); sqlite3_bind_int64(insertTransactionStatement, 3, static_cast(recordingData.address)); - sqlite3_bind_int(insertTransactionStatement, 4, static_cast(recordingData.burstLength)); + sqlite3_bind_int(insertTransactionStatement, 4, static_cast(recordingData.dataLength)); sqlite3_bind_int(insertTransactionStatement, 5, - static_cast(recordingData.arbiterExtension.getThread().ID())); + static_cast(recordingData.thread.ID())); sqlite3_bind_int(insertTransactionStatement, 6, - static_cast(recordingData.arbiterExtension.getChannel().ID())); - sqlite3_bind_int(insertTransactionStatement, 7, - static_cast(recordingData.controllerExtension.getRank().ID())); - sqlite3_bind_int(insertTransactionStatement, 8, - static_cast(recordingData.controllerExtension.getBankGroup().ID())); - sqlite3_bind_int(insertTransactionStatement, 9, - static_cast(recordingData.controllerExtension.getBank().ID())); - sqlite3_bind_int(insertTransactionStatement, 10, - static_cast(recordingData.controllerExtension.getRow().ID())); - sqlite3_bind_int(insertTransactionStatement, 11, - static_cast(recordingData.controllerExtension.getColumn().ID())); - sqlite3_bind_int64(insertTransactionStatement, 12, + static_cast(recordingData.channel.ID())); + sqlite3_bind_int64(insertTransactionStatement, 7, static_cast(recordingData.timeOnDataStrobe.start.value())); - sqlite3_bind_int64(insertTransactionStatement, 13, + sqlite3_bind_int64(insertTransactionStatement, 8, static_cast(recordingData.timeOnDataStrobe.end.value())); - sqlite3_bind_int64(insertTransactionStatement, 14, + sqlite3_bind_int64(insertTransactionStatement, 9, static_cast(recordingData.timeOfGeneration.value())); - sqlite3_bind_text(insertTransactionStatement, 15, + sqlite3_bind_text(insertTransactionStatement, 10, &recordingData.cmd, 1, nullptr); executeSqlStatement(insertTransactionStatement); @@ -449,15 +448,18 @@ void TlmRecorder::insertRangeInDB(uint64_t id, const sc_time &begin, executeSqlStatement(insertRangeStatement); } -void TlmRecorder::insertPhaseInDB(const std::string &phaseName, const sc_time &begin, - const sc_time &end, - uint64_t transactionID) +void TlmRecorder::insertPhaseInDB(const Transaction::Phase& phase, uint64_t transactionID) { - sqlite3_bind_text(insertPhaseStatement, 1, phaseName.c_str(), - static_cast(phaseName.length()), nullptr); - sqlite3_bind_int64(insertPhaseStatement, 2, static_cast(begin.value())); - sqlite3_bind_int64(insertPhaseStatement, 3, static_cast(end.value())); - sqlite3_bind_int64(insertPhaseStatement, 4, static_cast(transactionID)); + sqlite3_bind_text(insertPhaseStatement, 1, phase.name.c_str(), static_cast(phase.name.length()), nullptr); + sqlite3_bind_int64(insertPhaseStatement, 2, static_cast(phase.interval.start.value())); + sqlite3_bind_int64(insertPhaseStatement, 3, static_cast(phase.interval.end.value())); + sqlite3_bind_int(insertPhaseStatement, 4, static_cast(phase.rank.ID())); + sqlite3_bind_int(insertPhaseStatement, 5, static_cast(phase.bankGroup.ID())); + sqlite3_bind_int(insertPhaseStatement, 6, static_cast(phase.bank.ID())); + sqlite3_bind_int(insertPhaseStatement, 7, static_cast(phase.row.ID())); + sqlite3_bind_int(insertPhaseStatement, 8, static_cast(phase.column.ID())); + sqlite3_bind_int(insertPhaseStatement, 9, static_cast(phase.burstLength)); + sqlite3_bind_int64(insertPhaseStatement, 10, static_cast(transactionID)); executeSqlStatement(insertPhaseStatement); } diff --git a/DRAMSys/library/src/common/TlmRecorder.h b/DRAMSys/library/src/common/TlmRecorder.h index f531efd5..5186a215 100644 --- a/DRAMSys/library/src/common/TlmRecorder.h +++ b/DRAMSys/library/src/common/TlmRecorder.h @@ -91,25 +91,39 @@ private: struct Transaction { //Transaction() = default; - Transaction(uint64_t id, ArbiterExtension arbiterExtension, ControllerExtension controllerExtension) : - id(id), arbiterExtension(std::move(arbiterExtension)), - controllerExtension(std::move(controllerExtension)) {} + Transaction(uint64_t id, uint64_t address, unsigned int dataLength, char cmd, + const sc_core::sc_time& timeOfGeneration, Thread thread, Channel channel) : + id(id), address(address), dataLength(dataLength), cmd(cmd), timeOfGeneration(timeOfGeneration), + thread(thread), channel(channel) {} uint64_t id = 0; uint64_t address = 0; - unsigned int burstLength = 0; + unsigned int dataLength = 0; + //unsigned int burstLength = 0; // TODO: move to phase char cmd = 'X'; - ArbiterExtension arbiterExtension; - ControllerExtension controllerExtension; + //ArbiterExtension arbiterExtension; // TODO: remove + //ControllerExtension controllerExtension; // TODO: move to phase sc_core::sc_time timeOfGeneration; - TimeInterval timeOnDataStrobe; + TimeInterval timeOnDataStrobe; // TODO: move to phase + Thread thread; + Channel channel; struct Phase { - Phase(std::string name, const sc_core::sc_time& begin): name(std::move(name)), + Phase(std::string name, const sc_core::sc_time& begin) : name(std::move(name)), interval(begin, sc_core::SC_ZERO_TIME) {} + Phase(std::string name, const sc_core::sc_time& begin, Rank rank, BankGroup bankGroup, Bank bank, + Row row, Column column) : name(std::move(name)), interval(begin, sc_core::SC_ZERO_TIME), + rank(rank), bankGroup(bankGroup), bank(bank), row(row), column(column) {} std::string name; TimeInterval interval; + //TimeInterval intervalOnDataStrobe; + Rank rank = Rank(0); + BankGroup bankGroup = BankGroup(0); + Bank bank = Bank(0); + Row row = Row(0); + Column column = Column(0); + unsigned int burstLength = 0; }; std::vector recordedPhases; }; @@ -132,10 +146,9 @@ private: void commitRecordedDataToDB(); void insertGeneralInfo(); void insertCommandLengths(); - void insertTransactionInDB(Transaction &recordingData); + void insertTransactionInDB(const Transaction& recordingData); void insertRangeInDB(uint64_t id, const sc_core::sc_time &begin, const sc_core::sc_time &end); - void insertPhaseInDB(const std::string &phaseName, const sc_core::sc_time &begin, const sc_core::sc_time &end, - uint64_t transactionID); + void insertPhaseInDB(const Transaction::Phase& phase, uint64_t transactionID); void insertDebugMessageInDB(const std::string &message, const sc_core::sc_time &time); static constexpr unsigned transactionCommitRate = 8192; @@ -177,6 +190,12 @@ private: " PhaseName TEXT, \n" " PhaseBegin INTEGER, \n" " PhaseEnd INTEGER, \n" + " Rank INTEGER, \n" + " BankGroup INTEGER, \n" + " Bank INTEGER, \n" + " Row INTEGER, \n" + " Column INTEGER, \n" + " BurstLength INTEGER, \n" " Transact INTEGER \n" "); \n" " \n" @@ -242,14 +261,9 @@ private: " ID INTEGER, \n" " Range INTEGER, \n" " Address INTEGER, \n" - " Burstlength INTEGER, \n" - " TThread INTEGER, \n" - " TChannel INTEGER, \n" - " TRank INTEGER, \n" - " TBankgroup INTEGER, \n" - " TBank INTEGER, \n" - " TRow INTEGER, \n" - " TColumn INTEGER, \n" + " DataLength INTEGER, \n" + " Thread INTEGER, \n" + " Channel INTEGER, \n" " DataStrobeBegin INTEGER, \n" " DataStrobeEnd INTEGER, \n" " TimeOfGeneration INTEGER, \n" From 777d87c1948879c4353c8e185830ae50b645a15f Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Fri, 29 Apr 2022 11:09:35 +0200 Subject: [PATCH 06/29] Change database format (2). --- DRAMSys/library/src/common/TlmRecorder.cpp | 53 +++++++------------ DRAMSys/library/src/common/TlmRecorder.h | 27 +++++----- DRAMSys/library/src/controller/Command.cpp | 5 ++ DRAMSys/library/src/controller/Command.h | 1 + DRAMSys/library/src/controller/Controller.cpp | 9 +--- DRAMSys/library/src/controller/Controller.h | 1 - .../src/controller/ControllerRecordable.cpp | 13 ----- .../src/controller/ControllerRecordable.h | 1 - .../src/simulation/dram/DramRecordable.cpp | 14 ++++- 9 files changed, 54 insertions(+), 70 deletions(-) diff --git a/DRAMSys/library/src/common/TlmRecorder.cpp b/DRAMSys/library/src/common/TlmRecorder.cpp index 358886cb..d7739c8c 100644 --- a/DRAMSys/library/src/common/TlmRecorder.cpp +++ b/DRAMSys/library/src/common/TlmRecorder.cpp @@ -84,7 +84,6 @@ void TlmRecorder::finalize() sqlite3_finalize(insertGeneralInfoStatement); sqlite3_finalize(insertCommandLengthsStatement); sqlite3_finalize(insertDebugMessageStatement); - sqlite3_finalize(updateDataStrobeStatement); sqlite3_finalize(insertPowerStatement); sqlite3_finalize(insertBufferDepthStatement); sqlite3_finalize(insertBandwidthStatement); @@ -115,8 +114,8 @@ void TlmRecorder::recordBandwidth(double timeInSeconds, double averageBandwidth) executeSqlStatement(insertBandwidthStatement); } -void TlmRecorder::recordPhase(tlm_generic_payload &trans, - const tlm_phase &phase, const sc_time &time) +void TlmRecorder::recordPhase(tlm_generic_payload &trans, const tlm_phase &phase, const sc_time &time, + TimeInterval intervalOnDataStrobe) { if (currentTransactionsInSystem.find(&trans) == currentTransactionsInSystem.end()) introduceTransactionSystem(trans); @@ -136,8 +135,9 @@ void TlmRecorder::recordPhase(tlm_generic_payload &trans, { std::string phaseName = getPhaseName(phase).substr(6); // remove "BEGIN_" const ControllerExtension& extension = ControllerExtension::getExtension(trans); - currentTransactionsInSystem.at(&trans).recordedPhases.emplace_back(phaseName, time, extension.getRank(), - extension.getBankGroup(), extension.getBank(), extension.getRow(), extension.getColumn()); + currentTransactionsInSystem.at(&trans).recordedPhases.emplace_back(std::move(phaseName), time, + std::move(intervalOnDataStrobe), extension.getRank(), extension.getBankGroup(), extension.getBank(), + extension.getRow(), extension.getColumn(), extension.getBurstLength()); } if (currentTransactionsInSystem.at(&trans).cmd == 'X') @@ -164,16 +164,6 @@ void TlmRecorder::recordPhase(tlm_generic_payload &trans, simulationTimeCoveredByRecording = time; } - -void TlmRecorder::updateDataStrobe(const sc_time &begin, const sc_time &end, - tlm_generic_payload &trans) -{ - assert(currentTransactionsInSystem.count(&trans) != 0); - currentTransactionsInSystem.at(&trans).timeOnDataStrobe.start = begin; - currentTransactionsInSystem.at(&trans).timeOnDataStrobe.end = end; -} - - void TlmRecorder::recordDebugMessage(const std::string &message, const sc_time &time) { insertDebugMessageInDB(message, time); @@ -299,18 +289,16 @@ void TlmRecorder::prepareSqlStatements() { insertTransactionString = "INSERT INTO Transactions VALUES (:id,:rangeID,:address,:dataLength,:thread,:channel," - ":dataStrobeBegin,:dataStrobeEnd,:timeOfGeneration,:command)"; + ":timeOfGeneration,:command)"; insertRangeString = "INSERT INTO Ranges VALUES (:id,:begin,:end)"; updateRangeString = "UPDATE Ranges SET End = :end WHERE ID = :id"; - updateDataStrobeString = - "UPDATE Transactions SET DataStrobeBegin = :begin, DataStrobeEnd = :end WHERE ID = :id"; - insertPhaseString = - "INSERT INTO Phases (PhaseName,PhaseBegin,PhaseEnd,Rank,BankGroup,Bank,Row,Column,BurstLength,Transact) " - "VALUES (:name,:begin,:end,:rank,:bankGroup,:bank,:row,:column,:burstLength,:transaction)"; + "INSERT INTO Phases (PhaseName,PhaseBegin,PhaseEnd,DataStrobeBegin,DataStrobeEnd,Rank,BankGroup,Bank," + "Row,Column,BurstLength,Transact) VALUES (:name,:begin,:end,:strobeBegin,:strobeEnd,:rank,:bankGroup,:bank," + ":row,:column,:burstLength,:transaction)"; updatePhaseString = "UPDATE Phases SET PhaseEnd = :end WHERE Transact = :trans AND PhaseName = :name"; @@ -336,7 +324,6 @@ void TlmRecorder::prepareSqlStatements() sqlite3_prepare_v2(db, updateRangeString.c_str(), -1, &updateRangeStatement, nullptr); sqlite3_prepare_v2(db, insertPhaseString.c_str(), -1, &insertPhaseStatement, nullptr); sqlite3_prepare_v2(db, updatePhaseString.c_str(), -1, &updatePhaseStatement, nullptr); - sqlite3_prepare_v2(db, updateDataStrobeString.c_str(), -1, &updateDataStrobeStatement, nullptr); sqlite3_prepare_v2(db, insertGeneralInfoString.c_str(), -1, &insertGeneralInfoStatement, nullptr); sqlite3_prepare_v2(db, insertCommandLengthsString.c_str(), -1, &insertCommandLengthsStatement, nullptr); sqlite3_prepare_v2(db, insertDebugMessageString.c_str(), -1, &insertDebugMessageStatement, nullptr); @@ -428,12 +415,8 @@ void TlmRecorder::insertTransactionInDB(const Transaction &recordingData) sqlite3_bind_int(insertTransactionStatement, 6, static_cast(recordingData.channel.ID())); sqlite3_bind_int64(insertTransactionStatement, 7, - static_cast(recordingData.timeOnDataStrobe.start.value())); - sqlite3_bind_int64(insertTransactionStatement, 8, - static_cast(recordingData.timeOnDataStrobe.end.value())); - sqlite3_bind_int64(insertTransactionStatement, 9, static_cast(recordingData.timeOfGeneration.value())); - sqlite3_bind_text(insertTransactionStatement, 10, + sqlite3_bind_text(insertTransactionStatement, 8, &recordingData.cmd, 1, nullptr); executeSqlStatement(insertTransactionStatement); @@ -453,13 +436,15 @@ void TlmRecorder::insertPhaseInDB(const Transaction::Phase& phase, uint64_t tran sqlite3_bind_text(insertPhaseStatement, 1, phase.name.c_str(), static_cast(phase.name.length()), nullptr); sqlite3_bind_int64(insertPhaseStatement, 2, static_cast(phase.interval.start.value())); sqlite3_bind_int64(insertPhaseStatement, 3, static_cast(phase.interval.end.value())); - sqlite3_bind_int(insertPhaseStatement, 4, static_cast(phase.rank.ID())); - sqlite3_bind_int(insertPhaseStatement, 5, static_cast(phase.bankGroup.ID())); - sqlite3_bind_int(insertPhaseStatement, 6, static_cast(phase.bank.ID())); - sqlite3_bind_int(insertPhaseStatement, 7, static_cast(phase.row.ID())); - sqlite3_bind_int(insertPhaseStatement, 8, static_cast(phase.column.ID())); - sqlite3_bind_int(insertPhaseStatement, 9, static_cast(phase.burstLength)); - sqlite3_bind_int64(insertPhaseStatement, 10, static_cast(transactionID)); + sqlite3_bind_int64(insertPhaseStatement, 4, static_cast(phase.intervalOnDataStrobe.start.value())); + sqlite3_bind_int64(insertPhaseStatement, 5, static_cast(phase.intervalOnDataStrobe.end.value())); + sqlite3_bind_int(insertPhaseStatement, 6, static_cast(phase.rank.ID())); + sqlite3_bind_int(insertPhaseStatement, 7, static_cast(phase.bankGroup.ID())); + sqlite3_bind_int(insertPhaseStatement, 8, static_cast(phase.bank.ID())); + sqlite3_bind_int(insertPhaseStatement, 9, static_cast(phase.row.ID())); + sqlite3_bind_int(insertPhaseStatement, 10, static_cast(phase.column.ID())); + sqlite3_bind_int(insertPhaseStatement, 11, static_cast(phase.burstLength)); + sqlite3_bind_int64(insertPhaseStatement, 12, static_cast(transactionID)); executeSqlStatement(insertPhaseStatement); } diff --git a/DRAMSys/library/src/common/TlmRecorder.h b/DRAMSys/library/src/common/TlmRecorder.h index 5186a215..9f2740d0 100644 --- a/DRAMSys/library/src/common/TlmRecorder.h +++ b/DRAMSys/library/src/common/TlmRecorder.h @@ -76,13 +76,12 @@ public: traces = std::move(_traces); } - void recordPhase(tlm::tlm_generic_payload &trans, const tlm::tlm_phase &phase, const sc_core::sc_time &time); + void recordPhase(tlm::tlm_generic_payload &trans, const tlm::tlm_phase &phase, const sc_core::sc_time &time, + TimeInterval intervalOnDataStrobe = {sc_core::SC_ZERO_TIME, sc_core::SC_ZERO_TIME}); void recordPower(double timeInSeconds, double averagePower); void recordBufferDepth(double timeInSeconds, const std::vector &averageBufferDepth); void recordBandwidth(double timeInSeconds, double averageBandwidth); void recordDebugMessage(const std::string &message, const sc_core::sc_time &time); - void updateDataStrobe(const sc_core::sc_time &begin, const sc_core::sc_time &end, - tlm::tlm_generic_payload &trans); void finalize(); private: @@ -104,7 +103,7 @@ private: //ArbiterExtension arbiterExtension; // TODO: remove //ControllerExtension controllerExtension; // TODO: move to phase sc_core::sc_time timeOfGeneration; - TimeInterval timeOnDataStrobe; // TODO: move to phase + //TimeInterval timeOnDataStrobe; // TODO: move to phase Thread thread; Channel channel; @@ -112,12 +111,14 @@ private: { Phase(std::string name, const sc_core::sc_time& begin) : name(std::move(name)), interval(begin, sc_core::SC_ZERO_TIME) {} - Phase(std::string name, const sc_core::sc_time& begin, Rank rank, BankGroup bankGroup, Bank bank, - Row row, Column column) : name(std::move(name)), interval(begin, sc_core::SC_ZERO_TIME), - rank(rank), bankGroup(bankGroup), bank(bank), row(row), column(column) {} + Phase(std::string name, const sc_core::sc_time& begin, TimeInterval intervalOnDataStrobe, Rank rank, + BankGroup bankGroup, Bank bank, Row row, Column column, unsigned int burstLength) : + name(std::move(name)), interval(begin, sc_core::SC_ZERO_TIME), + intervalOnDataStrobe(std::move(intervalOnDataStrobe)), rank(rank), bankGroup(bankGroup), bank(bank), + row(row), column(column), burstLength(burstLength) {} std::string name; TimeInterval interval; - //TimeInterval intervalOnDataStrobe; + TimeInterval intervalOnDataStrobe = {sc_core::SC_ZERO_TIME, sc_core::SC_ZERO_TIME}; Rank rank = Rank(0); BankGroup bankGroup = BankGroup(0); Bank bank = Bank(0); @@ -166,11 +167,11 @@ private: sqlite3_stmt *insertTransactionStatement = nullptr, *insertRangeStatement = nullptr, *updateRangeStatement = nullptr, *insertPhaseStatement = nullptr, *updatePhaseStatement = nullptr, *insertGeneralInfoStatement = nullptr, *insertCommandLengthsStatement = nullptr, - *insertDebugMessageStatement = nullptr, *updateDataStrobeStatement = nullptr, - *insertPowerStatement = nullptr, *insertBufferDepthStatement = nullptr, *insertBandwidthStatement = nullptr; + *insertDebugMessageStatement = nullptr, *insertPowerStatement = nullptr, + *insertBufferDepthStatement = nullptr, *insertBandwidthStatement = nullptr; std::string insertTransactionString, insertRangeString, updateRangeString, insertPhaseString, updatePhaseString, insertGeneralInfoString, insertCommandLengthsString, - insertDebugMessageString, updateDataStrobeString, insertPowerString, + insertDebugMessageString, insertPowerString, insertBufferDepthString, insertBandwidthString; std::string initialCommand = @@ -190,6 +191,8 @@ private: " PhaseName TEXT, \n" " PhaseBegin INTEGER, \n" " PhaseEnd INTEGER, \n" + " DataStrobeBegin INTEGER, \n" + " DataStrobeEnd INTEGER, \n" " Rank INTEGER, \n" " BankGroup INTEGER, \n" " Bank INTEGER, \n" @@ -264,8 +267,6 @@ private: " DataLength INTEGER, \n" " Thread INTEGER, \n" " Channel INTEGER, \n" - " DataStrobeBegin INTEGER, \n" - " DataStrobeEnd INTEGER, \n" " TimeOfGeneration INTEGER, \n" " Command TEXT \n" "); \n" diff --git a/DRAMSys/library/src/controller/Command.cpp b/DRAMSys/library/src/controller/Command.cpp index 42d1121b..1fb8f81e 100644 --- a/DRAMSys/library/src/controller/Command.cpp +++ b/DRAMSys/library/src/controller/Command.cpp @@ -183,6 +183,11 @@ bool phaseNeedsEnd(tlm_phase phase) return (phase >= BEGIN_NOP && phase <= BEGIN_RFMAB); } +bool phaseHasDataStrobe(tlm_phase phase) +{ + return (phase >= BEGIN_RD && phase <= BEGIN_WRA); +} + tlm_phase getEndPhase(tlm_phase phase) { assert(phase >= BEGIN_NOP && phase <= BEGIN_RFMAB); diff --git a/DRAMSys/library/src/controller/Command.h b/DRAMSys/library/src/controller/Command.h index c84f82ff..322a7a58 100644 --- a/DRAMSys/library/src/controller/Command.h +++ b/DRAMSys/library/src/controller/Command.h @@ -152,6 +152,7 @@ public: DRAMPower::MemCommand::cmds phaseToDRAMPowerCommand(tlm::tlm_phase); bool phaseNeedsEnd(tlm::tlm_phase); +bool phaseHasDataStrobe(tlm::tlm_phase); tlm::tlm_phase getEndPhase(tlm::tlm_phase); struct CommandTuple diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index 4a410ebd..990958bd 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -329,7 +329,8 @@ void Controller::controllerMethod() powerDownManagers[rank.ID()]->triggerEntry(); sc_time fwDelay = thinkDelayFw + phyDelayFw; - sendToDram(command, *payload, fwDelay); + tlm_phase phase = command.toPhase(); + iSocket->nb_transport_fw(*payload, phase, fwDelay); } else readyCmdBlocked = true; @@ -518,9 +519,3 @@ void Controller::sendToFrontend(tlm_generic_payload& payload, tlm_phase& phase, { tSocket->nb_transport_bw(payload, phase, delay); } - -void Controller::sendToDram(Command command, tlm_generic_payload& payload, sc_time& delay) -{ - tlm_phase phase = command.toPhase(); - iSocket->nb_transport_fw(payload, phase, delay); -} diff --git a/DRAMSys/library/src/controller/Controller.h b/DRAMSys/library/src/controller/Controller.h index 16e3d521..e8339bc7 100644 --- a/DRAMSys/library/src/controller/Controller.h +++ b/DRAMSys/library/src/controller/Controller.h @@ -64,7 +64,6 @@ protected: unsigned int transport_dbg(tlm::tlm_generic_payload& trans) override; virtual void sendToFrontend(tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_core::sc_time& delay); - virtual void sendToDram(Command, tlm::tlm_generic_payload& trans, sc_core::sc_time& delay); virtual void controllerMethod(); diff --git a/DRAMSys/library/src/controller/ControllerRecordable.cpp b/DRAMSys/library/src/controller/ControllerRecordable.cpp index 6c188b71..8e1efdc8 100644 --- a/DRAMSys/library/src/controller/ControllerRecordable.cpp +++ b/DRAMSys/library/src/controller/ControllerRecordable.cpp @@ -77,19 +77,6 @@ void ControllerRecordable::sendToFrontend(tlm_generic_payload& payload, tlm_phas tSocket->nb_transport_bw(payload, phase, delay); } -void ControllerRecordable::sendToDram(Command command, tlm_generic_payload& payload, sc_time& delay) -{ - if (command.isCasCommand()) - { - TimeInterval dataStrobe = memSpec.getIntervalOnDataStrobe(command, payload); - tlmRecorder.updateDataStrobe(sc_time_stamp() + delay + dataStrobe.start, - sc_time_stamp() + delay + dataStrobe.end, payload); - } - tlm_phase phase = command.toPhase(); - - iSocket->nb_transport_fw(payload, phase, delay); -} - void ControllerRecordable::recordPhase(tlm_generic_payload &trans, const tlm_phase &phase, const sc_time &delay) { sc_time recTime = delay + sc_time_stamp(); diff --git a/DRAMSys/library/src/controller/ControllerRecordable.h b/DRAMSys/library/src/controller/ControllerRecordable.h index ef4d69fd..9cd0f7a2 100644 --- a/DRAMSys/library/src/controller/ControllerRecordable.h +++ b/DRAMSys/library/src/controller/ControllerRecordable.h @@ -54,7 +54,6 @@ protected: sc_core::sc_time &delay) override; void sendToFrontend(tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_core::sc_time& delay) override; - void sendToDram(Command command, tlm::tlm_generic_payload& trans, sc_core::sc_time& delay) override; void controllerMethod() override; diff --git a/DRAMSys/library/src/simulation/dram/DramRecordable.cpp b/DRAMSys/library/src/simulation/dram/DramRecordable.cpp index a64e71c4..117ef679 100644 --- a/DRAMSys/library/src/simulation/dram/DramRecordable.cpp +++ b/DRAMSys/library/src/simulation/dram/DramRecordable.cpp @@ -105,7 +105,19 @@ void DramRecordable::recordPhase(tlm_generic_payload &trans, const tlm bg) + " bank " + std::to_string(bank) + " row " + std::to_string(row) + " column " + std::to_string(col) + " at " + recTime.to_string()); - tlmRecorder.recordPhase(trans, phase, recTime); + Command command(phase); + + if (phaseHasDataStrobe(phase)) + { + TimeInterval intervalOnDataStrobe = this->memSpec.getIntervalOnDataStrobe(command, trans); + intervalOnDataStrobe.start = intervalOnDataStrobe.start + recTime; + intervalOnDataStrobe.end = intervalOnDataStrobe.end + recTime; + tlmRecorder.recordPhase(trans, phase, recTime, std::move(intervalOnDataStrobe)); + } + else + { + tlmRecorder.recordPhase(trans, phase, recTime); + } if (phaseNeedsEnd(phase)) { From 26d7e3e83eb298aab52c27fd3143cca28c04c2aa Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Mon, 2 May 2022 11:33:08 +0200 Subject: [PATCH 07/29] Simplify recording. --- DRAMSys/library/src/common/TlmRecorder.cpp | 63 +++++++++++++------ DRAMSys/library/src/common/TlmRecorder.h | 14 ++--- .../src/controller/ControllerRecordable.cpp | 28 +-------- .../src/controller/ControllerRecordable.h | 1 - .../src/simulation/dram/DramRecordable.cpp | 47 +------------- .../src/simulation/dram/DramRecordable.h | 2 - 6 files changed, 53 insertions(+), 102 deletions(-) diff --git a/DRAMSys/library/src/common/TlmRecorder.cpp b/DRAMSys/library/src/common/TlmRecorder.cpp index d7739c8c..3fc98de5 100644 --- a/DRAMSys/library/src/common/TlmRecorder.cpp +++ b/DRAMSys/library/src/common/TlmRecorder.cpp @@ -50,7 +50,8 @@ using namespace sc_core; using namespace tlm; TlmRecorder::TlmRecorder(const std::string& name, const Configuration& config, const std::string& dbName) : - name(name), config(config), totalNumTransactions(0), simulationTimeCoveredByRecording(SC_ZERO_TIME) + name(name), config(config), memSpec(*config.memSpec), totalNumTransactions(0), + simulationTimeCoveredByRecording(SC_ZERO_TIME) { currentDataBuffer = &recordingDataBuffer[0]; storageDataBuffer = &recordingDataBuffer[1]; @@ -114,9 +115,10 @@ void TlmRecorder::recordBandwidth(double timeInSeconds, double averageBandwidth) executeSqlStatement(insertBandwidthStatement); } -void TlmRecorder::recordPhase(tlm_generic_payload &trans, const tlm_phase &phase, const sc_time &time, - TimeInterval intervalOnDataStrobe) +void TlmRecorder::recordPhase(tlm_generic_payload& trans, const tlm_phase& phase, const sc_time& delay) { + const sc_time& currentTime = sc_time_stamp(); + if (currentTransactionsInSystem.find(&trans) == currentTransactionsInSystem.end()) introduceTransactionSystem(trans); @@ -124,32 +126,55 @@ void TlmRecorder::recordPhase(tlm_generic_payload &trans, const tlm_phase &phase { assert(getPhaseName(phase).substr(4) == currentTransactionsInSystem.at(&trans).recordedPhases.back().name); // TODO: this assumes that the controller does not start with a transaction until END_REQ has been sent, which is not true any more for big transactions - currentTransactionsInSystem.at(&trans).recordedPhases.back().interval.end = time; + if (phase == END_PDNA || phase == END_PDNP || phase == END_SREF) + currentTransactionsInSystem.at(&trans).recordedPhases.back().interval.end = currentTime + delay + + memSpec.getCommandLength(Command(phase)); + else + currentTransactionsInSystem.at(&trans).recordedPhases.back().interval.end = currentTime + delay; } else if (phase == BEGIN_REQ || phase == BEGIN_RESP) { std::string phaseName = getPhaseName(phase).substr(6); - currentTransactionsInSystem.at(&trans).recordedPhases.emplace_back(phaseName, time); + currentTransactionsInSystem.at(&trans).recordedPhases.emplace_back(phaseName, currentTime + delay); + } + else if (phase == BEGIN_PDNA || phase == BEGIN_PDNP || phase == BEGIN_SREF) + { + std::string phaseName = getPhaseName(phase).substr(6); // remove "BEGIN_" + const ControllerExtension& extension = ControllerExtension::getExtension(trans); + currentTransactionsInSystem.at(&trans).recordedPhases.emplace_back(std::move(phaseName), + std::move(TimeInterval(currentTime + delay, SC_ZERO_TIME)), + std::move(TimeInterval(SC_ZERO_TIME, SC_ZERO_TIME)), + extension.getRank(), extension.getBankGroup(), extension.getBank(), + extension.getRow(), extension.getColumn(), extension.getBurstLength()); } else { std::string phaseName = getPhaseName(phase).substr(6); // remove "BEGIN_" const ControllerExtension& extension = ControllerExtension::getExtension(trans); - currentTransactionsInSystem.at(&trans).recordedPhases.emplace_back(std::move(phaseName), time, + TimeInterval intervalOnDataStrobe; + if (phaseHasDataStrobe(phase)) + { + intervalOnDataStrobe = memSpec.getIntervalOnDataStrobe(Command(phase), trans); + intervalOnDataStrobe.start = currentTime + intervalOnDataStrobe.start; + intervalOnDataStrobe.end = currentTime + intervalOnDataStrobe.end; + } + + currentTransactionsInSystem.at(&trans).recordedPhases.emplace_back(std::move(phaseName), + std::move(TimeInterval(currentTime + delay, currentTime + delay + memSpec.getExecutionTime(Command(phase), trans))), std::move(intervalOnDataStrobe), extension.getRank(), extension.getBankGroup(), extension.getBank(), extension.getRow(), extension.getColumn(), extension.getBurstLength()); } if (currentTransactionsInSystem.at(&trans).cmd == 'X') { - if (phase == END_REFAB - || phase == END_RFMAB - || phase == END_REFPB - || phase == END_RFMPB - || phase == END_REFP2B - || phase == END_RFMP2B - || phase == END_REFSB - || phase == END_RFMSB + if (phase == BEGIN_REFAB + || phase == BEGIN_RFMAB + || phase == BEGIN_REFPB + || phase == BEGIN_RFMPB + || phase == BEGIN_REFP2B + || phase == BEGIN_RFMP2B + || phase == BEGIN_REFSB + || phase == BEGIN_RFMSB || phase == END_PDNA || phase == END_PDNP || phase == END_SREF) @@ -161,7 +186,7 @@ void TlmRecorder::recordPhase(tlm_generic_payload &trans, const tlm_phase &phase removeTransactionFromSystem(trans); } - simulationTimeCoveredByRecording = time; + simulationTimeCoveredByRecording = currentTime + delay; } void TlmRecorder::recordDebugMessage(const std::string &message, const sc_time &time) @@ -230,16 +255,16 @@ void TlmRecorder::terminateRemainingTransactions() { std::string beginPhase = transaction->second.recordedPhases.front().name; if (beginPhase == "PDNA") - recordPhase(*(transaction->first), END_PDNA, sc_time_stamp()); + recordPhase(*(transaction->first), END_PDNA, SC_ZERO_TIME); else if (beginPhase == "PDNP") - recordPhase(*(transaction->first), END_PDNP, sc_time_stamp()); + recordPhase(*(transaction->first), END_PDNP, SC_ZERO_TIME); else if (beginPhase == "SREF") - recordPhase(*(transaction->first), END_SREF, sc_time_stamp()); + recordPhase(*(transaction->first), END_SREF, SC_ZERO_TIME); else removeTransactionFromSystem(*transaction->first); } else - recordPhase(*(transaction->first), END_RESP, sc_time_stamp()); + recordPhase(*(transaction->first), END_RESP, SC_ZERO_TIME); } } diff --git a/DRAMSys/library/src/common/TlmRecorder.h b/DRAMSys/library/src/common/TlmRecorder.h index 9f2740d0..70664e63 100644 --- a/DRAMSys/library/src/common/TlmRecorder.h +++ b/DRAMSys/library/src/common/TlmRecorder.h @@ -76,8 +76,7 @@ public: traces = std::move(_traces); } - void recordPhase(tlm::tlm_generic_payload &trans, const tlm::tlm_phase &phase, const sc_core::sc_time &time, - TimeInterval intervalOnDataStrobe = {sc_core::SC_ZERO_TIME, sc_core::SC_ZERO_TIME}); + void recordPhase(tlm::tlm_generic_payload& trans, const tlm::tlm_phase& phase, const sc_core::sc_time& delay); void recordPower(double timeInSeconds, double averagePower); void recordBufferDepth(double timeInSeconds, const std::vector &averageBufferDepth); void recordBandwidth(double timeInSeconds, double averageBandwidth); @@ -86,10 +85,10 @@ public: private: const Configuration& config; + const MemSpec& memSpec; struct Transaction { - //Transaction() = default; Transaction(uint64_t id, uint64_t address, unsigned int dataLength, char cmd, const sc_core::sc_time& timeOfGeneration, Thread thread, Channel channel) : id(id), address(address), dataLength(dataLength), cmd(cmd), timeOfGeneration(timeOfGeneration), @@ -98,22 +97,19 @@ private: uint64_t id = 0; uint64_t address = 0; unsigned int dataLength = 0; - //unsigned int burstLength = 0; // TODO: move to phase char cmd = 'X'; - //ArbiterExtension arbiterExtension; // TODO: remove - //ControllerExtension controllerExtension; // TODO: move to phase sc_core::sc_time timeOfGeneration; - //TimeInterval timeOnDataStrobe; // TODO: move to phase Thread thread; Channel channel; struct Phase { + // for BEGIN_REQ and BEGIN_RESP Phase(std::string name, const sc_core::sc_time& begin) : name(std::move(name)), interval(begin, sc_core::SC_ZERO_TIME) {} - Phase(std::string name, const sc_core::sc_time& begin, TimeInterval intervalOnDataStrobe, Rank rank, + Phase(std::string name, TimeInterval interval, TimeInterval intervalOnDataStrobe, Rank rank, BankGroup bankGroup, Bank bank, Row row, Column column, unsigned int burstLength) : - name(std::move(name)), interval(begin, sc_core::SC_ZERO_TIME), + name(std::move(name)), interval(std::move(interval)), intervalOnDataStrobe(std::move(intervalOnDataStrobe)), rank(rank), bankGroup(bankGroup), bank(bank), row(row), column(column), burstLength(burstLength) {} std::string name; diff --git a/DRAMSys/library/src/controller/ControllerRecordable.cpp b/DRAMSys/library/src/controller/ControllerRecordable.cpp index 8e1efdc8..da6a0d0b 100644 --- a/DRAMSys/library/src/controller/ControllerRecordable.cpp +++ b/DRAMSys/library/src/controller/ControllerRecordable.cpp @@ -58,10 +58,8 @@ ControllerRecordable::ControllerRecordable(const sc_module_name &name, const Con tlm_sync_enum ControllerRecordable::nb_transport_fw(tlm_generic_payload &trans, tlm_phase &phase, sc_time &delay) { - // Important: delay must not be increased by nb_transport_fw - tlm_sync_enum returnValue = Controller::nb_transport_fw(trans, phase, delay); - recordPhase(trans, phase, delay); - return returnValue; + tlmRecorder.recordPhase(trans, phase, delay); + return Controller::nb_transport_fw(trans, phase, delay); } tlm_sync_enum ControllerRecordable::nb_transport_bw(tlm_generic_payload &, @@ -73,30 +71,10 @@ tlm_sync_enum ControllerRecordable::nb_transport_bw(tlm_generic_payload &, void ControllerRecordable::sendToFrontend(tlm_generic_payload& payload, tlm_phase& phase, sc_time& delay) { - recordPhase(payload, phase, delay); + tlmRecorder.recordPhase(payload, phase, delay); tSocket->nb_transport_bw(payload, phase, delay); } -void ControllerRecordable::recordPhase(tlm_generic_payload &trans, const tlm_phase &phase, const sc_time &delay) -{ - sc_time recTime = delay + sc_time_stamp(); - - NDEBUG_UNUSED(unsigned thr) = ArbiterExtension::getExtension(trans).getThread().ID(); - NDEBUG_UNUSED(unsigned ch) = ArbiterExtension::getExtension(trans).getChannel().ID(); - NDEBUG_UNUSED(unsigned bg) = ControllerExtension::getExtension(trans).getBankGroup().ID(); - NDEBUG_UNUSED(unsigned bank) = ControllerExtension::getExtension(trans).getBank().ID(); - NDEBUG_UNUSED(unsigned row) = ControllerExtension::getExtension(trans).getRow().ID(); - NDEBUG_UNUSED(unsigned col) = ControllerExtension::getExtension(trans).getColumn().ID(); - NDEBUG_UNUSED(uint64_t id) = ControllerExtension::getExtension(trans).getChannelPayloadID(); - - PRINTDEBUGMESSAGE(name(), "Recording " + getPhaseName(phase) + " thread " + - std::to_string(thr) + " channel " + std::to_string(ch) + " bank group " + std::to_string( - bg) + " bank " + std::to_string(bank) + " row " + std::to_string(row) + " column " + - std::to_string(col) + " id " + std::to_string(id) + " at " + recTime.to_string()); - - tlmRecorder.recordPhase(trans, phase, recTime); -} - void ControllerRecordable::controllerMethod() { if (enableWindowing) diff --git a/DRAMSys/library/src/controller/ControllerRecordable.h b/DRAMSys/library/src/controller/ControllerRecordable.h index 9cd0f7a2..8594fb23 100644 --- a/DRAMSys/library/src/controller/ControllerRecordable.h +++ b/DRAMSys/library/src/controller/ControllerRecordable.h @@ -58,7 +58,6 @@ protected: void controllerMethod() override; private: - void recordPhase(tlm::tlm_generic_payload &trans, const tlm::tlm_phase &phase, const sc_core::sc_time &delay); TlmRecorder& tlmRecorder; sc_core::sc_event windowEvent; diff --git a/DRAMSys/library/src/simulation/dram/DramRecordable.cpp b/DRAMSys/library/src/simulation/dram/DramRecordable.cpp index 117ef679..c4abfb96 100644 --- a/DRAMSys/library/src/simulation/dram/DramRecordable.cpp +++ b/DRAMSys/library/src/simulation/dram/DramRecordable.cpp @@ -79,55 +79,10 @@ template tlm_sync_enum DramRecordable::nb_transport_fw(tlm_generic_payload &payload, tlm_phase &phase, sc_time &delay) { - recordPhase(payload, phase, delay); + tlmRecorder.recordPhase(payload, phase, delay); return BaseDram::nb_transport_fw(payload, phase, delay); } -template -void DramRecordable::recordPhase(tlm_generic_payload &trans, const tlm_phase &phase, const sc_time &delay) -{ - sc_time recTime = sc_time_stamp() + delay; - - // These are terminating phases recorded by the DRAM. The execution - // time of the related command must be taken into consideration. - if (phase == END_PDNA || phase == END_PDNP || phase == END_SREF) - recTime += this->memSpec.getCommandLength(Command(phase)); - - NDEBUG_UNUSED(unsigned thr) = ArbiterExtension::getExtension(trans).getThread().ID(); - NDEBUG_UNUSED(unsigned ch) = ArbiterExtension::getExtension(trans).getChannel().ID(); - NDEBUG_UNUSED(unsigned bg) = ControllerExtension::getExtension(trans).getBankGroup().ID(); - NDEBUG_UNUSED(unsigned bank) = ControllerExtension::getExtension(trans).getBank().ID(); - NDEBUG_UNUSED(unsigned row) = ControllerExtension::getExtension(trans).getRow().ID(); - NDEBUG_UNUSED(unsigned col) = ControllerExtension::getExtension(trans).getColumn().ID(); - - PRINTDEBUGMESSAGE(this->name(), "Recording " + getPhaseName(phase) + " thread " + - std::to_string(thr) + " channel " + std::to_string(ch) + " bank group " + std::to_string( - bg) + " bank " + std::to_string(bank) + " row " + std::to_string(row) + " column " + - std::to_string(col) + " at " + recTime.to_string()); - - Command command(phase); - - if (phaseHasDataStrobe(phase)) - { - TimeInterval intervalOnDataStrobe = this->memSpec.getIntervalOnDataStrobe(command, trans); - intervalOnDataStrobe.start = intervalOnDataStrobe.start + recTime; - intervalOnDataStrobe.end = intervalOnDataStrobe.end + recTime; - tlmRecorder.recordPhase(trans, phase, recTime, std::move(intervalOnDataStrobe)); - } - else - { - tlmRecorder.recordPhase(trans, phase, recTime); - } - - if (phaseNeedsEnd(phase)) - { - recTime += this->memSpec.getExecutionTime(Command(phase), trans); - tlmRecorder.recordPhase(trans, getEndPhase(phase), recTime); - } - -} - - // This Thread is only triggered when Power Simulation is enabled. // It estimates the current average power which will be stored in the trace database for visualization purposes. template diff --git a/DRAMSys/library/src/simulation/dram/DramRecordable.h b/DRAMSys/library/src/simulation/dram/DramRecordable.h index 2dbc46d6..e7d78482 100644 --- a/DRAMSys/library/src/simulation/dram/DramRecordable.h +++ b/DRAMSys/library/src/simulation/dram/DramRecordable.h @@ -57,8 +57,6 @@ private: tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload, tlm::tlm_phase &phase, sc_core::sc_time &delay) override; - void recordPhase(tlm::tlm_generic_payload &trans, const tlm::tlm_phase &phase, const sc_core::sc_time &delay); - TlmRecorder& tlmRecorder; sc_core::sc_time powerWindowSize; From 489fa5f02b3df3edb8be8529d265be554cbb7212 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Mon, 2 May 2022 14:24:18 +0200 Subject: [PATCH 08/29] Remove unused END phases. --- DRAMSys/library/src/common/TlmRecorder.cpp | 66 ++++----- DRAMSys/library/src/controller/Command.cpp | 154 +++++++++++---------- DRAMSys/library/src/controller/Command.h | 29 +--- 3 files changed, 114 insertions(+), 135 deletions(-) diff --git a/DRAMSys/library/src/common/TlmRecorder.cpp b/DRAMSys/library/src/common/TlmRecorder.cpp index 3fc98de5..0d30e623 100644 --- a/DRAMSys/library/src/common/TlmRecorder.cpp +++ b/DRAMSys/library/src/common/TlmRecorder.cpp @@ -122,32 +122,18 @@ void TlmRecorder::recordPhase(tlm_generic_payload& trans, const tlm_phase& phase if (currentTransactionsInSystem.find(&trans) == currentTransactionsInSystem.end()) introduceTransactionSystem(trans); - if (phase == END_REQ || phase == END_RESP || phase >= END_PDNA) - { - assert(getPhaseName(phase).substr(4) == currentTransactionsInSystem.at(&trans).recordedPhases.back().name); - // TODO: this assumes that the controller does not start with a transaction until END_REQ has been sent, which is not true any more for big transactions - if (phase == END_PDNA || phase == END_PDNP || phase == END_SREF) - currentTransactionsInSystem.at(&trans).recordedPhases.back().interval.end = currentTime + delay - + memSpec.getCommandLength(Command(phase)); - else - currentTransactionsInSystem.at(&trans).recordedPhases.back().interval.end = currentTime + delay; - } - else if (phase == BEGIN_REQ || phase == BEGIN_RESP) + if (phase == BEGIN_REQ || phase == BEGIN_RESP) { std::string phaseName = getPhaseName(phase).substr(6); currentTransactionsInSystem.at(&trans).recordedPhases.emplace_back(phaseName, currentTime + delay); } - else if (phase == BEGIN_PDNA || phase == BEGIN_PDNP || phase == BEGIN_SREF) + else if (phase == END_REQ || phase == END_RESP) { - std::string phaseName = getPhaseName(phase).substr(6); // remove "BEGIN_" - const ControllerExtension& extension = ControllerExtension::getExtension(trans); - currentTransactionsInSystem.at(&trans).recordedPhases.emplace_back(std::move(phaseName), - std::move(TimeInterval(currentTime + delay, SC_ZERO_TIME)), - std::move(TimeInterval(SC_ZERO_TIME, SC_ZERO_TIME)), - extension.getRank(), extension.getBankGroup(), extension.getBank(), - extension.getRow(), extension.getColumn(), extension.getBurstLength()); + assert(getPhaseName(phase).substr(4) == currentTransactionsInSystem.at(&trans).recordedPhases.back().name); + // TODO: this assumes that the controller does not start with a transaction until END_REQ has been sent, which is not true any more for big transactions + currentTransactionsInSystem.at(&trans).recordedPhases.back().interval.end = currentTime + delay; } - else + else if (isFixedCommandPhase(phase)) { std::string phaseName = getPhaseName(phase).substr(6); // remove "BEGIN_" const ControllerExtension& extension = ControllerExtension::getExtension(trans); @@ -160,31 +146,29 @@ void TlmRecorder::recordPhase(tlm_generic_payload& trans, const tlm_phase& phase } currentTransactionsInSystem.at(&trans).recordedPhases.emplace_back(std::move(phaseName), - std::move(TimeInterval(currentTime + delay, currentTime + delay + memSpec.getExecutionTime(Command(phase), trans))), + std::move(TimeInterval(currentTime + delay, + currentTime + delay + memSpec.getExecutionTime(Command(phase), trans))), std::move(intervalOnDataStrobe), extension.getRank(), extension.getBankGroup(), extension.getBank(), extension.getRow(), extension.getColumn(), extension.getBurstLength()); } + else if (isPowerDownEntryPhase(phase)) + { + std::string phaseName = getPhaseName(phase).substr(6); // remove "BEGIN_" + const ControllerExtension& extension = ControllerExtension::getExtension(trans); + currentTransactionsInSystem.at(&trans).recordedPhases.emplace_back(std::move(phaseName), + std::move(TimeInterval(currentTime + delay, SC_ZERO_TIME)), + std::move(TimeInterval(SC_ZERO_TIME, SC_ZERO_TIME)), + extension.getRank(), extension.getBankGroup(), extension.getBank(), + extension.getRow(), extension.getColumn(), extension.getBurstLength()); + } + else if (isPowerDownExitPhase(phase)) + { + currentTransactionsInSystem.at(&trans).recordedPhases.back().interval.end = currentTime + delay + + memSpec.getCommandLength(Command(phase)); + } - if (currentTransactionsInSystem.at(&trans).cmd == 'X') - { - if (phase == BEGIN_REFAB - || phase == BEGIN_RFMAB - || phase == BEGIN_REFPB - || phase == BEGIN_RFMPB - || phase == BEGIN_REFP2B - || phase == BEGIN_RFMP2B - || phase == BEGIN_REFSB - || phase == BEGIN_RFMSB - || phase == END_PDNA - || phase == END_PDNP - || phase == END_SREF) - removeTransactionFromSystem(trans); - } - else - { - if (phase == END_RESP) - removeTransactionFromSystem(trans); - } + if (phase == END_RESP || isRefreshCommandPhase(phase) || isPowerDownExitPhase(phase)) + removeTransactionFromSystem(trans); simulationTimeCoveredByRecording = currentTime + delay; } diff --git a/DRAMSys/library/src/controller/Command.cpp b/DRAMSys/library/src/controller/Command.cpp index 1fb8f81e..04de89b1 100644 --- a/DRAMSys/library/src/controller/Command.cpp +++ b/DRAMSys/library/src/controller/Command.cpp @@ -42,6 +42,65 @@ using namespace tlm; using namespace DRAMPower; +MemCommand::cmds phaseToDRAMPowerCommand(tlm_phase phase) +{ + // TODO: add correct phases when DRAMPower supports DDR5 same bank refresh + assert(phase >= BEGIN_NOP && phase <= END_SREF); + static std::array phaseOfCommand = + { + MemCommand::NOP, // 0 + MemCommand::RD, // 1 + MemCommand::WR, // 2 + MemCommand::RDA, // 3 + MemCommand::WRA, // 4 + MemCommand::ACT, // 5 + MemCommand::PRE, // 6, PREPB + MemCommand::REFB, // 7, REFPB + MemCommand::NOP, // 8, RFMPB + MemCommand::NOP, // 9, REFP2B + MemCommand::NOP, // 10, RFMP2B + MemCommand::NOP, // 11, PRESB + MemCommand::NOP, // 12, REFSB + MemCommand::NOP, // 13, RFMSB + MemCommand::PREA, // 14, PREAB + MemCommand::REF, // 15, REFAB + MemCommand::NOP, // 16, RFMAB + MemCommand::PDN_S_ACT, // 17 + MemCommand::PDN_S_PRE, // 18 + MemCommand::SREN, // 19 + MemCommand::PUP_ACT, // 20 + MemCommand::PUP_PRE, // 21 + MemCommand::SREX // 22 + }; + return phaseOfCommand[phase - BEGIN_NOP]; +} + +bool phaseHasDataStrobe(tlm::tlm_phase phase) +{ + return (phase >= BEGIN_RD && phase <= BEGIN_WRA); +} + +bool isPowerDownEntryPhase(tlm::tlm_phase phase) +{ + return (phase >= BEGIN_PDNA && phase <= BEGIN_SREF); +} + +bool isPowerDownExitPhase(tlm::tlm_phase phase) +{ + return (phase >= END_PDNA && phase <= END_SREF); +} + +bool isFixedCommandPhase(tlm::tlm_phase phase) +{ + return (phase >= BEGIN_NOP && phase <= BEGIN_RFMAB); +} + +bool isRefreshCommandPhase(tlm::tlm_phase phase) +{ + return (phase == BEGIN_REFPB || phase == BEGIN_REFP2B || phase == BEGIN_REFSB || phase == BEGIN_REFAB + || phase == BEGIN_RFMPB || phase == BEGIN_RFMP2B || phase == BEGIN_RFMSB || phase == BEGIN_RFMAB); +} + Command::Command(Command::Type type) : type(type) {} Command::Command(tlm_phase phase) @@ -118,82 +177,33 @@ tlm_phase Command::toPhase() const assert(type >= Command::NOP && type <= Command::SREFEX); static std::array phaseOfCommand = { - BEGIN_NOP, // 0 - BEGIN_RD, // 1 - BEGIN_WR, // 2 - BEGIN_RDA, // 3 - BEGIN_WRA, // 4 - BEGIN_ACT, // 5 - BEGIN_PREPB, // 6 - BEGIN_REFPB, // 7 - BEGIN_RFMPB, // 8 - BEGIN_REFP2B, // 9 - BEGIN_RFMP2B, // 10 - BEGIN_PRESB, // 11 - BEGIN_REFSB, // 12 - BEGIN_RFMSB, // 13 - BEGIN_PREAB, // 14 - BEGIN_REFAB, // 15 - BEGIN_RFMAB, // 16 - BEGIN_PDNA, // 17 - BEGIN_PDNP, // 18 - BEGIN_SREF, // 19 - END_PDNA, // 20 - END_PDNP, // 21 - END_SREF // 22 + BEGIN_NOP, // 0 + BEGIN_RD, // 1 + BEGIN_WR, // 2 + BEGIN_RDA, // 3 + BEGIN_WRA, // 4 + BEGIN_ACT, // 5 + BEGIN_PREPB, // 6 + BEGIN_REFPB, // 7 + BEGIN_RFMPB, // 8 + BEGIN_REFP2B, // 9 + BEGIN_RFMP2B, // 10 + BEGIN_PRESB, // 11 + BEGIN_REFSB, // 12 + BEGIN_RFMSB, // 13 + BEGIN_PREAB, // 14 + BEGIN_REFAB, // 15 + BEGIN_RFMAB, // 16 + BEGIN_PDNA, // 17 + BEGIN_PDNP, // 18 + BEGIN_SREF, // 19 + END_PDNA, // 20 + END_PDNP, // 21 + END_SREF // 22 }; return phaseOfCommand[type]; } -MemCommand::cmds phaseToDRAMPowerCommand(tlm_phase phase) -{ - // TODO: add correct phases when DRAMPower supports DDR5 same bank refresh - assert(phase >= BEGIN_NOP && phase <= END_SREF); - static std::array phaseOfCommand = - { - MemCommand::NOP, // 0 - MemCommand::RD, // 1 - MemCommand::WR, // 2 - MemCommand::RDA, // 3 - MemCommand::WRA, // 4 - MemCommand::ACT, // 5 - MemCommand::PRE, // 6, PREPB - MemCommand::REFB, // 7, REFPB - MemCommand::NOP, // 8, RFMPB - MemCommand::NOP, // 9, REFP2B - MemCommand::NOP, // 10, RFMP2B - MemCommand::NOP, // 11, PRESB - MemCommand::NOP, // 12, REFSB - MemCommand::NOP, // 13, RFMSB - MemCommand::PREA, // 14, PREAB - MemCommand::REF, // 15, REFAB - MemCommand::NOP, // 16, RFMAB - MemCommand::PDN_S_ACT, // 17 - MemCommand::PDN_S_PRE, // 18 - MemCommand::SREN, // 19 - MemCommand::PUP_ACT, // 20 - MemCommand::PUP_PRE, // 21 - MemCommand::SREX // 22 - }; - return phaseOfCommand[phase - BEGIN_NOP]; -} - -bool phaseNeedsEnd(tlm_phase phase) -{ - return (phase >= BEGIN_NOP && phase <= BEGIN_RFMAB); -} - -bool phaseHasDataStrobe(tlm_phase phase) -{ - return (phase >= BEGIN_RD && phase <= BEGIN_WRA); -} - -tlm_phase getEndPhase(tlm_phase phase) -{ - assert(phase >= BEGIN_NOP && phase <= BEGIN_RFMAB); - return (phase + Command::Type::END_ENUM); -} - bool Command::isBankCommand() const { assert(type >= Command::NOP && type <= Command::SREFEX); diff --git a/DRAMSys/library/src/controller/Command.h b/DRAMSys/library/src/controller/Command.h index 322a7a58..fe3a19bd 100644 --- a/DRAMSys/library/src/controller/Command.h +++ b/DRAMSys/library/src/controller/Command.h @@ -69,6 +69,7 @@ DECLARE_EXTENDED_PHASE(BEGIN_RFMSB); // 18 DECLARE_EXTENDED_PHASE(BEGIN_PREAB); // 19 DECLARE_EXTENDED_PHASE(BEGIN_REFAB); // 20 DECLARE_EXTENDED_PHASE(BEGIN_RFMAB); // 21 + DECLARE_EXTENDED_PHASE(BEGIN_PDNA); // 22 DECLARE_EXTENDED_PHASE(BEGIN_PDNP); // 23 DECLARE_EXTENDED_PHASE(BEGIN_SREF); // 24 @@ -77,23 +78,12 @@ DECLARE_EXTENDED_PHASE(END_PDNA); // 25 DECLARE_EXTENDED_PHASE(END_PDNP); // 26 DECLARE_EXTENDED_PHASE(END_SREF); // 27 -DECLARE_EXTENDED_PHASE(END_NOP); // 28 -DECLARE_EXTENDED_PHASE(END_RD); // 29 -DECLARE_EXTENDED_PHASE(END_WR); // 30 -DECLARE_EXTENDED_PHASE(END_RDA); // 31 -DECLARE_EXTENDED_PHASE(END_WRA); // 32 -DECLARE_EXTENDED_PHASE(END_ACT); // 33 -DECLARE_EXTENDED_PHASE(END_PREPB); // 34 -DECLARE_EXTENDED_PHASE(END_REFPB); // 35 -DECLARE_EXTENDED_PHASE(END_RFMPB); // 36 -DECLARE_EXTENDED_PHASE(END_REFP2B); // 37 -DECLARE_EXTENDED_PHASE(END_RFMP2B); // 38 -DECLARE_EXTENDED_PHASE(END_PRESB); // 39 -DECLARE_EXTENDED_PHASE(END_REFSB); // 40 -DECLARE_EXTENDED_PHASE(END_RFMSB); // 41 -DECLARE_EXTENDED_PHASE(END_PREAB); // 42 -DECLARE_EXTENDED_PHASE(END_REFAB); // 43 -DECLARE_EXTENDED_PHASE(END_RFMAB); // 44 +DRAMPower::MemCommand::cmds phaseToDRAMPowerCommand(tlm::tlm_phase phase); +bool phaseHasDataStrobe(tlm::tlm_phase phase); +bool isPowerDownEntryPhase(tlm::tlm_phase phase); +bool isPowerDownExitPhase(tlm::tlm_phase phase); +bool isFixedCommandPhase(tlm::tlm_phase phase); +bool isRefreshCommandPhase(tlm::tlm_phase phase); class Command { @@ -150,11 +140,6 @@ public: } }; -DRAMPower::MemCommand::cmds phaseToDRAMPowerCommand(tlm::tlm_phase); -bool phaseNeedsEnd(tlm::tlm_phase); -bool phaseHasDataStrobe(tlm::tlm_phase); -tlm::tlm_phase getEndPhase(tlm::tlm_phase); - struct CommandTuple { using Type = std::tuple<::Command, tlm::tlm_generic_payload *, sc_core::sc_time>; From 14588dbb779e2c0538f7a21280d4c8a28b20da29 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Mon, 2 May 2022 17:44:56 +0200 Subject: [PATCH 09/29] Adapt TA to new database format (1). --- DRAMSys/library/src/common/TlmRecorder.cpp | 2 +- .../businessObjects/generalinfo.h | 5 +- .../businessObjects/phases/phase.cpp | 37 +++--- .../businessObjects/phases/phase.h | 31 ++++- .../businessObjects/phases/phasefactory.cpp | 113 ++++++++---------- .../businessObjects/phases/phasefactory.h | 5 +- .../businessObjects/transaction.cpp | 10 +- .../businessObjects/transaction.h | 11 +- DRAMSys/traceAnalyzer/data/QueryTexts.h | 5 +- DRAMSys/traceAnalyzer/data/tracedb.cpp | 43 +++---- .../presentation/transactiontreewidget.cpp | 35 +++--- DRAMSys/traceAnalyzer/queryeditor.cpp | 15 ++- 12 files changed, 158 insertions(+), 154 deletions(-) diff --git a/DRAMSys/library/src/common/TlmRecorder.cpp b/DRAMSys/library/src/common/TlmRecorder.cpp index 0d30e623..c062999e 100644 --- a/DRAMSys/library/src/common/TlmRecorder.cpp +++ b/DRAMSys/library/src/common/TlmRecorder.cpp @@ -368,7 +368,7 @@ void TlmRecorder::insertGeneralInfo() sqlite3_bind_int64(insertGeneralInfoStatement, 11, 0); sqlite3_bind_int(insertGeneralInfoStatement, 12, static_cast(config.refreshMaxPostponed)); sqlite3_bind_int(insertGeneralInfoStatement, 13, static_cast(config.refreshMaxPulledin)); - sqlite3_bind_int64(insertGeneralInfoStatement, 14, static_cast(UINT64_MAX)); + sqlite3_bind_int(insertGeneralInfoStatement, 14, static_cast(UINT_MAX)); sqlite3_bind_int(insertGeneralInfoStatement, 15, static_cast(config.requestBufferSize)); sqlite3_bind_int(insertGeneralInfoStatement, 16, static_cast(config.memSpec->getPer2BankOffset())); diff --git a/DRAMSys/traceAnalyzer/businessObjects/generalinfo.h b/DRAMSys/traceAnalyzer/businessObjects/generalinfo.h index 4f5ef2a6..c43a288e 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/generalinfo.h +++ b/DRAMSys/traceAnalyzer/businessObjects/generalinfo.h @@ -41,6 +41,7 @@ #include "timespan.h" #include +#include struct GeneralInfo { @@ -59,7 +60,7 @@ struct GeneralInfo uint64_t windowSize = 0; unsigned int refreshMaxPostponed = 0; unsigned int refreshMaxPulledin = 0; - uint64_t controllerThread = UINT64_MAX; + unsigned int controllerThread = UINT_MAX; unsigned int maxBufferDepth = 8; unsigned int per2BankOffset = 1; bool rowColumnCommandBus = false; @@ -69,7 +70,7 @@ struct GeneralInfo GeneralInfo(uint64_t numberOfTransactions, uint64_t numberOfPhases, Timespan span, unsigned int numberOfRanks, unsigned int numberOfBankgroups, unsigned int numberOfBanks, QString description, QString unitOfTime, uint64_t clkPeriod, uint64_t windowSize, unsigned int refreshMaxPostponed, - unsigned int refreshMaxPulledin, uint64_t controllerThread, unsigned int maxBufferDepth, + unsigned int refreshMaxPulledin, unsigned int controllerThread, unsigned int maxBufferDepth, unsigned int per2BankOffset, bool rowColumnCommandBus, bool pseudoChannelMode) : numberOfTransactions(numberOfTransactions), numberOfPhases(numberOfPhases), span(span), numberOfRanks(numberOfRanks), numberOfBankGroups(numberOfBankgroups), numberOfBanks(numberOfBanks), diff --git a/DRAMSys/traceAnalyzer/businessObjects/phases/phase.cpp b/DRAMSys/traceAnalyzer/businessObjects/phases/phase.cpp index 0cd31fd7..5ddec5a2 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/phases/phase.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/phases/phase.cpp @@ -84,7 +84,7 @@ void Phase::draw(QPainter *painter, const QwtScaleMap &xMap, const QwtScaleMap & } } - for (Timespan span : spansOnCommandBus) + for (Timespan spanOnCommandBus : spansOnCommandBus) { for (const auto &line : drawingProperties.getTracePlotLines()) { @@ -101,30 +101,30 @@ void Phase::draw(QPainter *painter, const QwtScaleMap &xMap, const QwtScaleMap & else if (line->data.type != AbstractTracePlotLineModel::CommandBusLine) continue; - drawPhaseSymbol(span.Begin(), span.End(), line->data.yVal, false, PhaseSymbol::Hexagon, painter, xMap, yMap, + drawPhaseSymbol(spanOnCommandBus.Begin(), spanOnCommandBus.End(), line->data.yVal, false, PhaseSymbol::Hexagon, painter, xMap, yMap, drawingProperties.textColor); } } - if (spanOnDataBus) + if (spanOnDataStrobe.End() != 0) { for (const auto &line : drawingProperties.getTracePlotLines()) { if (line->data.type == AbstractTracePlotLineModel::PseudoChannel0Line) { - if (transaction.lock()->rank != 0) + if (rank != 0) continue; } else if (line->data.type == AbstractTracePlotLineModel::PseudoChannel1Line) { - if (transaction.lock()->rank != 1) + if (rank != 1) continue; } else if (line->data.type != AbstractTracePlotLineModel::DataBusLine) continue; - drawPhaseSymbol(spanOnDataBus->Begin(), spanOnDataBus->End(), line->data.yVal, false, PhaseSymbol::Hexagon, - painter, xMap, yMap, drawingProperties.textColor); + drawPhaseSymbol(spanOnDataStrobe.Begin(), spanOnDataStrobe.End(), line->data.yVal, false, + PhaseSymbol::Hexagon, painter, xMap, yMap, drawingProperties.textColor); } } } @@ -207,9 +207,6 @@ std::vector Phase::getYVals(const TraceDrawingProperties &drawingProperties { std::vector yVals; - unsigned int transactionRank = transaction.lock()->rank; - unsigned int transactionBank = transaction.lock()->bank; - for (const auto &line : drawingProperties.getTracePlotLines()) { if (line->data.type != AbstractTracePlotLineModel::BankLine) @@ -217,26 +214,26 @@ std::vector Phase::getYVals(const TraceDrawingProperties &drawingProperties unsigned int yVal = line->data.yVal; - unsigned int rank = line->data.rank; - unsigned int bank = line->data.bank; + unsigned int drawnRank = line->data.rank; + unsigned int drawnBank = line->data.bank; bool shouldBeDrawn = false; switch (getGranularity()) { case Granularity::Rankwise: - shouldBeDrawn = (transactionRank == rank); + shouldBeDrawn = (rank == drawnRank); break; case Granularity::Groupwise: - shouldBeDrawn = (transactionRank == rank) && (transactionBank % drawingProperties.banksPerGroup == - bank % drawingProperties.banksPerGroup); + shouldBeDrawn = (rank == drawnRank) && (bank % drawingProperties.banksPerGroup == + drawnBank % drawingProperties.banksPerGroup); break; case Granularity::Bankwise: - shouldBeDrawn = (transactionBank == bank); + shouldBeDrawn = (bank == drawnBank); break; case Granularity::TwoBankwise: - shouldBeDrawn = (transactionBank == bank) || ((transactionBank + drawingProperties.per2BankOffset) == bank); + shouldBeDrawn = (bank == drawnBank) || ((bank + drawingProperties.per2BankOffset) == drawnBank); break; } @@ -332,18 +329,18 @@ bool Phase::isSelected(Timespan timespan, double yVal, const TraceDrawingPropert } } - if (spanOnDataBus && spanOnDataBus->overlaps(timespan)) + if (spanOnDataStrobe.End() != 0 && spanOnDataStrobe.overlaps(timespan)) { for (const auto &line : drawingProperties.getTracePlotLines()) { if (line->data.type == AbstractTracePlotLineModel::PseudoChannel0Line) { - if (transaction.lock()->rank != 0) + if (rank != 0) continue; } else if (line->data.type == AbstractTracePlotLineModel::PseudoChannel1Line) { - if (transaction.lock()->rank != 1) + if (rank != 1) continue; } else if (line->data.type != AbstractTracePlotLineModel::DataBusLine) diff --git a/DRAMSys/traceAnalyzer/businessObjects/phases/phase.h b/DRAMSys/traceAnalyzer/businessObjects/phases/phase.h index 9b9550d1..d02e28d5 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/phases/phase.h +++ b/DRAMSys/traceAnalyzer/businessObjects/phases/phase.h @@ -56,11 +56,12 @@ class Transaction; class Phase { public: - Phase(ID id, Timespan span, traceTime clk, const std::shared_ptr &transaction, - std::vector spansOnCommandBus, - std::shared_ptr spanOnDataBus): - id(id), span(span), clk(clk), transaction(transaction), - spansOnCommandBus(spansOnCommandBus), spanOnDataBus(spanOnDataBus), + Phase(ID id, Timespan span, Timespan spanOnDataStrobe, unsigned int rank, unsigned int bankGroup, + unsigned int bank, unsigned int row, unsigned int column, unsigned int burstLength, + traceTime clk, const std::shared_ptr &transaction, std::vector spansOnCommandBus) : + id(id), span(span), spanOnDataStrobe(spanOnDataStrobe), + rank(rank), bankGroup(bankGroup), bank(bank), row(row), column(column), burstLength(burstLength), + clk(clk), transaction(transaction), spansOnCommandBus(spansOnCommandBus), hexagonHeight(0.6), captionPosition(TextPositioning::bottomRight) {} void draw(QPainter *painter, const QwtScaleMap &xMap, const QwtScaleMap &yMap, @@ -83,10 +84,11 @@ public: protected: ID id; Timespan span; + Timespan spanOnDataStrobe; + unsigned int rank, bankGroup, bank, row, column, burstLength; traceTime clk; std::weak_ptr transaction; std::vector spansOnCommandBus; - std::shared_ptr spanOnDataBus; std::vector> mDependencies; double hexagonHeight; @@ -399,6 +401,23 @@ protected: } }; +class RFMPB final : public AUTO_REFRESH +{ +public: + using AUTO_REFRESH::AUTO_REFRESH; +protected: + QString Name() const override + { + return "RFMPB"; + } + QColor getPhaseColor() const override + { + QColor phaseColor = QColor(Qt::darkRed); + phaseColor.setAlpha(130); + return phaseColor; + } +}; + class REFP2B final : public AUTO_REFRESH { public: diff --git a/DRAMSys/traceAnalyzer/businessObjects/phases/phasefactory.cpp b/DRAMSys/traceAnalyzer/businessObjects/phases/phasefactory.cpp index 60847527..290034f4 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/phases/phasefactory.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/phases/phasefactory.cpp @@ -43,88 +43,77 @@ #include "businessObjects/timespan.h" std::shared_ptr PhaseFactory::CreatePhase(ID id, const QString &dbPhaseName, - const Timespan &span, const std::shared_ptr &trans, - TraceDB &database) + const Timespan& span, const Timespan& spanOnDataStrobe, + unsigned int rank, unsigned int bankGroup, unsigned int bank, unsigned int row, unsigned int column, + unsigned int burstLength, const std::shared_ptr &trans, TraceDB &database) { - traceTime clk = database.getGeneralInfo().clkPeriod; + traceTime clk = static_cast(database.getGeneralInfo().clkPeriod); const CommandLengths &cl = database.getCommandLengths(); if (dbPhaseName == "REQ") - return std::shared_ptr(new REQ(id, span, clk, trans, {}, std::shared_ptr())); + return std::shared_ptr(new REQ(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, burstLength, clk, trans, {})); else if (dbPhaseName == "RESP") - return std::shared_ptr(new RESP(id, span, clk, trans, {}, std::shared_ptr())); - /*else if (dbPhaseName == "PREB") - return shared_ptr(new PREB(id, span, clk, trans, - {Timespan(span.Begin(), span.Begin() + clk)}, std::shared_ptr()));*/ - else if (dbPhaseName == "PREPB" || dbPhaseName == "PRE") // for backwards compatibility - return std::shared_ptr(new PREPB(id, span, clk, trans, - {Timespan(span.Begin(), span.Begin() + clk * cl.PREPB)}, std::shared_ptr())); - /*else if (dbPhaseName == "ACTB") - return std::shared_ptr(new ACTB(id, span, clk, trans, - {Timespan(span.Begin(), span.Begin() + clk)}, std::shared_ptr()));*/ + return std::shared_ptr(new RESP(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column,burstLength, clk, trans, {})); + else if (dbPhaseName == "PREPB") + return std::shared_ptr(new PREPB(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, + burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.PREPB)})); else if (dbPhaseName == "ACT") - return std::shared_ptr(new ACT(id, span, clk, trans, - {Timespan(span.Begin(), span.Begin() + clk * cl.ACT)}, std::shared_ptr())); - else if (dbPhaseName == "PREAB" || dbPhaseName == "PREA") // for backwards compatibility - return std::shared_ptr(new PREAB(id, span, clk, trans, - {Timespan(span.Begin(), span.Begin() + clk * cl.PREAB)}, std::shared_ptr())); - else if (dbPhaseName == "REFAB" || dbPhaseName == "REFA") // for backwards compatibility - return std::shared_ptr(new REFAB(id, span, clk, trans, - {Timespan(span.Begin(), span.Begin() + clk * cl.REFAB)}, std::shared_ptr())); + return std::shared_ptr(new ACT(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, + burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.ACT)})); + else if (dbPhaseName == "PREAB") + return std::shared_ptr(new PREAB(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, + burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.PREAB)})); + else if (dbPhaseName == "REFAB") + return std::shared_ptr(new REFAB(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, + burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.REFAB)})); else if (dbPhaseName == "RFMAB") - return std::shared_ptr(new RFMAB(id, span, clk, trans, - {Timespan(span.Begin(), span.Begin() + clk * cl.RFMAB)}, std::shared_ptr())); - else if (dbPhaseName == "REFPB" || dbPhaseName == "REFB") // for backwards compatibility - return std::shared_ptr(new REFPB(id, span, clk, trans, - {Timespan(span.Begin(), span.Begin() + clk * cl.REFPB)}, std::shared_ptr())); + return std::shared_ptr(new RFMAB(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, + burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.RFMAB)})); + else if (dbPhaseName == "REFPB") + return std::shared_ptr(new REFPB(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, + burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.REFPB)})); else if (dbPhaseName == "RFMPB") - return std::shared_ptr(new REFPB(id, span, clk, trans, - {Timespan(span.Begin(), span.Begin() + clk * cl.RFMPB)}, std::shared_ptr())); + return std::shared_ptr(new RFMPB(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, + burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.RFMPB)})); else if (dbPhaseName == "REFP2B") - return std::shared_ptr(new REFP2B(id, span, clk, trans, - {Timespan(span.Begin(), span.Begin() + clk * cl.REFP2B)}, std::shared_ptr())); + return std::shared_ptr(new REFP2B(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, + burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.REFP2B)})); else if (dbPhaseName == "RFMP2B") - return std::shared_ptr(new REFP2B(id, span, clk, trans, - {Timespan(span.Begin(), span.Begin() + clk * cl.RFMP2B)}, std::shared_ptr())); + return std::shared_ptr(new RFMP2B(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, + burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.RFMP2B)})); else if (dbPhaseName == "PRESB") - return std::shared_ptr(new PRESB(id, span, clk, trans, - {Timespan(span.Begin(), span.Begin() + clk * cl.PRESB)}, std::shared_ptr())); + return std::shared_ptr(new PRESB(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, + burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.PRESB)})); else if (dbPhaseName == "REFSB") - return std::shared_ptr(new REFSB(id, span, clk, trans, - {Timespan(span.Begin(), span.Begin() + clk * cl.REFSB)}, std::shared_ptr())); + return std::shared_ptr(new REFSB(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, + burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.REFSB)})); else if (dbPhaseName == "RFMSB") - return std::shared_ptr(new RFMSB(id, span, clk, trans, - {Timespan(span.Begin(), span.Begin() + clk * cl.RFMSB)}, std::shared_ptr())); + return std::shared_ptr(new RFMSB(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, + burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.RFMSB)})); else if (dbPhaseName == "RD") - return std::shared_ptr(new RD(id, span, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.RD)}, - std::shared_ptr(new Timespan(trans->spanOnDataStrobe)))); + return std::shared_ptr(new RD(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, + burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.RD)})); else if (dbPhaseName == "RDA") - return std::shared_ptr(new RDA(id, span, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.RDA)}, - std::shared_ptr(new Timespan(trans->spanOnDataStrobe)))); + return std::shared_ptr(new RDA(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, + burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.RDA)})); else if (dbPhaseName == "WR") - return std::shared_ptr(new WR(id, span, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.WR)}, - std::shared_ptr(new Timespan(trans->spanOnDataStrobe)))); + return std::shared_ptr(new WR(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, + burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.WR)})); else if (dbPhaseName == "WRA") - return std::shared_ptr(new WRA(id, span, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.WRA)}, - std::shared_ptr(new Timespan(trans->spanOnDataStrobe)))); + return std::shared_ptr(new WRA(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, + burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.WRA)})); else if (dbPhaseName == "PDNA") - return std::shared_ptr(new PDNA(id, span, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.PDEA), - Timespan(span.End() - clk * cl.PDXA, span.End())}, std::shared_ptr())); - else if (dbPhaseName == "PDNAB") - return std::shared_ptr(new PDNAB(id, span, clk, trans, {Timespan(span.Begin(), span.Begin() + clk), - Timespan(span.End() - clk, span.End())}, std::shared_ptr())); + return std::shared_ptr(new PDNA(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, + burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.PDEA), + Timespan(span.End() - clk * cl.PDXA, span.End())})); else if (dbPhaseName == "PDNP") - return std::shared_ptr(new PDNP(id, span, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.PDEP), - Timespan(span.End() - clk * cl.PDXP, span.End())}, std::shared_ptr())); - else if (dbPhaseName == "PDNPB") - return std::shared_ptr(new PDNPB(id, span, clk, trans, {Timespan(span.Begin(), span.Begin() + clk), - Timespan(span.End() - clk, span.End())}, std::shared_ptr())); + return std::shared_ptr(new PDNP(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, + burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.PDEP), + Timespan(span.End() - clk * cl.PDXP, span.End())})); else if (dbPhaseName == "SREF") - return std::shared_ptr(new SREF(id, span, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.SREFEN), - Timespan(span.End() - clk * cl.SREFEX, span.End())}, std::shared_ptr())); - else if (dbPhaseName == "SREFB") - return std::shared_ptr(new SREFB(id, span, clk, trans, {Timespan(span.Begin(), span.Begin() + clk), - Timespan(span.End() - clk, span.End())}, std::shared_ptr())); + return std::shared_ptr(new SREF(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, + burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.SREFEN), + Timespan(span.End() - clk * cl.SREFEX, span.End())})); else throw std::runtime_error("DB phasename " + dbPhaseName.toStdString() + " unkown to phasefactory"); } diff --git a/DRAMSys/traceAnalyzer/businessObjects/phases/phasefactory.h b/DRAMSys/traceAnalyzer/businessObjects/phases/phasefactory.h index 4aef44c7..10d99b54 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/phases/phasefactory.h +++ b/DRAMSys/traceAnalyzer/businessObjects/phases/phasefactory.h @@ -50,8 +50,9 @@ class PhaseFactory public: PhaseFactory() = delete; static std::shared_ptr CreatePhase(ID id, const QString &dbPhaseName, - const Timespan &span, const std::shared_ptr &trans, - TraceDB &database); + const Timespan& span, const Timespan& spanOnDataStrobe, + unsigned int rank, unsigned int bankGroup, unsigned int bank, unsigned int row, unsigned int column, + unsigned int burstLength, const std::shared_ptr &trans, TraceDB &database); }; #endif // PHASEFACTORY_H diff --git a/DRAMSys/traceAnalyzer/businessObjects/transaction.cpp b/DRAMSys/traceAnalyzer/businessObjects/transaction.cpp index 11f188f7..e97dddf0 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/transaction.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/transaction.cpp @@ -42,13 +42,9 @@ using namespace std; unsigned int Transaction::mSNumTransactions = 0; -Transaction::Transaction(ID id, unsigned int address, unsigned int burstlength, - unsigned int thread, unsigned int channel, unsigned int rank, - unsigned int bankgroup, unsigned int bank, unsigned int row, unsigned int column, - Timespan span, Timespan spanOnDataStrobe, traceTime clk) - : clk(clk), address(address), burstlength(burstlength), thread(thread), channel(channel), - rank(rank), bankgroup(bankgroup), bank(bank), row(row), column(column), span(span), - spanOnDataStrobe(spanOnDataStrobe), id(id) {} +Transaction::Transaction(ID id, unsigned int address, unsigned int dataLength, + unsigned int thread, unsigned int channel, Timespan span, traceTime clk) + : clk(clk), address(address), dataLength(dataLength), thread(thread), channel(channel), span(span), id(id) {} void Transaction::addPhase(shared_ptr phase) { diff --git a/DRAMSys/traceAnalyzer/businessObjects/transaction.h b/DRAMSys/traceAnalyzer/businessObjects/transaction.h index d2c97990..f6caf329 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/transaction.h +++ b/DRAMSys/traceAnalyzer/businessObjects/transaction.h @@ -53,16 +53,13 @@ private: traceTime clk; public: - const unsigned int address, burstlength, thread, channel, rank, - bankgroup, bank, row, column; + const uint64_t address; + const unsigned int dataLength, thread, channel; const Timespan span; - const Timespan spanOnDataStrobe; const ID id; - Transaction(ID id, unsigned int address, unsigned int burstlength, - unsigned int thread, unsigned int channel, unsigned int rank, - unsigned int bankgroup, unsigned int bank, unsigned int row, unsigned int column, - Timespan span, Timespan spanOnDataStrobe, traceTime clk); + Transaction(ID id, unsigned int address, unsigned int dataLength, unsigned int thread, unsigned int channel, + Timespan span, traceTime clk); void draw(QPainter *painter, const QwtScaleMap &xMap, const QwtScaleMap &yMap, const QRectF &canvasRect, bool highlight, diff --git a/DRAMSys/traceAnalyzer/data/QueryTexts.h b/DRAMSys/traceAnalyzer/data/QueryTexts.h index 361ec855..996df475 100644 --- a/DRAMSys/traceAnalyzer/data/QueryTexts.h +++ b/DRAMSys/traceAnalyzer/data/QueryTexts.h @@ -50,11 +50,10 @@ struct TransactionQueryTexts { TransactionQueryTexts() { queryHead = - "SELECT Transactions.ID AS TransactionID, Ranges.begin, Ranges.end,DataStrobeBegin,DataStrobeEnd, Address,Burstlength, TThread, TChannel, TRank, TBankgroup, TBank, TRow, TColumn,Phases.ID AS PhaseID, PhaseName, PhaseBegin, PhaseEnd " + "SELECT Transactions.ID AS TransactionID, Ranges.begin, Ranges.end, Address, DataLength, Thread, Channel, Phases.ID AS PhaseID, PhaseName, PhaseBegin, PhaseEnd, DataStrobeBegin, DataStrobeEnd, Rank, BankGroup, Bank, Row, Column, BurstLength " " FROM Transactions INNER JOIN Phases ON Phases.Transact = Transactions.ID INNER JOIN Ranges ON Transactions.Range = Ranges.ID "; - selectTransactionsByTimespan = queryHead + - " WHERE Ranges.end >= :begin AND Ranges.begin <= :end"; + selectTransactionsByTimespan = queryHead + " WHERE Ranges.end >= :begin AND Ranges.begin <= :end"; selectTransactionById = queryHead + " WHERE Transactions.ID = :id"; checkDependenciesExist = "SELECT CASE WHEN 0 < (SELECT count(*) FROM sqlite_master WHERE type = 'table' AND " diff --git a/DRAMSys/traceAnalyzer/data/tracedb.cpp b/DRAMSys/traceAnalyzer/data/tracedb.cpp index b445e478..4b17e031 100644 --- a/DRAMSys/traceAnalyzer/data/tracedb.cpp +++ b/DRAMSys/traceAnalyzer/data/tracedb.cpp @@ -311,7 +311,7 @@ GeneralInfo TraceDB::getGeneralInfoFromDB() parameter = getParameterFromTable("RefreshMaxPulledin", "GeneralInfo"); unsigned refreshMaxPulledin = parameter.isValid() ? parameter.toUInt() : 0; parameter = getParameterFromTable("ControllerThread", "GeneralInfo"); - uint64_t controllerThread = parameter.isValid() ? parameter.toULongLong() : UINT64_MAX; + unsigned controllerThread = parameter.isValid() ? parameter.toUInt() : UINT_MAX; parameter = getParameterFromTable("MaxBufferDepth", "GeneralInfo"); unsigned maxBufferDepth = parameter.isValid() ? parameter.toUInt() : 8; parameter = getParameterFromTable("Per2BankOffset", "GeneralInfo"); @@ -535,34 +535,35 @@ std::vector> TraceDB::parseTransactionsFromQuery(QS ID currentID = 0; int i = -1; - while (query.next()) { - + while (query.next()) + { ID id = query.value(0).toInt(); - if (currentID != id || firstIteration) { + if (currentID != id || firstIteration) + { ++i; firstIteration = false; currentID = id; Timespan span(query.value(1).toLongLong(), query.value(2).toLongLong()); - Timespan spanOnStrobe(query.value(3).toLongLong(), query.value(4).toLongLong()); - unsigned int address = query.value(5).toInt(); - unsigned int burstlength = query.value(6).toInt(); - unsigned int thread = query.value(7).toInt(); - unsigned int channel = query.value(8).toInt(); - unsigned int rank = query.value(9).toInt(); - unsigned int bankgroup = query.value(10).toInt(); - unsigned int bank = query.value(11).toInt(); - unsigned int row = query.value(12).toInt(); - unsigned int column = query.value(13).toInt(); - result.push_back(std::make_shared(id, address, burstlength, - thread, channel, rank, bankgroup, bank, row, column, - span, spanOnStrobe, generalInfo.clkPeriod)); + uint64_t address = query.value(3).toULongLong(); + unsigned int dataLength = query.value(4).toUInt(); + unsigned int thread = query.value(5).toUInt(); + unsigned int channel = query.value(6).toUInt(); + result.push_back(std::make_shared(id, address, dataLength, thread, channel, span, generalInfo.clkPeriod)); } - unsigned int phaseID = query.value(14).toInt(); - QString phaseName = query.value(15).toString(); - Timespan span(query.value(16).toLongLong(), query.value(17).toLongLong()); - auto phase = PhaseFactory::CreatePhase(phaseID, phaseName, span, result.at(result.size() - 1), *this); + unsigned int phaseID = query.value(7).toInt(); + QString phaseName = query.value(8).toString(); + Timespan span(query.value(9).toLongLong(), query.value(10).toLongLong()); + Timespan spanOnDataStrobe(query.value(11).toLongLong(), query.value(12).toLongLong()); + unsigned int rank = query.value(13).toUInt(); + unsigned int bankGroup = query.value(14).toUInt(); + unsigned int bank = query.value(15).toUInt(); + unsigned int row = query.value(16).toUInt(); + unsigned int column = query.value(17).toUInt(); + unsigned int burstLength = query.value(18).toUInt(); + auto phase = PhaseFactory::CreatePhase(phaseID, phaseName, span, spanOnDataStrobe, rank, bankGroup, bank, + row, column, burstLength, result.at(result.size() - 1), *this); result.at(result.size() - 1)->addPhase(phase); if (updateVisiblePhases) diff --git a/DRAMSys/traceAnalyzer/presentation/transactiontreewidget.cpp b/DRAMSys/traceAnalyzer/presentation/transactiontreewidget.cpp index 759bbdde..f8e5637f 100644 --- a/DRAMSys/traceAnalyzer/presentation/transactiontreewidget.cpp +++ b/DRAMSys/traceAnalyzer/presentation/transactiontreewidget.cpp @@ -79,9 +79,9 @@ void TransactionTreeWidget::ContextMenuRequested(QPoint point) contextMenu.addActions({goToTransaction}); QAction *selectedContextMenuItems = contextMenu.exec(mapToGlobal(point)); - if (selectedContextMenuItems) { - TransactionTreeItem *item = static_cast - (selectedItems().at(0)); + if (selectedContextMenuItems) + { + TransactionTreeItem *item = dynamic_cast(selectedItems().at(0)); navigator->selectTransaction(item->Id()); } } @@ -95,29 +95,30 @@ TransactionTreeWidget::TransactionTreeItem::TransactionTreeItem( this->setText(0, QString::number(transaction->id)); this->id = transaction->id; - QTreeWidgetItem *time = new QTreeWidgetItem({"Timespan"}); + bool isControllerTransaction = (transaction->thread == generalInfo.controllerThread); + + auto* time = new QTreeWidgetItem({"Timespan"}); AppendTimespan(time, transaction->span); this->addChild(time); this->addChild(new QTreeWidgetItem({"Length", prettyFormatTime(transaction->span.timeCovered())})); - this->addChild(new QTreeWidgetItem({"Channel", QString::number(transaction->channel)})); - this->addChild(new QTreeWidgetItem({"Rank", QString::number(transaction->rank)})); - this->addChild(new QTreeWidgetItem({"Bankgroup", QString::number(transaction->bankgroup % generalInfo.groupsPerRank)})); - this->addChild(new QTreeWidgetItem({"Bank", QString::number(transaction->bank % generalInfo.banksPerGroup)})); - this->addChild(new QTreeWidgetItem({"Row", QString::number(transaction->row)})); - this->addChild(new QTreeWidgetItem({"Column", QString::number(transaction->column)})); + // TODO: move to phase + //this->addChild(new QTreeWidgetItem({"Rank", QString::number(transaction->rank)})); + //this->addChild(new QTreeWidgetItem({"Bankgroup", QString::number(transaction->bankgroup % generalInfo.groupsPerRank)})); + //this->addChild(new QTreeWidgetItem({"Bank", QString::number(transaction->bank % generalInfo.banksPerGroup)})); + //this->addChild(new QTreeWidgetItem({"Row", QString::number(transaction->row)})); + //this->addChild(new QTreeWidgetItem({"Column", QString::number(transaction->column)})); this->addChild(new QTreeWidgetItem({"Address", QString("0x") + QString::number(transaction->address, 16)})); - - if (transaction->thread != generalInfo.controllerThread) - { - this->addChild(new QTreeWidgetItem({"Burstlength", QString::number(transaction->burstlength)})); + if (!isControllerTransaction) + this->addChild(new QTreeWidgetItem({"Data Length", QString::number(transaction->dataLength)})); + this->addChild(new QTreeWidgetItem({"Channel", QString::number(transaction->channel)})); + if (!isControllerTransaction) this->addChild(new QTreeWidgetItem({"Thread", QString::number(transaction->thread)})); - } - QTreeWidgetItem *phasesNode = new QTreeWidgetItem(this); + auto* phasesNode = new QTreeWidgetItem(this); phasesNode->setText(0, "Phases"); phasesNode->addChild(new QTreeWidgetItem({"", "Begin", "End"})); - for (std::shared_ptr phase : transaction->Phases()) { + for (const std::shared_ptr& phase : transaction->Phases()) { AppendPhase(phasesNode, *phase); } } diff --git a/DRAMSys/traceAnalyzer/queryeditor.cpp b/DRAMSys/traceAnalyzer/queryeditor.cpp index 19086392..0a97f840 100644 --- a/DRAMSys/traceAnalyzer/queryeditor.cpp +++ b/DRAMSys/traceAnalyzer/queryeditor.cpp @@ -61,15 +61,18 @@ void QueryEditor::init(TraceNavigator *navigator) void QueryEditor::on_executeQuery_clicked() { - try { - std::vector> result = - navigator->TraceFile().getTransactionsWithCustomQuery(queryTexts.queryHead + " " - + ui->queryEdit->toPlainText()); + try + { + std::vector> result = navigator->TraceFile().getTransactionsWithCustomQuery( + queryTexts.queryHead + " " + ui->queryEdit->toPlainText()); ui->transactiontreeWidget->clear(); - for (const auto &trans : result) { + for (const auto& trans : result) + { ui->transactiontreeWidget->AppendTransaction(trans); } - } catch (sqlException ex) { + } + catch (sqlException ex) + { QMessageBox::warning(this, "Query failed", ex.what()); } } From d41f3d85784fb719942496f50b32f14b639d5e10 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Tue, 3 May 2022 16:00:16 +0200 Subject: [PATCH 10/29] Adapt TA to new database format (2). --- .../businessObjects/generalinfo.h | 2 +- .../businessObjects/phases/phase.h | 13 +++++----- .../businessObjects/phases/phasefactory.cpp | 6 ++--- .../businessObjects/phases/phasefactory.h | 4 +-- .../traceAnalyzer/businessObjects/timespan.h | 2 +- DRAMSys/traceAnalyzer/data/tracedb.cpp | 25 +++++++++---------- DRAMSys/traceAnalyzer/data/tracedb.h | 8 +++--- .../presentation/transactiontreewidget.cpp | 20 ++++++--------- .../presentation/transactiontreewidget.h | 4 +-- DRAMSys/traceAnalyzer/queryeditor.cpp | 8 +++--- DRAMSys/traceAnalyzer/queryeditor.h | 2 +- 11 files changed, 45 insertions(+), 49 deletions(-) diff --git a/DRAMSys/traceAnalyzer/businessObjects/generalinfo.h b/DRAMSys/traceAnalyzer/businessObjects/generalinfo.h index c43a288e..ae06a37b 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/generalinfo.h +++ b/DRAMSys/traceAnalyzer/businessObjects/generalinfo.h @@ -47,7 +47,7 @@ struct GeneralInfo { uint64_t numberOfTransactions = 0; uint64_t numberOfPhases = 0; - Timespan span = 0; + Timespan span = Timespan(); unsigned int numberOfRanks = 1; unsigned int numberOfBankGroups = 1; unsigned int numberOfBanks = 1; diff --git a/DRAMSys/traceAnalyzer/businessObjects/phases/phase.h b/DRAMSys/traceAnalyzer/businessObjects/phases/phase.h index d02e28d5..942c8929 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/phases/phase.h +++ b/DRAMSys/traceAnalyzer/businessObjects/phases/phase.h @@ -47,6 +47,7 @@ #include #include #include +#include #include typedef unsigned int ID; @@ -61,7 +62,7 @@ public: traceTime clk, const std::shared_ptr &transaction, std::vector spansOnCommandBus) : id(id), span(span), spanOnDataStrobe(spanOnDataStrobe), rank(rank), bankGroup(bankGroup), bank(bank), row(row), column(column), burstLength(burstLength), - clk(clk), transaction(transaction), spansOnCommandBus(spansOnCommandBus), + clk(clk), transaction(transaction), spansOnCommandBus(std::move(spansOnCommandBus)), hexagonHeight(0.6), captionPosition(TextPositioning::bottomRight) {} void draw(QPainter *painter, const QwtScaleMap &xMap, const QwtScaleMap &yMap, @@ -348,7 +349,7 @@ protected: } QColor getPhaseColor() const override { - QColor phaseColor = QColor(Qt::darkCyan); + auto phaseColor = QColor(Qt::darkCyan); phaseColor.setAlpha(130); return phaseColor; } @@ -384,7 +385,7 @@ protected: } QColor getPhaseColor() const override { - QColor phaseColor = QColor(Qt::darkRed); + auto phaseColor = QColor(Qt::darkRed); phaseColor.setAlpha(130); return phaseColor; } @@ -412,7 +413,7 @@ protected: } QColor getPhaseColor() const override { - QColor phaseColor = QColor(Qt::darkRed); + auto phaseColor = QColor(Qt::darkRed); phaseColor.setAlpha(130); return phaseColor; } @@ -448,7 +449,7 @@ protected: } QColor getPhaseColor() const override { - QColor phaseColor = QColor(Qt::darkRed); + auto phaseColor = QColor(Qt::darkRed); phaseColor.setAlpha(130); return phaseColor; } @@ -484,7 +485,7 @@ protected: } QColor getPhaseColor() const override { - QColor phaseColor = QColor(Qt::darkRed); + auto phaseColor = QColor(Qt::darkRed); phaseColor.setAlpha(130); return phaseColor; } diff --git a/DRAMSys/traceAnalyzer/businessObjects/phases/phasefactory.cpp b/DRAMSys/traceAnalyzer/businessObjects/phases/phasefactory.cpp index 290034f4..97e2c512 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/phases/phasefactory.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/phases/phasefactory.cpp @@ -42,12 +42,12 @@ #include "data/tracedb.h" #include "businessObjects/timespan.h" -std::shared_ptr PhaseFactory::CreatePhase(ID id, const QString &dbPhaseName, - const Timespan& span, const Timespan& spanOnDataStrobe, +std::shared_ptr PhaseFactory::createPhase(ID id, const QString &dbPhaseName, + Timespan span, Timespan spanOnDataStrobe, unsigned int rank, unsigned int bankGroup, unsigned int bank, unsigned int row, unsigned int column, unsigned int burstLength, const std::shared_ptr &trans, TraceDB &database) { - traceTime clk = static_cast(database.getGeneralInfo().clkPeriod); + auto clk = static_cast(database.getGeneralInfo().clkPeriod); const CommandLengths &cl = database.getCommandLengths(); if (dbPhaseName == "REQ") diff --git a/DRAMSys/traceAnalyzer/businessObjects/phases/phasefactory.h b/DRAMSys/traceAnalyzer/businessObjects/phases/phasefactory.h index 10d99b54..b875371c 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/phases/phasefactory.h +++ b/DRAMSys/traceAnalyzer/businessObjects/phases/phasefactory.h @@ -49,8 +49,8 @@ class PhaseFactory { public: PhaseFactory() = delete; - static std::shared_ptr CreatePhase(ID id, const QString &dbPhaseName, - const Timespan& span, const Timespan& spanOnDataStrobe, + static std::shared_ptr createPhase(ID id, const QString &dbPhaseName, + Timespan span, Timespan spanOnDataStrobe, unsigned int rank, unsigned int bankGroup, unsigned int bank, unsigned int row, unsigned int column, unsigned int burstLength, const std::shared_ptr &trans, TraceDB &database); }; diff --git a/DRAMSys/traceAnalyzer/businessObjects/timespan.h b/DRAMSys/traceAnalyzer/businessObjects/timespan.h index 4dfb4974..695e0039 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/timespan.h +++ b/DRAMSys/traceAnalyzer/businessObjects/timespan.h @@ -47,7 +47,7 @@ class Timespan traceTime end; public: - Timespan(traceTime begin = 0, traceTime end = 0) : begin(begin), end(end) {} + explicit Timespan(traceTime begin = 0, traceTime end = 0) : begin(begin), end(end) {} traceTime timeCovered() const { return std::abs(End() - Begin()); diff --git a/DRAMSys/traceAnalyzer/data/tracedb.cpp b/DRAMSys/traceAnalyzer/data/tracedb.cpp index 4b17e031..1a446049 100644 --- a/DRAMSys/traceAnalyzer/data/tracedb.cpp +++ b/DRAMSys/traceAnalyzer/data/tracedb.cpp @@ -52,7 +52,7 @@ //define symbol printqueries if all queries should be printed to the console //#define printqueries -TraceDB::TraceDB(QString path, bool openExisting) +TraceDB::TraceDB(const QString& path, bool openExisting) { this->pathToDB = path; @@ -131,8 +131,7 @@ void TraceDB::refreshData() //QueryText must select the fields //TransactionID, Ranges.begin, Ranges.end, Address, TThread, TChannel, TBank, TRow, TColumn, Phases.ID AS PhaseID, PhaseName, PhaseBegin, PhaseEnd -std::vector> TraceDB::getTransactionsWithCustomQuery( - QString queryText) +std::vector> TraceDB::getTransactionsWithCustomQuery(const QString& queryText) { QSqlQuery query(database); query.prepare(queryText); @@ -287,7 +286,7 @@ GeneralInfo TraceDB::getGeneralInfoFromDB() parameter = getParameterFromTable("NumberOfTransactions", "GeneralInfo"); uint64_t numberOfTransactions = parameter.isValid() ? parameter.toULongLong() : 0; parameter = getParameterFromTable("TraceEnd", "GeneralInfo"); - traceTime traceEnd = parameter.isValid() ? parameter.toULongLong() : 0; + traceTime traceEnd = parameter.isValid() ? static_cast(parameter.toULongLong()) : 0; parameter = getParameterFromTable("NumberOfRanks", "GeneralInfo"); unsigned numberOfRanks = parameter.isValid() ? parameter.toUInt() : 1; parameter = getParameterFromTable("NumberOfBankgroups", "GeneralInfo"); @@ -317,9 +316,9 @@ GeneralInfo TraceDB::getGeneralInfoFromDB() parameter = getParameterFromTable("Per2BankOffset", "GeneralInfo"); unsigned per2BankOffset = parameter.isValid() ? parameter.toUInt() : 1; parameter = getParameterFromTable("RowColumnCommandBus", "GeneralInfo"); - bool rowColumnCommandBus = parameter.isValid() ? parameter.toBool() : false; + bool rowColumnCommandBus = parameter.isValid() && parameter.toBool(); parameter = getParameterFromTable("PseudoChannelMode", "GeneralInfo"); - bool pseudoChannelMode = parameter.isValid() ? parameter.toBool() : false; + bool pseudoChannelMode = parameter.isValid() && parameter.toBool(); uint64_t numberOfPhases = getNumberOfPhases(); @@ -395,8 +394,8 @@ CommandLengths TraceDB::getCommandLengthsFromDB() unsigned WRA = getCommandLength("WRA"); unsigned ACT = getCommandLength("ACT"); - unsigned PREPB = getCommandLengthOrElse("PREPB", "PRE"); - unsigned REFPB = getCommandLengthOrElse("REFPB", "REFB"); + unsigned PREPB = getCommandLength("PREPB"); + unsigned REFPB = getCommandLength("REFPB"); unsigned RFMPB = getCommandLength("RFMPB"); unsigned REFP2B = getCommandLength("REFP2B"); @@ -405,8 +404,8 @@ CommandLengths TraceDB::getCommandLengthsFromDB() unsigned REFSB = getCommandLength("REFSB"); unsigned RFMSB = getCommandLength("RFMSB"); - unsigned PREAB = getCommandLengthOrElse("PREAB", "PREA"); - unsigned REFAB = getCommandLengthOrElse("REFAB", "REFA"); + unsigned PREAB = getCommandLength("PREAB"); + unsigned REFAB = getCommandLength("REFAB"); unsigned RFMAB = getCommandLength("RFMAB"); unsigned PDEA = getCommandLength("PDEA"); @@ -562,7 +561,7 @@ std::vector> TraceDB::parseTransactionsFromQuery(QS unsigned int row = query.value(16).toUInt(); unsigned int column = query.value(17).toUInt(); unsigned int burstLength = query.value(18).toUInt(); - auto phase = PhaseFactory::CreatePhase(phaseID, phaseName, span, spanOnDataStrobe, rank, bankGroup, bank, + auto phase = PhaseFactory::createPhase(phaseID, phaseName, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, burstLength, result.at(result.size() - 1), *this); result.at(result.size() - 1)->addPhase(phase); @@ -661,7 +660,7 @@ void TraceDB::executeQuery(QSqlQuery query) } } -QString TraceDB::queryToString(QSqlQuery query) +QString TraceDB::queryToString(const QSqlQuery& query) { QString str = query.lastQuery(); QMapIterator it(query.boundValues()); @@ -678,7 +677,7 @@ void TraceDB::dropAndCreateTables() executeScriptFile("common/static/createTraceDB.sql"); } -void TraceDB::executeScriptFile(QString fileName) +void TraceDB::executeScriptFile(const QString& fileName) { QSqlQuery query(database); QFile scriptFile(fileName); diff --git a/DRAMSys/traceAnalyzer/data/tracedb.h b/DRAMSys/traceAnalyzer/data/tracedb.h index 0ee3e3cb..6f91c33a 100644 --- a/DRAMSys/traceAnalyzer/data/tracedb.h +++ b/DRAMSys/traceAnalyzer/data/tracedb.h @@ -64,7 +64,7 @@ class TraceDB : public QObject Q_OBJECT public: - TraceDB(QString path, bool openExisting); + TraceDB(const QString& path, bool openExisting); const QString &getPathToDB() const { return pathToDB; @@ -86,7 +86,7 @@ public: } std::vector> getTransactionsWithCustomQuery( - QString queryText); + const QString& queryText); std::vector> getTransactionsInTimespan(const Timespan &span, bool updateVisiblePhases = false); std::shared_ptr getNextPrecharge(traceTime time); @@ -133,7 +133,7 @@ private: TransactionQueryTexts queryTexts; void prepareQueries(); void executeQuery(QSqlQuery query); - static QString queryToString(QSqlQuery query); + static QString queryToString(const QSqlQuery& query); std::shared_ptr parseTransactionFromQuery(QSqlQuery &query); std::vector> parseTransactionsFromQuery(QSqlQuery &query, bool updateVisiblePhases = false); @@ -142,7 +142,7 @@ private: void mUpdateDependenciesFromQuery(QSqlQuery &query); static DependencyInfos parseDependencyInfos(QSqlQuery &query, const DependencyInfos::Type infoType); - void executeScriptFile(QString fileName); + void executeScriptFile(const QString& fileName); void dropAndCreateTables(); uint64_t getNumberOfPhases(); diff --git a/DRAMSys/traceAnalyzer/presentation/transactiontreewidget.cpp b/DRAMSys/traceAnalyzer/presentation/transactiontreewidget.cpp index f8e5637f..96c6617a 100644 --- a/DRAMSys/traceAnalyzer/presentation/transactiontreewidget.cpp +++ b/DRAMSys/traceAnalyzer/presentation/transactiontreewidget.cpp @@ -87,9 +87,9 @@ void TransactionTreeWidget::ContextMenuRequested(QPoint point) } } -TransactionTreeWidget::TransactionTreeItem::TransactionTreeItem( - QTreeWidget *parent, const shared_ptr &transaction, - const GeneralInfo &generalInfo) +TransactionTreeWidget::TransactionTreeItem::TransactionTreeItem(QTreeWidget *parent, + const shared_ptr &transaction, + const GeneralInfo &generalInfo) : QTreeWidgetItem(parent, transactionTreeItemType) { this->setText(0, QString::number(transaction->id)); @@ -118,23 +118,19 @@ TransactionTreeWidget::TransactionTreeItem::TransactionTreeItem( phasesNode->setText(0, "Phases"); phasesNode->addChild(new QTreeWidgetItem({"", "Begin", "End"})); - for (const std::shared_ptr& phase : transaction->Phases()) { + for (const std::shared_ptr& phase : transaction->Phases()) AppendPhase(phasesNode, *phase); - } } -void TransactionTreeWidget::TransactionTreeItem::AppendPhase( - QTreeWidgetItem *parent, const Phase &phase) +void TransactionTreeWidget::TransactionTreeItem::AppendPhase(QTreeWidgetItem *parent, const Phase &phase) { - QTreeWidgetItem *node = new QTreeWidgetItem(parent); - node->setText(0, phase.Name() + QString(" [") + QString::number( - phase.Id()) + QString("]")); + auto* node = new QTreeWidgetItem(parent); + node->setText(0, phase.Name() + QString(" [") + QString::number(phase.Id()) + QString("]")); AppendTimespan(node, phase.Span()); } -void TransactionTreeWidget::TransactionTreeItem::AppendTimespan( - QTreeWidgetItem *parent, const Timespan ×pan) +void TransactionTreeWidget::TransactionTreeItem::AppendTimespan(QTreeWidgetItem *parent, const Timespan ×pan) { parent->setText(1, prettyFormatTime(timespan.Begin())); parent->setText(2, prettyFormatTime(timespan.End())); diff --git a/DRAMSys/traceAnalyzer/presentation/transactiontreewidget.h b/DRAMSys/traceAnalyzer/presentation/transactiontreewidget.h index 5cda6399..5963ee43 100644 --- a/DRAMSys/traceAnalyzer/presentation/transactiontreewidget.h +++ b/DRAMSys/traceAnalyzer/presentation/transactiontreewidget.h @@ -78,8 +78,8 @@ private: } private: ID id; - void AppendTimespan(QTreeWidgetItem *parent, const Timespan ×pan); - void AppendPhase(QTreeWidgetItem *parent, const Phase &phase); + static void AppendTimespan(QTreeWidgetItem *parent, const Timespan ×pan); + static void AppendPhase(QTreeWidgetItem *parent, const Phase &phase); }; }; diff --git a/DRAMSys/traceAnalyzer/queryeditor.cpp b/DRAMSys/traceAnalyzer/queryeditor.cpp index 0a97f840..7dc6df5d 100644 --- a/DRAMSys/traceAnalyzer/queryeditor.cpp +++ b/DRAMSys/traceAnalyzer/queryeditor.cpp @@ -53,10 +53,10 @@ QueryEditor::~QueryEditor() delete ui; } -void QueryEditor::init(TraceNavigator *navigator) +void QueryEditor::init(TraceNavigator* _navigator) { - this->navigator = navigator; - ui->transactiontreeWidget->init(navigator); + this->navigator = _navigator; + ui->transactiontreeWidget->init(_navigator); } void QueryEditor::on_executeQuery_clicked() @@ -71,7 +71,7 @@ void QueryEditor::on_executeQuery_clicked() ui->transactiontreeWidget->AppendTransaction(trans); } } - catch (sqlException ex) + catch (const sqlException& ex) { QMessageBox::warning(this, "Query failed", ex.what()); } diff --git a/DRAMSys/traceAnalyzer/queryeditor.h b/DRAMSys/traceAnalyzer/queryeditor.h index 2e87f387..46d3f124 100644 --- a/DRAMSys/traceAnalyzer/queryeditor.h +++ b/DRAMSys/traceAnalyzer/queryeditor.h @@ -53,7 +53,7 @@ class QueryEditor : public QWidget public: explicit QueryEditor(QWidget *parent = 0); ~QueryEditor(); - void init(TraceNavigator *navigator); + void init(TraceNavigator *_navigator); private Q_SLOTS: void on_executeQuery_clicked(); From e9942d5aa254b2d3b068e566b37392ebd590698a Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Mon, 9 May 2022 13:09:19 +0200 Subject: [PATCH 11/29] First working implementation. --- DRAMSys/library/src/common/TlmRecorder.cpp | 37 ++- DRAMSys/library/src/common/TlmRecorder.h | 2 +- DRAMSys/library/src/common/dramExtensions.cpp | 100 ++++++++ DRAMSys/library/src/common/dramExtensions.h | 38 +++ DRAMSys/library/src/controller/Controller.cpp | 221 ++++++++++++++---- DRAMSys/library/src/controller/Controller.h | 16 ++ 6 files changed, 358 insertions(+), 56 deletions(-) diff --git a/DRAMSys/library/src/common/TlmRecorder.cpp b/DRAMSys/library/src/common/TlmRecorder.cpp index c062999e..390aacf5 100644 --- a/DRAMSys/library/src/common/TlmRecorder.cpp +++ b/DRAMSys/library/src/common/TlmRecorder.cpp @@ -119,22 +119,41 @@ void TlmRecorder::recordPhase(tlm_generic_payload& trans, const tlm_phase& phase { const sc_time& currentTime = sc_time_stamp(); - if (currentTransactionsInSystem.find(&trans) == currentTransactionsInSystem.end()) - introduceTransactionSystem(trans); - - if (phase == BEGIN_REQ || phase == BEGIN_RESP) + if (phase == BEGIN_REQ) + { + introduceTransactionToSystem(trans); + std::string phaseName = getPhaseName(phase).substr(6); + currentTransactionsInSystem.at(&trans).recordedPhases.emplace_back(phaseName, currentTime + delay); + } + if (phase == BEGIN_RESP) { std::string phaseName = getPhaseName(phase).substr(6); currentTransactionsInSystem.at(&trans).recordedPhases.emplace_back(phaseName, currentTime + delay); } - else if (phase == END_REQ || phase == END_RESP) + else if (phase == END_REQ) { - assert(getPhaseName(phase).substr(4) == currentTransactionsInSystem.at(&trans).recordedPhases.back().name); - // TODO: this assumes that the controller does not start with a transaction until END_REQ has been sent, which is not true any more for big transactions + // BEGIN_REQ is always the first phase of a normal transaction + currentTransactionsInSystem.at(&trans).recordedPhases.front().interval.end = currentTime + delay; + } + else if (phase == END_RESP) + { + // BEGIN_RESP is always the last phase of a normal transaction at this point currentTransactionsInSystem.at(&trans).recordedPhases.back().interval.end = currentTime + delay; } else if (isFixedCommandPhase(phase)) { + tlm_generic_payload* keyTrans; + if (ChildExtension::isChildTrans(trans)) + { + keyTrans = &trans.get_extension()->getParentTrans(); + } + else + { + if (currentTransactionsInSystem.find(&trans) == currentTransactionsInSystem.end()) + introduceTransactionToSystem(trans); + keyTrans = &trans; + } + std::string phaseName = getPhaseName(phase).substr(6); // remove "BEGIN_" const ControllerExtension& extension = ControllerExtension::getExtension(trans); TimeInterval intervalOnDataStrobe; @@ -145,7 +164,7 @@ void TlmRecorder::recordPhase(tlm_generic_payload& trans, const tlm_phase& phase intervalOnDataStrobe.end = currentTime + intervalOnDataStrobe.end; } - currentTransactionsInSystem.at(&trans).recordedPhases.emplace_back(std::move(phaseName), + currentTransactionsInSystem.at(keyTrans).recordedPhases.emplace_back(std::move(phaseName), std::move(TimeInterval(currentTime + delay, currentTime + delay + memSpec.getExecutionTime(Command(phase), trans))), std::move(intervalOnDataStrobe), extension.getRank(), extension.getBankGroup(), extension.getBank(), @@ -181,7 +200,7 @@ void TlmRecorder::recordDebugMessage(const std::string &message, const sc_time & // ------------- internal ----------------------- -void TlmRecorder::introduceTransactionSystem(tlm_generic_payload& trans) +void TlmRecorder::introduceTransactionToSystem(tlm_generic_payload& trans) { totalNumTransactions++; diff --git a/DRAMSys/library/src/common/TlmRecorder.h b/DRAMSys/library/src/common/TlmRecorder.h index 70664e63..c11985a6 100644 --- a/DRAMSys/library/src/common/TlmRecorder.h +++ b/DRAMSys/library/src/common/TlmRecorder.h @@ -136,7 +136,7 @@ private: void openDB(const std::string &dbName); void closeConnection(); - void introduceTransactionSystem(tlm::tlm_generic_payload &trans); + void introduceTransactionToSystem(tlm::tlm_generic_payload &trans); void removeTransactionFromSystem(tlm::tlm_generic_payload &trans); void terminateRemainingTransactions(); diff --git a/DRAMSys/library/src/common/dramExtensions.cpp b/DRAMSys/library/src/common/dramExtensions.cpp index 3c486087..9bb02758 100644 --- a/DRAMSys/library/src/common/dramExtensions.cpp +++ b/DRAMSys/library/src/common/dramExtensions.cpp @@ -360,3 +360,103 @@ bool operator !=(const Column &lhs, const Column &rhs) { return !(lhs == rhs); } + + +tlm::tlm_extension_base* ChildExtension::clone() const +{ + return new ChildExtension(*parentTrans); +} + +void ChildExtension::copy_from(const tlm::tlm_extension_base& ext) +{ + const auto& cpyFrom = dynamic_cast(ext); + parentTrans = cpyFrom.parentTrans; +} + +tlm::tlm_generic_payload& ChildExtension::getParentTrans() +{ + return *parentTrans; +} + +void ChildExtension::setExtension(tlm::tlm_generic_payload& childTrans, tlm::tlm_generic_payload& parentTrans) +{ + auto* extension = childTrans.get_extension(); + + if (extension != nullptr) + { + extension->parentTrans = &parentTrans; + } + else + { + extension = new ChildExtension(parentTrans); + childTrans.set_auto_extension(extension); + } +} + +bool ChildExtension::isChildTrans(const tlm::tlm_generic_payload& trans) +{ + if (trans.get_extension() != nullptr) + return true; + else + return false; +} + +bool ChildExtension::notifyChildTransCompletion() +{ + return parentTrans->get_extension()->notifyChildTransCompletion(); +} + +tlm_extension_base* ParentExtension::clone() const +{ + return new ParentExtension(childTranses); +} + +void ParentExtension::copy_from(const tlm_extension_base& ext) +{ + const auto& cpyFrom = dynamic_cast(ext); + childTranses = cpyFrom.childTranses; +} + +bool ParentExtension::isParentTrans(const tlm::tlm_generic_payload& trans) +{ + auto* extension = trans.get_extension(); + if (extension != nullptr) + return !extension->childTranses.empty(); + else + return false; +} + +void ParentExtension::setExtension(tlm::tlm_generic_payload& parentTrans, std::vector childTranses) +{ + auto* extension = parentTrans.get_extension(); + + if (extension != nullptr) + { + extension->childTranses = std::move(childTranses); + extension->nextEndReqChildId = 0; + extension->completedChildTranses = 0; + } + else + { + extension = new ParentExtension(std::move(childTranses)); + parentTrans.set_auto_extension(extension); + } +} + +const std::vector& ParentExtension::getChildTranses() +{ + return childTranses; +} + +bool ParentExtension::notifyChildTransCompletion() +{ + completedChildTranses++; + return completedChildTranses == childTranses.size(); +} + +void ParentExtension::releaseChildTranses() +{ + std::for_each(childTranses.begin(), childTranses.end(), + [](tlm::tlm_generic_payload* childTrans){childTrans->release();}); + childTranses.clear(); +} \ No newline at end of file diff --git a/DRAMSys/library/src/common/dramExtensions.h b/DRAMSys/library/src/common/dramExtensions.h index 7f164186..76e61e8c 100644 --- a/DRAMSys/library/src/common/dramExtensions.h +++ b/DRAMSys/library/src/common/dramExtensions.h @@ -252,4 +252,42 @@ bool operator!=(const Row &lhs, const Row &rhs); bool operator==(const Column &lhs, const Column &rhs); bool operator!=(const Column &lhs, const Column &rhs); +class ChildExtension : public tlm::tlm_extension +{ +private: + tlm::tlm_generic_payload* parentTrans; + explicit ChildExtension(tlm::tlm_generic_payload& parentTrans) : parentTrans(&parentTrans) {} + +public: + //ChildExtension() = delete; + + tlm::tlm_extension_base* clone() const override; + void copy_from(const tlm::tlm_extension_base& ext) override; + tlm::tlm_generic_payload& getParentTrans(); + static void setExtension(tlm::tlm_generic_payload& childTrans, tlm::tlm_generic_payload& parentTrans); + static bool isChildTrans(const tlm::tlm_generic_payload& trans); + bool notifyChildTransCompletion(); +}; + +class ParentExtension : public tlm::tlm_extension +{ +private: + std::vector childTranses; + unsigned nextEndReqChildId = 0; + unsigned completedChildTranses = 0; + explicit ParentExtension(std::vector _childTranses) + : childTranses(std::move(_childTranses)) {} + +public: + ParentExtension() = delete; + + tlm_extension_base* clone() const override; + void copy_from(const tlm_extension_base& ext) override; + static bool isParentTrans(const tlm::tlm_generic_payload& trans); + static void setExtension(tlm::tlm_generic_payload& parentTrans, std::vector childTranses); + const std::vector& getChildTranses(); + bool notifyChildTransCompletion(); + void releaseChildTranses(); +}; + #endif // DRAMEXTENSIONS_H diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index 990958bd..b735d97f 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -72,7 +72,8 @@ using namespace tlm; Controller::Controller(const sc_module_name& name, const Configuration& config, const AddressDecoder& addressDecoder) : ControllerIF(name, config), addressDecoder(addressDecoder), thinkDelayFw(config.thinkDelayFw), thinkDelayBw(config.thinkDelayBw), - phyDelayFw(config.phyDelayFw), phyDelayBw(config.phyDelayBw) + phyDelayFw(config.phyDelayFw), phyDelayBw(config.phyDelayBw), + maxBytesPerBurst(config.memSpec->maxBytesPerBurst) { SC_METHOD(controllerMethod); sensitive << beginReqEvent << endRespEvent << controllerEvent << dataResponseEvent; @@ -370,13 +371,6 @@ tlm_sync_enum Controller::nb_transport_fw(tlm_generic_payload &trans, transToAcquire.payload = &trans; transToAcquire.time = sc_time_stamp() + delay; beginReqEvent.notify(delay); - - DecodedAddress decodedAddress = addressDecoder.decodeAddress(transToAcquire.payload->get_address()); - ControllerExtension::setAutoExtension(*transToAcquire.payload, nextChannelPayloadIDToAppend++, - Rank(decodedAddress.rank), BankGroup(decodedAddress.bankgroup), - Bank(decodedAddress.bank), Row(decodedAddress.row), - Column(decodedAddress.column), - transToAcquire.payload->get_data_length() / memSpec.bytesPerBeat); } else if (phase == END_RESP) { @@ -408,34 +402,62 @@ void Controller::manageRequests(const sc_time &delay) { if (transToAcquire.payload != nullptr && transToAcquire.time <= sc_time_stamp()) { - // Check size of transaction -// unsigned numSubTrans = transToAcquire.payload->get_data_length() / memSpec.maxBytesPerBurst; -// if (numSubTrans > 1) -// { -// // Split create child transactions -// // Address decoding!!! -// } - + // TODO: here we assume that the scheduler always has space not only for a single burst transaction but for a maximum size transaction if (scheduler->hasBufferSpace()) { - NDEBUG_UNUSED(uint64_t id) = ControllerExtension::getChannelPayloadID(*transToAcquire.payload); - PRINTDEBUGMESSAGE(name(), "Payload " + std::to_string(id) + " entered system."); + //NDEBUG_UNUSED(uint64_t id) = ControllerExtension::getChannelPayloadID(*transToAcquire.payload); + //PRINTDEBUGMESSAGE(name(), "Payload " + std::to_string(id) + " entered system."); if (totalNumberOfPayloads == 0) idleTimeCollector.end(); - totalNumberOfPayloads++; + totalNumberOfPayloads++; // seems to be ok - Rank rank = ControllerExtension::getRank(*transToAcquire.payload); - if (ranksNumberOfPayloads[rank.ID()] == 0) - powerDownManagers[rank.ID()]->triggerExit(); - - ranksNumberOfPayloads[rank.ID()]++; - - scheduler->storeRequest(*transToAcquire.payload); transToAcquire.payload->acquire(); - Bank bank = ControllerExtension::getBank(*transToAcquire.payload); - bankMachines[bank.ID()]->start(); + unsigned numChildTranses = transToAcquire.payload->get_data_length() / maxBytesPerBurst; + if (numChildTranses <= 1) + { + DecodedAddress decodedAddress = addressDecoder.decodeAddress(transToAcquire.payload->get_address()); + ControllerExtension::setAutoExtension(*transToAcquire.payload, nextChannelPayloadIDToAppend++, + Rank(decodedAddress.rank), BankGroup(decodedAddress.bankgroup), + Bank(decodedAddress.bank), Row(decodedAddress.row), + Column(decodedAddress.column), + transToAcquire.payload->get_data_length() / memSpec.bytesPerBeat); + + Rank rank = Rank(decodedAddress.rank); + if (ranksNumberOfPayloads[rank.ID()] == 0) + powerDownManagers[rank.ID()]->triggerExit(); + ranksNumberOfPayloads[rank.ID()]++; + + scheduler->storeRequest(*transToAcquire.payload); + Bank bank = Bank(decodedAddress.bank); + bankMachines[bank.ID()]->start(); + } + else + { + createChildTranses(*transToAcquire.payload, numChildTranses); + const std::vector& childTranses = + transToAcquire.payload->get_extension()->getChildTranses(); + for (auto* childTrans : childTranses) + { + DecodedAddress decodedAddress = addressDecoder.decodeAddress(childTrans->get_address()); + ControllerExtension::setAutoExtension(*childTrans, nextChannelPayloadIDToAppend, + Rank(decodedAddress.rank), BankGroup(decodedAddress.bankgroup), + Bank(decodedAddress.bank), Row(decodedAddress.row), + Column(decodedAddress.column), + childTrans->get_data_length() / memSpec.bytesPerBeat); + + Rank rank = Rank(decodedAddress.rank); + if (ranksNumberOfPayloads[rank.ID()] == 0) + powerDownManagers[rank.ID()]->triggerExit(); + ranksNumberOfPayloads[rank.ID()]++; + + scheduler->storeRequest(*childTrans); + Bank bank = Bank(decodedAddress.bank); + bankMachines[bank.ID()]->start(); + } + nextChannelPayloadIDToAppend++; + } transToAcquire.payload->set_response_status(TLM_OK_RESPONSE); tlm_phase bwPhase = END_REQ; @@ -463,7 +485,7 @@ void Controller::manageResponses() numberOfBeatsServed += ControllerExtension::getBurstLength(*transToRelease.payload); transToRelease.payload->release(); transToRelease.payload = nullptr; - totalNumberOfPayloads--; + totalNumberOfPayloads--; // Important!! has to be done once for parent transaction if (totalNumberOfPayloads == 0) { @@ -471,15 +493,42 @@ void Controller::manageResponses() } else { - transToRelease.payload = respQueue->nextPayload(); + // TODO: hier fehlt noch was + tlm_generic_payload* nextPayloadInQueue = respQueue->nextPayload(); + //transToRelease.payload = respQueue->nextPayload(); - if (transToRelease.payload != nullptr) + if (nextPayloadInQueue != nullptr) { - // last payload was released in this cycle - tlm_phase bwPhase = BEGIN_RESP; - sc_time bwDelay = memSpec.tCK; - sendToFrontend(*transToRelease.payload, bwPhase, bwDelay); - transToRelease.time = sc_max_time(); + if (ChildExtension::isChildTrans(*nextPayloadInQueue)) + { + tlm_generic_payload& parentTrans = nextPayloadInQueue->get_extension()->getParentTrans(); + bool allChildTransesCompleted = parentTrans.get_extension()->notifyChildTransCompletion(); + if (allChildTransesCompleted) + { + parentTrans.get_extension()->releaseChildTranses(); + transToRelease.payload = &parentTrans; + // last payload was released in this cycle + tlm_phase bwPhase = BEGIN_RESP; + sc_time bwDelay = memSpec.tCK; + sendToFrontend(*transToRelease.payload, bwPhase, bwDelay); + transToRelease.time = sc_max_time(); + } + else + { + sc_time triggerTime = respQueue->getTriggerTime(); + if (triggerTime != sc_max_time()) + dataResponseEvent.notify(triggerTime - sc_time_stamp()); + } + } + else + { + transToRelease.payload = nextPayloadInQueue; + // last payload was released in this cycle + tlm_phase bwPhase = BEGIN_RESP; + sc_time bwDelay = memSpec.tCK; + sendToFrontend(*transToRelease.payload, bwPhase, bwDelay); + transToRelease.time = sc_max_time(); + } } else { @@ -492,19 +541,50 @@ void Controller::manageResponses() } else { - transToRelease.payload = respQueue->nextPayload(); + tlm_generic_payload* nextPayloadInQueue = respQueue->nextPayload(); - if (transToRelease.payload != nullptr) + if (nextPayloadInQueue != nullptr) { - tlm_phase bwPhase = BEGIN_RESP; - sc_time bwDelay; - if (transToRelease.time == sc_time_stamp()) // last payload was released in this cycle - bwDelay = memSpec.tCK; - else - bwDelay = SC_ZERO_TIME; + if (ChildExtension::isChildTrans(*nextPayloadInQueue)) + { + tlm_generic_payload& parentTrans = nextPayloadInQueue->get_extension()->getParentTrans(); + bool allChildTransesCompleted = parentTrans.get_extension()->notifyChildTransCompletion(); + if (allChildTransesCompleted) + { + parentTrans.get_extension()->releaseChildTranses(); + transToRelease.payload = &parentTrans; + // last payload was released in this cycle + tlm_phase bwPhase = BEGIN_RESP; + sc_time bwDelay; + if (transToRelease.time == sc_time_stamp()) // last payload was released in this cycle + bwDelay = memSpec.tCK; + else + bwDelay = SC_ZERO_TIME; - sendToFrontend(*transToRelease.payload, bwPhase, bwDelay); - transToRelease.time = sc_max_time(); + sendToFrontend(*transToRelease.payload, bwPhase, bwDelay); + transToRelease.time = sc_max_time(); + } + else + { + sc_time triggerTime = respQueue->getTriggerTime(); + if (triggerTime != sc_max_time()) + dataResponseEvent.notify(triggerTime - sc_time_stamp()); + } + } + else + { + transToRelease.payload = nextPayloadInQueue; + // last payload was released in this cycle + tlm_phase bwPhase = BEGIN_RESP; + sc_time bwDelay; + if (transToRelease.time == sc_time_stamp()) // last payload was released in this cycle + bwDelay = memSpec.tCK; + else + bwDelay = SC_ZERO_TIME; + + sendToFrontend(*transToRelease.payload, bwPhase, bwDelay); + transToRelease.time = sc_max_time(); + } } else { @@ -519,3 +599,52 @@ void Controller::sendToFrontend(tlm_generic_payload& payload, tlm_phase& phase, { tSocket->nb_transport_bw(payload, phase, delay); } + +Controller::MemoryManager::~MemoryManager() +{ + while (!freePayloads.empty()) + { + tlm_generic_payload* payload = freePayloads.top(); + freePayloads.pop(); + payload->reset(); + delete payload; + } + +} + +tlm::tlm_generic_payload& Controller::MemoryManager::allocate() +{ + if (freePayloads.empty()) + { + return *new tlm_generic_payload(this); + } + else + { + tlm_generic_payload* result = freePayloads.top(); + freePayloads.pop(); + return *result; + } +} + +void Controller::MemoryManager::free(tlm::tlm_generic_payload* payload) +{ + freePayloads.push(payload); +} + +void Controller::createChildTranses(tlm::tlm_generic_payload& parentTrans, unsigned int numChildTranses) +{ + std::vector childTranses; + + for (unsigned childId = 0; childId < numChildTranses; childId++) + { + tlm_generic_payload& childTrans = memoryManager.allocate(); + childTrans.acquire(); + childTrans.set_command(parentTrans.get_command()); + childTrans.set_address(parentTrans.get_address() + childId * maxBytesPerBurst); + childTrans.set_data_length(maxBytesPerBurst); + childTrans.set_data_ptr(parentTrans.get_data_ptr() + childId * maxBytesPerBurst); + ChildExtension::setExtension(childTrans, parentTrans); + childTranses.push_back(&childTrans); + } + ParentExtension::setExtension(parentTrans, std::move(childTranses)); +} \ No newline at end of file diff --git a/DRAMSys/library/src/controller/Controller.h b/DRAMSys/library/src/controller/Controller.h index e8339bc7..2432099d 100644 --- a/DRAMSys/library/src/controller/Controller.h +++ b/DRAMSys/library/src/controller/Controller.h @@ -37,6 +37,7 @@ #include +#include #include #include @@ -100,6 +101,21 @@ private: void manageRequests(const sc_core::sc_time &delay); sc_core::sc_event beginReqEvent, endRespEvent, controllerEvent, dataResponseEvent; + + const unsigned maxBytesPerBurst; + + void createChildTranses(tlm::tlm_generic_payload& parentTrans, unsigned numChildTranses); + + class MemoryManager : public tlm::tlm_mm_interface + { + public: + ~MemoryManager() override; + tlm::tlm_generic_payload& allocate(); + void free(tlm::tlm_generic_payload* payload) override; + + private: + std::stack freePayloads; + } memoryManager; }; #endif // CONTROLLER_H From 9293a4871717fff2775cd87792930405f59cb51c Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Tue, 10 May 2022 14:08:31 +0200 Subject: [PATCH 12/29] Simplify manageResponses, segmentation fault for large transactions! --- DRAMSys/library/src/common/TlmRecorder.cpp | 4 +- DRAMSys/library/src/common/TlmRecorder.h | 3 +- DRAMSys/library/src/common/dramExtensions.cpp | 40 +++--- DRAMSys/library/src/common/dramExtensions.h | 6 +- DRAMSys/library/src/controller/Controller.cpp | 121 +++++------------- 5 files changed, 58 insertions(+), 116 deletions(-) diff --git a/DRAMSys/library/src/common/TlmRecorder.cpp b/DRAMSys/library/src/common/TlmRecorder.cpp index 390aacf5..81b2f1d3 100644 --- a/DRAMSys/library/src/common/TlmRecorder.cpp +++ b/DRAMSys/library/src/common/TlmRecorder.cpp @@ -145,7 +145,7 @@ void TlmRecorder::recordPhase(tlm_generic_payload& trans, const tlm_phase& phase tlm_generic_payload* keyTrans; if (ChildExtension::isChildTrans(trans)) { - keyTrans = &trans.get_extension()->getParentTrans(); + keyTrans = &ChildExtension::getParentTrans(trans); } else { @@ -230,7 +230,7 @@ void TlmRecorder::removeTransactionFromSystem(tlm_generic_payload &trans) PRINTDEBUGMESSAGE(name, "Removing transaction #" + std::to_string(currentTransactionsInSystem.at(&trans).id)); - Transaction &recordingData = currentTransactionsInSystem.at(&trans); + Transaction& recordingData = currentTransactionsInSystem.at(&trans); currentDataBuffer->push_back(recordingData); currentTransactionsInSystem.erase(&trans); diff --git a/DRAMSys/library/src/common/TlmRecorder.h b/DRAMSys/library/src/common/TlmRecorder.h index c11985a6..7e0cc505 100644 --- a/DRAMSys/library/src/common/TlmRecorder.h +++ b/DRAMSys/library/src/common/TlmRecorder.h @@ -89,6 +89,7 @@ private: struct Transaction { + Transaction(const Transaction& other) = default; Transaction(uint64_t id, uint64_t address, unsigned int dataLength, char cmd, const sc_core::sc_time& timeOfGeneration, Thread thread, Channel channel) : id(id), address(address), dataLength(dataLength), cmd(cmd), timeOfGeneration(timeOfGeneration), @@ -154,7 +155,7 @@ private: std::vector *storageDataBuffer; std::thread storageThread; - std::unordered_map currentTransactionsInSystem; + std::unordered_map currentTransactionsInSystem; uint64_t totalNumTransactions; sc_core::sc_time simulationTimeCoveredByRecording; diff --git a/DRAMSys/library/src/common/dramExtensions.cpp b/DRAMSys/library/src/common/dramExtensions.cpp index 9bb02758..b77a57ba 100644 --- a/DRAMSys/library/src/common/dramExtensions.cpp +++ b/DRAMSys/library/src/common/dramExtensions.cpp @@ -378,6 +378,11 @@ tlm::tlm_generic_payload& ChildExtension::getParentTrans() return *parentTrans; } +tlm::tlm_generic_payload& ChildExtension::getParentTrans(tlm::tlm_generic_payload& childTrans) +{ + return childTrans.get_extension()->getParentTrans(); +} + void ChildExtension::setExtension(tlm::tlm_generic_payload& childTrans, tlm::tlm_generic_payload& parentTrans) { auto* extension = childTrans.get_extension(); @@ -401,11 +406,6 @@ bool ChildExtension::isChildTrans(const tlm::tlm_generic_payload& trans) return false; } -bool ChildExtension::notifyChildTransCompletion() -{ - return parentTrans->get_extension()->notifyChildTransCompletion(); -} - tlm_extension_base* ParentExtension::clone() const { return new ParentExtension(childTranses); @@ -417,15 +417,6 @@ void ParentExtension::copy_from(const tlm_extension_base& ext) childTranses = cpyFrom.childTranses; } -bool ParentExtension::isParentTrans(const tlm::tlm_generic_payload& trans) -{ - auto* extension = trans.get_extension(); - if (extension != nullptr) - return !extension->childTranses.empty(); - else - return false; -} - void ParentExtension::setExtension(tlm::tlm_generic_payload& parentTrans, std::vector childTranses) { auto* extension = parentTrans.get_extension(); @@ -433,7 +424,6 @@ void ParentExtension::setExtension(tlm::tlm_generic_payload& parentTrans, std::v if (extension != nullptr) { extension->childTranses = std::move(childTranses); - extension->nextEndReqChildId = 0; extension->completedChildTranses = 0; } else @@ -451,12 +441,20 @@ const std::vector& ParentExtension::getChildTranses() bool ParentExtension::notifyChildTransCompletion() { completedChildTranses++; - return completedChildTranses == childTranses.size(); + if (completedChildTranses == childTranses.size()) + { + std::for_each(childTranses.begin(), childTranses.end(), + [](tlm::tlm_generic_payload* childTrans){childTrans->release();}); + childTranses.clear(); + return true; + } + else + { + return false; + } } -void ParentExtension::releaseChildTranses() +bool ParentExtension::notifyChildTransCompletion(tlm::tlm_generic_payload& trans) { - std::for_each(childTranses.begin(), childTranses.end(), - [](tlm::tlm_generic_payload* childTrans){childTrans->release();}); - childTranses.clear(); -} \ No newline at end of file + return trans.get_extension()->notifyChildTransCompletion(); +} diff --git a/DRAMSys/library/src/common/dramExtensions.h b/DRAMSys/library/src/common/dramExtensions.h index 76e61e8c..7a8a80c1 100644 --- a/DRAMSys/library/src/common/dramExtensions.h +++ b/DRAMSys/library/src/common/dramExtensions.h @@ -264,16 +264,15 @@ public: tlm::tlm_extension_base* clone() const override; void copy_from(const tlm::tlm_extension_base& ext) override; tlm::tlm_generic_payload& getParentTrans(); + static tlm::tlm_generic_payload& getParentTrans(tlm::tlm_generic_payload& childTrans); static void setExtension(tlm::tlm_generic_payload& childTrans, tlm::tlm_generic_payload& parentTrans); static bool isChildTrans(const tlm::tlm_generic_payload& trans); - bool notifyChildTransCompletion(); }; class ParentExtension : public tlm::tlm_extension { private: std::vector childTranses; - unsigned nextEndReqChildId = 0; unsigned completedChildTranses = 0; explicit ParentExtension(std::vector _childTranses) : childTranses(std::move(_childTranses)) {} @@ -283,11 +282,10 @@ public: tlm_extension_base* clone() const override; void copy_from(const tlm_extension_base& ext) override; - static bool isParentTrans(const tlm::tlm_generic_payload& trans); static void setExtension(tlm::tlm_generic_payload& parentTrans, std::vector childTranses); const std::vector& getChildTranses(); bool notifyChildTransCompletion(); - void releaseChildTranses(); + static bool notifyChildTransCompletion(tlm::tlm_generic_payload& trans); }; #endif // DRAMEXTENSIONS_H diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index b735d97f..248efc6f 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -477,104 +477,30 @@ void Controller::manageResponses() if (transToRelease.payload != nullptr) { assert(transToRelease.time >= sc_time_stamp()); - if (transToRelease.time == sc_time_stamp()) + if (transToRelease.time == sc_time_stamp()) // END_RESP completed { - NDEBUG_UNUSED(uint64_t id) = ControllerExtension::getChannelPayloadID(*transToRelease.payload); - PRINTDEBUGMESSAGE(name(), "Payload " + std::to_string(id) + " left system."); - - numberOfBeatsServed += ControllerExtension::getBurstLength(*transToRelease.payload); transToRelease.payload->release(); transToRelease.payload = nullptr; - totalNumberOfPayloads--; // Important!! has to be done once for parent transaction + totalNumberOfPayloads--; if (totalNumberOfPayloads == 0) { idleTimeCollector.start(); } - else - { - // TODO: hier fehlt noch was - tlm_generic_payload* nextPayloadInQueue = respQueue->nextPayload(); - //transToRelease.payload = respQueue->nextPayload(); - - if (nextPayloadInQueue != nullptr) - { - if (ChildExtension::isChildTrans(*nextPayloadInQueue)) - { - tlm_generic_payload& parentTrans = nextPayloadInQueue->get_extension()->getParentTrans(); - bool allChildTransesCompleted = parentTrans.get_extension()->notifyChildTransCompletion(); - if (allChildTransesCompleted) - { - parentTrans.get_extension()->releaseChildTranses(); - transToRelease.payload = &parentTrans; - // last payload was released in this cycle - tlm_phase bwPhase = BEGIN_RESP; - sc_time bwDelay = memSpec.tCK; - sendToFrontend(*transToRelease.payload, bwPhase, bwDelay); - transToRelease.time = sc_max_time(); - } - else - { - sc_time triggerTime = respQueue->getTriggerTime(); - if (triggerTime != sc_max_time()) - dataResponseEvent.notify(triggerTime - sc_time_stamp()); - } - } - else - { - transToRelease.payload = nextPayloadInQueue; - // last payload was released in this cycle - tlm_phase bwPhase = BEGIN_RESP; - sc_time bwDelay = memSpec.tCK; - sendToFrontend(*transToRelease.payload, bwPhase, bwDelay); - transToRelease.time = sc_max_time(); - } - } - else - { - sc_time triggerTime = respQueue->getTriggerTime(); - if (triggerTime != sc_max_time()) - dataResponseEvent.notify(triggerTime - sc_time_stamp()); - } - } } } - else + + tlm_generic_payload* nextPayloadInRespQueue = respQueue->nextPayload(); + + if (nextPayloadInRespQueue != nullptr) { - tlm_generic_payload* nextPayloadInQueue = respQueue->nextPayload(); - - if (nextPayloadInQueue != nullptr) + numberOfBeatsServed += ControllerExtension::getBurstLength(*nextPayloadInRespQueue); + if (ChildExtension::isChildTrans(*nextPayloadInRespQueue)) { - if (ChildExtension::isChildTrans(*nextPayloadInQueue)) + tlm_generic_payload& parentTrans = ChildExtension::getParentTrans(*nextPayloadInRespQueue); + if (ParentExtension::notifyChildTransCompletion(parentTrans)) { - tlm_generic_payload& parentTrans = nextPayloadInQueue->get_extension()->getParentTrans(); - bool allChildTransesCompleted = parentTrans.get_extension()->notifyChildTransCompletion(); - if (allChildTransesCompleted) - { - parentTrans.get_extension()->releaseChildTranses(); - transToRelease.payload = &parentTrans; - // last payload was released in this cycle - tlm_phase bwPhase = BEGIN_RESP; - sc_time bwDelay; - if (transToRelease.time == sc_time_stamp()) // last payload was released in this cycle - bwDelay = memSpec.tCK; - else - bwDelay = SC_ZERO_TIME; - - sendToFrontend(*transToRelease.payload, bwPhase, bwDelay); - transToRelease.time = sc_max_time(); - } - else - { - sc_time triggerTime = respQueue->getTriggerTime(); - if (triggerTime != sc_max_time()) - dataResponseEvent.notify(triggerTime - sc_time_stamp()); - } - } - else - { - transToRelease.payload = nextPayloadInQueue; - // last payload was released in this cycle + transToRelease.payload = &parentTrans; tlm_phase bwPhase = BEGIN_RESP; sc_time bwDelay; if (transToRelease.time == sc_time_stamp()) // last payload was released in this cycle @@ -585,14 +511,33 @@ void Controller::manageResponses() sendToFrontend(*transToRelease.payload, bwPhase, bwDelay); transToRelease.time = sc_max_time(); } + else + { + sc_time triggerTime = respQueue->getTriggerTime(); + if (triggerTime != sc_max_time()) + dataResponseEvent.notify(triggerTime - sc_time_stamp()); + } } else { - sc_time triggerTime = respQueue->getTriggerTime(); - if (triggerTime != sc_max_time()) - dataResponseEvent.notify(triggerTime - sc_time_stamp()); + transToRelease.payload = nextPayloadInRespQueue; + tlm_phase bwPhase = BEGIN_RESP; + sc_time bwDelay; + if (transToRelease.time == sc_time_stamp()) // last payload was released in this cycle + bwDelay = memSpec.tCK; + else + bwDelay = SC_ZERO_TIME; + + sendToFrontend(*transToRelease.payload, bwPhase, bwDelay); + transToRelease.time = sc_max_time(); } } + else + { + sc_time triggerTime = respQueue->getTriggerTime(); + if (triggerTime != sc_max_time()) + dataResponseEvent.notify(triggerTime - sc_time_stamp()); + } } void Controller::sendToFrontend(tlm_generic_payload& payload, tlm_phase& phase, sc_time& delay) From e1444a45a4c1fc4bcd856338513dd833bb43f1ec Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Tue, 10 May 2022 17:09:02 +0200 Subject: [PATCH 13/29] Add debugging example config. --- DRAMSys/library/resources/simulations/ddr5-example.json | 8 +++++++- DRAMSys/library/src/simulation/DRAMSysRecordable.cpp | 1 + 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/DRAMSys/library/resources/simulations/ddr5-example.json b/DRAMSys/library/resources/simulations/ddr5-example.json index e85d1b92..695b783a 100644 --- a/DRAMSys/library/resources/simulations/ddr5-example.json +++ b/DRAMSys/library/resources/simulations/ddr5-example.json @@ -9,7 +9,13 @@ "tracesetup": [ { "clkMhz": 2000, - "name": "ddr3_example.stl" + "name": "gen0", + "type": "generator", + "numRequests": 20, + "rwRatio": 1, + "addressDistribution": "random", + "dataLength": 64, + "seed": 1 } ] } diff --git a/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp b/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp index 24e9a2a9..aae02150 100644 --- a/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp +++ b/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp @@ -92,6 +92,7 @@ void DRAMSysRecordable::end_of_simulation() void DRAMSysRecordable::setupTlmRecorders(const std::string& traceName, const DRAMSysConfiguration::Configuration& configLib) { + //tlmRecorders.reserve(config.memSpec->numberOfChannels); // Create TLM Recorders, one per channel. for (std::size_t i = 0; i < config.memSpec->numberOfChannels; i++) { From 21f08335b2cf3771a3f9ad5b045be74563aa23a7 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Wed, 11 May 2022 15:56:04 +0200 Subject: [PATCH 14/29] Revert debug example, fix segfault in TlmRecorder. --- DRAMSys/library/resources/simulations/ddr5-example.json | 8 +------- DRAMSys/library/src/simulation/DRAMSysRecordable.cpp | 5 ++++- 2 files changed, 5 insertions(+), 8 deletions(-) diff --git a/DRAMSys/library/resources/simulations/ddr5-example.json b/DRAMSys/library/resources/simulations/ddr5-example.json index 695b783a..e85d1b92 100644 --- a/DRAMSys/library/resources/simulations/ddr5-example.json +++ b/DRAMSys/library/resources/simulations/ddr5-example.json @@ -9,13 +9,7 @@ "tracesetup": [ { "clkMhz": 2000, - "name": "gen0", - "type": "generator", - "numRequests": 20, - "rwRatio": 1, - "addressDistribution": "random", - "dataLength": 64, - "seed": 1 + "name": "ddr3_example.stl" } ] } diff --git a/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp b/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp index aae02150..324f6e2c 100644 --- a/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp +++ b/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp @@ -92,8 +92,11 @@ void DRAMSysRecordable::end_of_simulation() void DRAMSysRecordable::setupTlmRecorders(const std::string& traceName, const DRAMSysConfiguration::Configuration& configLib) { - //tlmRecorders.reserve(config.memSpec->numberOfChannels); // Create TLM Recorders, one per channel. + // Reserve is required because the recorders use double buffers that are accessed with pointers. + // Without a reserve, the vector reallocates storage before inserting a second + // element and the pointers are not valid anymore. + tlmRecorders.reserve(config.memSpec->numberOfChannels); for (std::size_t i = 0; i < config.memSpec->numberOfChannels; i++) { std::string dbName = traceName + std::string("_ch") + std::to_string(i) + ".tdb"; From 6988dd10d2e041d245880789eb36a0c0a22856af Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Wed, 11 May 2022 16:25:24 +0200 Subject: [PATCH 15/29] Show relevant attributes in Phases in TA --- .../businessObjects/phases/phase.cpp | 6 + .../businessObjects/phases/phase.h | 223 ++++++++++++++++-- .../presentation/transactiontreewidget.cpp | 58 +++-- 3 files changed, 246 insertions(+), 41 deletions(-) diff --git a/DRAMSys/traceAnalyzer/businessObjects/phases/phase.cpp b/DRAMSys/traceAnalyzer/businessObjects/phases/phase.cpp index 5ddec5a2..8f8460b5 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/phases/phase.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/phases/phase.cpp @@ -372,3 +372,9 @@ void Phase::addDependency(std::shared_ptr dependency) { mDependencies.push_back(dependency); } + +RelevantAttributes Phase::getRelevantAttributes() const +{ + return RelevantAttributes::Rank | RelevantAttributes::Bankgroup | RelevantAttributes::Bank | + RelevantAttributes::Column | RelevantAttributes::Row; +} diff --git a/DRAMSys/traceAnalyzer/businessObjects/phases/phase.h b/DRAMSys/traceAnalyzer/businessObjects/phases/phase.h index 942c8929..29bdfc1f 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/phases/phase.h +++ b/DRAMSys/traceAnalyzer/businessObjects/phases/phase.h @@ -54,6 +54,25 @@ typedef unsigned int ID; //enum TextPositioning; class Transaction; +enum class RelevantAttributes +{ + Rank = 0x01, + Bankgroup = 0x02, + Bank = 0x04, + Row = 0x08, + Column = 0x10 +}; + +inline RelevantAttributes operator|(RelevantAttributes a, RelevantAttributes b) +{ + return static_cast(static_cast(a) | static_cast(b)); +} + +inline RelevantAttributes operator&(RelevantAttributes a, RelevantAttributes b) +{ + return static_cast(static_cast(a) & static_cast(b)); +} + class Phase { public: @@ -70,14 +89,44 @@ public: const TraceDrawingProperties &drawingProperties) const; bool isSelected(Timespan timespan, double yVal, const TraceDrawingProperties &drawingproperties) const; bool isColumnCommand() const; + const Timespan &Span() const { return span; } + ID Id() const { return id; } + + unsigned int getRank() const + { + return rank; + } + + unsigned int getBankgroup() const + { + return bankGroup; + } + + unsigned int getBank() const + { + return bank; + } + + unsigned int getRow() const + { + return row; + } + + unsigned int getColumn() const + { + return column; + } + + virtual RelevantAttributes getRelevantAttributes() const; + virtual QString Name() const = 0; void addDependency(std::shared_ptr dependency); @@ -123,6 +172,7 @@ class REQ final : public Phase { public: using Phase::Phase; + protected: QColor getPhaseColor() const override { @@ -133,6 +183,11 @@ protected: return "REQ"; } + RelevantAttributes getRelevantAttributes() const override + { + return static_cast(0); + } + std::vector getYVals(const TraceDrawingProperties &drawingProperties) const override; }; @@ -140,6 +195,7 @@ class RESP final : public Phase { public: using Phase::Phase; + protected: QColor getPhaseColor() const override { @@ -150,6 +206,11 @@ protected: return "RESP"; } + RelevantAttributes getRelevantAttributes() const override + { + return static_cast(0); + } + std::vector getYVals(const TraceDrawingProperties &drawingProperties) const override; }; /* @@ -172,6 +233,7 @@ class PREPB final : public Phase { public: using Phase::Phase; + protected: QColor getPhaseColor() const override { @@ -181,12 +243,18 @@ protected: { return "PREPB"; } + + RelevantAttributes getRelevantAttributes() const override + { + return RelevantAttributes::Rank | RelevantAttributes::Bankgroup | RelevantAttributes::Bank; + } }; class PRESB final : public Phase { public: using Phase::Phase; + protected: QString Name() const override { @@ -196,10 +264,10 @@ protected: { return {span.Begin()}; } - QColor getColor(const TraceDrawingProperties &drawingProperties) const - override + QColor getColor(const TraceDrawingProperties &drawingProperties) const override { - Q_UNUSED(drawingProperties) return getPhaseColor(); + Q_UNUSED(drawingProperties) + return getPhaseColor(); } QColor getPhaseColor() const override { @@ -209,12 +277,18 @@ protected: { return Granularity::Groupwise; } + + RelevantAttributes getRelevantAttributes() const override + { + return RelevantAttributes::Rank | RelevantAttributes::Bankgroup | RelevantAttributes::Bank; + } }; class PREAB final : public Phase { public: using Phase::Phase; + protected: QString Name() const override { @@ -224,10 +298,10 @@ protected: { return {span.Begin()}; } - QColor getColor(const TraceDrawingProperties &drawingProperties) const - override + QColor getColor(const TraceDrawingProperties &drawingProperties) const override { - Q_UNUSED(drawingProperties) return getPhaseColor(); + Q_UNUSED(drawingProperties) + return getPhaseColor(); } QColor getPhaseColor() const override { @@ -237,6 +311,11 @@ protected: { return Granularity::Rankwise; } + + RelevantAttributes getRelevantAttributes() const override + { + return RelevantAttributes::Rank; + } }; /* class ACTB final : public Phase @@ -258,6 +337,7 @@ class ACT final : public Phase { public: using Phase::Phase; + protected: QColor getPhaseColor() const override { @@ -267,12 +347,19 @@ protected: { return "ACT"; } + + RelevantAttributes getRelevantAttributes() const override + { + return RelevantAttributes::Rank | RelevantAttributes::Bankgroup | RelevantAttributes::Bank | + RelevantAttributes::Row; + } }; class RD final : public Phase { public: using Phase::Phase; + protected: QColor getPhaseColor() const override { @@ -282,12 +369,19 @@ protected: { return "RD"; } + + RelevantAttributes getRelevantAttributes() const override + { + return RelevantAttributes::Rank | RelevantAttributes::Bankgroup | RelevantAttributes::Bank | + RelevantAttributes::Column; + } }; class RDA final : public Phase { public: using Phase::Phase; + protected: QColor getPhaseColor() const override { @@ -297,12 +391,19 @@ protected: { return "RDA"; } + + RelevantAttributes getRelevantAttributes() const override + { + return RelevantAttributes::Rank | RelevantAttributes::Bankgroup | RelevantAttributes::Bank | + RelevantAttributes::Column; + } }; class WR final : public Phase { public: using Phase::Phase; + protected: QColor getPhaseColor() const override { @@ -312,12 +413,19 @@ protected: { return "WR"; } + + RelevantAttributes getRelevantAttributes() const override + { + return RelevantAttributes::Rank | RelevantAttributes::Bankgroup | RelevantAttributes::Bank | + RelevantAttributes::Column; + } }; class WRA final : public Phase { public: using Phase::Phase; + protected: QColor getPhaseColor() const override { @@ -327,12 +435,19 @@ protected: { return "WRA"; } + + RelevantAttributes getRelevantAttributes() const override + { + return RelevantAttributes::Rank | RelevantAttributes::Bankgroup | RelevantAttributes::Bank | + RelevantAttributes::Column; + } }; class AUTO_REFRESH : public Phase { public: using Phase::Phase; + protected: QString Name() const override { @@ -342,10 +457,10 @@ protected: { return {span.Begin()}; } - QColor getColor(const TraceDrawingProperties &drawingProperties) const - override + QColor getColor(const TraceDrawingProperties &drawingProperties) const override { - Q_UNUSED(drawingProperties) return getPhaseColor(); + Q_UNUSED(drawingProperties) + return getPhaseColor(); } QColor getPhaseColor() const override { @@ -359,6 +474,7 @@ class REFAB final : public AUTO_REFRESH { public: using AUTO_REFRESH::AUTO_REFRESH; + protected: QString Name() const override { @@ -368,12 +484,18 @@ protected: { return Granularity::Rankwise; } + + RelevantAttributes getRelevantAttributes() const override + { + return RelevantAttributes::Rank; + } }; class RFMAB final : public AUTO_REFRESH { public: using AUTO_REFRESH::AUTO_REFRESH; + protected: QString Name() const override { @@ -389,23 +511,35 @@ protected: phaseColor.setAlpha(130); return phaseColor; } + + RelevantAttributes getRelevantAttributes() const override + { + return RelevantAttributes::Rank; + } }; class REFPB final : public AUTO_REFRESH { public: using AUTO_REFRESH::AUTO_REFRESH; + protected: QString Name() const override { return "REFPB"; } + + RelevantAttributes getRelevantAttributes() const override + { + return RelevantAttributes::Rank | RelevantAttributes::Bankgroup | RelevantAttributes::Bank; + } }; class RFMPB final : public AUTO_REFRESH { public: using AUTO_REFRESH::AUTO_REFRESH; + protected: QString Name() const override { @@ -417,12 +551,18 @@ protected: phaseColor.setAlpha(130); return phaseColor; } + + RelevantAttributes getRelevantAttributes() const override + { + return RelevantAttributes::Rank | RelevantAttributes::Bankgroup | RelevantAttributes::Bank; + } }; class REFP2B final : public AUTO_REFRESH { public: using AUTO_REFRESH::AUTO_REFRESH; + protected: QString Name() const override { @@ -432,12 +572,18 @@ protected: { return Granularity::TwoBankwise; } + + RelevantAttributes getRelevantAttributes() const override + { + return RelevantAttributes::Rank | RelevantAttributes::Bankgroup | RelevantAttributes::Bank; + } }; class RFMP2B final : public AUTO_REFRESH { public: using AUTO_REFRESH::AUTO_REFRESH; + protected: QString Name() const override { @@ -453,12 +599,18 @@ protected: phaseColor.setAlpha(130); return phaseColor; } + + RelevantAttributes getRelevantAttributes() const override + { + return RelevantAttributes::Rank | RelevantAttributes::Bankgroup | RelevantAttributes::Bank; + } }; class REFSB final : public AUTO_REFRESH { public: using AUTO_REFRESH::AUTO_REFRESH; + protected: QString Name() const override { @@ -468,12 +620,18 @@ protected: { return Granularity::Groupwise; } + + RelevantAttributes getRelevantAttributes() const override + { + return RelevantAttributes::Rank | RelevantAttributes::Bankgroup | RelevantAttributes::Bank; + } }; class RFMSB final : public AUTO_REFRESH { public: using AUTO_REFRESH::AUTO_REFRESH; + protected: QString Name() const override { @@ -489,6 +647,11 @@ protected: phaseColor.setAlpha(130); return phaseColor; } + + RelevantAttributes getRelevantAttributes() const override + { + return RelevantAttributes::Rank | RelevantAttributes::Bankgroup | RelevantAttributes::Bank; + } }; class PDNAB : public Phase @@ -506,10 +669,10 @@ protected: { return Qt::Dense6Pattern; } - QColor getColor(const TraceDrawingProperties &drawingProperties) const - override + QColor getColor(const TraceDrawingProperties &drawingProperties) const override { - Q_UNUSED(drawingProperties) return getPhaseColor(); + Q_UNUSED(drawingProperties) + return getPhaseColor(); } QColor getPhaseColor() const override { @@ -519,12 +682,18 @@ protected: { return PhaseSymbol::Rect; } + + RelevantAttributes getRelevantAttributes() const override + { + return RelevantAttributes::Rank; + } }; class PDNA final : public PDNAB { public: using PDNAB::PDNAB; + protected: QString Name() const override { @@ -534,6 +703,11 @@ protected: { return Granularity::Rankwise; } + + RelevantAttributes getRelevantAttributes() const override + { + return RelevantAttributes::Rank; + } }; class PDNPB : public Phase @@ -551,10 +725,10 @@ protected: { return Qt::Dense4Pattern; } - QColor getColor(const TraceDrawingProperties &drawingProperties) const - override + QColor getColor(const TraceDrawingProperties &drawingProperties) const override { - Q_UNUSED(drawingProperties) return getPhaseColor(); + Q_UNUSED(drawingProperties) + return getPhaseColor(); } QColor getPhaseColor() const override { @@ -564,12 +738,18 @@ protected: { return PhaseSymbol::Rect; } + + RelevantAttributes getRelevantAttributes() const override + { + return RelevantAttributes::Rank | RelevantAttributes::Bankgroup | RelevantAttributes::Bank; + } }; class PDNP final : public PDNPB { public: using PDNPB::PDNPB; + protected: QString Name() const override { @@ -596,10 +776,10 @@ protected: { return Qt::Dense1Pattern; } - QColor getColor(const TraceDrawingProperties &drawingProperties) const - override + QColor getColor(const TraceDrawingProperties &drawingProperties) const override { - Q_UNUSED(drawingProperties) return getPhaseColor(); + Q_UNUSED(drawingProperties) + return getPhaseColor(); } QColor getPhaseColor() const override { @@ -609,12 +789,18 @@ protected: { return PhaseSymbol::Rect; } + + RelevantAttributes getRelevantAttributes() const override + { + return RelevantAttributes::Rank | RelevantAttributes::Bankgroup | RelevantAttributes::Bank; + } }; class SREF : public SREFB { public: using SREFB::SREFB; + protected: QString Name() const override { @@ -626,5 +812,4 @@ protected: } }; - #endif // BANKPHASE_H diff --git a/DRAMSys/traceAnalyzer/presentation/transactiontreewidget.cpp b/DRAMSys/traceAnalyzer/presentation/transactiontreewidget.cpp index 96c6617a..6f65ce58 100644 --- a/DRAMSys/traceAnalyzer/presentation/transactiontreewidget.cpp +++ b/DRAMSys/traceAnalyzer/presentation/transactiontreewidget.cpp @@ -38,16 +38,14 @@ #include "transactiontreewidget.h" #include "data/tracedb.h" #include -#include #include +#include using namespace std; -TransactionTreeWidget::TransactionTreeWidget(QWidget *parent) : QTreeWidget( - parent), isInitialized(false) +TransactionTreeWidget::TransactionTreeWidget(QWidget *parent) : QTreeWidget(parent), isInitialized(false) { - QObject::connect(this, SIGNAL(customContextMenuRequested(QPoint)), this, - SLOT(ContextMenuRequested(QPoint))); + QObject::connect(this, SIGNAL(customContextMenuRequested(QPoint)), this, SLOT(ContextMenuRequested(QPoint))); setContextMenuPolicy(Qt::CustomContextMenu); goToTransaction = new QAction("Move to", this); } @@ -62,19 +60,17 @@ void TransactionTreeWidget::init(TraceNavigator *navigator) setHeaderLabels(QStringList({"Transaction", "Value", "Value"})); } -void TransactionTreeWidget::AppendTransaction(const shared_ptr - &transaction) +void TransactionTreeWidget::AppendTransaction(const shared_ptr &transaction) { - QTreeWidgetItem *node = new TransactionTreeItem(this, transaction, - navigator->GeneralTraceInfo()); + QTreeWidgetItem *node = new TransactionTreeItem(this, transaction, navigator->GeneralTraceInfo()); addTopLevelItem(node); } void TransactionTreeWidget::ContextMenuRequested(QPoint point) { - if (selectedItems().count() > 0 - && selectedItems().at(0)->type() == - TransactionTreeWidget::TransactionTreeItem::transactionTreeItemType) { + if (selectedItems().count() > 0 && + selectedItems().at(0)->type() == TransactionTreeWidget::TransactionTreeItem::transactionTreeItemType) + { QMenu contextMenu; contextMenu.addActions({goToTransaction}); QAction *selectedContextMenuItems = contextMenu.exec(mapToGlobal(point)); @@ -97,16 +93,10 @@ TransactionTreeWidget::TransactionTreeItem::TransactionTreeItem(QTreeWidget *par bool isControllerTransaction = (transaction->thread == generalInfo.controllerThread); - auto* time = new QTreeWidgetItem({"Timespan"}); + auto *time = new QTreeWidgetItem({"Timespan"}); AppendTimespan(time, transaction->span); this->addChild(time); this->addChild(new QTreeWidgetItem({"Length", prettyFormatTime(transaction->span.timeCovered())})); - // TODO: move to phase - //this->addChild(new QTreeWidgetItem({"Rank", QString::number(transaction->rank)})); - //this->addChild(new QTreeWidgetItem({"Bankgroup", QString::number(transaction->bankgroup % generalInfo.groupsPerRank)})); - //this->addChild(new QTreeWidgetItem({"Bank", QString::number(transaction->bank % generalInfo.banksPerGroup)})); - //this->addChild(new QTreeWidgetItem({"Row", QString::number(transaction->row)})); - //this->addChild(new QTreeWidgetItem({"Column", QString::number(transaction->column)})); this->addChild(new QTreeWidgetItem({"Address", QString("0x") + QString::number(transaction->address, 16)})); if (!isControllerTransaction) this->addChild(new QTreeWidgetItem({"Data Length", QString::number(transaction->dataLength)})); @@ -114,20 +104,44 @@ TransactionTreeWidget::TransactionTreeItem::TransactionTreeItem(QTreeWidget *par if (!isControllerTransaction) this->addChild(new QTreeWidgetItem({"Thread", QString::number(transaction->thread)})); - auto* phasesNode = new QTreeWidgetItem(this); + auto *phasesNode = new QTreeWidgetItem(this); phasesNode->setText(0, "Phases"); phasesNode->addChild(new QTreeWidgetItem({"", "Begin", "End"})); - for (const std::shared_ptr& phase : transaction->Phases()) + for (const std::shared_ptr &phase : transaction->Phases()) AppendPhase(phasesNode, *phase); } void TransactionTreeWidget::TransactionTreeItem::AppendPhase(QTreeWidgetItem *parent, const Phase &phase) { - auto* node = new QTreeWidgetItem(parent); + auto *node = new QTreeWidgetItem(parent); node->setText(0, phase.Name() + QString(" [") + QString::number(phase.Id()) + QString("]")); AppendTimespan(node, phase.Span()); + + auto addMapping = [node](std::string_view label, unsigned value) + { + auto *mappingNode = new QTreeWidgetItem(node); + mappingNode->setText(0, label.data()); + mappingNode->setText(1, QString::number(value)); + }; + + { + if (static_cast(phase.getRelevantAttributes() & RelevantAttributes::Rank)) + addMapping("Rank", phase.getRank()); + + if (static_cast(phase.getRelevantAttributes() & RelevantAttributes::Bankgroup)) + addMapping("Bankgroup", phase.getBankgroup()); + + if (static_cast(phase.getRelevantAttributes() & RelevantAttributes::Bank)) + addMapping("Bank", phase.getBank()); + + if (static_cast(phase.getRelevantAttributes() & RelevantAttributes::Row)) + addMapping("Row", phase.getRow()); + + if (static_cast(phase.getRelevantAttributes() & RelevantAttributes::Column)) + addMapping("Column", phase.getColumn()); + } } void TransactionTreeWidget::TransactionTreeItem::AppendTimespan(QTreeWidgetItem *parent, const Timespan ×pan) From 684f57a2d9dbc41411ae2a37351ee563f79566b1 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Thu, 12 May 2022 15:10:54 +0200 Subject: [PATCH 16/29] Small adaptions in TA. --- .../businessObjects/phases/phase.cpp | 16 ++---- .../businessObjects/phases/phase.h | 51 ++++++++++--------- .../businessObjects/phases/phasefactory.cpp | 46 +++++++++-------- .../businessObjects/transaction.cpp | 13 +++-- .../businessObjects/transaction.h | 7 +-- DRAMSys/traceAnalyzer/data/QueryTexts.h | 2 +- DRAMSys/traceAnalyzer/data/tracedb.cpp | 24 +++++---- .../presentation/tracemetrictreewidget.h | 2 +- .../traceAnalyzer/presentation/traceplot.cpp | 6 +-- .../presentation/transactiontreewidget.cpp | 18 +++++-- .../presentation/transactiontreewidget.h | 8 ++- 11 files changed, 103 insertions(+), 90 deletions(-) diff --git a/DRAMSys/traceAnalyzer/businessObjects/phases/phase.cpp b/DRAMSys/traceAnalyzer/businessObjects/phases/phase.cpp index 8f8460b5..f42d126b 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/phases/phase.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/phases/phase.cpp @@ -130,7 +130,7 @@ void Phase::draw(QPainter *painter, const QwtScaleMap &xMap, const QwtScaleMap & } void Phase::drawPhaseSymbol(traceTime begin, traceTime end, double y, bool drawtext, PhaseSymbol symbol, - QPainter *painter, const QwtScaleMap &xMap, const QwtScaleMap &yMap, QColor textColor) const + QPainter *painter, const QwtScaleMap &xMap, const QwtScaleMap &yMap, const QColor& textColor) const { double yVal = yMap.transform(y); double symbolHeight = yMap.transform(0) - yMap.transform(hexagonHeight); @@ -177,7 +177,7 @@ void Phase::drawPhaseDependencies(traceTime begin, traceTime end, double y, QPoint depLineTo(static_cast(xMap.transform(begin /* + (end + offset - begin)/4*/)), static_cast(yVal)); - for (auto dep : mDependencies) + for (const auto& dep : mDependencies) { bool visible = false; if (dep->isVisible()) @@ -304,9 +304,9 @@ bool Phase::isSelected(Timespan timespan, double yVal, const TraceDrawingPropert return true; } - for (Timespan span : spansOnCommandBus) + for (Timespan _span : spansOnCommandBus) { - if (span.overlaps(timespan)) + if (_span.overlaps(timespan)) { for (const auto &line : drawingProperties.getTracePlotLines()) { @@ -368,13 +368,7 @@ Phase::PhaseSymbol Phase::getPhaseSymbol() const return PhaseSymbol::Hexagon; } -void Phase::addDependency(std::shared_ptr dependency) +void Phase::addDependency(const std::shared_ptr& dependency) { mDependencies.push_back(dependency); } - -RelevantAttributes Phase::getRelevantAttributes() const -{ - return RelevantAttributes::Rank | RelevantAttributes::Bankgroup | RelevantAttributes::Bank | - RelevantAttributes::Column | RelevantAttributes::Row; -} diff --git a/DRAMSys/traceAnalyzer/businessObjects/phases/phase.h b/DRAMSys/traceAnalyzer/businessObjects/phases/phase.h index 29bdfc1f..ebfb6f8f 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/phases/phase.h +++ b/DRAMSys/traceAnalyzer/businessObjects/phases/phase.h @@ -57,7 +57,7 @@ class Transaction; enum class RelevantAttributes { Rank = 0x01, - Bankgroup = 0x02, + BankGroup = 0x02, Bank = 0x04, Row = 0x08, Column = 0x10 @@ -78,10 +78,12 @@ class Phase public: Phase(ID id, Timespan span, Timespan spanOnDataStrobe, unsigned int rank, unsigned int bankGroup, unsigned int bank, unsigned int row, unsigned int column, unsigned int burstLength, - traceTime clk, const std::shared_ptr &transaction, std::vector spansOnCommandBus) : + traceTime clk, const std::shared_ptr &transaction, std::vector spansOnCommandBus, + unsigned int groupsPerRank, unsigned int banksPerGroup) : id(id), span(span), spanOnDataStrobe(spanOnDataStrobe), rank(rank), bankGroup(bankGroup), bank(bank), row(row), column(column), burstLength(burstLength), clk(clk), transaction(transaction), spansOnCommandBus(std::move(spansOnCommandBus)), + groupsPerRank(groupsPerRank), banksPerGroup(banksPerGroup), hexagonHeight(0.6), captionPosition(TextPositioning::bottomRight) {} void draw(QPainter *painter, const QwtScaleMap &xMap, const QwtScaleMap &yMap, @@ -105,14 +107,14 @@ public: return rank; } - unsigned int getBankgroup() const + unsigned int getBankGroup() const { - return bankGroup; + return bankGroup % groupsPerRank; } unsigned int getBank() const { - return bank; + return bank % banksPerGroup; } unsigned int getRow() const @@ -125,17 +127,18 @@ public: return column; } - virtual RelevantAttributes getRelevantAttributes() const; + virtual RelevantAttributes getRelevantAttributes() const = 0; virtual QString Name() const = 0; - void addDependency(std::shared_ptr dependency); + void addDependency(const std::shared_ptr& dependency); protected: ID id; Timespan span; Timespan spanOnDataStrobe; unsigned int rank, bankGroup, bank, row, column, burstLength; + unsigned int groupsPerRank, banksPerGroup; traceTime clk; std::weak_ptr transaction; std::vector spansOnCommandBus; @@ -153,7 +156,7 @@ protected: virtual std::vector getYVals(const TraceDrawingProperties &drawingProperties) const; virtual void drawPhaseSymbol(traceTime begin, traceTime end, double y, bool drawtext, PhaseSymbol symbol, QPainter *painter, const QwtScaleMap &xMap, - const QwtScaleMap &yMap, QColor textColor) const; + const QwtScaleMap &yMap, const QColor& textColor) const; virtual void drawPhaseDependencies(traceTime begin, traceTime end, double y, const TraceDrawingProperties &drawingProperties, QPainter *painter, const QwtScaleMap &xMap, const QwtScaleMap &yMap) const; @@ -246,7 +249,7 @@ protected: RelevantAttributes getRelevantAttributes() const override { - return RelevantAttributes::Rank | RelevantAttributes::Bankgroup | RelevantAttributes::Bank; + return RelevantAttributes::Rank | RelevantAttributes::BankGroup | RelevantAttributes::Bank; } }; @@ -280,7 +283,7 @@ protected: RelevantAttributes getRelevantAttributes() const override { - return RelevantAttributes::Rank | RelevantAttributes::Bankgroup | RelevantAttributes::Bank; + return RelevantAttributes::Rank | RelevantAttributes::Bank; } }; @@ -350,7 +353,7 @@ protected: RelevantAttributes getRelevantAttributes() const override { - return RelevantAttributes::Rank | RelevantAttributes::Bankgroup | RelevantAttributes::Bank | + return RelevantAttributes::Rank | RelevantAttributes::BankGroup | RelevantAttributes::Bank | RelevantAttributes::Row; } }; @@ -372,7 +375,7 @@ protected: RelevantAttributes getRelevantAttributes() const override { - return RelevantAttributes::Rank | RelevantAttributes::Bankgroup | RelevantAttributes::Bank | + return RelevantAttributes::Rank | RelevantAttributes::BankGroup | RelevantAttributes::Bank | RelevantAttributes::Column; } }; @@ -394,7 +397,7 @@ protected: RelevantAttributes getRelevantAttributes() const override { - return RelevantAttributes::Rank | RelevantAttributes::Bankgroup | RelevantAttributes::Bank | + return RelevantAttributes::Rank | RelevantAttributes::BankGroup | RelevantAttributes::Bank | RelevantAttributes::Column; } }; @@ -416,7 +419,7 @@ protected: RelevantAttributes getRelevantAttributes() const override { - return RelevantAttributes::Rank | RelevantAttributes::Bankgroup | RelevantAttributes::Bank | + return RelevantAttributes::Rank | RelevantAttributes::BankGroup | RelevantAttributes::Bank | RelevantAttributes::Column; } }; @@ -438,7 +441,7 @@ protected: RelevantAttributes getRelevantAttributes() const override { - return RelevantAttributes::Rank | RelevantAttributes::Bankgroup | RelevantAttributes::Bank | + return RelevantAttributes::Rank | RelevantAttributes::BankGroup | RelevantAttributes::Bank | RelevantAttributes::Column; } }; @@ -531,7 +534,7 @@ protected: RelevantAttributes getRelevantAttributes() const override { - return RelevantAttributes::Rank | RelevantAttributes::Bankgroup | RelevantAttributes::Bank; + return RelevantAttributes::Rank | RelevantAttributes::BankGroup | RelevantAttributes::Bank; } }; @@ -554,7 +557,7 @@ protected: RelevantAttributes getRelevantAttributes() const override { - return RelevantAttributes::Rank | RelevantAttributes::Bankgroup | RelevantAttributes::Bank; + return RelevantAttributes::Rank | RelevantAttributes::BankGroup | RelevantAttributes::Bank; } }; @@ -575,7 +578,7 @@ protected: RelevantAttributes getRelevantAttributes() const override { - return RelevantAttributes::Rank | RelevantAttributes::Bankgroup | RelevantAttributes::Bank; + return RelevantAttributes::Rank | RelevantAttributes::BankGroup | RelevantAttributes::Bank; } }; @@ -602,7 +605,7 @@ protected: RelevantAttributes getRelevantAttributes() const override { - return RelevantAttributes::Rank | RelevantAttributes::Bankgroup | RelevantAttributes::Bank; + return RelevantAttributes::Rank | RelevantAttributes::BankGroup | RelevantAttributes::Bank; } }; @@ -623,7 +626,7 @@ protected: RelevantAttributes getRelevantAttributes() const override { - return RelevantAttributes::Rank | RelevantAttributes::Bankgroup | RelevantAttributes::Bank; + return RelevantAttributes::Rank | RelevantAttributes::Bank; } }; @@ -650,7 +653,7 @@ protected: RelevantAttributes getRelevantAttributes() const override { - return RelevantAttributes::Rank | RelevantAttributes::Bankgroup | RelevantAttributes::Bank; + return RelevantAttributes::Rank | RelevantAttributes::Bank; } }; @@ -685,7 +688,7 @@ protected: RelevantAttributes getRelevantAttributes() const override { - return RelevantAttributes::Rank; + return RelevantAttributes::Rank | RelevantAttributes::BankGroup | RelevantAttributes::Bank; } }; @@ -741,7 +744,7 @@ protected: RelevantAttributes getRelevantAttributes() const override { - return RelevantAttributes::Rank | RelevantAttributes::Bankgroup | RelevantAttributes::Bank; + return RelevantAttributes::Rank | RelevantAttributes::BankGroup | RelevantAttributes::Bank; } }; @@ -792,7 +795,7 @@ protected: RelevantAttributes getRelevantAttributes() const override { - return RelevantAttributes::Rank | RelevantAttributes::Bankgroup | RelevantAttributes::Bank; + return RelevantAttributes::Rank | RelevantAttributes::BankGroup | RelevantAttributes::Bank; } }; diff --git a/DRAMSys/traceAnalyzer/businessObjects/phases/phasefactory.cpp b/DRAMSys/traceAnalyzer/businessObjects/phases/phasefactory.cpp index 97e2c512..99a20ab4 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/phases/phasefactory.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/phases/phasefactory.cpp @@ -48,72 +48,76 @@ std::shared_ptr PhaseFactory::createPhase(ID id, const QString &dbPhaseNa unsigned int burstLength, const std::shared_ptr &trans, TraceDB &database) { auto clk = static_cast(database.getGeneralInfo().clkPeriod); + unsigned int groupsPerRank = database.getGeneralInfo().groupsPerRank; + unsigned int banksPerGroup = database.getGeneralInfo().banksPerGroup; const CommandLengths &cl = database.getCommandLengths(); if (dbPhaseName == "REQ") - return std::shared_ptr(new REQ(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, burstLength, clk, trans, {})); + return std::shared_ptr(new REQ(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, + burstLength, clk, trans, {}, groupsPerRank, banksPerGroup)); else if (dbPhaseName == "RESP") - return std::shared_ptr(new RESP(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column,burstLength, clk, trans, {})); + return std::shared_ptr(new RESP(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, + burstLength, clk, trans, {}, groupsPerRank, banksPerGroup)); else if (dbPhaseName == "PREPB") return std::shared_ptr(new PREPB(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, - burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.PREPB)})); + burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.PREPB)}, groupsPerRank, banksPerGroup)); else if (dbPhaseName == "ACT") return std::shared_ptr(new ACT(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, - burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.ACT)})); + burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.ACT)}, groupsPerRank, banksPerGroup)); else if (dbPhaseName == "PREAB") return std::shared_ptr(new PREAB(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, - burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.PREAB)})); + burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.PREAB)}, groupsPerRank, banksPerGroup)); else if (dbPhaseName == "REFAB") return std::shared_ptr(new REFAB(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, - burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.REFAB)})); + burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.REFAB)}, groupsPerRank, banksPerGroup)); else if (dbPhaseName == "RFMAB") return std::shared_ptr(new RFMAB(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, - burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.RFMAB)})); + burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.RFMAB)}, groupsPerRank, banksPerGroup)); else if (dbPhaseName == "REFPB") return std::shared_ptr(new REFPB(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, - burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.REFPB)})); + burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.REFPB)}, groupsPerRank, banksPerGroup)); else if (dbPhaseName == "RFMPB") return std::shared_ptr(new RFMPB(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, - burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.RFMPB)})); + burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.RFMPB)}, groupsPerRank, banksPerGroup)); else if (dbPhaseName == "REFP2B") return std::shared_ptr(new REFP2B(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, - burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.REFP2B)})); + burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.REFP2B)}, groupsPerRank, banksPerGroup)); else if (dbPhaseName == "RFMP2B") return std::shared_ptr(new RFMP2B(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, - burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.RFMP2B)})); + burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.RFMP2B)}, groupsPerRank, banksPerGroup)); else if (dbPhaseName == "PRESB") return std::shared_ptr(new PRESB(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, - burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.PRESB)})); + burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.PRESB)}, groupsPerRank, banksPerGroup)); else if (dbPhaseName == "REFSB") return std::shared_ptr(new REFSB(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, - burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.REFSB)})); + burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.REFSB)}, groupsPerRank, banksPerGroup)); else if (dbPhaseName == "RFMSB") return std::shared_ptr(new RFMSB(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, - burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.RFMSB)})); + burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.RFMSB)}, groupsPerRank, banksPerGroup)); else if (dbPhaseName == "RD") return std::shared_ptr(new RD(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, - burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.RD)})); + burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.RD)}, groupsPerRank, banksPerGroup)); else if (dbPhaseName == "RDA") return std::shared_ptr(new RDA(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, - burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.RDA)})); + burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.RDA)}, groupsPerRank, banksPerGroup)); else if (dbPhaseName == "WR") return std::shared_ptr(new WR(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, - burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.WR)})); + burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.WR)}, groupsPerRank, banksPerGroup)); else if (dbPhaseName == "WRA") return std::shared_ptr(new WRA(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, - burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.WRA)})); + burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.WRA)}, groupsPerRank, banksPerGroup)); else if (dbPhaseName == "PDNA") return std::shared_ptr(new PDNA(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.PDEA), - Timespan(span.End() - clk * cl.PDXA, span.End())})); + Timespan(span.End() - clk * cl.PDXA, span.End())}, groupsPerRank, banksPerGroup)); else if (dbPhaseName == "PDNP") return std::shared_ptr(new PDNP(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.PDEP), - Timespan(span.End() - clk * cl.PDXP, span.End())})); + Timespan(span.End() - clk * cl.PDXP, span.End())}, groupsPerRank, banksPerGroup)); else if (dbPhaseName == "SREF") return std::shared_ptr(new SREF(id, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, burstLength, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.SREFEN), - Timespan(span.End() - clk * cl.SREFEX, span.End())})); + Timespan(span.End() - clk * cl.SREFEX, span.End())}, groupsPerRank, banksPerGroup)); else throw std::runtime_error("DB phasename " + dbPhaseName.toStdString() + " unkown to phasefactory"); } diff --git a/DRAMSys/traceAnalyzer/businessObjects/transaction.cpp b/DRAMSys/traceAnalyzer/businessObjects/transaction.cpp index e97dddf0..4eae7753 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/transaction.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/transaction.cpp @@ -38,15 +38,18 @@ #include "transaction.h" +#include + using namespace std; unsigned int Transaction::mSNumTransactions = 0; -Transaction::Transaction(ID id, unsigned int address, unsigned int dataLength, +Transaction::Transaction(ID id, QString command, unsigned int address, unsigned int dataLength, unsigned int thread, unsigned int channel, Timespan span, traceTime clk) - : clk(clk), address(address), dataLength(dataLength), thread(thread), channel(channel), span(span), id(id) {} + : clk(clk), command(std::move(command)), address(address), dataLength(dataLength), thread(thread), channel(channel), + span(span), id(id) {} -void Transaction::addPhase(shared_ptr phase) +void Transaction::addPhase(const shared_ptr& phase) { phases.push_back(phase); } @@ -55,7 +58,7 @@ void Transaction::draw(QPainter *painter, const QwtScaleMap &xMap, const QwtScaleMap &yMap, const QRectF &canvasRect, bool highlight, const TraceDrawingProperties &drawingProperties) const { - for (shared_ptr phase : phases) + for (const shared_ptr& phase : phases) phase->draw(painter, xMap, yMap, canvasRect, highlight, drawingProperties); } @@ -63,7 +66,7 @@ bool Transaction::isSelected(Timespan timespan, double yVal, const TraceDrawingP { if (span.overlaps(timespan)) { - for (shared_ptr phase : phases) + for (const shared_ptr& phase : phases) { if (phase->isSelected(timespan, yVal, drawingproperties)) return true; diff --git a/DRAMSys/traceAnalyzer/businessObjects/transaction.h b/DRAMSys/traceAnalyzer/businessObjects/transaction.h index f6caf329..8e8357e1 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/transaction.h +++ b/DRAMSys/traceAnalyzer/businessObjects/transaction.h @@ -53,18 +53,19 @@ private: traceTime clk; public: + const QString command; const uint64_t address; const unsigned int dataLength, thread, channel; const Timespan span; const ID id; - Transaction(ID id, unsigned int address, unsigned int dataLength, unsigned int thread, unsigned int channel, - Timespan span, traceTime clk); + Transaction(ID id, QString command, unsigned int address, unsigned int dataLength, unsigned int thread, + unsigned int channel, Timespan span, traceTime clk); void draw(QPainter *painter, const QwtScaleMap &xMap, const QwtScaleMap &yMap, const QRectF &canvasRect, bool highlight, const TraceDrawingProperties &drawingProperties) const; - void addPhase(std::shared_ptr phase); + void addPhase(const std::shared_ptr& phase); bool isSelected(Timespan timespan, double yVal, const TraceDrawingProperties &drawingproperties) const; diff --git a/DRAMSys/traceAnalyzer/data/QueryTexts.h b/DRAMSys/traceAnalyzer/data/QueryTexts.h index 996df475..080fe9f2 100644 --- a/DRAMSys/traceAnalyzer/data/QueryTexts.h +++ b/DRAMSys/traceAnalyzer/data/QueryTexts.h @@ -50,7 +50,7 @@ struct TransactionQueryTexts { TransactionQueryTexts() { queryHead = - "SELECT Transactions.ID AS TransactionID, Ranges.begin, Ranges.end, Address, DataLength, Thread, Channel, Phases.ID AS PhaseID, PhaseName, PhaseBegin, PhaseEnd, DataStrobeBegin, DataStrobeEnd, Rank, BankGroup, Bank, Row, Column, BurstLength " + "SELECT Transactions.ID AS TransactionID, Ranges.begin, Ranges.end, Address, DataLength, Thread, Channel, Command, Phases.ID AS PhaseID, PhaseName, PhaseBegin, PhaseEnd, DataStrobeBegin, DataStrobeEnd, Rank, BankGroup, Bank, Row, Column, BurstLength " " FROM Transactions INNER JOIN Phases ON Phases.Transact = Transactions.ID INNER JOIN Ranges ON Transactions.Range = Ranges.ID "; selectTransactionsByTimespan = queryHead + " WHERE Ranges.end >= :begin AND Ranges.begin <= :end"; diff --git a/DRAMSys/traceAnalyzer/data/tracedb.cpp b/DRAMSys/traceAnalyzer/data/tracedb.cpp index 1a446049..81d2cbb8 100644 --- a/DRAMSys/traceAnalyzer/data/tracedb.cpp +++ b/DRAMSys/traceAnalyzer/data/tracedb.cpp @@ -548,19 +548,21 @@ std::vector> TraceDB::parseTransactionsFromQuery(QS unsigned int dataLength = query.value(4).toUInt(); unsigned int thread = query.value(5).toUInt(); unsigned int channel = query.value(6).toUInt(); - result.push_back(std::make_shared(id, address, dataLength, thread, channel, span, generalInfo.clkPeriod)); + QString command = query.value(7).toString(); + result.push_back(std::make_shared(id, std::move(command), address, dataLength, thread, channel, + span, generalInfo.clkPeriod)); } - unsigned int phaseID = query.value(7).toInt(); - QString phaseName = query.value(8).toString(); - Timespan span(query.value(9).toLongLong(), query.value(10).toLongLong()); - Timespan spanOnDataStrobe(query.value(11).toLongLong(), query.value(12).toLongLong()); - unsigned int rank = query.value(13).toUInt(); - unsigned int bankGroup = query.value(14).toUInt(); - unsigned int bank = query.value(15).toUInt(); - unsigned int row = query.value(16).toUInt(); - unsigned int column = query.value(17).toUInt(); - unsigned int burstLength = query.value(18).toUInt(); + unsigned int phaseID = query.value(8).toInt(); + QString phaseName = query.value(9).toString(); + Timespan span(query.value(10).toLongLong(), query.value(11).toLongLong()); + Timespan spanOnDataStrobe(query.value(12).toLongLong(), query.value(13).toLongLong()); + unsigned int rank = query.value(14).toUInt(); + unsigned int bankGroup = query.value(15).toUInt(); + unsigned int bank = query.value(16).toUInt(); + unsigned int row = query.value(17).toUInt(); + unsigned int column = query.value(18).toUInt(); + unsigned int burstLength = query.value(19).toUInt(); auto phase = PhaseFactory::createPhase(phaseID, phaseName, span, spanOnDataStrobe, rank, bankGroup, bank, row, column, burstLength, result.at(result.size() - 1), *this); result.at(result.size() - 1)->addPhase(phase); diff --git a/DRAMSys/traceAnalyzer/presentation/tracemetrictreewidget.h b/DRAMSys/traceAnalyzer/presentation/tracemetrictreewidget.h index 6cca4177..b487933c 100644 --- a/DRAMSys/traceAnalyzer/presentation/tracemetrictreewidget.h +++ b/DRAMSys/traceAnalyzer/presentation/tracemetrictreewidget.h @@ -46,7 +46,7 @@ class TraceMetricTreeWidget : public QTreeWidget { Q_OBJECT public: - TraceMetricTreeWidget(QWidget *parent = 0); + explicit TraceMetricTreeWidget(QWidget *parent = nullptr); void addTraceMetricResults(const TraceCalculatedMetrics &result); void addTracePlotResults(QString traceName, QString outputFiles); diff --git a/DRAMSys/traceAnalyzer/presentation/traceplot.cpp b/DRAMSys/traceAnalyzer/presentation/traceplot.cpp index d066dc1f..b0071013 100644 --- a/DRAMSys/traceAnalyzer/presentation/traceplot.cpp +++ b/DRAMSys/traceAnalyzer/presentation/traceplot.cpp @@ -309,9 +309,9 @@ void TracePlot::setUpDrawingProperties() drawingProperties.numberOfRanks = navigator->GeneralTraceInfo().numberOfRanks; drawingProperties.numberOfBankGroups = navigator->GeneralTraceInfo().numberOfBankGroups; drawingProperties.numberOfBanks = navigator->GeneralTraceInfo().numberOfBanks; - drawingProperties.banksPerRank = drawingProperties.numberOfBanks / drawingProperties.numberOfRanks; - drawingProperties.groupsPerRank = drawingProperties.numberOfBankGroups / drawingProperties.numberOfRanks; - drawingProperties.banksPerGroup = drawingProperties.numberOfBanks / drawingProperties.numberOfBankGroups; + drawingProperties.banksPerRank = navigator->GeneralTraceInfo().banksPerRank; + drawingProperties.groupsPerRank = navigator->GeneralTraceInfo().groupsPerRank; + drawingProperties.banksPerGroup = navigator->GeneralTraceInfo().banksPerGroup; drawingProperties.per2BankOffset = navigator->GeneralTraceInfo().per2BankOffset; } diff --git a/DRAMSys/traceAnalyzer/presentation/transactiontreewidget.cpp b/DRAMSys/traceAnalyzer/presentation/transactiontreewidget.cpp index 6f65ce58..b20ba0a0 100644 --- a/DRAMSys/traceAnalyzer/presentation/transactiontreewidget.cpp +++ b/DRAMSys/traceAnalyzer/presentation/transactiontreewidget.cpp @@ -50,12 +50,12 @@ TransactionTreeWidget::TransactionTreeWidget(QWidget *parent) : QTreeWidget(pare goToTransaction = new QAction("Move to", this); } -void TransactionTreeWidget::init(TraceNavigator *navigator) +void TransactionTreeWidget::init(TraceNavigator *_navigator) { Q_ASSERT(isInitialized == false); isInitialized = true; - this->navigator = navigator; + this->navigator = _navigator; setColumnCount(3); setHeaderLabels(QStringList({"Transaction", "Value", "Value"})); } @@ -96,8 +96,16 @@ TransactionTreeWidget::TransactionTreeItem::TransactionTreeItem(QTreeWidget *par auto *time = new QTreeWidgetItem({"Timespan"}); AppendTimespan(time, transaction->span); this->addChild(time); + if (!isControllerTransaction) + { + if (transaction->command == "R") + this->addChild(new QTreeWidgetItem({"Command", "Read"})); + else // if (transaction->command == "W") + this->addChild(new QTreeWidgetItem({"Command", "Write"})); + } this->addChild(new QTreeWidgetItem({"Length", prettyFormatTime(transaction->span.timeCovered())})); - this->addChild(new QTreeWidgetItem({"Address", QString("0x") + QString::number(transaction->address, 16)})); + if (!isControllerTransaction) + this->addChild(new QTreeWidgetItem({"Address", QString("0x") + QString::number(transaction->address, 16)})); if (!isControllerTransaction) this->addChild(new QTreeWidgetItem({"Data Length", QString::number(transaction->dataLength)})); this->addChild(new QTreeWidgetItem({"Channel", QString::number(transaction->channel)})); @@ -130,8 +138,8 @@ void TransactionTreeWidget::TransactionTreeItem::AppendPhase(QTreeWidgetItem *pa if (static_cast(phase.getRelevantAttributes() & RelevantAttributes::Rank)) addMapping("Rank", phase.getRank()); - if (static_cast(phase.getRelevantAttributes() & RelevantAttributes::Bankgroup)) - addMapping("Bankgroup", phase.getBankgroup()); + if (static_cast(phase.getRelevantAttributes() & RelevantAttributes::BankGroup)) + addMapping("Bank Group", phase.getBankGroup()); if (static_cast(phase.getRelevantAttributes() & RelevantAttributes::Bank)) addMapping("Bank", phase.getBank()); diff --git a/DRAMSys/traceAnalyzer/presentation/transactiontreewidget.h b/DRAMSys/traceAnalyzer/presentation/transactiontreewidget.h index 5963ee43..930b74e9 100644 --- a/DRAMSys/traceAnalyzer/presentation/transactiontreewidget.h +++ b/DRAMSys/traceAnalyzer/presentation/transactiontreewidget.h @@ -49,10 +49,10 @@ class TransactionTreeWidget : public QTreeWidget Q_OBJECT public: - TransactionTreeWidget(QWidget *parent); + explicit TransactionTreeWidget(QWidget *parent); void AppendTransaction(const std::shared_ptr &transaction); - virtual void init(TraceNavigator *navigator); + virtual void init(TraceNavigator *_navigator); public Q_SLOTS: void ContextMenuRequested(QPoint point); @@ -62,8 +62,6 @@ protected: private: bool isInitialized; - void AppendTimespan(QTreeWidgetItem *parent, const Timespan ×pan); - void AppendPhase(QTreeWidgetItem *parent, const Phase &phase); QAction *goToTransaction; class TransactionTreeItem : public QTreeWidgetItem @@ -72,7 +70,7 @@ private: static constexpr int transactionTreeItemType = 1001; TransactionTreeItem(QTreeWidget *parent, const std::shared_ptr &trans, const GeneralInfo &generalInfo); - ID Id() + ID Id() const { return id; } From 404343d2b431021b57fdba593788c6dc0e8f6347 Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Thu, 12 May 2022 15:23:22 +0200 Subject: [PATCH 17/29] Collapse phases by defaul in transaction tree widget --- .../selectedtransactiontreewidget.cpp | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/DRAMSys/traceAnalyzer/presentation/selectedtransactiontreewidget.cpp b/DRAMSys/traceAnalyzer/presentation/selectedtransactiontreewidget.cpp index b830ddc4..e2ccc598 100644 --- a/DRAMSys/traceAnalyzer/presentation/selectedtransactiontreewidget.cpp +++ b/DRAMSys/traceAnalyzer/presentation/selectedtransactiontreewidget.cpp @@ -46,6 +46,22 @@ void SelectedTransactionTreeWidget::selectedTransactionsChanged() AppendTransaction(transaction); } expandAll(); + + for (size_t k = 0; k < topLevelItemCount(); k++) + { + auto node = topLevelItem(k); + for (size_t i = 0; i < node->childCount(); i++) + { + if (node->child(i)->text(0) == "Phases") + { + auto phaseNode = node->child(i); + + for (size_t j = 0; j < phaseNode->childCount(); j++) + phaseNode->child(j)->setExpanded(false); + } + } + } + resizeColumnToContents(0); } From 5d336fea459ee6fe6c5205509884b948319c19f5 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Fri, 13 May 2022 11:00:53 +0200 Subject: [PATCH 18/29] Add address checks. --- .../library/src/simulation/AddressDecoder.cpp | 34 +++++++++++++++++-- DRAMSys/library/src/simulation/Arbiter.cpp | 1 + 2 files changed, 33 insertions(+), 2 deletions(-) diff --git a/DRAMSys/library/src/simulation/AddressDecoder.cpp b/DRAMSys/library/src/simulation/AddressDecoder.cpp index cd9321de..4179ca70 100644 --- a/DRAMSys/library/src/simulation/AddressDecoder.cpp +++ b/DRAMSys/library/src/simulation/AddressDecoder.cpp @@ -101,14 +101,44 @@ AddressDecoder::AddressDecoder(const Configuration& config, const DRAMSysConfigu maximumAddress = static_cast(bytes) * columns * rows * banks * bankGroups * ranks * channels - 1; + auto totalAddressBits = static_cast(std::log2(maximumAddress)); + for (unsigned bitPosition = 0; bitPosition < totalAddressBits; bitPosition++) + { + if (std::count(vChannelBits.begin(), vChannelBits.end(), bitPosition) + + std::count(vRankBits.begin(), vRankBits.end(), bitPosition) + + std::count(vBankGroupBits.begin(), vBankGroupBits.end(), bitPosition) + + std::count(vBankBits.begin(), vBankBits.end(), bitPosition) + + std::count(vRowBits.begin(), vRowBits.end(), bitPosition) + + std::count(vColumnBits.begin(), vColumnBits.end(), bitPosition) + + std::count(vByteBits.begin(), vByteBits.end(), bitPosition) + != 1) + SC_REPORT_FATAL("AddressDecoder", "Not all address bits occur exactly once"); + } + + const MemSpec& memSpec = *config.memSpec; + + unsigned highestByteBit = *std::max_element(vByteBits.begin(), vByteBits.end()); + + for (unsigned bitPosition = 0; bitPosition <= highestByteBit; bitPosition++) + { + if (std::find(vByteBits.begin(), vByteBits.end(), bitPosition) == vByteBits.end()) + SC_REPORT_FATAL("AddressDecoder", "Byte bits are not continuous starting from 0"); + } + + auto maxBurstLengthBits = static_cast(std::log2(memSpec.maxBurstLength)); + + for (unsigned bitPosition = highestByteBit + 1; bitPosition < highestByteBit + 1 + maxBurstLengthBits; bitPosition++) + { + if (std::find(vColumnBits.begin(), vColumnBits.end(), bitPosition) == vColumnBits.end()) + SC_REPORT_FATAL("AddressDecoder", "No continuous column bits for maximum burst length"); + } + bankgroupsPerRank = bankGroups; bankGroups = bankgroupsPerRank * ranks; banksPerGroup = banks; banks = banksPerGroup * bankGroups; - const MemSpec& memSpec = *config.memSpec; - if (memSpec.numberOfChannels != channels || memSpec.ranksPerChannel != ranks || memSpec.bankGroupsPerChannel != bankGroups || memSpec.banksPerChannel != banks || memSpec.rowsPerBank != rows || memSpec.columnsPerRow != columns diff --git a/DRAMSys/library/src/simulation/Arbiter.cpp b/DRAMSys/library/src/simulation/Arbiter.cpp index 57c545bf..39a911e6 100644 --- a/DRAMSys/library/src/simulation/Arbiter.cpp +++ b/DRAMSys/library/src/simulation/Arbiter.cpp @@ -139,6 +139,7 @@ tlm_sync_enum Arbiter::nb_transport_fw(int id, tlm_generic_payload &payload, payload.set_address(adjustedAddress); unsigned channel = addressDecoder.decodeChannel(adjustedAddress); + assert(addressDecoder.decodeChannel(adjustedAddress + payload.get_data_length() - 1) == channel); ArbiterExtension::setAutoExtension(payload, Thread(id), Channel(channel)); payload.acquire(); } From 5237f70439bc067aabb008a24ed599bb6fd66757 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Fri, 13 May 2022 14:38:32 +0200 Subject: [PATCH 19/29] Fix unaligned bursts. --- DRAMSys/library/src/controller/Controller.cpp | 69 +++++++++++++------ DRAMSys/library/src/controller/Controller.h | 3 +- .../businessObjects/phases/phase.h | 16 +++-- .../presentation/transactiontreewidget.cpp | 3 + 4 files changed, 65 insertions(+), 26 deletions(-) diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index 248efc6f..d97a252b 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -73,6 +73,7 @@ Controller::Controller(const sc_module_name& name, const Configuration& config, ControllerIF(name, config), addressDecoder(addressDecoder), thinkDelayFw(config.thinkDelayFw), thinkDelayBw(config.thinkDelayBw), phyDelayFw(config.phyDelayFw), phyDelayBw(config.phyDelayBw), + minBytesPerBurst(config.memSpec->defaultBytesPerBurst), maxBytesPerBurst(config.memSpec->maxBytesPerBurst) { SC_METHOD(controllerMethod); @@ -402,20 +403,23 @@ void Controller::manageRequests(const sc_time &delay) { if (transToAcquire.payload != nullptr && transToAcquire.time <= sc_time_stamp()) { - // TODO: here we assume that the scheduler always has space not only for a single burst transaction but for a maximum size transaction + // TODO: here we assume that the scheduler always has space not only for a single burst transaction + // but for a maximum size transaction if (scheduler->hasBufferSpace()) { - //NDEBUG_UNUSED(uint64_t id) = ControllerExtension::getChannelPayloadID(*transToAcquire.payload); - //PRINTDEBUGMESSAGE(name(), "Payload " + std::to_string(id) + " entered system."); - if (totalNumberOfPayloads == 0) idleTimeCollector.end(); totalNumberOfPayloads++; // seems to be ok transToAcquire.payload->acquire(); - unsigned numChildTranses = transToAcquire.payload->get_data_length() / maxBytesPerBurst; - if (numChildTranses <= 1) + // Align address to minimum burst length + uint64_t alignedAddress = transToAcquire.payload->get_address() & ~(minBytesPerBurst - UINT64_C(1)); + transToAcquire.payload->set_address(alignedAddress); + + // continuous block of data that can be fetched with a single burst + if ((alignedAddress / maxBytesPerBurst) + == ((alignedAddress + transToAcquire.payload->get_data_length() - 1) / maxBytesPerBurst)) { DecodedAddress decodedAddress = addressDecoder.decodeAddress(transToAcquire.payload->get_address()); ControllerExtension::setAutoExtension(*transToAcquire.payload, nextChannelPayloadIDToAppend++, @@ -435,25 +439,18 @@ void Controller::manageRequests(const sc_time &delay) } else { - createChildTranses(*transToAcquire.payload, numChildTranses); + createChildTranses(*transToAcquire.payload); const std::vector& childTranses = transToAcquire.payload->get_extension()->getChildTranses(); for (auto* childTrans : childTranses) { - DecodedAddress decodedAddress = addressDecoder.decodeAddress(childTrans->get_address()); - ControllerExtension::setAutoExtension(*childTrans, nextChannelPayloadIDToAppend, - Rank(decodedAddress.rank), BankGroup(decodedAddress.bankgroup), - Bank(decodedAddress.bank), Row(decodedAddress.row), - Column(decodedAddress.column), - childTrans->get_data_length() / memSpec.bytesPerBeat); - - Rank rank = Rank(decodedAddress.rank); + Rank rank = ControllerExtension::getRank(*childTrans); if (ranksNumberOfPayloads[rank.ID()] == 0) powerDownManagers[rank.ID()]->triggerExit(); ranksNumberOfPayloads[rank.ID()]++; scheduler->storeRequest(*childTrans); - Bank bank = Bank(decodedAddress.bank); + Bank bank = ControllerExtension::getBank(*childTrans); bankMachines[bank.ID()]->start(); } nextChannelPayloadIDToAppend++; @@ -488,10 +485,11 @@ void Controller::manageResponses() idleTimeCollector.start(); } } + else + return; // END_RESP not completed } tlm_generic_payload* nextPayloadInRespQueue = respQueue->nextPayload(); - if (nextPayloadInRespQueue != nullptr) { numberOfBeatsServed += ControllerExtension::getBurstLength(*nextPayloadInRespQueue); @@ -576,20 +574,51 @@ void Controller::MemoryManager::free(tlm::tlm_generic_payload* payload) freePayloads.push(payload); } -void Controller::createChildTranses(tlm::tlm_generic_payload& parentTrans, unsigned int numChildTranses) +void Controller::createChildTranses(tlm::tlm_generic_payload& parentTrans) { std::vector childTranses; + uint64_t startAddress = parentTrans.get_address() & ~(maxBytesPerBurst - UINT64_C(1)); + unsigned char* startDataPtr = parentTrans.get_data_ptr(); + unsigned numChildTranses = parentTrans.get_data_length() / maxBytesPerBurst; + for (unsigned childId = 0; childId < numChildTranses; childId++) { tlm_generic_payload& childTrans = memoryManager.allocate(); childTrans.acquire(); childTrans.set_command(parentTrans.get_command()); - childTrans.set_address(parentTrans.get_address() + childId * maxBytesPerBurst); + childTrans.set_address(startAddress + childId * maxBytesPerBurst); childTrans.set_data_length(maxBytesPerBurst); - childTrans.set_data_ptr(parentTrans.get_data_ptr() + childId * maxBytesPerBurst); + childTrans.set_data_ptr(startDataPtr + childId * maxBytesPerBurst); ChildExtension::setExtension(childTrans, parentTrans); childTranses.push_back(&childTrans); } + + if (startAddress != parentTrans.get_address()) + { + tlm_generic_payload& firstChildTrans = *childTranses.front(); + firstChildTrans.set_address(firstChildTrans.get_address() + minBytesPerBurst); + firstChildTrans.set_data_ptr(firstChildTrans.get_data_ptr() + minBytesPerBurst); + firstChildTrans.set_data_length(minBytesPerBurst); + tlm_generic_payload& lastChildTrans = memoryManager.allocate(); + lastChildTrans.acquire(); + lastChildTrans.set_command(parentTrans.get_command()); + lastChildTrans.set_address(startAddress + numChildTranses * maxBytesPerBurst); + lastChildTrans.set_data_length(minBytesPerBurst); + lastChildTrans.set_data_ptr(startDataPtr + numChildTranses * maxBytesPerBurst); + ChildExtension::setExtension(lastChildTrans, parentTrans); + childTranses.push_back(&lastChildTrans); + } + + for (auto* childTrans : childTranses) + { + DecodedAddress decodedAddress = addressDecoder.decodeAddress(childTrans->get_address()); + ControllerExtension::setAutoExtension(*childTrans, nextChannelPayloadIDToAppend, + Rank(decodedAddress.rank), BankGroup(decodedAddress.bankgroup), + Bank(decodedAddress.bank), Row(decodedAddress.row), + Column(decodedAddress.column), + childTrans->get_data_length() / memSpec.bytesPerBeat); + } + nextChannelPayloadIDToAppend++; ParentExtension::setExtension(parentTrans, std::move(childTranses)); } \ No newline at end of file diff --git a/DRAMSys/library/src/controller/Controller.h b/DRAMSys/library/src/controller/Controller.h index 2432099d..58ebbd69 100644 --- a/DRAMSys/library/src/controller/Controller.h +++ b/DRAMSys/library/src/controller/Controller.h @@ -102,9 +102,10 @@ private: sc_core::sc_event beginReqEvent, endRespEvent, controllerEvent, dataResponseEvent; + const unsigned minBytesPerBurst; const unsigned maxBytesPerBurst; - void createChildTranses(tlm::tlm_generic_payload& parentTrans, unsigned numChildTranses); + void createChildTranses(tlm::tlm_generic_payload& parentTrans); class MemoryManager : public tlm::tlm_mm_interface { diff --git a/DRAMSys/traceAnalyzer/businessObjects/phases/phase.h b/DRAMSys/traceAnalyzer/businessObjects/phases/phase.h index ebfb6f8f..e6fab72a 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/phases/phase.h +++ b/DRAMSys/traceAnalyzer/businessObjects/phases/phase.h @@ -60,7 +60,8 @@ enum class RelevantAttributes BankGroup = 0x02, Bank = 0x04, Row = 0x08, - Column = 0x10 + Column = 0x10, + BurstLength = 0x20 }; inline RelevantAttributes operator|(RelevantAttributes a, RelevantAttributes b) @@ -127,6 +128,11 @@ public: return column; } + unsigned int getBurstLength() const + { + return burstLength; + } + virtual RelevantAttributes getRelevantAttributes() const = 0; virtual QString Name() const = 0; @@ -376,7 +382,7 @@ protected: RelevantAttributes getRelevantAttributes() const override { return RelevantAttributes::Rank | RelevantAttributes::BankGroup | RelevantAttributes::Bank | - RelevantAttributes::Column; + RelevantAttributes::Column | RelevantAttributes::BurstLength; } }; @@ -398,7 +404,7 @@ protected: RelevantAttributes getRelevantAttributes() const override { return RelevantAttributes::Rank | RelevantAttributes::BankGroup | RelevantAttributes::Bank | - RelevantAttributes::Column; + RelevantAttributes::Column | RelevantAttributes::BurstLength; } }; @@ -420,7 +426,7 @@ protected: RelevantAttributes getRelevantAttributes() const override { return RelevantAttributes::Rank | RelevantAttributes::BankGroup | RelevantAttributes::Bank | - RelevantAttributes::Column; + RelevantAttributes::Column | RelevantAttributes::BurstLength; } }; @@ -442,7 +448,7 @@ protected: RelevantAttributes getRelevantAttributes() const override { return RelevantAttributes::Rank | RelevantAttributes::BankGroup | RelevantAttributes::Bank | - RelevantAttributes::Column; + RelevantAttributes::Column | RelevantAttributes::BurstLength; } }; diff --git a/DRAMSys/traceAnalyzer/presentation/transactiontreewidget.cpp b/DRAMSys/traceAnalyzer/presentation/transactiontreewidget.cpp index b20ba0a0..b8d5137c 100644 --- a/DRAMSys/traceAnalyzer/presentation/transactiontreewidget.cpp +++ b/DRAMSys/traceAnalyzer/presentation/transactiontreewidget.cpp @@ -149,6 +149,9 @@ void TransactionTreeWidget::TransactionTreeItem::AppendPhase(QTreeWidgetItem *pa if (static_cast(phase.getRelevantAttributes() & RelevantAttributes::Column)) addMapping("Column", phase.getColumn()); + + if (static_cast(phase.getRelevantAttributes() & RelevantAttributes::BurstLength)) + addMapping("Burst Length", phase.getBurstLength()); } } From 005ac89cb3c811846f430ded3982a067557267b9 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Tue, 17 May 2022 11:18:43 +0200 Subject: [PATCH 20/29] Adapt metrics to new DB format. --- DRAMSys/traceAnalyzer/scripts/memUtil.py | 9 +- DRAMSys/traceAnalyzer/scripts/metrics.py | 467 +++++++++++------------ 2 files changed, 231 insertions(+), 245 deletions(-) diff --git a/DRAMSys/traceAnalyzer/scripts/memUtil.py b/DRAMSys/traceAnalyzer/scripts/memUtil.py index 774006ba..e6444a11 100755 --- a/DRAMSys/traceAnalyzer/scripts/memUtil.py +++ b/DRAMSys/traceAnalyzer/scripts/memUtil.py @@ -140,25 +140,26 @@ def getControllerThread(connection): def get_phase_occurrences(connection, phase): cursor = connection.cursor() - query = "select count(*) from Phases where PhaseName = :phase" + query = "SELECT count(*) FROM Phases WHERE PhaseName = :phase" cursor.execute(query, {"phase": phase}) r = cursor.fetchone() cnt = r[0] - if (cnt is None): + if cnt is None: cnt = 0 return cnt def get_total_time_in_phase(connection, phase): cursor = connection.cursor() - query = "select sum(PhaseEnd - PhaseBegin) / 1000 from Phases where PhaseName = :phase" + query = "SELECT SUM(PhaseEnd - PhaseBegin) / 1000 FROM Phases WHERE PhaseName = :phase" cursor.execute(query, {"phase": phase}) time = cursor.fetchone() totalTime = time[0] - if (totalTime is None): + if totalTime is None: totalTime = 0.0 return totalTime + def getCommandLengthForPhase(connection, phase): cursor = connection.cursor() cursor.execute("SELECT " + phase + " FROM CommandLengths") diff --git a/DRAMSys/traceAnalyzer/scripts/metrics.py b/DRAMSys/traceAnalyzer/scripts/metrics.py index 6bf5529b..98e2445f 100644 --- a/DRAMSys/traceAnalyzer/scripts/metrics.py +++ b/DRAMSys/traceAnalyzer/scripts/metrics.py @@ -21,8 +21,7 @@ def threadMetric(function): def getThreads(connection): cthread = getControllerThread(connection) cursor = connection.cursor() - query = "SELECT DISTINCT(TThread) FROM transactions WHERE TThread != " + str(cthread) + " ORDER BY TThread" - cursor.execute(query) + cursor.execute("SELECT DISTINCT(Thread) FROM Transactions WHERE Thread != " + str(cthread) + " ORDER BY Thread") result = [] for currentRow in cursor: result.append(currentRow[0]) @@ -32,10 +31,11 @@ def getThreads(connection): @metric def trace_length_in_ns(connection): cursor = connection.cursor() - cursor.execute(""" SELECT max(PhaseEnd)/1000 FROM PHASES; """) + cursor.execute("SELECT MAX(PhaseEnd) / 1000 FROM Phases") result = cursor.fetchone() return result[0] + @metric def command_bus_utilisation_in_percent(connection): cursor = connection.cursor() @@ -75,7 +75,7 @@ def command_bus_utilisation_in_percent(connection): ON Phases.PhaseName = CommandLengths.Command """) util = cursor.fetchone()[0] - if (util is None): + if util is None: util = 0 clk, _ = getClock(connection) @@ -83,142 +83,133 @@ def command_bus_utilisation_in_percent(connection): commandBusOccupied = util * clk / traceEnd * 100 return ": {}".format(commandBusOccupied) + @metric def average_response_latency_in_ns(connection): cursor = connection.cursor() - cursor.execute("""SELECT AVG(RESP.PHASEBEGIN - REQ.PHASEBEGIN)/1000 FROM PHASES REQ, PHASES RESP - WHERE REQ.PHASENAME = 'REQ' AND RESP.PHASENAME='RESP' AND REQ.TRANSACT = RESP.TRANSACT """) + cursor.execute(""" + SELECT AVG(Resp.PhaseBegin - Req.PhaseBegin) / 1000 + FROM Phases Req, Phases Resp + WHERE Req.PhaseName = 'REQ' AND Resp.PhaseName='RESP' AND Req.Transact = Resp.Transact + """) result = cursor.fetchone() return round(result[0], 1) + @metric def average_rd_response_latency_in_ns(connection): cursor = connection.cursor() cursor.execute(""" - SELECT - AVG(RESP.PHASEBEGIN - REQ.PHASEBEGIN) / 1000 - FROM - PHASES REQ, - PHASES RESP - INNER JOIN - Transactions - ON REQ.TRANSACT = Transactions.ID - WHERE - REQ.PHASENAME = 'REQ' - AND RESP.PHASENAME = 'RESP' - AND REQ.TRANSACT = RESP.TRANSACT - AND Transactions.Command = "R" + SELECT AVG(Resp.PhaseBegin - Req.PhaseBegin) / 1000 + FROM Phases Req, Phases Resp + INNER JOIN Transactions + ON Req.Transact = Transactions.ID + WHERE Req.PhaseName = 'REQ' AND Resp.PhaseName = 'RESP' + AND Req.Transact = Resp.Transact AND Transactions.Command = 'R' """) result = cursor.fetchone() return round(result[0], 1) + @metric def average_wr_response_latency_in_ns(connection): cursor = connection.cursor() cursor.execute(""" - SELECT - AVG(RESP.PHASEBEGIN - REQ.PHASEBEGIN) / 1000 - FROM - PHASES REQ, - PHASES RESP - INNER JOIN - Transactions - ON REQ.TRANSACT = Transactions.ID - WHERE - REQ.PHASENAME = 'REQ' - AND RESP.PHASENAME = 'RESP' - AND REQ.TRANSACT = RESP.TRANSACT - AND Transactions.Command = "W" + SELECT AVG(Resp.PhaseBegin - Req.PhaseBegin) / 1000 + FROM Phases Req, Phases Resp + INNER JOIN Transactions + ON Req.Transact = Transactions.ID + WHERE Req.PhaseName = 'REQ' AND Resp.PhaseName = 'RESP' + AND Req.Transact = Resp.Transact AND Transactions.Command = 'W' """) result = cursor.fetchone() return round(result[0], 1) + @metric def max_response_latency_in_ns(connection): cursor = connection.cursor() - cursor.execute(""" SELECT max(RESP.PHASEBEGIN - REQ.PHASEBEGIN)/1000 FROM PHASES REQ, PHASES RESP - WHERE REQ.PHASENAME = 'REQ' AND RESP.PHASENAME='RESP' AND REQ.TRANSACT = RESP.TRANSACT """) + cursor.execute(""" + SELECT MAX(Resp.PhaseBegin - Req.PhaseBegin) / 1000 + FROM Phases Req, Phases Resp + WHERE Req.PhaseName = 'REQ' AND Resp.PhaseName = 'RESP' AND Req.Transact = Resp.Transact + """) result = cursor.fetchone() return result[0] + @metric def max_rd_response_latency_in_ns(connection): cursor = connection.cursor() cursor.execute(""" - SELECT - max(RESP.PHASEBEGIN - REQ.PHASEBEGIN) / 1000 - FROM - PHASES REQ, - PHASES RESP - INNER JOIN - Transactions - ON REQ.TRANSACT = Transactions.ID - WHERE - REQ.PHASENAME = 'REQ' - AND RESP.PHASENAME = 'RESP' - AND REQ.TRANSACT = RESP.TRANSACT - AND Transactions.Command = "R" + SELECT MAX(Resp.PhaseBegin - Req.PhaseBegin) / 1000 + FROM Phases Req, Phases Resp + INNER JOIN Transactions + ON Req.Transact = Transactions.ID + WHERE Req.PhaseName = 'REQ' AND Resp.PhaseName = 'RESP' + AND Req.Transact = Resp.Transact AND Transactions.Command = 'R' """) result = cursor.fetchone() return round(result[0], 1) + @metric def max_wr_response_latency_in_ns(connection): cursor = connection.cursor() cursor.execute(""" - SELECT - max(RESP.PHASEBEGIN - REQ.PHASEBEGIN) / 1000 - FROM - PHASES REQ, - PHASES RESP - INNER JOIN - Transactions - ON REQ.TRANSACT = Transactions.ID - WHERE - REQ.PHASENAME = 'REQ' - AND RESP.PHASENAME = 'RESP' - AND REQ.TRANSACT = RESP.TRANSACT - AND Transactions.Command = "W" + SELECT MAX(Resp.PhaseBegin - Req.PhaseBegin) / 1000 + FROM Phases Req, Phases Resp + INNER JOIN Transactions + ON Req.Transact = Transactions.ID + WHERE Req.PhaseName = 'REQ' AND Resp.PhaseName = 'RESP' + AND Req.Transact = Resp.Transact AND Transactions.Command = 'W' """) result = cursor.fetchone() return round(result[0], 1) + @metric def trans_with_max_response_latency(connection): cursor = connection.cursor() - cursor.execute(""" SELECT REQ.TRANSACT, max(RESP.PHASEBEGIN - REQ.PHASEBEGIN)/1000 FROM PHASES REQ, PHASES RESP - WHERE REQ.PHASENAME = 'REQ' AND RESP.PHASENAME='RESP' AND REQ.TRANSACT = RESP.TRANSACT """) + cursor.execute(""" + SELECT Req.Transact, MAX(Resp.PhaseBegin - Req.PhaseBegin) / 1000 + FROM Phases Req, Phases Resp + WHERE Req.PhaseName = 'REQ' AND Resp.PhaseName = 'RESP' AND Req.Transact = Resp.Transact + """) result = cursor.fetchone() return result[0] + @metric def memory_active_in_clks(connection): cursor = connection.cursor() - cursor.execute("""SELECT sum(DataStrobeEnd - DataStrobeBegin) FROM Transactions""") + cursor.execute("SELECT SUM(DataStrobeEnd - DataStrobeBegin) FROM Phases") active = cursor.fetchone()[0] if getPseudoChannelMode(connection): active /= 2 clk, _ = getClock(connection) - return (active / clk) + return active / clk + @metric def memory_total_in_clks(connection): cursor = connection.cursor() - cursor.execute(""" SELECT max(DataStrobeEnd) FROM Transactions """) + cursor.execute("SELECT MAX(DataStrobeEnd) FROM Phases") total = cursor.fetchone() clk, _ = getClock(connection) - return (total[0]/clk) + return total[0] / clk + @metric def memory_idle_in_clks(connection): - # This complex query identifies idle times where the DRAM is not used. + # This complex query identifies idle times when the DRAM is not used. # The code works also if schedulers are used. cursor = connection.cursor() # Create a table with transactions sorted by BeginRequest: # (RowNum, BeginRequest) - query = """ DROP TABLE IF EXISTS transactionsInRequestOrder; """ + query = """DROP TABLE IF EXISTS transactionsInRequestOrder;""" cursor.execute(query) query = """ @@ -229,50 +220,50 @@ def memory_idle_in_clks(connection): FROM Phases p WHERE - p.PhaseName = "REQ"; + p.PhaseName = 'REQ'; """ cursor.execute(query) # Create a table with transactions sorted by BeginResponse: # (RowNum, ID, EndResponse) - query = """ DROP TABLE IF EXISTS transactionsInResponseOrder; """ + query = """DROP TABLE IF EXISTS transactionsInResponseOrder;""" cursor.execute(query) query = """ CREATE TEMPORARY TABLE transactionsInResponseOrder AS SELECT ROW_NUMBER () OVER (ORDER BY q.PhaseBegin) RowNum, - q.Transact AS ID, - q.PhaseEnd AS EndResponse + q.PhaseEnd AS EndResponse FROM Phases q WHERE - q.PhaseName = "RESP"; + q.PhaseName = 'RESP'; """ cursor.execute(query) # Sum up the idle times: query = """ SELECT - sum(c.BeginRequest - b.EndResponse) AS idle + SUM(c.BeginRequest - b.EndResponse) AS idle FROM transactionsInRequestOrder AS a, transactionsInResponseOrder AS b, transactionsInRequestOrder AS c WHERE - a.RowNum=b.RowNum AND - c.RowNum=(a.RowNum+1) AND - c.BeginRequest>b.EndResponse; + a.RowNum = b.RowNum AND + c.RowNum = (a.RowNum + 1) AND + c.BeginRequest > b.EndResponse; """ cursor.execute(query) idle = cursor.fetchone() - cursor.execute(""" SELECT min(PhaseBegin) FROM Phases WHERE PhaseName = 'REQ' """) + cursor.execute("""SELECT MIN(PhaseBegin) FROM Phases WHERE PhaseName = 'REQ'""") idle_start = cursor.fetchone() clk, unit = getClock(connection) - if (idle[0] is None): - return (idle_start[0] / clk) + if idle[0] is None: + return idle_start[0] / clk else: - return ((idle[0] + idle_start[0]) / clk) + return (idle[0] + idle_start[0]) / clk + @metric def memory_delayed_in_clks(connection): @@ -281,71 +272,69 @@ def memory_delayed_in_clks(connection): idle = memory_idle_in_clks(connection) return total - active - idle + @metric def delayed_reasons(connection): cursor = connection.cursor() - # Create a table with sorted Datastrobes: + # Create a table with sorted data strobes: # (RowNum, ID, Begin, End) - query = """ DROP TABLE IF EXISTS dataStrobesInOrder; """ - cursor.execute(query) + cursor.execute("DROP TABLE IF EXISTS dataStrobesInOrder;") - query = """ + cursor.execute(""" CREATE TEMPORARY TABLE dataStrobesInOrder AS SELECT - ROW_NUMBER () OVER (ORDER BY t.DataStrobeBegin) RowNum, - t.ID as ID, - t.DataStrobeBegin as Begin, - t.DataStrobeEnd as End, - t.TRow as Row, - t.TBank as Bank, - t.Command as Command + ROW_NUMBER () OVER (ORDER BY DataStrobeBegin) RowNum, + Transact AS ID, + DataStrobeBegin AS Begin, + DataStrobeEnd AS End, + Row, + Bank, + PhaseName AS Command FROM - Transactions t + Phases WHERE - t.DataStrobeBegin <> 0 AND - t.DataStrobeEnd <> 0; - """ - cursor.execute(query) + DataStrobeBegin <> 0 AND + DataStrobeEnd <> 0; + """) # Create a table with transactions sorted by BeginRequest: # (RowNum, BeginRequest) - query = """ DROP TABLE IF EXISTS transactionsInRequestOrder; """ - cursor.execute(query) + cursor.execute("""DROP TABLE IF EXISTS transactionsInRequestOrder;""") query = """ CREATE TEMPORARY TABLE transactionsInRequestOrder AS SELECT - ROW_NUMBER () OVER (ORDER BY p.PhaseBegin) RowNum, - p.PhaseBegin AS BeginRequest + ROW_NUMBER () OVER (ORDER BY PhaseBegin) RowNum, + PhaseBegin AS BeginRequest FROM - Phases p + Phases WHERE - p.PhaseName = "REQ"; + PhaseName = 'REQ'; """ cursor.execute(query) # Create a table with transactions sorted by BeginResponse: # (RowNum, ID, EndResponse) - query = """ DROP TABLE IF EXISTS transactionsInResponseOrder; """ + query = """DROP TABLE IF EXISTS transactionsInResponseOrder;""" cursor.execute(query) query = """ CREATE TEMPORARY TABLE transactionsInResponseOrder AS SELECT - ROW_NUMBER () OVER (ORDER BY q.PhaseBegin) RowNum, - q.Transact AS ID, - q.PhaseEnd AS EndResponse + ROW_NUMBER () OVER (ORDER BY PhaseBegin) RowNum, + Transact AS ID, + PhaseEnd AS EndResponse FROM - Phases q + Phases WHERE - q.PhaseName = "RESP"; + PhaseName = 'RESP'; """ cursor.execute(query) - # Create a table with transaction IDs that start a idle time: + # Create a table with transaction IDs that start an idle time: # (ID) - query = """ DROP TABLE IF EXISTS idleGaps; """ + query = """DROP TABLE IF EXISTS idleGaps;""" cursor.execute(query) query = """ @@ -355,15 +344,15 @@ def delayed_reasons(connection): FROM transactionsInRequestOrder AS a, transactionsInResponseOrder AS b, transactionsInRequestOrder AS c WHERE - a.RowNum=b.RowNum AND - c.RowNum=(a.RowNum+1) AND - c.BeginRequest>b.EndResponse; + a.RowNum = b.RowNum AND + c.RowNum = (a.RowNum + 1) AND + c.BeginRequest > b.EndResponse; """ cursor.execute(query) - # Create a table which features IDs that form gaps on the databus: + # Create a table which features IDs that form gaps on the data bus: # (gapBeginID, gapEndID) - query = """ DROP TABLE IF EXISTS delayedDataBusGaps; """ + query = """DROP TABLE IF EXISTS delayedDataBusGaps;""" cursor.execute(query) query = """ @@ -377,9 +366,9 @@ def delayed_reasons(connection): dataStrobesInOrder a, dataStrobesInOrder b WHERE - (a.RowNum) = (b.RowNum-1) AND + a.RowNum = b.RowNum - 1 AND b.Begin > a.End AND - a.ID not in (SELECT ID FROM idleGaps); + a.ID NOT IN (SELECT ID FROM idleGaps); """ cursor.execute(query) @@ -389,8 +378,8 @@ def delayed_reasons(connection): COUNT(*) FROM delayedDataBusGaps WHERE - gapBeginCommand = "R" AND - gapEndCommand = "W"; + (gapBeginCommand = 'RD' OR gapBeginCommand = 'RDA') AND + (gapEndCommand = 'WR' OR gapEndCommand = 'WRA'); """ cursor.execute(query) RW = cursor.fetchone()[0] @@ -402,8 +391,8 @@ def delayed_reasons(connection): FROM delayedDataBusGaps WHERE - gapBeginCommand = "W" AND - gapEndCommand = "R"; + (gapBeginCommand = 'WR' OR gapBeginCommand = 'WRA') AND + (gapEndCommand = 'RD' OR gapEndCommand = 'RDA'); """ cursor.execute(query) WR = cursor.fetchone()[0] @@ -417,10 +406,10 @@ def delayed_reasons(connection): FROM delayedDataBusGaps d, Phases p WHERE - d.gapBeginCommand = "R" AND - d.gapEndCommand = "R" AND + (d.gapBeginCommand = 'RD' OR d.gapBeginCommand = 'RDA') AND + (d.gapEndCommand = 'RD' OR d.gapEndCommand = 'RDA') AND p.Transact = d.gapEndID AND - p.PhaseName = "ACT" + p.PhaseName = 'ACT' GROUP BY d.gapBeginID ) @@ -437,10 +426,10 @@ def delayed_reasons(connection): FROM delayedDataBusGaps d, Phases p WHERE - d.gapBeginCommand = "W" AND - d.gapEndCommand = "W" AND + (d.gapBeginCommand = 'WR' OR d.gapBeginCommand = 'WRA') AND + (d.gapEndCommand = 'WR' OR d.gapEndCommand = 'WRA') AND p.Transact = d.gapEndID AND - p.PhaseName = "ACT" + p.PhaseName = 'ACT' GROUP BY d.gapBeginID ) @@ -468,27 +457,33 @@ def delayed_reasons(connection): result = "RW: {}, WR: {}, RRM: {}, WWM: {}, Other: {}".format(RW, WR, RRM, WWM, other) return result + @metric def memory_idle_in_percent(connection): total = memory_total_in_clks(connection) idle = memory_idle_in_clks(connection) return (idle/total)*100 + @metric def memory_active_in_percent(connection): total = memory_total_in_clks(connection) active = memory_active_in_clks(connection) return (active/total)*100 + @metric def memory_delayed_in_percent(connection): total = memory_total_in_clks(connection) delayed = memory_delayed_in_clks(connection) return (delayed/total)*100 + @metric def memory_idle_active_delayed_check(connection): - return memory_idle_in_percent(connection) + memory_active_in_percent(connection) + memory_delayed_in_percent(connection) + return memory_idle_in_percent(connection) + memory_active_in_percent(connection) \ + + memory_delayed_in_percent(connection) + @metric def memory_utilisation_percent_without_idle(connection): @@ -497,72 +492,77 @@ def memory_utilisation_percent_without_idle(connection): idle = memory_idle_in_clks(connection) return (active/(total-idle))*100 + @metric def memory_utilisation_in_Gibps_without_idle(connection): - # This function calculates the memory utilisation in Gibit/s considering the memory_utilisation_percent_new function result. + # This function calculates the memory utilisation in Gibit/s considering + # the memory_utilisation_percent_new function result. maxDataRate = maximum_data_rate(connection) memoryPercent = memory_utilisation_percent_without_idle(connection) return (memoryPercent/100)*(maxDataRate/1024) + @metric def memory_utilisation_percent_including_idle(connection): cursor = connection.cursor() - cursor.execute(""" SELECT sum(DataStrobeEnd - DataStrobeBegin) FROM transactions """) + cursor.execute("""SELECT SUM(DataStrobeEnd - DataStrobeBegin) FROM Phases""") active = cursor.fetchone() cursor = connection.cursor() - cursor.execute(""" SELECT max(DataStrobeEnd) FROM Transactions """) + cursor.execute("""SELECT MAX(DataStrobeEnd) FROM Phases""") total = cursor.fetchone() - return (active[0]/total[0])*100 + return (active[0] / total[0]) * 100 -def refreshMissDecision(connection, calculatedMetrics): - cursor = connection.cursor() - cursor.execute("""SELECT phases.ID,PhaseBegin,PhaseEnd,TBank FROM Phases INNER JOIN transactions - on transactions.id = phases.transact WHERE PhaseName IN ('REFAB')' """) - queryMinREQ = """SELECT id,min(PhaseBegin) FROM (SELECT transactions.id, PhaseBegin FROM transactions - inner join ranges on ranges.id = transactions.range inner join phases on phases.transact = transactions.id - where tthread != 0 and tbank = :bank and PhaseName = "REQ" and ranges.begin<:begin and ranges.end>:end)""" - queryMinRESP = """SELECT id,min(PhaseBegin) FROM (SELECT transactions.id, PhaseBegin FROM transactions - inner join ranges on ranges.id = transactions.range inner join phases on phases.transact = transactions.id - where tthread != 0 and tbank = :bank and PhaseName = "RESP" and ranges.begin<:begin and ranges.end>:end) """ - - missDecisions = 0 - totalDecisios = 0 - - for refresh in cursor: - id = refresh[0] - begin = refresh[1] - end = refresh[2] - bank = refresh[3] - # print('Refresh: {0} {1} {2} {3}'.format(id,begin,end,bank)) - - cursorMinREQ = connection.cursor() - cursorMinRESP = connection.cursor() - - cursorMinREQ.execute(queryMinREQ, {"bank": bank, "begin": begin, "end": end}) - cursorMinRESP.execute(queryMinRESP, {"bank": bank, "begin": begin, "end": end}) - - earliestReq = cursorMinREQ.fetchone() - earliestResp = cursorMinRESP.fetchone() - if (earliestReq[0] is not None): - totalDecisios = totalDecisios + 1 - if(earliestReq[0] != earliestResp[0]): - missDecisions = missDecisions + 1 - # print("earliest Req: {0}| earliest Res: {1}".format(earliestReq[0], earliestResp[0])) - - if (totalDecisios != 0): - # calculatedMetrics.append(("Total Missdecisions", missDecisions)) - calculatedMetrics.append(("Relative Missdecisions", 1.0*missDecisions/totalDecisios)) - else: - calculatedMetrics.append(("Total Missdecisions", 0)) - calculatedMetrics.append(("Relative Missdecisions", 0)) +# def refreshMissDecision(connection, calculatedMetrics): +# cursor = connection.cursor() +# cursor.execute("""SELECT Phases.ID, PhaseBegin, PhaseEnd, TBank FROM Phases INNER JOIN Transactions +# ON Transactions.ID = Phases.Transact WHERE PhaseName IN ('REFAB')' """) +# queryMinREQ = """SELECT ID, MIN(PhaseBegin) FROM (SELECT Transactions.ID, PhaseBegin FROM Transactions +# INNER JOIN ranges ON ranges.id = Transactions.Range INNER JOIN Phases ON Phases.Transact = Transactions.ID +# WHERE TThread != 0 AND TBank = :bank and PhaseName = "REQ" and ranges.begin < :begin AND ranges.end > :end)""" +# +# queryMinRESP = """SELECT ID, MIN(PhaseBegin) FROM (SELECT Transactions.ID, PhaseBegin FROM Transactions +# INNER JOIN ranges ON ranges.id = Transactions.Range INNER JOIN Phases ON Phases.Transact = Transactions.ID +# WHERE TThread != 0 AND TBank = :bank AND PhaseName = "RESP" AND ranges.begin < :begin AND ranges.end > :end) """ +# +# missDecisions = 0 +# totalDecisions = 0 +# +# for refresh in cursor: +# id = refresh[0] +# begin = refresh[1] +# end = refresh[2] +# bank = refresh[3] +# # print('Refresh: {0} {1} {2} {3}'.format(id,begin,end,bank)) +# +# cursorMinREQ = connection.cursor() +# cursorMinRESP = connection.cursor() +# +# cursorMinREQ.execute(queryMinREQ, {"bank": bank, "begin": begin, "end": end}) +# cursorMinRESP.execute(queryMinRESP, {"bank": bank, "begin": begin, "end": end}) +# +# earliestReq = cursorMinREQ.fetchone() +# earliestResp = cursorMinRESP.fetchone() +# if earliestReq[0] is not None: +# totalDecisions = totalDecisions + 1 +# if earliestReq[0] != earliestResp[0]: +# missDecisions = missDecisions + 1 +# # print("earliest Req: {0}| earliest Res: {1}".format(earliestReq[0], earliestResp[0])) +# +# if totalDecisions != 0: +# # calculatedMetrics.append(("Total Missdecisions", missDecisions)) +# calculatedMetrics.append(("Relative Missdecisions", 1.0*missDecisions/totalDecisions)) +# else: +# calculatedMetrics.append(("Total Missdecisions", 0)) +# calculatedMetrics.append(("Relative Missdecisions", 0)) @threadMetric def average_response_latency_in_ns(connection, thread): cursor = connection.cursor() - query = """SELECT avg(PhaseBegin-timeOfGeneration)/1000 FROM transactions INNER JOIN Phases - ON phases.transact = transactions.ID WHERE PhaseName='RESP' AND TThread = :Thread """ + query = """SELECT AVG(Resp.PhaseBegin - Req.PhaseBegin) / 1000 FROM Phases Req, Phases Resp INNER JOIN Transactions + ON Req.Transact = Transactions.ID WHERE Req.Transact = Resp.Transact AND Req.PhaseName = 'REQ' + AND Resp.PhaseName = 'RESP' AND Thread = :thread""" cursor.execute(query, {"Thread": thread}) result = cursor.fetchone() @@ -572,7 +572,7 @@ def average_response_latency_in_ns(connection, thread): def addStallTime(times, begin, end): time = begin while time <= end: - if(time in times): + if time in times: times[time] = times[time] + 1 else: times[time] = 1 @@ -580,12 +580,12 @@ def addStallTime(times, begin, end): # @threadMetric -def paralellism(connection, thread): +def parallelism(connection, thread): cursor = connection.cursor() stalltimes = {} - query = """SELECT transactions.ID,MIN(phaseBegin)/:clk,MAX(phaseEnd)/:clk - from phases inner join transactions on phases.transact=transactions.id - where phaseName Not in ('REQ','RESP') and tthread=:Thread group by transactions.ID """ + query = """SELECT Transactions.ID, MIN(PhaseBegin) / :clk, MAX(PhaseEnd) / :clk + FROM Phases INNER JOIN Transactions ON Phases.Transact = Transactions.ID + WHERE PhaseName NOT IN ('REQ','RESP') AND Thread = :thread GROUP BY Transactions.ID """ clk, unit = getClock(connection) cursor.execute(query, {"Thread": thread, "clk": clk}) @@ -600,7 +600,9 @@ def paralellism(connection, thread): @threadMetric def thread_conclusion_in_ns(connection, thread): cursor = connection.cursor() - query = """ SELECT max(PhaseEnd)/1000 FROM Phases INNER JOIN Transactions on Phases.transact=Transactions.id WHERE TThread = :Thread """ + query = """ + SELECT max(PhaseEnd) / 1000 FROM Phases INNER JOIN Transactions + ON Phases.Transact = Transactions.ID WHERE Thread = :thread """ cursor.execute(query, {"Thread": thread}) result = cursor.fetchone() return result[0] @@ -738,98 +740,81 @@ def SREFB_count(connection): @metric def number_of_accesses(connection): - return REQ_count(connection) + return RD_count(connection) + RDA_count(connection) + WR_count(connection) + WRA_count(connection) @metric def accesses_per_activate(connection): - return round(float(REQ_count(connection)) / ACT_count(connection), 1) + return round(float(number_of_accesses(connection)) / ACT_count(connection), 1) @metric def bank_overlap_ratio(connection): # Calculates how many banks are open in parallel clk, unit = getClock(connection) + numberOfRanks = getNumberOfRanks(connection) + numberOfBankGroups = getNumberOfBankGroups(connection) + numberOfBanks = getNumberOfBanks(connection) + per2BankOffset = getPer2BankOffset(connection) + banksPerRank = int(numberOfBanks / numberOfRanks) + banksPerGroup = int(numberOfBanks / numberOfBankGroups) cursor = connection.cursor() - cursor.execute("select TraceEnd from GeneralInfo") + cursor.execute("SELECT TraceEnd FROM GeneralInfo") traceEndTMP = cursor.fetchone() - traceEnd = int(traceEndTMP[0]/clk) + traceEnd = int(traceEndTMP[0] / clk) trace = [] cursor.execute(""" - select p1.PhaseBegin, p1.PhaseName from Phases p1 - where - (p1.PhaseName = "ACT" or p1.PhaseName = "PREPB" or p1.PhaseName = "PRE" or p1.PhaseName = "PRESB" - or p1.PhaseName = "PREAB" or p1.PhaseName = "PREA" or p1.PhaseName = "RDA" or p1.PhaseName = "WRA") - order by PhaseBegin + SELECT PhaseBegin, PhaseName, Rank, BankGroup, Bank + FROM Phases + WHERE (PhaseName = 'ACT' OR PhaseName = 'PREPB' OR PhaseName = 'PREP2B' OR PhaseName = 'PRESB' + OR PhaseName = 'PREAB' OR PhaseName = 'RDA' OR PhaseName = 'WRA') + ORDER BY PhaseBegin """) - prevPhase = "PREAB" - prevTime = 0 + # prevPhase = "PREAB" + # prevTime = 0 + + # clk of command, name, rank, bank group, bank for c in cursor: - trace.append([(int(c[0]/clk)), c[1]]) + trace.append([(int(c[0] / clk)), c[1], c[2], c[3], c[4]]) - # Insert a pseudo precharge all to mark the end of the trace - trace.append([traceEnd, "PREAB"]) + # Insert a pseudo precharge all to mark the end of the trace on all ranks + for i in range(numberOfRanks): + trace.append([traceEnd, "PREAB", i, 0, 0]) - bankCounter = 0 - bankTime = [] - - for i in range(0, getNumberOfBanks(connection)+1): - bankTime.append(0) + bankCounter = [False] * numberOfBanks + # + 1 because we have #banks + 1 active states (0 to all banks active) + bankTime = [0.0] * (numberOfBanks + 1) currentTime = 0 - validBankRange = range(0, getNumberOfBanks(connection) + 1) - # RGR uses ACTB and PREB for refresh - actbCnt = 0 for t in trace: interval = t[0] - currentTime - bankTime[bankCounter] += interval + bankTime[sum(bankCounter)] += interval currentTime = t[0] - if(t[1] == "ACT"): - bankCounter += 1 - if not (bankCounter in validBankRange): - print("Unexpected ACT. bankCounter was {0} valid range is python range {1}".format(bankCounter, validBankRange)) - elif t[1] == "ACTB": - actbCnt += 1 - elif(t[1] == "PREAB" or t[1] == "PREA"): - bankCounter = 0 - elif(t[1] == "PREPB" or t[1] == "PRE"): - if (bankCounter > 0): - bankCounter -= 1 - else: - print("Unexpected PREPB. bankCounter was {0} valid range is python range {1}".format(bankCounter, validBankRange)) - elif(t[1] == "PREB"): - # RGR first PREB closes the row ACT follows, then PREB again. - if actbCnt > 0: - # Ignore the second PREB - actbCnt -= 1 - else: - # Treat the first PREB which closes the row - if bankCounter > 0: - bankCounter -= 1 - else: - print("Unexpected PREB. bankCounter was {0} valid range is python range {1}".format(bankCounter, validBankRange)) - elif(t[1] == "WRA"): - if (bankCounter > 0): - bankCounter -= 1 - else: - print("Unexpected WRA. bankCounter was {0} valid range is python range {1}".format(bankCounter, validBankRange)) - elif(t[1] == "RDA"): - if (bankCounter > 0): - bankCounter -= 1 - else: - print("Unexpected RDA. bankCounter was {0} valid range is python range {1}".format(bankCounter, validBankRange)) + if t[1] == "ACT": + bankCounter[t[4]] = True + elif t[1] in ["PREPB", "RDA", "WRA"]: + bankCounter[t[4]] = False + elif t[1] == "PREP2B": + bankCounter[t[4]] = False + bankCounter[t[4] + per2BankOffset] = False + elif t[1] == "PRESB": + for i in range(t[4], t[4] + banksPerRank, banksPerGroup): + bankCounter[i] = False + elif t[1] == "PREAB": + for i in range(t[2] * banksPerRank, (t[2] + 1) * banksPerRank): + bankCounter[i] = False else: print("ERROR") return 0 - for i in range(0, getNumberOfBanks(connection)+1): - bankTime[i] = round(bankTime[i]/traceEnd * 100, 2) + for i in range(numberOfBanks + 1): + bankTime[i] = round(bankTime[i] / traceEnd * 100, 2) return ",".join(format(x, "6.2f") for x in bankTime) From f5fb97d757e2e759d2edee66eb36947446cc4a0a Mon Sep 17 00:00:00 2001 From: Iron Prando da Silva Date: Wed, 18 May 2022 09:17:18 +0200 Subject: [PATCH 21/29] Updating query text of PhaseDependenciesTracker. --- .../dramTimeDependencies/phasedependenciestracker.cpp | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/phasedependenciestracker.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/phasedependenciestracker.cpp index eb935e2d..196bc116 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/phasedependenciestracker.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/phasedependenciestracker.cpp @@ -156,10 +156,8 @@ const std::vector> PhaseDependenciesTracker::mGetFilteredPhases(const std::shared_ptr deviceConfig, TraceDB& tdb, const std::vector& commands) { std::vector> phases; - QString queryStr = "SELECT Phases.*, Transactions.TBank, Transactions.TBankgroup, Transactions.TRank " + QString queryStr = "SELECT Phases.ID, Phases.PhaseName, Phases.PhaseBegin, Phases.PhaseEnd, Phases.Transact, Phases.Bank, Phases.Bankgroup, Phases.Rank " " FROM Phases " - " INNER JOIN Transactions " - " ON Phases.Transact=Transactions.ID " " WHERE PhaseName IN ("; for (const auto& cmd : commands) { From 91aed11a4e1ed77eefd101fdf3d70adaa18304bd Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Wed, 18 May 2022 11:22:45 +0200 Subject: [PATCH 22/29] Set response status in length converter. --- DRAMSys/simulator/LengthConverter.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/DRAMSys/simulator/LengthConverter.cpp b/DRAMSys/simulator/LengthConverter.cpp index b4d8a571..288bf458 100644 --- a/DRAMSys/simulator/LengthConverter.cpp +++ b/DRAMSys/simulator/LengthConverter.cpp @@ -143,6 +143,7 @@ void LengthConverter::peqCallback(tlm_generic_payload &cbTrans, const tlm_phase tlm_generic_payload* parentTrans = cbTrans.get_extension()->getParentTrans(); tlm_phase bwPhase = BEGIN_RESP; sc_time bwDelay = SC_ZERO_TIME; + parentTrans->set_response_status(tlm::TLM_OK_RESPONSE); tlm_sync_enum returnStatus = tSocket->nb_transport_bw(*parentTrans, bwPhase, bwDelay); } } @@ -150,6 +151,7 @@ void LengthConverter::peqCallback(tlm_generic_payload &cbTrans, const tlm_phase { tlm_phase bwPhase = BEGIN_RESP; sc_time bwDelay = SC_ZERO_TIME; + cbTrans.set_response_status(tlm::TLM_OK_RESPONSE); tlm_sync_enum returnStatus = tSocket->nb_transport_bw(cbTrans, bwPhase, bwDelay); } } From 99ca6691a93d7b9265a455b905551e75ef9d547b Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Wed, 18 May 2022 11:43:54 +0200 Subject: [PATCH 23/29] Remove length converter. --- DRAMSys/simulator/TrafficInitiator.h | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/DRAMSys/simulator/TrafficInitiator.h b/DRAMSys/simulator/TrafficInitiator.h index 88afe1b3..4464e423 100644 --- a/DRAMSys/simulator/TrafficInitiator.h +++ b/DRAMSys/simulator/TrafficInitiator.h @@ -57,11 +57,9 @@ class TrafficInitiator : public sc_core::sc_module public: tlm_utils::simple_initiator_socket iSocket; TrafficInitiator(const sc_core::sc_module_name &name, const Configuration& config, TraceSetup& setup, - unsigned int maxPendingReadRequests, unsigned int maxPendingWriteRequests, - unsigned int defaultDataLength, bool addLengthConverter); + unsigned int maxPendingReadRequests, unsigned int maxPendingWriteRequests, unsigned int defaultDataLength); SC_HAS_PROCESS(TrafficInitiator); virtual void sendNextPayload() = 0; - const bool addLengthConverter = false; protected: static sc_core::sc_time evaluateGeneratorClk(const DRAMSysConfiguration::TrafficInitiator &conf); From 1741ebd59ea3b84c222dc97146cd668317b3a09e Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Wed, 18 May 2022 11:44:30 +0200 Subject: [PATCH 24/29] Remove length converter (2). --- .../src/common/configuration/TraceSetup.cpp | 4 ---- .../library/src/common/configuration/TraceSetup.h | 1 - DRAMSys/simulator/StlPlayer.cpp | 4 ++-- DRAMSys/simulator/StlPlayer.h | 1 - DRAMSys/simulator/TraceSetup.cpp | 12 ++---------- DRAMSys/simulator/TrafficGenerator.cpp | 10 ++++------ DRAMSys/simulator/TrafficGenerator.h | 2 +- DRAMSys/simulator/TrafficInitiator.cpp | 4 +--- DRAMSys/simulator/main.cpp | 14 -------------- README.md | 4 +--- 10 files changed, 11 insertions(+), 45 deletions(-) diff --git a/DRAMSys/library/src/common/configuration/TraceSetup.cpp b/DRAMSys/library/src/common/configuration/TraceSetup.cpp index 454977c2..d8824ad9 100644 --- a/DRAMSys/library/src/common/configuration/TraceSetup.cpp +++ b/DRAMSys/library/src/common/configuration/TraceSetup.cpp @@ -64,7 +64,6 @@ void to_json(json &j, const TraceSetup &c) initiator_j["clkMhz"] = initiator.clkMhz; initiator_j["maxPendingReadRequests"] = initiator.maxPendingReadRequests; initiator_j["maxPendingWriteRequests"] = initiator.maxPendingWriteRequests; - initiator_j["addLengthConverter"] = initiator.addLengthConverter; using T = std::decay_t; if constexpr (std::is_same_v) @@ -292,9 +291,6 @@ void from_json(const json &j, TraceSetup &c) if (initiator_j.contains("maxPendingWriteRequests")) initiator_j.at("maxPendingWriteRequests").get_to(initiator.maxPendingWriteRequests); - - if (initiator_j.contains("addLengthConverter")) - initiator_j.at("addLengthConverter").get_to(initiator.addLengthConverter); }, initiator); diff --git a/DRAMSys/library/src/common/configuration/TraceSetup.h b/DRAMSys/library/src/common/configuration/TraceSetup.h index c3c04ef6..c651b94a 100644 --- a/DRAMSys/library/src/common/configuration/TraceSetup.h +++ b/DRAMSys/library/src/common/configuration/TraceSetup.h @@ -78,7 +78,6 @@ struct TrafficInitiator std::string name; std::optional maxPendingReadRequests; std::optional maxPendingWriteRequests; - std::optional addLengthConverter; }; struct TracePlayer : public TrafficInitiator diff --git a/DRAMSys/simulator/StlPlayer.cpp b/DRAMSys/simulator/StlPlayer.cpp index 6de5dffd..f02c703f 100644 --- a/DRAMSys/simulator/StlPlayer.cpp +++ b/DRAMSys/simulator/StlPlayer.cpp @@ -45,9 +45,9 @@ using namespace tlm; StlPlayer::StlPlayer(const sc_module_name &name, const Configuration& config, const std::string &pathToTrace, const sc_time &playerClk, unsigned int maxPendingReadRequests, unsigned int maxPendingWriteRequests, - bool addLengthConverter, TraceSetup& setup, bool relative) : + TraceSetup& setup, bool relative) : TrafficInitiator(name, config, setup, maxPendingReadRequests, maxPendingWriteRequests, - config.memSpec->defaultBytesPerBurst, addLengthConverter), + config.memSpec->defaultBytesPerBurst), file(pathToTrace), relative(relative), playerClk(playerClk) { currentBuffer = &lineContents[0]; diff --git a/DRAMSys/simulator/StlPlayer.h b/DRAMSys/simulator/StlPlayer.h index b6055ad7..e2e995b8 100644 --- a/DRAMSys/simulator/StlPlayer.h +++ b/DRAMSys/simulator/StlPlayer.h @@ -70,7 +70,6 @@ public: const sc_core::sc_time &playerClk, unsigned int maxPendingReadRequests, unsigned int maxPendingWriteRequests, - bool addLengthConverter, TraceSetup& setup, bool relative); diff --git a/DRAMSys/simulator/TraceSetup.cpp b/DRAMSys/simulator/TraceSetup.cpp index df60b302..c294a1b7 100644 --- a/DRAMSys/simulator/TraceSetup.cpp +++ b/DRAMSys/simulator/TraceSetup.cpp @@ -79,14 +79,6 @@ TraceSetup::TraceSetup(const Configuration& config, return 0; }(); - bool addLengthConverter = [=]() -> bool - { - if (const auto &addLengthConverter = initiator.addLengthConverter) - return *addLengthConverter; - else - return false; - }(); - using T = std::decay_t; if constexpr (std::is_same_v) { @@ -109,10 +101,10 @@ TraceSetup::TraceSetup(const Configuration& config, StlPlayer *player; if (ext == "stl") player = new StlPlayer(moduleName.c_str(), config, stlFile, playerClk, maxPendingReadRequests, - maxPendingWriteRequests, addLengthConverter, *this, false); + maxPendingWriteRequests, *this, false); else if (ext == "rstl") player = new StlPlayer(moduleName.c_str(), config, stlFile, playerClk, maxPendingReadRequests, - maxPendingWriteRequests, addLengthConverter, *this, true); + maxPendingWriteRequests, *this, true); else throw std::runtime_error("Unsupported file extension in " + name); diff --git a/DRAMSys/simulator/TrafficGenerator.cpp b/DRAMSys/simulator/TrafficGenerator.cpp index 864f34df..8b2c8d51 100644 --- a/DRAMSys/simulator/TrafficGenerator.cpp +++ b/DRAMSys/simulator/TrafficGenerator.cpp @@ -47,9 +47,8 @@ using namespace tlm; TrafficGeneratorIf::TrafficGeneratorIf(const sc_core::sc_module_name& name, const Configuration& config, TraceSetup& setup, unsigned int maxPendingReadRequests, unsigned int maxPendingWriteRequests, - unsigned int dataLength, bool addLengthConverter) - : TrafficInitiator(name, config, setup, maxPendingReadRequests, maxPendingWriteRequests, dataLength, - addLengthConverter) + unsigned int dataLength) + : TrafficInitiator(name, config, setup, maxPendingReadRequests, maxPendingWriteRequests, dataLength) { } @@ -99,8 +98,7 @@ TrafficGenerator::TrafficGenerator(const sc_module_name& name, const Configurati const DRAMSysConfiguration::TraceGenerator& conf, TraceSetup& setup) : TrafficGeneratorIf(name, config, setup, conf.maxPendingReadRequests.value_or(defaultMaxPendingReadRequests), conf.maxPendingWriteRequests.value_or(defaultMaxPendingWriteRequests), - conf.dataLength.value_or(config.memSpec->defaultBytesPerBurst), - conf.addLengthConverter.value_or(false)), + conf.dataLength.value_or(config.memSpec->defaultBytesPerBurst)), generatorClk(TrafficInitiator::evaluateGeneratorClk(conf)), conf(conf), maxTransactions(conf.maxTransactions.value_or(std::numeric_limits::max())), simMemSizeInBytes(config.memSpec->getSimMemSizeInBytes()), @@ -381,7 +379,7 @@ uint64_t TrafficGenerator::evaluateMaxAddress(const DRAMSysConfiguration::TraceG TrafficGeneratorHammer::TrafficGeneratorHammer(const sc_core::sc_module_name &name, const Configuration& config, const DRAMSysConfiguration::TraceHammer &conf, TraceSetup& setup) - : TrafficGeneratorIf(name, config, setup, 1, 1, config.memSpec->defaultBytesPerBurst, false), + : TrafficGeneratorIf(name, config, setup, 1, 1, config.memSpec->defaultBytesPerBurst), generatorClk(evaluateGeneratorClk(conf)), rowIncrement(conf.rowIncrement), numRequests(conf.numRequests) { } diff --git a/DRAMSys/simulator/TrafficGenerator.h b/DRAMSys/simulator/TrafficGenerator.h index 4f66672f..b5025d8c 100644 --- a/DRAMSys/simulator/TrafficGenerator.h +++ b/DRAMSys/simulator/TrafficGenerator.h @@ -51,7 +51,7 @@ class TrafficGeneratorIf : public TrafficInitiator public: TrafficGeneratorIf(const sc_core::sc_module_name &name, const Configuration& config, TraceSetup& setup, unsigned int maxPendingReadRequests, unsigned int maxPendingWriteRequests, - unsigned int dataLength, bool addLengthConverter); + unsigned int dataLength); private: void sendNextPayload() override; diff --git a/DRAMSys/simulator/TrafficInitiator.cpp b/DRAMSys/simulator/TrafficInitiator.cpp index 4631cbd2..5155d7b1 100644 --- a/DRAMSys/simulator/TrafficInitiator.cpp +++ b/DRAMSys/simulator/TrafficInitiator.cpp @@ -44,10 +44,8 @@ using namespace sc_core; using namespace tlm; TrafficInitiator::TrafficInitiator(const sc_module_name &name, const Configuration& config, TraceSetup& setup, - unsigned int maxPendingReadRequests, unsigned int maxPendingWriteRequests, - unsigned int defaultDataLength, bool addLengthConverter) : + unsigned int maxPendingReadRequests, unsigned int maxPendingWriteRequests, unsigned int defaultDataLength) : sc_module(name), - addLengthConverter(addLengthConverter), payloadEventQueue(this, &TrafficInitiator::peqCallback), setup(setup), maxPendingReadRequests(maxPendingReadRequests), diff --git a/DRAMSys/simulator/main.cpp b/DRAMSys/simulator/main.cpp index 5d8e5772..189d8349 100644 --- a/DRAMSys/simulator/main.cpp +++ b/DRAMSys/simulator/main.cpp @@ -121,21 +121,7 @@ int sc_main(int argc, char **argv) // Bind STL Players with DRAMSys: for (auto& player : players) - { - if (player->addLengthConverter) - { - std::string converterName("Converter_"); - lengthConverters.emplace_back(std::make_unique(converterName.append(player->name()).c_str(), - dramSys->getConfig().memSpec->maxBytesPerBurst, - dramSys->getConfig().storeMode != Configuration::StoreMode::NoStorage)); - player->iSocket.bind(lengthConverters.back()->tSocket); - lengthConverters.back()->iSocket.bind(dramSys->tSocket); - } - else - { player->iSocket.bind(dramSys->tSocket); - } - } // Store the starting of the simulation in wallclock time: auto start = std::chrono::high_resolution_clock::now(); diff --git a/README.md b/README.md index 481a3a7a..78024b07 100644 --- a/README.md +++ b/README.md @@ -122,8 +122,7 @@ The JSON code below shows an example configuration: "tracesetup": [ { "clkMhz": 300, - "name": "ddr3_example.stl", - "addLengthConverter": true + "name": "ddr3_example.stl" }, { "clkMhz": 2000, @@ -160,7 +159,6 @@ Field Descriptions: Each **trace setup** device configuration can be a **trace player** ("type": "player"), a **traffic generator** ("type": "generator") or a **row hammer generator** ("type": "hammer"). By not specifing the **type** parameter, the device will act as a **trace player**. All device configurations must define a **clkMhz** (operation frequency of the **traffic initiator**) and a **name** (in case of a trace player this specifies the **trace file** to play; in case of a generator this field is only for identification purposes). -The optional parameter **addLengthConverter** adds a transaction length converter between initiator and DRAMSys. This unit divides a large transaction up into several smaller transactions with the maximum length of one DRAM burst access. The **maxPendingReadRequests** and **maxPendingWriteRequests** parameters define the maximum number of outstanding read/write requests. The current implementation delays all memory accesses if one limit is reached. The default value (0) disables the limit. A **traffic generator** can be configured to generate **numRequests** requests in total, of which the **rwRatio** field defines the probability of one request being a read request. The length of a request (in bytes) can be specified with the **dataLength** parameter. The **seed** parameter can be used to produce identical results for all simulations. **minAddress** and **maxAddress** specify the address range, by default the whole address range is used. The parameter **addressDistribution** can either be set to **random** or **sequential**. In case of **sequential** the additional **addressIncrement** field must be specified, defining the address increment after each request. From 0a5daf52ed48e905b3f3d611cd9a91ecee6f2baf Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Wed, 18 May 2022 15:25:17 +0200 Subject: [PATCH 25/29] Bugfix in recorder, fix all metrics. --- DRAMSys/library/src/common/TlmRecorder.cpp | 9 +- .../businessObjects/phases/phase.h | 8 + DRAMSys/traceAnalyzer/scripts/metrics.py | 203 +++++++++--------- 3 files changed, 114 insertions(+), 106 deletions(-) diff --git a/DRAMSys/library/src/common/TlmRecorder.cpp b/DRAMSys/library/src/common/TlmRecorder.cpp index 81b2f1d3..48c4171f 100644 --- a/DRAMSys/library/src/common/TlmRecorder.cpp +++ b/DRAMSys/library/src/common/TlmRecorder.cpp @@ -139,6 +139,7 @@ void TlmRecorder::recordPhase(tlm_generic_payload& trans, const tlm_phase& phase { // BEGIN_RESP is always the last phase of a normal transaction at this point currentTransactionsInSystem.at(&trans).recordedPhases.back().interval.end = currentTime + delay; + removeTransactionFromSystem(trans); } else if (isFixedCommandPhase(phase)) { @@ -169,9 +170,13 @@ void TlmRecorder::recordPhase(tlm_generic_payload& trans, const tlm_phase& phase currentTime + delay + memSpec.getExecutionTime(Command(phase), trans))), std::move(intervalOnDataStrobe), extension.getRank(), extension.getBankGroup(), extension.getBank(), extension.getRow(), extension.getColumn(), extension.getBurstLength()); + + if (isRefreshCommandPhase(phase)) + removeTransactionFromSystem(trans); } else if (isPowerDownEntryPhase(phase)) { + introduceTransactionToSystem(trans); std::string phaseName = getPhaseName(phase).substr(6); // remove "BEGIN_" const ControllerExtension& extension = ControllerExtension::getExtension(trans); currentTransactionsInSystem.at(&trans).recordedPhases.emplace_back(std::move(phaseName), @@ -184,10 +189,8 @@ void TlmRecorder::recordPhase(tlm_generic_payload& trans, const tlm_phase& phase { currentTransactionsInSystem.at(&trans).recordedPhases.back().interval.end = currentTime + delay + memSpec.getCommandLength(Command(phase)); - } - - if (phase == END_RESP || isRefreshCommandPhase(phase) || isPowerDownExitPhase(phase)) removeTransactionFromSystem(trans); + } simulationTimeCoveredByRecording = currentTime + delay; } diff --git a/DRAMSys/traceAnalyzer/businessObjects/phases/phase.h b/DRAMSys/traceAnalyzer/businessObjects/phases/phase.h index e6fab72a..433c8cb5 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/phases/phase.h +++ b/DRAMSys/traceAnalyzer/businessObjects/phases/phase.h @@ -768,6 +768,10 @@ protected: { return Granularity::Rankwise; } + RelevantAttributes getRelevantAttributes() const override + { + return RelevantAttributes::Rank; + } }; class SREFB : public Phase @@ -819,6 +823,10 @@ protected: { return Granularity::Rankwise; } + RelevantAttributes getRelevantAttributes() const override + { + return RelevantAttributes::Rank; + } }; #endif // BANKPHASE_H diff --git a/DRAMSys/traceAnalyzer/scripts/metrics.py b/DRAMSys/traceAnalyzer/scripts/metrics.py index 98e2445f..d712e385 100644 --- a/DRAMSys/traceAnalyzer/scripts/metrics.py +++ b/DRAMSys/traceAnalyzer/scripts/metrics.py @@ -50,7 +50,7 @@ def command_bus_utilisation_in_percent(connection): rowBusUtil = cursor.fetchone()[0] if rowBusUtil is None: rowBusUtil = 0 - + cursor.execute(""" SELECT SUM(CommandLengths.Length) FROM Phases @@ -61,13 +61,13 @@ def command_bus_utilisation_in_percent(connection): columnBusUtil = cursor.fetchone()[0] if columnBusUtil is None: columnBusUtil = 0 - + clk, _ = getClock(connection) traceEnd = getTraceEndTime(connection) rowBusOccupied = rowBusUtil * clk / traceEnd * 100 columnBusOccupied = columnBusUtil * clk / traceEnd * 100 return "row commands: {}, column commands: {}".format(rowBusOccupied, columnBusOccupied) - else: + else: cursor.execute(""" SELECT SUM(CommandLengths.Length) FROM Phases @@ -204,14 +204,14 @@ def memory_total_in_clks(connection): def memory_idle_in_clks(connection): # This complex query identifies idle times when the DRAM is not used. # The code works also if schedulers are used. - + cursor = connection.cursor() - + # Create a table with transactions sorted by BeginRequest: # (RowNum, BeginRequest) query = """DROP TABLE IF EXISTS transactionsInRequestOrder;""" cursor.execute(query) - + query = """ CREATE TEMPORARY TABLE transactionsInRequestOrder AS SELECT @@ -223,12 +223,12 @@ def memory_idle_in_clks(connection): p.PhaseName = 'REQ'; """ cursor.execute(query) - + # Create a table with transactions sorted by BeginResponse: # (RowNum, ID, EndResponse) query = """DROP TABLE IF EXISTS transactionsInResponseOrder;""" cursor.execute(query) - + query = """ CREATE TEMPORARY TABLE transactionsInResponseOrder AS SELECT @@ -240,7 +240,7 @@ def memory_idle_in_clks(connection): q.PhaseName = 'RESP'; """ cursor.execute(query) - + # Sum up the idle times: query = """ SELECT @@ -252,9 +252,9 @@ def memory_idle_in_clks(connection): c.RowNum = (a.RowNum + 1) AND c.BeginRequest > b.EndResponse; """ - cursor.execute(query) + cursor.execute(query) idle = cursor.fetchone() - + cursor.execute("""SELECT MIN(PhaseBegin) FROM Phases WHERE PhaseName = 'REQ'""") idle_start = cursor.fetchone() clk, unit = getClock(connection) @@ -265,7 +265,7 @@ def memory_idle_in_clks(connection): return (idle[0] + idle_start[0]) / clk -@metric +@metric def memory_delayed_in_clks(connection): total = memory_total_in_clks(connection) active = memory_active_in_clks(connection) @@ -297,11 +297,11 @@ def delayed_reasons(connection): DataStrobeBegin <> 0 AND DataStrobeEnd <> 0; """) - + # Create a table with transactions sorted by BeginRequest: # (RowNum, BeginRequest) cursor.execute("""DROP TABLE IF EXISTS transactionsInRequestOrder;""") - + query = """ CREATE TEMPORARY TABLE transactionsInRequestOrder AS SELECT @@ -313,12 +313,12 @@ def delayed_reasons(connection): PhaseName = 'REQ'; """ cursor.execute(query) - + # Create a table with transactions sorted by BeginResponse: # (RowNum, ID, EndResponse) query = """DROP TABLE IF EXISTS transactionsInResponseOrder;""" cursor.execute(query) - + query = """ CREATE TEMPORARY TABLE transactionsInResponseOrder AS SELECT @@ -331,7 +331,7 @@ def delayed_reasons(connection): PhaseName = 'RESP'; """ cursor.execute(query) - + # Create a table with transaction IDs that start an idle time: # (ID) query = """DROP TABLE IF EXISTS idleGaps;""" @@ -354,7 +354,7 @@ def delayed_reasons(connection): # (gapBeginID, gapEndID) query = """DROP TABLE IF EXISTS delayedDataBusGaps;""" cursor.execute(query) - + query = """ CREATE TEMPORARY TABLE delayedDataBusGaps AS SELECT @@ -445,13 +445,13 @@ def delayed_reasons(connection): """ cursor.execute(query) total = cursor.fetchone()[0] - + other = total - RW - WR - RRM - WWM - RW /= total / 100.0 - WR /= total / 100.0 - RRM /= total / 100.0 - WWM /= total / 100.0 + RW /= total / 100.0 + WR /= total / 100.0 + RRM /= total / 100.0 + WWM /= total / 100.0 other /= total / 100.0 result = "RW: {}, WR: {}, RRM: {}, WWM: {}, Other: {}".format(RW, WR, RRM, WWM, other) @@ -462,21 +462,21 @@ def delayed_reasons(connection): def memory_idle_in_percent(connection): total = memory_total_in_clks(connection) idle = memory_idle_in_clks(connection) - return (idle/total)*100 + return (idle / total) * 100 @metric def memory_active_in_percent(connection): total = memory_total_in_clks(connection) active = memory_active_in_clks(connection) - return (active/total)*100 + return (active / total) * 100 @metric def memory_delayed_in_percent(connection): total = memory_total_in_clks(connection) delayed = memory_delayed_in_clks(connection) - return (delayed/total)*100 + return (delayed / total) * 100 @metric @@ -490,7 +490,7 @@ def memory_utilisation_percent_without_idle(connection): total = memory_total_in_clks(connection) active = memory_active_in_clks(connection) idle = memory_idle_in_clks(connection) - return (active/(total-idle))*100 + return (active / (total - idle)) * 100 @metric @@ -499,7 +499,7 @@ def memory_utilisation_in_Gibps_without_idle(connection): # the memory_utilisation_percent_new function result. maxDataRate = maximum_data_rate(connection) memoryPercent = memory_utilisation_percent_without_idle(connection) - return (memoryPercent/100)*(maxDataRate/1024) + return (memoryPercent / 100) * (maxDataRate / 1024) @metric @@ -557,16 +557,16 @@ def memory_utilisation_percent_including_idle(connection): # calculatedMetrics.append(("Relative Missdecisions", 0)) -@threadMetric -def average_response_latency_in_ns(connection, thread): - cursor = connection.cursor() - query = """SELECT AVG(Resp.PhaseBegin - Req.PhaseBegin) / 1000 FROM Phases Req, Phases Resp INNER JOIN Transactions - ON Req.Transact = Transactions.ID WHERE Req.Transact = Resp.Transact AND Req.PhaseName = 'REQ' - AND Resp.PhaseName = 'RESP' AND Thread = :thread""" - - cursor.execute(query, {"Thread": thread}) - result = cursor.fetchone() - return round(result[0], 1) +# @threadMetric # FIXME: Fix thread metrics +# def average_response_latency_in_ns(connection, thread): +# cursor = connection.cursor() +# query = """SELECT AVG(Resp.PhaseBegin - Req.PhaseBegin) / 1000 FROM Phases Req, Phases Resp INNER JOIN Transactions +# ON Req.Transact = Transactions.ID WHERE Req.Transact = Resp.Transact AND Req.PhaseName = 'REQ' +# AND Resp.PhaseName = 'RESP' AND Thread = :Thread""" +# +# cursor.execute(query, {"Thread": thread}) +# result = cursor.fetchone() +# return round(result[0], 1) def addStallTime(times, begin, end): @@ -579,33 +579,33 @@ def addStallTime(times, begin, end): time = time + 1 -# @threadMetric -def parallelism(connection, thread): - cursor = connection.cursor() - stalltimes = {} - query = """SELECT Transactions.ID, MIN(PhaseBegin) / :clk, MAX(PhaseEnd) / :clk - FROM Phases INNER JOIN Transactions ON Phases.Transact = Transactions.ID - WHERE PhaseName NOT IN ('REQ','RESP') AND Thread = :thread GROUP BY Transactions.ID """ - - clk, unit = getClock(connection) - cursor.execute(query, {"Thread": thread, "clk": clk}) - for currentRow in cursor: - addStallTime(stalltimes, currentRow[1], currentRow[2]) - para = 0 - for time in stalltimes: - para = para + stalltimes[time] - return round(para/len(stalltimes), 2) +# @threadMetric # FIXME: Fix thread metrics +# def parallelism(connection, thread): +# cursor = connection.cursor() +# stalltimes = {} +# query = """SELECT Transactions.ID, MIN(PhaseBegin) / :clk, MAX(PhaseEnd) / :clk +# FROM Phases INNER JOIN Transactions ON Phases.Transact = Transactions.ID +# WHERE PhaseName NOT IN ('REQ','RESP') AND Thread = :Thread GROUP BY Transactions.ID """ +# +# clk, unit = getClock(connection) +# cursor.execute(query, {"Thread": thread, "clk": clk}) +# for currentRow in cursor: +# addStallTime(stalltimes, currentRow[1], currentRow[2]) +# para = 0 +# for time in stalltimes: +# para = para + stalltimes[time] +# return round(para / len(stalltimes), 2) -@threadMetric -def thread_conclusion_in_ns(connection, thread): - cursor = connection.cursor() - query = """ - SELECT max(PhaseEnd) / 1000 FROM Phases INNER JOIN Transactions - ON Phases.Transact = Transactions.ID WHERE Thread = :thread """ - cursor.execute(query, {"Thread": thread}) - result = cursor.fetchone() - return result[0] +# @threadMetric # FIXME: Fix thread metrics +# def thread_conclusion_in_ns(connection, thread): +# cursor = connection.cursor() +# query = """ +# SELECT max(PhaseEnd) / 1000 FROM Phases INNER JOIN Transactions +# ON Phases.Transact = Transactions.ID WHERE Thread = :Thread """ +# cursor.execute(query, {"Thread": thread}) +# result = cursor.fetchone() +# return result[0] @metric @@ -618,8 +618,8 @@ def RESP_count(connection): return get_phase_occurrences(connection, 'RESP') -#@metric -#def ACTB_count(connection): +# @metric +# def ACTB_count(connection): # return get_phase_occurrences(connection, 'ACTB') @@ -628,8 +628,8 @@ def ACT_count(connection): return get_phase_occurrences(connection, 'ACT') -#@metric -#def PREB_count(connection): +# @metric +# def PREB_count(connection): # return get_phase_occurrences(connection, 'PREB') @@ -881,9 +881,9 @@ def time_in_SREFB_percent(connection): @metric def time_in_power_down_states_in_ns(connection): mcconfig = MCConfig(connection) - #bankwiseLogic = mcconfig.getValue("BankwiseLogic") + # bankwiseLogic = mcconfig.getValue("BankwiseLogic") bankwiseLogic = "0" - + if bankwiseLogic == "0": totalTimeInPDNA = time_in_PDNA_in_ns(connection) totalTimeInPDNP = time_in_PDNP_in_ns(connection) @@ -901,9 +901,9 @@ def time_in_power_down_states_in_ns(connection): @metric def time_in_power_down_states_percent(connection): mcconfig = MCConfig(connection) - #bankwiseLogic = mcconfig.getValue("BankwiseLogic") + # bankwiseLogic = mcconfig.getValue("BankwiseLogic") bankwiseLogic = "0" - + if bankwiseLogic == "0": totalTimeAllBanks = trace_length_in_ns(connection) else: @@ -961,24 +961,26 @@ def getMetrics(pathToTrace): connection = sqlite3.connect(pathToTrace) mcconfig = MCConfig(connection) - #bankwiseLogic = mcconfig.getValue("BankwiseLogic") + # bankwiseLogic = mcconfig.getValue("BankwiseLogic") bankwiseLogic = "0" if bankwiseLogic == "0": - pdnMetrics = [time_in_PDNA_in_ns, time_in_PDNA_percent, time_in_PDNP_in_ns, time_in_PDNP_percent, time_in_SREF_in_ns, time_in_SREF_percent] + pdnMetrics = [time_in_PDNA_in_ns, time_in_PDNA_percent, time_in_PDNP_in_ns, time_in_PDNP_percent, + time_in_SREF_in_ns, time_in_SREF_percent] else: - pdnMetrics = [time_in_PDNAB_in_ns, time_in_PDNAB_percent, time_in_PDNPB_in_ns, time_in_PDNPB_percent, time_in_SREFB_in_ns, time_in_SREFB_percent] + pdnMetrics = [time_in_PDNAB_in_ns, time_in_PDNAB_percent, time_in_PDNPB_in_ns, time_in_PDNPB_percent, + time_in_SREFB_in_ns, time_in_SREFB_percent] for metric in pdnMetrics: if metric not in metrics: metrics.append(metric) - if (len(getThreads(connection)) >= 1): + if len(getThreads(connection)) >= 1: for metric in metrics: res = metric.__name__.replace("_", " ") selectedMetrics.append(res) - if (len(getThreads(connection)) > 1): + if len(getThreads(connection)) > 1: for thread in getThreads(connection): for threadMetric in threadMetrics: res = "Thread {0}: {1}".format(thread, threadMetric.__name__.replace("_", " ")) @@ -990,23 +992,18 @@ def getMetrics(pathToTrace): return selectedMetrics -def calculateMetrics(pathToTrace, selectedMetrics=[]): - +def calculateMetrics(pathToTrace, selectedMetrics=None): + if selectedMetrics is None: + selectedMetrics = [] calculatedMetrics = [] connection = sqlite3.connect(pathToTrace) mcconfig = MCConfig(connection) - #bankwiseLogic = mcconfig.getValue("BankwiseLogic") - bankwiseLogic = "0" + # bankwiseLogic = mcconfig.getValue("BankwiseLogic") - if bankwiseLogic == "0": - pdnMetrics = [time_in_PDNA_in_ns, time_in_PDNA_percent, - time_in_PDNP_in_ns, time_in_PDNP_percent, - time_in_SREF_in_ns, time_in_SREF_percent] - else: - pdnMetrics = [time_in_PDNAB_in_ns, time_in_PDNAB_percent, - time_in_PDNPB_in_ns, time_in_PDNPB_percent, - time_in_SREFB_in_ns, time_in_SREFB_percent] + pdnMetrics = [time_in_PDNA_in_ns, time_in_PDNA_percent, + time_in_PDNP_in_ns, time_in_PDNP_percent, + time_in_SREF_in_ns, time_in_SREF_percent] for m in pdnMetrics: if m not in metrics: @@ -1018,18 +1015,18 @@ def calculateMetrics(pathToTrace, selectedMetrics=[]): print("Number of threads is {0}".format(len(getThreads(connection)))) if not selectedMetrics: - selectedMetrics = [0] * (len(metrics) + len(getThreads(connection))*len(threadMetrics) + 1) + selectedMetrics = [0] * (len(metrics) + len(getThreads(connection)) * len(threadMetrics) + 1) for i in range(len(selectedMetrics)): selectedMetrics[i] = True - if (len(getThreads(connection)) >= 1): + if len(getThreads(connection)) >= 1: for metric in metrics: if selectedMetrics[metrics.index(metric)]: mres = metric(connection) mname = metric.__name__.replace("_", " ") res = (mname, mres) - if (metric.__name__ == "bank_overlap_ratio"): + if metric.__name__ == "bank_overlap_ratio": values = mres.split(",") nbanks = 0 for v in values: @@ -1037,7 +1034,7 @@ def calculateMetrics(pathToTrace, selectedMetrics=[]): nbanks = nbanks + 1 r = (name, float(v)) calculatedMetrics.append(r) - elif (metric.__name__ == "delayed_reasons" or metric.__name__ == "command_bus_utilisation_in_percent"): + elif metric.__name__ == "delayed_reasons" or metric.__name__ == "command_bus_utilisation_in_percent": values = mres.split(",") for v in values: name = mname + " (" + v.partition(":")[0].strip() + ")" @@ -1049,21 +1046,21 @@ def calculateMetrics(pathToTrace, selectedMetrics=[]): print("{0}: {1}".format(res[0], res[1])) - if (len(getThreads(connection)) > 1): + if len(getThreads(connection)) > 1: for thread in getThreads(connection): for metric in threadMetrics: - if(selectedMetrics[len(metrics) + len(threadMetrics)*(thread-1) + threadMetrics.index(metric)]): + if selectedMetrics[len(metrics) + len(threadMetrics) * (thread - 1) + threadMetrics.index(metric)]: mres = metric(connection, thread) mname = "Thread {0} - {1}".format(thread, metric.__name__.replace("_", " ")) res = (mname, mres) calculatedMetrics.append(res) print("{0}: {1}".format(res[0], res[1])) - if (selectedMetrics[len(selectedMetrics) - 1]): - calculatedMetrics.extend(passRatio(connection)) + # if selectedMetrics[len(selectedMetrics) - 1]: # FIXME: Add pass ratio + # calculatedMetrics.extend(passRatio(connection)) # refreshMissDecision(connection, calculatedMetrics) - if (len(getThreads(connection)) == 0): + if len(getThreads(connection)) == 0: res = ("No accesses were performed for this channel, number of metrics generated", 0.0) calculatedMetrics.append(res) @@ -1071,8 +1068,8 @@ def calculateMetrics(pathToTrace, selectedMetrics=[]): connection.close() return calculatedMetrics -def calculateMetricsFromFuncs(pathToTrace, selectedMetrics): +def calculateMetricsFromFuncs(pathToTrace, selectedMetrics): calculatedMetrics = [] connection = sqlite3.connect(pathToTrace) @@ -1084,7 +1081,7 @@ def calculateMetricsFromFuncs(pathToTrace, selectedMetrics): print("Number of threads is {0}".format(len(getThreads(connection)))) if not selectedMetrics: - selectedMetrics = [0] * (len(metrics) + len(getThreads(connection))*len(threadMetrics) + 1) + selectedMetrics = [0] * (len(metrics) + len(getThreads(connection)) * len(threadMetrics) + 1) for i in range(len(selectedMetrics)): selectedMetrics[i] = True @@ -1093,7 +1090,7 @@ def calculateMetricsFromFuncs(pathToTrace, selectedMetrics): mname = metric.__name__.replace("_", " ") res = (mname, mres) - if (metric.__name__ == "bank_overlap_ratio"): + if metric.__name__ == "bank_overlap_ratio": values = mres.split(",") nbanks = 0 for v in values: @@ -1110,6 +1107,7 @@ def calculateMetricsFromFuncs(pathToTrace, selectedMetrics): connection.close() return calculatedMetrics + if __name__ == "__main__": """ Only non-threaded metrics are implemented for selection through command line @@ -1120,7 +1118,7 @@ if __name__ == "__main__": dic_metric_functions = {} for m in metrics: - parser.add_argument("--"+m.__name__, action='store_true') + parser.add_argument("--" + m.__name__, action='store_true') dic_metric_functions[m.__name__] = m arg_namespace = parser.parse_args(sys.argv[1:]) @@ -1132,8 +1130,7 @@ if __name__ == "__main__": if v: selected_metrics.append(dic_metric_functions[k]) - - if selected_metrics == []: + if not selected_metrics: calculateMetrics(arg_namespace.path) else: calculateMetricsFromFuncs(arg_namespace.path, selected_metrics) From e739dd24132c59f6c2d10d63a54a772e9a537805 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Thu, 19 May 2022 11:16:47 +0200 Subject: [PATCH 26/29] Add module name to DB name to allow running multiple instances of DRAMSys. --- DRAMSys/library/src/common/DebugManager.h | 6 ++++-- DRAMSys/library/src/simulation/DRAMSys.cpp | 2 +- DRAMSys/library/src/simulation/DRAMSys.h | 2 +- DRAMSys/library/src/simulation/DRAMSysRecordable.cpp | 2 +- DRAMSys/library/src/simulation/DRAMSysRecordable.h | 1 - DRAMSys/simulator/main.cpp | 1 - 6 files changed, 7 insertions(+), 7 deletions(-) diff --git a/DRAMSys/library/src/common/DebugManager.h b/DRAMSys/library/src/common/DebugManager.h index c52c2536..c8d0b7da 100644 --- a/DRAMSys/library/src/common/DebugManager.h +++ b/DRAMSys/library/src/common/DebugManager.h @@ -65,8 +65,10 @@ public: private: DebugManager(); - DebugManager(const DebugManager &); - DebugManager & operator = (const DebugManager &); + +public: + DebugManager(const DebugManager&) = delete; + DebugManager& operator=(const DebugManager&) = delete; public: void setup(bool _debugEnabled, bool _writeToConsole, bool _writeToFile); diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index 9582b765..4037fda4 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -136,7 +136,7 @@ void DRAMSys::logo() #undef BOLDTXT } -void DRAMSys::setupDebugManager(NDEBUG_UNUSED(const std::string &traceName)) +void DRAMSys::setupDebugManager(NDEBUG_UNUSED(const std::string &traceName)) const { #ifndef NDEBUG auto& dbg = DebugManager::getInstance(); diff --git a/DRAMSys/library/src/simulation/DRAMSys.h b/DRAMSys/library/src/simulation/DRAMSys.h index 33cdba50..313d7273 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.h +++ b/DRAMSys/library/src/simulation/DRAMSys.h @@ -105,7 +105,7 @@ private: void instantiateModules(const DRAMSysConfiguration::AddressMapping &addressMapping); - void setupDebugManager(const std::string &traceName); + void setupDebugManager(const std::string &traceName) const; }; #endif // DRAMSYS_H diff --git a/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp b/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp index 324f6e2c..5bf417c7 100644 --- a/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp +++ b/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp @@ -99,7 +99,7 @@ void DRAMSysRecordable::setupTlmRecorders(const std::string& traceName, const DR tlmRecorders.reserve(config.memSpec->numberOfChannels); for (std::size_t i = 0; i < config.memSpec->numberOfChannels; i++) { - std::string dbName = traceName + std::string("_ch") + std::to_string(i) + ".tdb"; + std::string dbName = std::string(name()) + "_" + traceName + "_ch" + std::to_string(i) + ".tdb"; std::string recorderName = "tlmRecorder" + std::to_string(i); tlmRecorders.emplace_back(recorderName, config, dbName); diff --git a/DRAMSys/library/src/simulation/DRAMSysRecordable.h b/DRAMSys/library/src/simulation/DRAMSysRecordable.h index 9340a8d3..9ce40629 100644 --- a/DRAMSys/library/src/simulation/DRAMSysRecordable.h +++ b/DRAMSys/library/src/simulation/DRAMSysRecordable.h @@ -57,7 +57,6 @@ private: void setupTlmRecorders(const std::string &traceName, const DRAMSysConfiguration::Configuration &configLib); void instantiateModules(const std::string &traceName, const DRAMSysConfiguration::Configuration &configLib); - }; #endif // DRAMSYSRECORDABLE_H diff --git a/DRAMSys/simulator/main.cpp b/DRAMSys/simulator/main.cpp index 189d8349..8c732297 100644 --- a/DRAMSys/simulator/main.cpp +++ b/DRAMSys/simulator/main.cpp @@ -51,7 +51,6 @@ #include "simulation/DRAMSys.h" #include "TraceSetup.h" #include "TrafficInitiator.h" -#include "LengthConverter.h" #ifdef RECORDING #include "simulation/DRAMSysRecordable.h" From edf884d099c4cb1fbcc8b4e2fda4660c8d0883e0 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Fri, 5 Aug 2022 14:07:03 +0200 Subject: [PATCH 27/29] Fix typo. --- DRAMSys/library/src/common/TlmRecorder.cpp | 2 +- DRAMSys/library/src/configuration/memspec/MemSpec.cpp | 2 +- DRAMSys/library/src/configuration/memspec/MemSpec.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/DRAMSys/library/src/common/TlmRecorder.cpp b/DRAMSys/library/src/common/TlmRecorder.cpp index 84b50c9d..70681f8a 100644 --- a/DRAMSys/library/src/common/TlmRecorder.cpp +++ b/DRAMSys/library/src/common/TlmRecorder.cpp @@ -433,7 +433,7 @@ void TlmRecorder::insertCommandLengths() auto commandName = command.toString(); sqlite3_bind_text(insertCommandLengthsStatement, 1, commandName.c_str(), commandName.length(), nullptr); - sqlite3_bind_double(insertCommandLengthsStatement, 2, memSpec.getCommandLengthInCylcles(command)); + sqlite3_bind_double(insertCommandLengthsStatement, 2, memSpec.getCommandLengthInCycles(command)); executeSqlStatement(insertCommandLengthsStatement); }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp index 3b0e5ac9..f675a806 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp @@ -83,7 +83,7 @@ sc_time MemSpec::getCommandLength(Command command) const return tCK * commandLengthInCycles[command]; } -double MemSpec::getCommandLengthInCylcles(Command command) const +double MemSpec::getCommandLengthInCycles(Command command) const { return commandLengthInCycles[command]; } diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.h b/DRAMSys/library/src/configuration/memspec/MemSpec.h index 8a72cc78..0a1d0894 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.h @@ -97,7 +97,7 @@ public: virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const = 0; sc_core::sc_time getCommandLength(Command) const; - double getCommandLengthInCylcles(Command) const; + double getCommandLengthInCycles(Command) const; uint64_t getSimMemSizeInBytes() const; protected: From 263d28d1be451668d37eb2dde06e46f698f88637 Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Thu, 25 Aug 2022 16:49:32 +0200 Subject: [PATCH 28/29] Fix HBM2 assertion in TimingChecker. --- DRAMSys/library/src/controller/checker/CheckerHBM2.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp b/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp index 671dcb07..76bd4650 100644 --- a/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp @@ -135,7 +135,7 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, const tlm_generic else if (command == Command::WR || command == Command::WRA) { unsigned burstLength = ControllerExtension::getBurstLength(payload); - assert(!(memSpec->ranksPerChannel == 1) || (burstLength == 2)); // Legacy mode + assert(!(memSpec->ranksPerChannel == 1) || (burstLength == 2 || burstLength == 4)); // Legacy mode assert(!(memSpec->ranksPerChannel == 2) || (burstLength == 4)); // Pseudo-channel mode lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; From 8a66b5628193eaabe84404dad8588caa7df37912 Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Thu, 25 Aug 2022 16:51:09 +0200 Subject: [PATCH 29/29] Update test cases --- DRAMSys/tests/DDR3/ci.yml | 1 + DRAMSys/tests/DDR4/ci.yml | 1 + DRAMSys/tests/HBM2/ci.yml | 2 ++ DRAMSys/tests/LPDDR4/ci.yml | 1 + 4 files changed, 5 insertions(+) diff --git a/DRAMSys/tests/DDR3/ci.yml b/DRAMSys/tests/DDR3/ci.yml index 92b444bc..3a2c1eb0 100644 --- a/DRAMSys/tests/DDR3/ci.yml +++ b/DRAMSys/tests/DDR3/ci.yml @@ -6,6 +6,7 @@ example_DDR3: - export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}') - cd build/simulator - ./DRAMSys ../../DRAMSys/tests/DDR3/simulations/ddr3-example.json ../../DRAMSys/tests/DDR3/ + - mv DRAMSys_ddr3-dual-rank_ddr3_ch0.tdb ddr3-dual-rank_ddr3_ch0.tdb - ls -lah - ls -lah ../../DRAMSys/tests/DDR3/expected/ - sqldiff ../../DRAMSys/tests/DDR3/expected/ddr3-dual-rank_ddr3_ch0.tdb ddr3-dual-rank_ddr3_ch0.tdb diff --git a/DRAMSys/tests/DDR4/ci.yml b/DRAMSys/tests/DDR4/ci.yml index 23ffd8ea..86bddbbb 100644 --- a/DRAMSys/tests/DDR4/ci.yml +++ b/DRAMSys/tests/DDR4/ci.yml @@ -6,6 +6,7 @@ example_DDR4: - export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}') - cd build/simulator - ./DRAMSys ../../DRAMSys/tests/DDR4/simulations/ddr4-example.json ../../DRAMSys/tests/DDR4/ + - mv DRAMSys_ddr4-bankgrp_ddr4_ch0.tdb ddr4-bankgrp_ddr4_ch0.tdb - ls -lah - ls -lah ../../DRAMSys/tests/DDR4/expected/ - sqldiff ../../DRAMSys/tests/DDR4/expected/ddr4-bankgrp_ddr4_ch0.tdb ddr4-bankgrp_ddr4_ch0.tdb diff --git a/DRAMSys/tests/HBM2/ci.yml b/DRAMSys/tests/HBM2/ci.yml index af9761c1..91636d65 100644 --- a/DRAMSys/tests/HBM2/ci.yml +++ b/DRAMSys/tests/HBM2/ci.yml @@ -5,6 +5,8 @@ example_HBM2: - export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}') - cd build/simulator - ./DRAMSys ../../DRAMSys/tests/HBM2/simulations/hbm2-example.json ../../DRAMSys/tests/HBM2/ + - mv DRAMSys_hbm2-example_hbm2_ch0.tdb hbm2-example_hbm2_ch0.tdb + - mv DRAMSys_hbm2-example_hbm2_ch1.tdb hbm2-example_hbm2_ch1.tdb - ls -lah - ls -lah ../../DRAMSys/tests/HBM2/expected/ - sqldiff ../../DRAMSys/tests/HBM2/expected/hbm2-example_hbm2_ch0.tdb hbm2-example_hbm2_ch0.tdb diff --git a/DRAMSys/tests/LPDDR4/ci.yml b/DRAMSys/tests/LPDDR4/ci.yml index 6fc7b6ee..8f3ab1fd 100644 --- a/DRAMSys/tests/LPDDR4/ci.yml +++ b/DRAMSys/tests/LPDDR4/ci.yml @@ -6,6 +6,7 @@ example_LPDDR4: - export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}') - cd build/simulator - ./DRAMSys ../../DRAMSys/tests/LPDDR4/simulations/lpddr4-example.json ../../DRAMSys/tests/LPDDR4/ + - mv DRAMSys_lpddr4-example_lpddr4_ch0.tdb lpddr4-example_lpddr4_ch0.tdb - ls -lah - ls -lah ../../DRAMSys/tests/LPDDR4/expected/ - sqldiff ../../DRAMSys/tests/LPDDR4/expected/lpddr4-example_lpddr4_ch0.tdb lpddr4-example_lpddr4_ch0.tdb