From bda10dca2f7ef0c319b2fcb711b796d2c886a366 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Mon, 23 Sep 2019 14:31:47 +0200 Subject: [PATCH] Individual memspec files for different DRAMs. --- DRAMSys/library/library.pro | 13 ++- .../library/src/common/timingCalculations.cpp | 2 +- .../library/src/configuration/Configuration.h | 2 +- .../src/configuration/ConfigurationLoader.cpp | 9 +- .../configuration/{ => memspec}/MemSpec.cpp | 37 +------ .../src/configuration/{ => memspec}/MemSpec.h | 97 +------------------ .../src/configuration/memspec/MemSpecDDR3.h | 57 +++++++++++ .../src/configuration/memspec/MemSpecDDR4.h | 63 ++++++++++++ .../configuration/memspec/MemSpecLPDDR4.cpp | 67 +++++++++++++ .../src/configuration/memspec/MemSpecLPDDR4.h | 65 +++++++++++++ .../src/configuration/memspec/MemSpecWideIO.h | 66 +++++++++++++ .../src/controller/checker/CheckerDDR3.h | 2 +- .../src/controller/checker/CheckerWideIO.h | 2 +- .../core/scheduling/ScheduledCommand.cpp | 1 - .../src/controller/refresh/RefreshManager.h | 2 +- .../refresh/RefreshManagerBankwise.h | 2 +- DRAMSys/library/src/simulation/Dram.h | 2 +- DRAMSys/library/src/simulation/DramDDR3.cpp | 2 +- DRAMSys/library/src/simulation/DramDDR4.cpp | 2 +- DRAMSys/library/src/simulation/DramWideIO.cpp | 4 +- 20 files changed, 352 insertions(+), 145 deletions(-) rename DRAMSys/library/src/configuration/{ => memspec}/MemSpec.cpp (77%) rename DRAMSys/library/src/configuration/{ => memspec}/MemSpec.h (69%) create mode 100644 DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h create mode 100644 DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h create mode 100644 DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp create mode 100644 DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h create mode 100644 DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h diff --git a/DRAMSys/library/library.pro b/DRAMSys/library/library.pro index b7eae32c..3bc74e25 100644 --- a/DRAMSys/library/library.pro +++ b/DRAMSys/library/library.pro @@ -122,7 +122,7 @@ SOURCES += \ src/simulation/DramDDR4.cpp \ src/simulation/DramRecordable.cpp \ src/simulation/DramWideIO.cpp \ - src/configuration/MemSpec.cpp \ + src/configuration/memspec/MemSpec.cpp \ src/controller/BankMachine.cpp \ src/controller/Controller.cpp \ src/controller/scheduler/SchedulerFifo.cpp \ @@ -134,7 +134,8 @@ SOURCES += \ src/controller/refresh/RefreshManager.cpp \ src/controller/refresh/RefreshManagerDummy.cpp \ src/controller/refresh/RefreshManagerBankwise.cpp \ - src/controller/checker/CheckerWideIO.cpp + src/controller/checker/CheckerWideIO.cpp \ + src/configuration/memspec/MemSpecLPDDR4.cpp HEADERS += \ src/common/third_party/tinyxml2/tinyxml2.h \ @@ -153,7 +154,7 @@ HEADERS += \ src/simulation/Arbiter.h \ src/common/libDRAMPower.h \ src/simulation/ReorderBuffer.h \ - src/configuration/MemSpec.h \ + src/configuration/memspec/MemSpec.h \ src/simulation/StlPlayer.h \ src/simulation/TracePlayerListener.h \ src/simulation/TraceGenerator.h \ @@ -202,7 +203,11 @@ HEADERS += \ src/controller/refresh/RefreshManager.h \ src/controller/refresh/RefreshManagerDummy.h \ src/controller/refresh/RefreshManagerBankwise.h \ - src/controller/checker/CheckerWideIO.h + src/controller/checker/CheckerWideIO.h \ + src/configuration/memspec/MemSpecDDR3.h \ + src/configuration/memspec/MemSpecWideIO.h \ + src/configuration/memspec/MemSpecDDR4.h \ + src/configuration/memspec/MemSpecLPDDR4.h #src/common/third_party/json/include/nlohmann/json.hpp \ thermalsim = $$(THERMALSIM) diff --git a/DRAMSys/library/src/common/timingCalculations.cpp b/DRAMSys/library/src/common/timingCalculations.cpp index ddf06098..be69fb44 100644 --- a/DRAMSys/library/src/common/timingCalculations.cpp +++ b/DRAMSys/library/src/common/timingCalculations.cpp @@ -35,7 +35,7 @@ */ #include "timingCalculations.h" -#include "../configuration/MemSpec.h" +#include "../configuration/memspec/MemSpec.h" #include "DebugManager.h" #include "../configuration/Configuration.h" #include "utils.h" diff --git a/DRAMSys/library/src/configuration/Configuration.h b/DRAMSys/library/src/configuration/Configuration.h index 9802b58e..e8fb6bc6 100644 --- a/DRAMSys/library/src/configuration/Configuration.h +++ b/DRAMSys/library/src/configuration/Configuration.h @@ -42,7 +42,7 @@ #include #include #include -#include "MemSpec.h" +#include "memspec/MemSpec.h" #include "TemperatureSimConfig.h" #include "../common/utils.h" diff --git a/DRAMSys/library/src/configuration/ConfigurationLoader.cpp b/DRAMSys/library/src/configuration/ConfigurationLoader.cpp index 71ae8b25..d003def8 100644 --- a/DRAMSys/library/src/configuration/ConfigurationLoader.cpp +++ b/DRAMSys/library/src/configuration/ConfigurationLoader.cpp @@ -36,7 +36,11 @@ */ #include "ConfigurationLoader.h" -#include "MemSpec.h" +#include "memspec/MemSpec.h" +#include "memspec/MemSpecDDR3.h" +#include "memspec/MemSpecDDR4.h" +#include "memspec/MemSpecWideIO.h" +#include "memspec/MemSpecLPDDR4.h" #include "../common/timingCalculations.h" using namespace tinyxml2; @@ -189,7 +193,6 @@ void ConfigurationLoader::loadCommons(Configuration &config, XMLElement *xmlSpec memSpec->clkMHz = queryDoubleParameter(timings, "clkMhz"); memSpec->clk = FrequencyToClk(memSpec->clkMHz); sc_time clk = memSpec->clk; - memSpec->tAL = clk * queryUIntParameter(timings, "AL"); memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR"); //memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); @@ -236,6 +239,7 @@ void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *xmlSpec) memSpec->tRP = clk * queryUIntParameter(timings, "RP"); memSpec->tRRD = clk * queryUIntParameter(timings, "RRD"); memSpec->tWTR = clk * queryUIntParameter(timings, "WTR"); + memSpec->tAL = clk * queryUIntParameter(timings, "AL"); memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL"); memSpec->tXSDLL = clk * queryUIntParameter(timings, "XSDLL"); @@ -279,6 +283,7 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec) memSpec->tRRD_L = clk * queryUIntParameter(timings, "RRD_L"); memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR_S"); memSpec->tWTR_L = clk * queryUIntParameter(timings, "WTR_L"); + memSpec->tAL = clk * queryUIntParameter(timings, "AL"); memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL"); memSpec->tXSDLL = clk * queryUIntParameter(timings, "XSDLL"); diff --git a/DRAMSys/library/src/configuration/MemSpec.cpp b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp similarity index 77% rename from DRAMSys/library/src/configuration/MemSpec.cpp rename to DRAMSys/library/src/configuration/memspec/MemSpec.cpp index 891252d2..83b32a7f 100644 --- a/DRAMSys/library/src/configuration/MemSpec.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp @@ -37,8 +37,8 @@ #include #include -#include "../controller/Command.h" -#include "Configuration.h" +#include "../../controller/Command.h" +#include "../Configuration.h" using namespace tlm; @@ -78,7 +78,6 @@ sc_time MemSpec::getMinExecutionTimeForPowerDownCmd(Command command) const TimeInterval MemSpec::getIntervalOnDataStrobe(Command command) const { - // TODO: implement this function for different memspecs, add AL for DDR3 if (command == Command::RD || command == Command::RDA) return TimeInterval(sc_time_stamp() + tRL, sc_time_stamp() + tRL + getReadAccessTime()); else if (command == Command::WR || command == Command::WRA) @@ -91,7 +90,6 @@ TimeInterval MemSpec::getIntervalOnDataStrobe(Command command) const } // Returns the execution time for commands that have a fixed execution time -// TODO: override this method for different MemSpecs? sc_time MemSpec::getExecutionTime(Command command) const { if (command == Command::PRE || command == Command::PREA) @@ -101,6 +99,7 @@ sc_time MemSpec::getExecutionTime(Command command) const else if (command == Command::RD) return tRL + getReadAccessTime(); else if (command == Command::RDA) + // this time is wrong (controller internally waits for tRAS) return tRTP + tRP; else if (command == Command::WR) return tWL + getWriteAccessTime(); @@ -119,33 +118,3 @@ sc_time MemSpec::getExecutionTime(Command command) const return SC_ZERO_TIME; } } - -sc_time MemSpecLPDDR4::getExecutionTime(Command command) const -{ - if (command == Command::PRE) - return tRP; - else if (command == Command::PREA) - return tRPAB; - else if (command == Command::ACT) - return tRCD; - else if (command == Command::RD) - return tRL + getReadAccessTime(); - else if (command == Command::RDA) - return tRTP + tRP; - else if (command == Command::WR) - return tWL + getWriteAccessTime(); - else if (command == Command::WRA) - return tWL + getWriteAccessTime() + tWR + tRP; - else if (command == Command::REFA) - return tRFC; - else if (command == Command::REFB) - return tRFCPB; - else if (command == Command::PDXA || command == Command::PDXP || command == Command::SREFEX) - return clk; - else - { - SC_REPORT_FATAL("getExecutionTime", - "command not known or command doesn't have a fixed execution time"); - return SC_ZERO_TIME; - } -} diff --git a/DRAMSys/library/src/configuration/MemSpec.h b/DRAMSys/library/src/configuration/memspec/MemSpec.h similarity index 69% rename from DRAMSys/library/src/configuration/MemSpec.h rename to DRAMSys/library/src/configuration/memspec/MemSpec.h index 6d277e5a..f053be72 100644 --- a/DRAMSys/library/src/configuration/MemSpec.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.h @@ -40,9 +40,9 @@ #include #include -#include "../common/dramExtensions.h" -#include "../controller/Command.h" -#include "../common/utils.h" +#include "../../common/dramExtensions.h" +#include "../../controller/Command.h" +#include "../../common/utils.h" using namespace tlm; @@ -91,7 +91,6 @@ struct MemSpec sc_time tRFC; sc_time tRP; // only used in DRAMPower - sc_time tAL; // additive delay (delayed execution in dram) sc_time tDQSCK; // Currents and Voltages: @@ -104,10 +103,7 @@ struct MemSpec double iDD6; double vDD; - // For different refresh frequencies on different banks, not implemented - //std::map refreshTimings; - - // Command lengths on bus: + // Command lengths on bus, standardly one clock cycle: unsigned clACT = 1; unsigned clPRE = 1; unsigned clPREA = 1; @@ -127,90 +123,5 @@ struct MemSpec virtual ~MemSpec() {} }; -struct MemSpecDDR3 : public MemSpec -{ - sc_time tCCD; - sc_time tFAW; - sc_time tRRD; - sc_time tWTR; - sc_time tXPDLL; - sc_time tXSDLL; - - double iDD2P0; - double iDD2P1; - double iDD3P0; - double iDD3P1; -}; - -struct MemSpecDDR4 : public MemSpec -{ - sc_time tCCD_S; - sc_time tCCD_L; - sc_time tFAW; - sc_time tRRD_S; - sc_time tRRD_L; - sc_time tWTR_S; - sc_time tWTR_L; - sc_time tXPDLL; - sc_time tXSDLL; - - double iDD02; - double iDD2P0; - double iDD2P1; - double iDD3P0; - double iDD3P1; - double iDD62; - double vDD2; -}; - -struct MemSpecLPDDR4 : public MemSpec -{ - sc_time tCCD; - sc_time tCCDMW; - sc_time tESCKE; - sc_time tFAW; - sc_time tWTR; - sc_time tPPD; - sc_time tREFIPB; - sc_time tRFCPB; - sc_time tRPAB; - sc_time tRRD; - - double iDD02; - double iDD2P0; - double iDD2P1; - double iDD3P0; - double iDD3P1; - double iDD62; - double vDD2; - - virtual sc_time getExecutionTime(Command) const override; -}; - -struct MemSpecWideIO : public MemSpec -{ - sc_time tCCD; - sc_time tRRD; - sc_time tTAW; - sc_time tWTR; - - double iDD02; - double iDD2P0; - double iDD2P02; - double iDD2P1; - double iDD2P12; - double iDD2N2; - double iDD3P0; - double iDD3P02; - double iDD3P1; - double iDD3P12; - double iDD3N2; - double iDD4R2; - double iDD4W2; - double iDD52; - double iDD62; - double vDD2; -}; - #endif // MEMSPEC_H diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h new file mode 100644 index 00000000..4589288a --- /dev/null +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#ifndef MEMSPECDDR3_H +#define MEMSPECDDR3_H + +#include "MemSpec.h" + +struct MemSpecDDR3 : public MemSpec +{ + sc_time tCCD; + sc_time tFAW; + sc_time tRRD; + sc_time tWTR; + sc_time tXPDLL; + sc_time tXSDLL; + sc_time tAL; + + double iDD2P0; + double iDD2P1; + double iDD3P0; + double iDD3P1; +}; + +#endif // MEMSPECDDR3_H diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h new file mode 100644 index 00000000..5df15101 --- /dev/null +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#ifndef MEMSPECDDR4_H +#define MEMSPECDDR4_H + +#include "MemSpec.h" + +struct MemSpecDDR4 : public MemSpec +{ + sc_time tCCD_S; + sc_time tCCD_L; + sc_time tFAW; + sc_time tRRD_S; + sc_time tRRD_L; + sc_time tWTR_S; + sc_time tWTR_L; + sc_time tAL; + sc_time tXPDLL; + sc_time tXSDLL; + + double iDD02; + double iDD2P0; + double iDD2P1; + double iDD3P0; + double iDD3P1; + double iDD62; + double vDD2; +}; + +#endif // MEMSPECDDR4_H diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp new file mode 100644 index 00000000..5bfeeef6 --- /dev/null +++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#include "MemSpecLPDDR4.h" + +sc_time MemSpecLPDDR4::getExecutionTime(Command command) const +{ + if (command == Command::PRE) + return tRP; + else if (command == Command::PREA) + return tRPAB; + else if (command == Command::ACT) + return tRCD; + else if (command == Command::RD) + return tRL + getReadAccessTime(); + else if (command == Command::RDA) + return tRTP + tRP; + else if (command == Command::WR) + return tWL + getWriteAccessTime(); + else if (command == Command::WRA) + return tWL + getWriteAccessTime() + tWR + tRP; + else if (command == Command::REFA) + return tRFC; + else if (command == Command::REFB) + return tRFCPB; + else if (command == Command::PDXA || command == Command::PDXP || command == Command::SREFEX) + return clk; + else + { + SC_REPORT_FATAL("getExecutionTime", + "command not known or command doesn't have a fixed execution time"); + return SC_ZERO_TIME; + } +} + diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h new file mode 100644 index 00000000..cbb86823 --- /dev/null +++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#ifndef MEMSPECLPDDR4_H +#define MEMSPECLPDDR4_H + +#include "MemSpec.h" + +struct MemSpecLPDDR4 : public MemSpec +{ + sc_time tCCD; + sc_time tCCDMW; + sc_time tESCKE; + sc_time tFAW; + sc_time tWTR; + sc_time tPPD; + sc_time tREFIPB; + sc_time tRFCPB; + sc_time tRPAB; + sc_time tRRD; + + double iDD02; + double iDD2P0; + double iDD2P1; + double iDD3P0; + double iDD3P1; + double iDD62; + double vDD2; + + virtual sc_time getExecutionTime(Command) const override; +}; + +#endif // MEMSPECLPDDR4_H diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h new file mode 100644 index 00000000..fd9f1cc5 --- /dev/null +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#ifndef MEMSPECWIDEIO_H +#define MEMSPECWIDEIO_H + +#include "MemSpec.h" + +struct MemSpecWideIO : public MemSpec +{ + sc_time tCCD; + sc_time tRRD; + sc_time tTAW; + sc_time tWTR; + + double iDD02; + double iDD2P0; + double iDD2P02; + double iDD2P1; + double iDD2P12; + double iDD2N2; + double iDD3P0; + double iDD3P02; + double iDD3P1; + double iDD3P12; + double iDD3N2; + double iDD4R2; + double iDD4W2; + double iDD52; + double iDD62; + double vDD2; +}; + +#endif // MEMSPECWIDEIO_H diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.h b/DRAMSys/library/src/controller/checker/CheckerDDR3.h index b3632ba4..45043c94 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.h +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.h @@ -38,7 +38,7 @@ #include "CheckerIF.h" #include #include -#include "../../configuration/MemSpec.h" +#include "../../configuration/memspec/MemSpecDDR3.h" #include "../../configuration/Configuration.h" class RefreshCheckerDDR3Dummy; diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO.h b/DRAMSys/library/src/controller/checker/CheckerWideIO.h index cddbe9f5..db22f8f7 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO.h +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO.h @@ -38,7 +38,7 @@ #include "CheckerIF.h" #include #include -#include "../../configuration/MemSpec.h" +#include "../../configuration/memspec/MemSpecWideIO.h" #include "../../configuration/Configuration.h" class RefreshCheckerWideIODummy; diff --git a/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.cpp b/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.cpp index e26a56c0..c9950e9a 100644 --- a/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.cpp @@ -38,7 +38,6 @@ #include "../../../common/timingCalculations.h" #include "../../../common/utils.h" #include "../../../configuration/Configuration.h" -//#include "../configuration/MemSpec.h" bool ScheduledCommand::isNoCommand() const { diff --git a/DRAMSys/library/src/controller/refresh/RefreshManager.h b/DRAMSys/library/src/controller/refresh/RefreshManager.h index 9c424674..e18192b4 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManager.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManager.h @@ -36,7 +36,7 @@ #define REFRESHMANAGER_H #include "RefreshManagerIF.h" -#include "../../configuration/MemSpec.h" +#include "../../configuration/memspec/MemSpec.h" #include "../BankMachine.h" using namespace tlm; diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h index c58d4595..b4a9c6da 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h @@ -36,7 +36,7 @@ #define REFRESHMANAGERBANKWISE_H #include "RefreshManagerIF.h" -#include "../../configuration/MemSpec.h" +#include "../../configuration/memspec/MemSpec.h" #include "../BankMachine.h" #include #include diff --git a/DRAMSys/library/src/simulation/Dram.h b/DRAMSys/library/src/simulation/Dram.h index ea0a2822..7b1bf5e0 100644 --- a/DRAMSys/library/src/simulation/Dram.h +++ b/DRAMSys/library/src/simulation/Dram.h @@ -45,7 +45,7 @@ #include #include "../common/protocol.h" #include "../configuration/Configuration.h" -#include "../configuration/MemSpec.h" +#include "../configuration/memspec/MemSpec.h" #include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" using namespace std; diff --git a/DRAMSys/library/src/simulation/DramDDR3.cpp b/DRAMSys/library/src/simulation/DramDDR3.cpp index 66d70e08..0f507b74 100644 --- a/DRAMSys/library/src/simulation/DramDDR3.cpp +++ b/DRAMSys/library/src/simulation/DramDDR3.cpp @@ -38,7 +38,7 @@ #include "Dram.h" #include "../configuration/Configuration.h" #include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" -#include "../configuration/MemSpec.h" +#include "../configuration/memspec/MemSpecDDR3.h" DramDDR3::DramDDR3(sc_module_name name) : Dram(name) { diff --git a/DRAMSys/library/src/simulation/DramDDR4.cpp b/DRAMSys/library/src/simulation/DramDDR4.cpp index 36caf370..f62eb99c 100644 --- a/DRAMSys/library/src/simulation/DramDDR4.cpp +++ b/DRAMSys/library/src/simulation/DramDDR4.cpp @@ -38,7 +38,7 @@ #include "Dram.h" #include "../configuration/Configuration.h" #include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" -#include "../configuration/MemSpec.h" +#include "../configuration/memspec/MemSpecDDR4.h" DramDDR4::DramDDR4(sc_module_name name) : Dram(name) { diff --git a/DRAMSys/library/src/simulation/DramWideIO.cpp b/DRAMSys/library/src/simulation/DramWideIO.cpp index 41f05077..98699d02 100644 --- a/DRAMSys/library/src/simulation/DramWideIO.cpp +++ b/DRAMSys/library/src/simulation/DramWideIO.cpp @@ -41,7 +41,7 @@ #include "../configuration/Configuration.h" #include "../error/errormodel.h" #include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" -#include "../configuration/MemSpec.h" +#include "../configuration/memspec/MemSpecWideIO.h" using namespace tlm; @@ -76,7 +76,7 @@ DramWideIO::DramWideIO(sc_module_name name) : Dram(name) memTimingSpec.RRDB = memSpec->tRRD / clk; memTimingSpec.RRDB_L = memSpec->tRRD / clk; memTimingSpec.RRDB_S = memSpec->tRRD / clk; - memTimingSpec.AL = memSpec->tAL / clk; + memTimingSpec.AL = 0; memTimingSpec.CCD = memSpec->tCCD / clk; memTimingSpec.CCD_L = memSpec->tCCD / clk; memTimingSpec.CCD_S = memSpec->tCCD / clk;