diff --git a/analyzer/analyzer/paths.pro b/analyzer/analyzer/paths.pro
index 102db5af..b19fe4eb 100644
--- a/analyzer/analyzer/paths.pro
+++ b/analyzer/analyzer/paths.pro
@@ -8,8 +8,8 @@ CONFIG(qwt){
CONFIG(python){
-# LIBS += -L/opt/python/lib -lpython3.4m
-# INCLUDEPATH += /opt/python/include/python3.4m
- LIBS += -lpython3.3m
- INCLUDEPATH += /usr/include/python3.3
+ LIBS += -L/opt/python/lib -lpython3.4m
+ INCLUDEPATH += /opt/python/include/python3.4m
+# LIBS += -lpython3.3m
+# INCLUDEPATH += /usr/include/python3.3
}
diff --git a/dram/dramSys/dramSys.pro b/dram/dramSys/dramSys.pro
index f0052a93..9a679742 100644
--- a/dram/dramSys/dramSys.pro
+++ b/dram/dramSys/dramSys.pro
@@ -8,15 +8,15 @@ LIBS += -L/opt/systemc/lib-linux64 -lsystemc
LIBS += -L/opt/boost/lib -lboost_filesystem -lboost_system
LIBS += -L/opt/sqlite3/lib -lsqlite3
LIBS += -lpthread
-LIBS += -lxerces-c
-LIBS += -L../src/common/third_party/DRAMPower/src/ -ldrampowerxml
-LIBS += -L../src/common/third_party/DRAMPower/src/ -ldrampower
+#LIBS += -lxerces-c
+#LIBS += -L../src/common/third_party/DRAMPower/src/ -ldrampowerxml
+#LIBS += -L../src/common/third_party/DRAMPower/src/ -ldrampower
INCLUDEPATH += /opt/systemc/include
INCLUDEPATH += /opt/boost/include
INCLUDEPATH += /opt/sqlite3/include
-INCLUDEPATH += ../src/common/third_party/DRAMPower/src
-INCLUDEPATH += ../src/common/third_party/DRAMPower/src/libdrampower
+#INCLUDEPATH += ../src/common/third_party/DRAMPower/src
+#INCLUDEPATH += ../src/common/third_party/DRAMPower/src/libdrampower
DEFINES += TIXML_USE_STL
DEFINES += SC_INCLUDE_DYNAMIC_PROCESSES
@@ -121,5 +121,6 @@ HEADERS += \
../src/simulation/Arbiter.h \
../src/common/libDRAMPower.h \
../src/controller/core/RowBufferStates.h \
- ../src/controller/scheduler/readwritegrouper.h
+ ../src/controller/scheduler/readwritegrouper.h \
+ ../src/simulation/ReorderBuffer.h
diff --git a/dram/resources/configs/amconfigs/am_ddr4 (4th copy).xml b/dram/resources/configs/amconfigs/am_ddr4 (4th copy).xml
deleted file mode 100755
index 73d9cb36..00000000
--- a/dram/resources/configs/amconfigs/am_ddr4 (4th copy).xml
+++ /dev/null
@@ -1,27 +0,0 @@
-
-
-
-
-
- |
-
-
-
-
-
-
-
diff --git a/dram/resources/simulations/sim-batch.xml b/dram/resources/simulations/sim-batch.xml
index 7b793ec0..21a24d7c 100644
--- a/dram/resources/simulations/sim-batch.xml
+++ b/dram/resources/simulations/sim-batch.xml
@@ -1,22 +1,17 @@
WideIO.xml
-
-
am_wideio.xml
-
- fifo.xml
-
-
+
+ fr_fcfs.xml
+
+
- mediabench-epic_32.stl
+ test.stl
diff --git a/dram/src/controller/Controller.h b/dram/src/controller/Controller.h
index 34a1c4e8..814ffc56 100644
--- a/dram/src/controller/Controller.h
+++ b/dram/src/controller/Controller.h
@@ -120,9 +120,10 @@ void Controller::buildScheduler()
if (selectedScheduler == "FR_FCFS")
{
- Scheduler* s = new FR_FCFS(*controllerCore, Configuration::getInstance().RefreshAwareScheduling,
- Configuration::getInstance().AdaptiveOpenPagePolicy);
- scheduler = new ReadWriteGrouper(s);
+ //Scheduler* s = new FR_FCFS(*controllerCore, Configuration::getInstance().RefreshAwareScheduling,
+ // Configuration::getInstance().AdaptiveOpenPagePolicy);
+ //scheduler = new ReadWriteGrouper(s);
+ scheduler = new FR_FCFS(*controllerCore, Configuration::getInstance().RefreshAwareScheduling,Configuration::getInstance().AdaptiveOpenPagePolicy);
}
else if (selectedScheduler == "PAR_BS")
{
diff --git a/dram/src/controller/core/configuration/TimingConfiguration.h b/dram/src/controller/core/configuration/TimingConfiguration.h
index e990c6fd..cb080c94 100644
--- a/dram/src/controller/core/configuration/TimingConfiguration.h
+++ b/dram/src/controller/core/configuration/TimingConfiguration.h
@@ -15,8 +15,8 @@ namespace core{
struct RefreshTiming
{
- RefreshTiming() {};
- RefreshTiming(sc_time tRFC, sc_time tREFI) : tRFC(tRFC), tREFI(tREFI) {};
+ RefreshTiming() {}
+ RefreshTiming(sc_time tRFC, sc_time tREFI) : tRFC(tRFC), tREFI(tREFI) {}
sc_time tRFC;
sc_time tREFI;
};
diff --git a/dram/src/controller/scheduler/readwritegrouper.cpp b/dram/src/controller/scheduler/readwritegrouper.cpp
index 5797fddb..efb202d4 100644
--- a/dram/src/controller/scheduler/readwritegrouper.cpp
+++ b/dram/src/controller/scheduler/readwritegrouper.cpp
@@ -1,13 +1,17 @@
#include "readwritegrouper.h"
+#include "../../common/DebugManager.h"
namespace scheduler{
using namespace tlm;
+using namespace std;
+
+string ReadWriteGrouper::senderName = "ReadWriteGrouper";
ReadWriteGrouper::ReadWriteGrouper(Scheduler *scheduler):
scheduler(scheduler), mode(Mode::read)
{
-
+ printDebugMessage("In read mode");
}
ReadWriteGrouper::~ReadWriteGrouper()
@@ -23,9 +27,9 @@ void ReadWriteGrouper::removePayload(gp *payload)
//if scheduler is empty now
if(!scheduler->hasPayloads())
{
- if(mode == Mode::read && !writeQueue.empty())
- switchToWriteMode();
- else if(mode == Mode::readToWrite)
+ printDebugMessage("No more transactions in scheduler");
+
+ if((mode == Mode::read && !writeQueue.empty()) || mode == Mode::readToWrite)
switchToWriteMode();
else
switchToReadMode();
@@ -42,7 +46,7 @@ if(mode == Mode::read)
if(command == TLM_READ_COMMAND)
{
//if scheduling the read would cause a hazard switch to readToWriteMode and put the read into the readQueue
- if(schedulingReadCausesHazard(payload))
+ if(schedulingReadCausesHazardWithQueuedWrite(payload))
{
switchToReadToWriteMode();
readQueue.push_back(payload);
@@ -50,7 +54,7 @@ if(mode == Mode::read)
else
scheduler->schedule(payload);
}
- else
+ else if(command == TLM_WRITE_COMMAND)
{
writeQueue.push_back(payload);
if(!scheduler->hasPayloads())
@@ -62,14 +66,14 @@ else if(mode == Mode::readToWrite)
{
if(command == TLM_READ_COMMAND)
readQueue.push_back(payload);
- else
+ else if(command == TLM_WRITE_COMMAND)
writeQueue.push_back(payload);
}
else if(mode == Mode::write)
{
if(command == TLM_READ_COMMAND)
readQueue.push_back(payload);
- else
+ else if(command == TLM_WRITE_COMMAND)
scheduler->schedule(payload);
}
@@ -86,7 +90,7 @@ bool ReadWriteGrouper::hasPayloads()
}
-bool ReadWriteGrouper::schedulingReadCausesHazard(gp *payload)
+bool ReadWriteGrouper::schedulingReadCausesHazardWithQueuedWrite(gp *payload)
{
sc_assert(payload->is_read());
for(gp* write: writeQueue)
@@ -99,6 +103,8 @@ bool ReadWriteGrouper::schedulingReadCausesHazard(gp *payload)
void ReadWriteGrouper::switchToReadMode()
{
+ printDebugMessage("Switching to read mode");
+ sc_assert(!scheduler->hasPayloads());
mode = Mode::read;
for(gp* read: readQueue)
scheduler->schedule(read);
@@ -107,6 +113,8 @@ void ReadWriteGrouper::switchToReadMode()
void ReadWriteGrouper::switchToWriteMode()
{
+ printDebugMessage("Switching to write mode");
+ sc_assert(!scheduler->hasPayloads());
mode = Mode::write;
for(gp* write: writeQueue)
scheduler->schedule(write);
@@ -115,7 +123,13 @@ void ReadWriteGrouper::switchToWriteMode()
void ReadWriteGrouper::switchToReadToWriteMode()
{
+ printDebugMessage("Switching to read-to-write-mode");
mode = Mode::readToWrite;
}
+void printDebugMessage(string message)
+{
+ DebugManager::getInstance().printDebugMessage(ReadWriteGrouper::senderName, message);
+}
+
}
diff --git a/dram/src/controller/scheduler/readwritegrouper.h b/dram/src/controller/scheduler/readwritegrouper.h
index 4e8b359f..9f5945f1 100644
--- a/dram/src/controller/scheduler/readwritegrouper.h
+++ b/dram/src/controller/scheduler/readwritegrouper.h
@@ -20,6 +20,8 @@ public:
virtual gp* getNextPayload() override;
virtual void removePayload(gp* payload) override;
+ static std::string senderName;
+
private:
Scheduler *scheduler;
std::vector readQueue, writeQueue;
@@ -28,10 +30,12 @@ private:
enum class Mode{read,readToWrite, write};
Mode mode;
- bool schedulingReadCausesHazard(gp* payload);
+ bool schedulingReadCausesHazardWithQueuedWrite(gp* payload);
void switchToReadMode();
void switchToWriteMode();
void switchToReadToWriteMode();
+ void printDebugMessage(std::string message);
+
};
diff --git a/dram/src/simulation/Arbiter.h b/dram/src/simulation/Arbiter.h
index 410ea46c..e21af2ec 100644
--- a/dram/src/simulation/Arbiter.h
+++ b/dram/src/simulation/Arbiter.h
@@ -45,10 +45,12 @@ public:
private:
tlm_utils::peq_with_cb_and_phase payloadEventQueue;
bool channelIsFree;
- deque backpressure;
+ //used to account for the request_accept_delay in the dram controllers
+ deque pendingRequests;
+ //used to account for the response_accept_delay in the initiators (traceplayer,core etc.)
+ deque pendingResponses[NUMBER_OF_THREADS];
-
- // Initiated by dram
+ // Initiated by dram side
tlm_sync_enum nb_transport_bw(tlm_generic_payload& payload, tlm_phase& phase, sc_time& bwDelay)
{
TlmRecorder::getInstance().recordPhase(payload, phase, bwDelay + sc_time_stamp());
@@ -56,7 +58,7 @@ private:
return TLM_ACCEPTED;
}
- // Initiated by senders
+ // Initiated by initiator side
tlm_sync_enum nb_transport_fw(int socketId, tlm_generic_payload& payload, tlm_phase& phase,
sc_time& fwDelay)
{
@@ -66,7 +68,9 @@ private:
payload.acquire();
}
else if(phase == END_RESP)
+ {
payload.release();
+ }
payloadEventQueue.notify(payload, phase, fwDelay);
return TLM_ACCEPTED;
@@ -74,6 +78,9 @@ private:
void peqCallback(tlm_generic_payload& payload, const tlm_phase& phase)
{
+ unsigned int initiatorSocket = DramExtension::getExtension(payload).getThread().ID()-1;
+
+
//Phases initiated by intiator side
if (phase == BEGIN_REQ)
{
@@ -84,32 +91,40 @@ private:
}
else
{
- backpressure.push_back(&payload);
+ pendingRequests.push_back(&payload);
}
}
else if (phase == END_RESP)
{
- sendToChannel(payload, phase, SC_ZERO_TIME );
+ sendToChannel(payload, phase, SC_ZERO_TIME);
+ pendingResponses[initiatorSocket].pop_front();
+ if(!pendingResponses[initiatorSocket].empty())
+ {
+ tlm_generic_payload* payloadToSend = pendingResponses[initiatorSocket].front();
+ sendToInitiator(initiatorSocket,*payloadToSend,BEGIN_RESP,SC_ZERO_TIME);
+ }
}
//Phases initiated by dram side
else if (phase == END_REQ)
{
channelIsFree = true;
- sendToInitiator(DramExtension::getExtension(payload).getThread().ID()-1, payload, phase, SC_ZERO_TIME);
+ sendToInitiator(initiatorSocket, payload, phase, SC_ZERO_TIME);
- if(!backpressure.empty())
+ if(!pendingRequests.empty())
{
- tlm_generic_payload* payloadToSend = backpressure.front();
- backpressure.pop_front();
+ tlm_generic_payload* payloadToSend = pendingRequests.front();
+ pendingRequests.pop_front();
sendToChannel(*payloadToSend, BEGIN_REQ, SC_ZERO_TIME );
channelIsFree = false;
}
}
else if (phase == BEGIN_RESP)
- {
- sendToInitiator(DramExtension::getExtension(payload).getThread().ID()-1, payload, phase, SC_ZERO_TIME);
+ {
+ if(pendingResponses[initiatorSocket].empty())
+ sendToInitiator(initiatorSocket, payload, phase, SC_ZERO_TIME);
+ pendingResponses[initiatorSocket].push_back(&payload);
}
else
@@ -136,7 +151,7 @@ private:
{
unsigned int burstlength = payload.get_streaming_width();
DecodedAddress decodedAddress = xmlAddressDecoder::getInstance().decodeAddress(payload.get_address());
- DramExtension* extension = new DramExtension(Thread(socketId+1), Channel(decodedAddress.channel), Bank(decodedAddress.bank),
+ DramExtension* extension = new DramExtension(Thread(socketId+1), Channel(0), Bank(decodedAddress.bank),
BankGroup(decodedAddress.bankgroup), Row(decodedAddress.row), Column(decodedAddress.column),burstlength);
payload.set_auto_extension(extension);
}
diff --git a/dram/src/simulation/Arbiter.h.autosave b/dram/src/simulation/Arbiter.h.autosave
new file mode 100644
index 00000000..b7421545
--- /dev/null
+++ b/dram/src/simulation/Arbiter.h.autosave
@@ -0,0 +1,163 @@
+/*
+ * arbiter.h
+ *
+ * Created on: Mar 16, 2014
+ * Author: robert
+ */
+
+#ifndef ARBITER_H_
+#define ARBITER_H_
+
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include "../common/xmlAddressdecoder.h"
+#include "../common/dramExtension.h"
+#include "../controller/core/TimingCalculation.h"
+#include
+
+
+using namespace std;
+using namespace tlm;
+
+template
+struct Arbiter: public sc_module
+{
+public:
+ tlm_utils::simple_initiator_socket iSocket;
+ tlm_utils::simple_target_socket_tagged tSockets[NUMBER_OF_THREADS];
+
+ SC_CTOR(Arbiter) :
+ payloadEventQueue(this, &Arbiter::peqCallback), channelIsFree(true)
+ {
+ iSocket.register_nb_transport_bw(this, &Arbiter::nb_transport_bw);
+
+ for (unsigned int i = 0; i < NUMBER_OF_THREADS; ++i)
+ {
+ tSockets[i].register_nb_transport_fw(this, &Arbiter::nb_transport_fw, i);
+ }
+ }
+
+private:
+ tlm_utils::peq_with_cb_and_phase payloadEventQueue;
+ bool channelIsFree;
+ //used to account for the request_accept_delay in the dram controllers
+ deque pendingRequests;
+ //used to account for the response_accept_delay in the initiators (traceplayer,core etc.)
+ deque receivedResponses[NUMBER_OF_THREADS];
+
+ // Initiated by dram side
+ tlm_sync_enum nb_transport_bw(tlm_generic_payload& payload, tlm_phase& phase, sc_time& bwDelay)
+ {
+ TlmRecorder::getInstance().recordPhase(payload, phase, bwDelay + sc_time_stamp());
+ payloadEventQueue.notify(payload, phase, bwDelay);
+ return TLM_ACCEPTED;
+ }
+
+ // Initiated by initiator side
+ tlm_sync_enum nb_transport_fw(int socketId, tlm_generic_payload& payload, tlm_phase& phase,
+ sc_time& fwDelay)
+ {
+ if(phase == BEGIN_REQ)
+ {
+ appendDramExtension(socketId, payload);
+ payload.acquire();
+ }
+ else if(phase == END_RESP)
+ {
+ payload.release();
+ }
+
+ payloadEventQueue.notify(payload, phase, fwDelay);
+ return TLM_ACCEPTED;
+ }
+
+ void peqCallback(tlm_generic_payload& payload, const tlm_phase& phase)
+ {
+ unsigned int initiatorSocket = DramExtension::getExtension(payload).getThread().ID()-1;
+
+
+ //Phases initiated by intiator side
+ if (phase == BEGIN_REQ)
+ {
+ if(channelIsFree)
+ {
+ channelIsFree = false;
+ sendToChannel(payload, phase, SC_ZERO_TIME );
+ }
+ else
+ {
+ pendingRequests.push_back(&payload);
+ }
+ }
+
+ else if (phase == END_RESP)
+ {
+ sendToChannel(payload, phase, SC_ZERO_TIME);
+ receivedResponses[initiatorSocket].pop_front();
+ if(!receivedResponses[initiatorSocket].empty())
+ {
+ tlm_generic_payload* payloadToSend = receivedResponses[initiatorSocket].front();
+ sendToInitiator(initiatorSocket,*payloadToSend,BEGIN_RESP,SC_ZERO_TIME);
+ }
+ }
+
+ //Phases initiated by dram side
+ else if (phase == END_REQ)
+ {
+ channelIsFree = true;
+ sendToInitiator(initiatorSocket, payload, phase, SC_ZERO_TIME);
+
+ if(!pendingRequests.empty())
+ {
+ tlm_generic_payload* payloadToSend = pendingRequests.front();
+ pendingRequests.pop_front();
+ sendToChannel(*payloadToSend, BEGIN_REQ, SC_ZERO_TIME );
+ channelIsFree = false;
+ }
+ }
+ else if (phase == BEGIN_RESP)
+ {
+ if(receivedResponses[initiatorSocket].empty())
+ sendToInitiator(initiatorSocket, payload, phase, SC_ZERO_TIME);
+ receivedResponses[initiatorSocket].push_back(&payload);
+ }
+
+ else
+ {
+ SC_REPORT_FATAL(0, "Payload event queue in arbiter was triggered with unknown phase");
+ }
+ }
+
+ void sendToChannel(tlm_generic_payload& payload, const tlm_phase& phase, const sc_time& delay)
+ {
+ tlm_phase TPhase = phase;
+ sc_time TDelay = delay;
+ iSocket->nb_transport_fw(payload, TPhase, TDelay);
+ }
+
+ void sendToInitiator(unsigned int id, tlm_generic_payload& payload, const tlm_phase& phase, const sc_time& delay)
+ {
+ tlm_phase TPhase = phase;
+ sc_time TDelay = delay;
+ tSockets[id]->nb_transport_bw(payload, TPhase, TDelay);
+ }
+
+ void appendDramExtension(int socketId, tlm_generic_payload& payload)
+ {
+ unsigned int burstlength = payload.get_streaming_width();
+ DecodedAddress decodedAddress = xmlAddressDecoder::getInstance().decodeAddress(payload.get_address());
+ DramExtension* extension = new DramExtension(Thread(socketId+1), Channel(0), Bank(decodedAddress.bank),
+ BankGroup(decodedAddress.bankgroup), Row(decodedAddress.row), Column(decodedAddress.column),burstlength);
+ payload.set_auto_extension(extension);
+ }
+};
+
+
+
+
+#endif /* ARBITER_H_ */
diff --git a/dram/src/simulation/Dram.h b/dram/src/simulation/Dram.h
index 69c882ba..f28b1749 100644
--- a/dram/src/simulation/Dram.h
+++ b/dram/src/simulation/Dram.h
@@ -19,38 +19,38 @@
#include "../common/protocol.h"
#include "../common/Utils.h"
#include "../common/TlmRecorder.h"
-#include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
-#include "../common/third_party/DRAMPower/src/xmlparser/MemSpecParser.h"
-#include "../common/third_party/DRAMPower/src/MemorySpecification.h"
-#include "../common/third_party/DRAMPower/src/MemCommand.h"
+//#include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
+//#include "../common/third_party/DRAMPower/src/xmlparser/MemSpecParser.h"
+//#include "../common/third_party/DRAMPower/src/MemorySpecification.h"
+//#include "../common/third_party/DRAMPower/src/MemCommand.h"
using namespace std;
using namespace tlm;
using namespace core;
-using namespace Data;
+//using namespace Data;
template
struct Dram: sc_module
{
tlm_utils::simple_target_socket tSocket;
- libDRAMPower *DRAMPower;
+ //libDRAMPower *DRAMPower;
SC_CTOR(Dram) : tSocket("socket")
{
tSocket.register_nb_transport_fw(this, &Dram::nb_transport_fw);
- MemorySpecification memSpec(MemSpecParser::getMemSpecFromXML(Configuration::getInstance().memspecUri));
- //MemorySpecification::getMemSpecFromXML(Configuration::getInstance().memspecUri));
- DRAMPower = new libDRAMPower( memSpec, 1,1,1,0,0 );
+// MemorySpecification memSpec(MemSpecParser::getMemSpecFromXML(Configuration::getInstance().memspecUri));
+// //MemorySpecification::getMemSpecFromXML(Configuration::getInstance().memspecUri));
+// DRAMPower = new libDRAMPower( memSpec, 1,1,1,0,0 );
}
~Dram()
{
- DRAMPower->updateCounters(true);
- DRAMPower->getEnergy();
- cout << "Total Energy" << "\t" << DRAMPower->mpm.energy.total_energy << endl;
- cout << "Average Power" << "\t" << DRAMPower->mpm.power.average_power << endl;
+// DRAMPower->updateCounters(true);
+// DRAMPower->getEnergy();
+// cout << "Total Energy" << "\t" << DRAMPower->mpm.energy.total_energy << endl;
+// cout << "Average Power" << "\t" << DRAMPower->mpm.power.average_power << endl;
}
virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& payload, tlm::tlm_phase& phase, sc_time& delay)
@@ -58,47 +58,47 @@ struct Dram: sc_module
TlmRecorder::getInstance().recordPhase(payload, phase, sc_time_stamp() + delay);
// This is only needed for power simulation:
- unsigned long long cycle = sc_time_stamp().value()/Configuration::getInstance().Timings.clk.value();
+ //unsigned long long cycle = sc_time_stamp().value()/Configuration::getInstance().Timings.clk.value();
unsigned int bank = DramExtension::getExtension(payload).getBank().ID();
if (phase == BEGIN_PRE)
{
- DRAMPower->doCommand(MemCommand::PRE, bank, cycle);
+ //DRAMPower->doCommand(MemCommand::PRE, bank, cycle);
sendToController(payload, END_PRE, delay + getExecutionTime(Command::Precharge, payload));
}
else if (phase == BEGIN_PRE_ALL)
{
- DRAMPower->doCommand(MemCommand::PREA, bank, cycle);
+ //DRAMPower->doCommand(MemCommand::PREA, bank, cycle);
sendToController(payload, END_PRE_ALL,delay + getExecutionTime(Command::PrechargeAll, payload));
}
else if (phase == BEGIN_ACT)
{
- DRAMPower->doCommand(MemCommand::ACT, bank, cycle);
+ //DRAMPower->doCommand(MemCommand::ACT, bank, cycle);
sendToController(payload, END_ACT, delay + getExecutionTime(Command::Activate, payload));
}
else if (phase == BEGIN_WR)
{
- DRAMPower->doCommand(MemCommand::WR, bank, cycle);
+ //DRAMPower->doCommand(MemCommand::WR, bank, cycle);
sendToController(payload, END_WR, delay + getExecutionTime(Command::Write, payload));
}
else if (phase == BEGIN_RD)
{
- DRAMPower->doCommand(MemCommand::RD, bank, cycle);
+ //DRAMPower->doCommand(MemCommand::RD, bank, cycle);
sendToController(payload, END_RD, delay + getExecutionTime(Command::Read, payload));
}
else if (phase == BEGIN_WRA)
{
- DRAMPower->doCommand(MemCommand::WRA, bank, cycle);
+ //DRAMPower->doCommand(MemCommand::WRA, bank, cycle);
sendToController(payload, END_WRA, delay + getExecutionTime(Command::WriteA, payload));
}
else if (phase == BEGIN_RDA)
{
- DRAMPower->doCommand(MemCommand::RDA, bank, cycle);
+ //DRAMPower->doCommand(MemCommand::RDA, bank, cycle);
sendToController(payload, END_RDA, delay + getExecutionTime(Command::ReadA, payload));
}
else if (phase == BEGIN_AUTO_REFRESH)
{
- DRAMPower->doCommand(MemCommand::REF, bank, cycle);
+ //DRAMPower->doCommand(MemCommand::REF, bank, cycle);
sendToController(payload, END_AUTO_REFRESH, delay + getExecutionTime(Command::AutoRefresh, payload));
}
@@ -109,7 +109,7 @@ struct Dram: sc_module
{
if(bank == 0)
{
- DRAMPower->doCommand(MemCommand::PDN_S_PRE, bank, cycle);
+ //DRAMPower->doCommand(MemCommand::PDN_S_PRE, bank, cycle);
}
}
}
@@ -119,7 +119,7 @@ struct Dram: sc_module
{
if(bank == 0)
{
- DRAMPower->doCommand(MemCommand::PUP_PRE, bank, cycle);
+ //DRAMPower->doCommand(MemCommand::PUP_PRE, bank, cycle);
}
}
}
@@ -129,7 +129,7 @@ struct Dram: sc_module
{
if(bank == 0)
{
- DRAMPower->doCommand(MemCommand::PDN_S_ACT, bank, cycle);
+ //DRAMPower->doCommand(MemCommand::PDN_S_ACT, bank, cycle);
}
}
}
@@ -139,17 +139,17 @@ struct Dram: sc_module
{
if(bank == 0)
{
- DRAMPower->doCommand(MemCommand::PUP_ACT, bank, cycle);
+ //DRAMPower->doCommand(MemCommand::PUP_ACT, bank, cycle);
}
}
}
else if (phase == BEGIN_SREF)
{
- DRAMPower->doCommand(MemCommand::SREN, bank, cycle);
+ //DRAMPower->doCommand(MemCommand::SREN, bank, cycle);
}
else if (phase == END_SREF)
{
- DRAMPower->doCommand(MemCommand::SREX, bank, cycle);
+ //DRAMPower->doCommand(MemCommand::SREX, bank, cycle);
}
else
{
diff --git a/dram/src/simulation/ReorderBuffer.h b/dram/src/simulation/ReorderBuffer.h
new file mode 100644
index 00000000..d1ce1fff
--- /dev/null
+++ b/dram/src/simulation/ReorderBuffer.h
@@ -0,0 +1,121 @@
+#ifndef REORDERBUFFER_H
+#define REORDERBUFFER_H
+
+#include
+#include
+#include
+
+using namespace std;
+using namespace tlm;
+
+template
+struct ReorderBuffer: public sc_module
+{
+public:
+ tlm_utils::simple_initiator_socket iSocket;
+ tlm_utils::simple_target_socket_tagged tSocket;
+
+ SC_CTOR(ReorderBuffer) :
+ payloadEventQueue(this, &ReorderBuffer::peqCallback), responseIsPendingInInitator(false)
+ {
+ iSocket.register_nb_transport_bw(this, &ReorderBuffer::nb_transport_bw);
+ tSocket.register_nb_transport_fw(this, &ReorderBuffer::nb_transport_fw);
+ }
+
+private:
+ tlm_utils::peq_with_cb_and_phase payloadEventQueue;
+ deque requestsInOrder;
+ set receivedResponses;
+
+ bool responseIsPendingInInitator;
+
+
+ // Initiated by dram side
+ tlm_sync_enum nb_transport_bw(tlm_generic_payload& payload, tlm_phase& phase, sc_time& bwDelay)
+ {
+ payloadEventQueue.notify(payload, phase, bwDelay);
+ return TLM_ACCEPTED;
+ }
+
+ // Initiated by initator side (players)
+ tlm_sync_enum nb_transport_fw(tlm_generic_payload& payload, tlm_phase& phase,
+ sc_time& fwDelay)
+ {
+ if (phase == BEGIN_REQ)
+ {
+ payload.acquire();
+ }
+ else if (phase == END_RESP)
+ {
+ payload.release();
+ }
+
+ payloadEventQueue.notify(payload, phase, fwDelay);
+ return TLM_ACCEPTED;
+ }
+
+ void peqCallback(tlm_generic_payload& payload, const tlm_phase& phase)
+ {
+ //Phases initiated by initiator side
+ if (phase == BEGIN_REQ)
+ {
+ requestsInOrder.push_back(&payload);
+ sendToTarget(payload, phase, SC_ZERO_TIME );
+ }
+
+ else if (phase == END_RESP)
+ {
+ responseIsPendingInInitator = false;
+ sendNextResponse();
+ }
+
+ //Phases initiated by dram side
+ else if (phase == END_REQ)
+ {
+ sendToInitiator(payload, phase, SC_ZERO_TIME);
+ }
+ else if (phase == BEGIN_RESP)
+ {
+ sendToTarget(payload, END_RESP, SC_ZERO_TIME);
+ receivedResponses.emplace(&payload);
+ sendNextResponse();
+ }
+
+ else
+ {
+ SC_REPORT_FATAL(0, "Payload event queue in arbiter was triggered with unknown phase");
+ }
+ }
+
+ void sendToTarget(tlm_generic_payload& payload, const tlm_phase& phase, const sc_time& delay)
+ {
+ tlm_phase TPhase = phase;
+ sc_time TDelay = delay;
+ iSocket->nb_transport_fw(payload, TPhase, TDelay);
+ }
+
+ void sendToInitiator(tlm_generic_payload& payload, const tlm_phase& phase, const sc_time& delay)
+ {
+ tlm_phase TPhase = phase;
+ sc_time TDelay = delay;
+ tSocket->nb_transport_bw(payload, TPhase, TDelay);
+ }
+
+ void sendNextResponse()
+ {
+ if(!responseIsPendingInInitator && receivedResponses.count(requestsInOrder.front()))
+ {
+ tlm_generic_payload* payloadToSend = requestsInOrder.front();
+ requestsInOrder.pop_front();
+ receivedResponses.erase(payloadToSend);
+ responseIsPendingInInitator = true;
+ sendToInitiator(payloadToSend,BEGIN_RESP,SC_ZERO_TIME);
+ }
+ }
+
+};
+
+
+
+
+#endif // REORDERBUFFER_H
diff --git a/dram/src/simulation/Simulation.cpp b/dram/src/simulation/Simulation.cpp
index 31507a77..48158a40 100644
--- a/dram/src/simulation/Simulation.cpp
+++ b/dram/src/simulation/Simulation.cpp
@@ -44,14 +44,15 @@ void Simulation::setupDebugManager(const string& traceName)
{
auto& dbg = DebugManager::getInstance();
-// dbg.addToWhiteList(controller->name());
-// dbg.addToWhiteList(player2->name());
-// dbg.addToWhiteList(player1->name());
-// dbg.addToWhiteList(this->name());
-// dbg.addToWhiteList(Scheduler::sendername);
-// dbg.addToWhiteList(TlmRecorder::senderName);
-// dbg.addToWhiteList(ControllerCore::senderName);
-// dbg.addToWhiteList(PowerDownManagerBankwise::senderName);
+ dbg.addToWhiteList(controller->name());
+ dbg.addToWhiteList(player2->name());
+ dbg.addToWhiteList(player1->name());
+ dbg.addToWhiteList(this->name());
+ dbg.addToWhiteList(Scheduler::sendername);
+ dbg.addToWhiteList(TlmRecorder::senderName);
+ dbg.addToWhiteList(ControllerCore::senderName);
+ dbg.addToWhiteList(PowerDownManagerBankwise::senderName);
+ dbg.addToWhiteList(ReadWriteGrouper::senderName);
dbg.writeToConsole = true;
dbg.writeToFile = true;
diff --git a/dram/src/simulation/Simulation.h b/dram/src/simulation/Simulation.h
index 1075291f..7e1017ed 100644
--- a/dram/src/simulation/Simulation.h
+++ b/dram/src/simulation/Simulation.h
@@ -11,6 +11,7 @@
#include "Dram.h"
#include "Arbiter.h"
#include "TracePlayer.h"
+#include "ReorderBuffer.h"
#include "../controller/Controller.h"
#include "ISimulation.h"
#include