integrated scheduler into core

dram/src/core/Controller.cpp

@@ -49,7 +49,7 @@ void DramController::scheduleRefresh(sc_time time)
 	refreshManager.scheduleRefresh(time);
 }
 
-void DramController::schedule(sc_time start, tlm::tlm_generic_payload& payload)
+bool DramController::schedule(sc_time start, tlm::tlm_generic_payload& payload)
 {
 	bus.cleanUpBus(start);
 
@@ -62,30 +62,39 @@ void DramController::schedule(sc_time start, tlm::tlm_generic_payload& payload)
 			payload);
 	CommandSchedule schedule = commandSequenceScheduler.schedule(sequence, start, payload);
 
-	//commandbuschecker (schedule)
-
-	while (refreshManager.hasCollision(schedule))
+	if (refreshManager.hasCollision(schedule))
 	{
 		resetState();
-		refreshManager.scheduleRefresh(start);
-		saveState();
-
-
-		sequence = commandSequenceGenerator.generateCommandSequence(payload);
-		schedule = commandSequenceScheduler.schedule(sequence, start, payload);
-		assert(schedule.getExecutionTime() < config.Timings.refreshTimings[0].tREFI); //TODO make nice
+		return false;
+	}
+	else
+	{
+		bus.send(schedule);
+		return true;
 	}
-
-	bus.send(schedule);
 }
 
-
-/*const ICommandChecker& DramController::getChecker(Command command) const
+bool core::DramController::isBusy(sc_time currentTime, Bank bank)
 {
-	std::map<Command, ICommandChecker*>::const_iterator result = commandChecker.find(command);
-	assert(result != commandChecker.end());
-	return *(result->second);
-}*/
+	ScheduledCommand lastScheduledCommand = state.getLastCommand(bank);
+	if(lastScheduledCommand.isNoCommand())
+		return false;
+	else if(lastScheduledCommand.getCommand() == Write || lastScheduledCommand.getCommand() == Read)
+	{
+		return (currentTime < lastScheduledCommand.getStart());
+	}
+	else if(lastScheduledCommand.getCommand() == Refresh)
+	{
+		return (currentTime < lastScheduledCommand.getEnd());
+	}
+	else
+	{
+		SC_ASSERT_(false, "last command in command sequence was activate or precharge");
+		return false;
+	}
+
+}
 
 } /* namespace controller */
 
+