From bb357b44f543854d8591b543967e5aa404577870 Mon Sep 17 00:00:00 2001
From: Lukas Steiner <lsteiner@rhrk.uni-kl.de>
Date: Mon, 27 Apr 2020 13:56:59 +0200
Subject: [PATCH] Adapted config files for CI.

---
 .gitlab-ci.yml                                |  2 +-
 .../am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml         | 59 +++++++++--------
 .../DDR3/configs/mcconfigs/fifoStrict.xml     | 64 +++++--------------
 .../tests/DDR3/configs/mcconfigs/fr_fcfs.xml  | 62 +++++-------------
 4 files changed, 68 insertions(+), 119 deletions(-)

diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 718fd16c..9011e4ab 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -20,7 +20,7 @@ build:
         - mkdir -p build
         - cd build
         - cmake ../DRAMSys
-        - make -j4
+        - make -j16
         - find . -name "*.o" -type f -delete
         - rm -rf ${CI_PROJECT_DIR}/coverage
         - mkdir -p ${CI_PROJECT_DIR}/coverage
diff --git a/DRAMSys/tests/DDR3/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml b/DRAMSys/tests/DDR3/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml
index 39d66692..b2c3af48 100644
--- a/DRAMSys/tests/DDR3/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml
+++ b/DRAMSys/tests/DDR3/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml
@@ -1,25 +1,34 @@
-<!-- 
-DDR3 Example:
-1GB x64 DIMM with: 8 * 1 Gb x8 Devices (e.g. Micron MT41J128M8) with Page Size: 1KB
-
-Device Characteristics:
-
-Rows: 16 K [13:0]  -> 14 bit
-Bank: 8    [2:0]   -> 3  bit
-Cols: 1 K  [9:0]   -> 10 bit
-
-Due to the DIMM we have a Byte Offset Y
-       
-2 2 2 | 2 2 2 2 2 2 2 1 1 1 1 1 1 1 | 1 1 1 
-9 8 7 | 6 5 4 3 2 1 0 9 8 7 6 5 4 3 | 2 1 0 9 8 7 6 5 4 3 | 2 1 0
-B B B | R R R R R R R R R R R R R R | C C C C C C C C C C | Y Y Y
--->
-
-<addressmapping>
-    <channel from="128"  to="128"  /> <!-- only one channel -->
-    <bank    from="27"   to="29"   />
-    <row     from="13"   to="26"   />
-    <column  from="3"    to="12"   />
-    <bytes   from="0"    to="2"    />
-</addressmapping>
-
+<CONGEN>
+    <SOLUTION ID="0">
+        <BYTE_BIT>0</BYTE_BIT>
+        <BYTE_BIT>1</BYTE_BIT>
+        <BYTE_BIT>2</BYTE_BIT>
+        <COLUMN_BIT>3</COLUMN_BIT>
+        <COLUMN_BIT>4</COLUMN_BIT>
+        <COLUMN_BIT>5</COLUMN_BIT>
+        <COLUMN_BIT>6</COLUMN_BIT>
+        <COLUMN_BIT>7</COLUMN_BIT>
+        <COLUMN_BIT>8</COLUMN_BIT>
+        <COLUMN_BIT>9</COLUMN_BIT>
+        <COLUMN_BIT>10</COLUMN_BIT>
+        <COLUMN_BIT>11</COLUMN_BIT>
+        <COLUMN_BIT>12</COLUMN_BIT>
+        <ROW_BIT>13</ROW_BIT>
+        <ROW_BIT>14</ROW_BIT>
+        <ROW_BIT>15</ROW_BIT>
+        <ROW_BIT>16</ROW_BIT>
+        <ROW_BIT>17</ROW_BIT>
+        <ROW_BIT>18</ROW_BIT>
+        <ROW_BIT>19</ROW_BIT>
+        <ROW_BIT>20</ROW_BIT>
+        <ROW_BIT>21</ROW_BIT>
+        <ROW_BIT>22</ROW_BIT>
+        <ROW_BIT>23</ROW_BIT>
+        <ROW_BIT>24</ROW_BIT>
+        <ROW_BIT>25</ROW_BIT>
+        <ROW_BIT>26</ROW_BIT>
+        <BANK_BIT>27</BANK_BIT>
+        <BANK_BIT>28</BANK_BIT>
+        <BANK_BIT>29</BANK_BIT>
+    </SOLUTION>
+</CONGEN>
\ No newline at end of file
diff --git a/DRAMSys/tests/DDR3/configs/mcconfigs/fifoStrict.xml b/DRAMSys/tests/DDR3/configs/mcconfigs/fifoStrict.xml
index ed869b57..44bf294e 100644
--- a/DRAMSys/tests/DDR3/configs/mcconfigs/fifoStrict.xml
+++ b/DRAMSys/tests/DDR3/configs/mcconfigs/fifoStrict.xml
@@ -1,50 +1,20 @@
 <mcconfig>
-    <OpenPagePolicy value="1" />
-    <MaxNrOfTransactions value="8" />
-    <Scheduler value="FifoStrict" />
-    <Capsize value="5" />
-    <!-- 4 Modes: NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
-    <PowerDownMode value="NoPowerDown" />
+	<!-- Open, OpenAdaptive, Closed, ClosedAdaptive -->
+	<PagePolicy value="Open" />
+	<!-- Fifo, FrFcfs, FrFcfsGrp -->
+    <Scheduler value="Fifo" />
+	<RequestBufferSize value="8" />
+	<!-- Oldest, Strict -->
+	<CmdMux value="Strict" />
+	<!-- Fifo, Reorder -->
+	<RespQueue value="Fifo" />
+	<!-- NoRefresh, Rankwise, Bankwise -->
+	<RefreshPolicy value="Rankwise" />
+	<!-- 1: 1X, 2: 2X, 4: 4X (e.g., DDR4) -->
+	<RefreshMode value="1" />
+	<RefreshMaxPostponed value="0"/>
+    <RefreshMaxPulledin value="0"/>
+    <!-- NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
+    <PowerDownPolicy value="NoPowerDown" />
     <PowerDownTimeout value="100" />
-	<!-- Bankwise -->
-    <BankwiseLogic value="0"/>
-	<!-- Refresh yes, no -->
-    <ControllerCoreRefDisable value="0"/>
-	<!-- Refresh Mode. 1: 1X, 2: 2X, 4: 4X (e.g., DDR4) -->
-    <ControllerCoreRefMode value="1"/>
-    <!-- Number of AR commands in a tREFI in 1X mode -->
-    <ControllerCoreRefNumARCmdsIntREFI value="8192"/>
-	<!-- RGR -->
-    <ControllerCoreRGR value="0"/>
-    <ControllerCoreRGRRowInc value="1"/>
-	<!-- Banks to be refreshed in RGR mode. 1: yes, 0: no (max. 16 banks) -->
-    <ControllerCoreRGRB0  value="1"/>
-    <ControllerCoreRGRB1  value="1"/>
-    <ControllerCoreRGRB2  value="1"/>
-    <ControllerCoreRGRB3  value="1"/>
-    <ControllerCoreRGRB4  value="1"/>
-    <ControllerCoreRGRB5  value="1"/>
-    <ControllerCoreRGRB6  value="1"/>
-    <ControllerCoreRGRB7  value="1"/>
-    <ControllerCoreRGRB8  value="0"/>
-    <ControllerCoreRGRB9  value="0"/>
-    <ControllerCoreRGRB10 value="0"/>
-    <ControllerCoreRGRB11 value="0"/>
-    <ControllerCoreRGRB12 value="0"/>
-    <ControllerCoreRGRB13 value="0"/>
-    <ControllerCoreRGRB14 value="0"/>
-    <ControllerCoreRGRB15 value="0"/>
-	<!-- Timings for RGR normal or optimal values -->
-    <ControllerCoreRGRtRASBInClkCycles value="22"/>
-    <ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
-    <ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
-    <ControllerCoreRGRtRPBInClkCycles value="15"/>
-    <ControllerCoreRGRtRCBInClkCycles value="37"/>
-    <ControllerCoreRGRtFAWBInClkCycles value="0"/>
-	<!-- Postpone, pull-in -->
-    <ControllerCoreRefEnablePostpone value="0"/>
-    <ControllerCoreRefEnablePullIn value="0"/>
-    <ControllerCoreRefMaxPostponed value="8"/>
-    <ControllerCoreRefMaxPulledIn value="8"/>
-    <ControllerCoreRefForceMaxPostponeBurst value="0"/>
 </mcconfig>
diff --git a/DRAMSys/tests/DDR3/configs/mcconfigs/fr_fcfs.xml b/DRAMSys/tests/DDR3/configs/mcconfigs/fr_fcfs.xml
index 20db08cd..7240485d 100644
--- a/DRAMSys/tests/DDR3/configs/mcconfigs/fr_fcfs.xml
+++ b/DRAMSys/tests/DDR3/configs/mcconfigs/fr_fcfs.xml
@@ -1,50 +1,20 @@
 <mcconfig>
-    <OpenPagePolicy value="1" />
-    <MaxNrOfTransactions value="8" />
+	<!-- Open, OpenAdaptive, Closed, ClosedAdaptive -->
+	<PagePolicy value="Open" />
+	<!-- Fifo, FrFcfs, FrFcfsGrp -->
     <Scheduler value="FrFcfs" />
-    <Capsize value="5" />
-    <!-- 4 Modes: NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
-    <PowerDownMode value="NoPowerDown" />
+	<RequestBufferSize value="8" />
+	<!-- Oldest, Strict -->
+	<CmdMux value="Oldest" />
+	<!-- Fifo, Reorder -->
+	<RespQueue value="Fifo" />
+	<!-- NoRefresh, Rankwise, Bankwise -->
+	<RefreshPolicy value="Rankwise" />
+	<!-- 1: 1X, 2: 2X, 4: 4X (e.g., DDR4) -->
+	<RefreshMode value="1" />
+	<RefreshMaxPostponed value="0"/>
+    <RefreshMaxPulledin value="0"/>
+    <!-- NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
+    <PowerDownPolicy value="NoPowerDown" />
     <PowerDownTimeout value="100" />
-	<!-- Bankwise -->
-    <BankwiseLogic value="0"/>
-	<!-- Refresh yes, no -->
-    <ControllerCoreRefDisable value="0"/>
-	<!-- Refresh Mode. 1: 1X, 2: 2X, 4: 4X (e.g., DDR4) -->
-    <ControllerCoreRefMode value="1"/>
-    <!-- Number of AR commands in a tREFI in 1X mode -->
-    <ControllerCoreRefNumARCmdsIntREFI value="8192"/>
-	<!-- RGR -->
-    <ControllerCoreRGR value="0"/>
-    <ControllerCoreRGRRowInc value="1"/>
-	<!-- Banks to be refreshed in RGR mode. 1: yes, 0: no (max. 16 banks) -->
-    <ControllerCoreRGRB0  value="1"/>
-    <ControllerCoreRGRB1  value="1"/>
-    <ControllerCoreRGRB2  value="1"/>
-    <ControllerCoreRGRB3  value="1"/>
-    <ControllerCoreRGRB4  value="1"/>
-    <ControllerCoreRGRB5  value="1"/>
-    <ControllerCoreRGRB6  value="1"/>
-    <ControllerCoreRGRB7  value="1"/>
-    <ControllerCoreRGRB8  value="0"/>
-    <ControllerCoreRGRB9  value="0"/>
-    <ControllerCoreRGRB10 value="0"/>
-    <ControllerCoreRGRB11 value="0"/>
-    <ControllerCoreRGRB12 value="0"/>
-    <ControllerCoreRGRB13 value="0"/>
-    <ControllerCoreRGRB14 value="0"/>
-    <ControllerCoreRGRB15 value="0"/>
-	<!-- Timings for RGR normal or optimal values -->
-    <ControllerCoreRGRtRASBInClkCycles value="22"/>
-    <ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
-    <ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
-    <ControllerCoreRGRtRPBInClkCycles value="15"/>
-    <ControllerCoreRGRtRCBInClkCycles value="37"/>
-    <ControllerCoreRGRtFAWBInClkCycles value="0"/>
-	<!-- Postpone, pull-in -->
-    <ControllerCoreRefEnablePostpone value="0"/>
-    <ControllerCoreRefEnablePullIn value="0"/>
-    <ControllerCoreRefMaxPostponed value="8"/>
-    <ControllerCoreRefMaxPulledIn value="8"/>
-    <ControllerCoreRefForceMaxPostponeBurst value="0"/>
 </mcconfig>