Updated readme, code formatting.

DRAMSys/gem5/main.cpp

@@ -65,7 +65,7 @@ public:
         Gem5SystemC::Gem5SimControl("gem5", configFile, 0, "MemoryAccess")
     {}
 
-    void afterSimulate()
+    virtual void afterSimulate() override
     {
         sc_stop();
     }
@@ -144,17 +144,21 @@ int sc_main(int argc, char **argv)
     Gem5SystemC::Gem5SlaveTransactor *t;
     std::vector<Gem5SystemC::Gem5SlaveTransactor *> transactors;
 
-    if (argc == 4) {
+    if (argc == 4)
+    {
         // Get path of resources:
         resources = pathOfFile(argv[0])
                     + std::string("/../../DRAMSys/library/resources/");
 
         simulationJson = argv[1];
         gem5ConfigFile = argv[2];
-        numTransactors = std::stoul(argv[3]);
+        numTransactors = static_cast<unsigned>(std::stoul(argv[3]));
 
-    } else {
+    }
+    else
+    {
         SC_REPORT_FATAL("sc_main", "Please provide configuration files and number of ports");
+        return EXIT_FAILURE;
     }
 
     // Instantiate DRAMSys:
@@ -177,13 +181,17 @@ int sc_main(int argc, char **argv)
     // - for a single port the port name is "transactor"
     // - for multiple ports names are transactor1, transactor2, ..., transactorN
     // Names generated here must match port names used by the gem5 config file, e.g., config.ini
-    if (numTransactors == 1) {
+    if (numTransactors == 1)
+    {
         t = new Gem5SystemC::Gem5SlaveTransactor("transactor", "transactor");
         t->socket.bind(dramSys->tSocket);
         t->sim_control.bind(sim_control);
         transactors.push_back(t);
-    } else {
+    }
-        for (unsigned i = 0; i < numTransactors; i++) {
+    else
+    {
+        for (unsigned i = 0; i < numTransactors; i++)
+        {
             // If there are two or more ports
             unsigned index = i + 1;
             std::string name = "transactor" + std::to_string(index);
@@ -218,7 +226,8 @@ int sc_main(int argc, char **argv)
     sc_core::sc_set_stop_mode(SC_STOP_FINISH_DELTA);
     sc_core::sc_start();
 
-    if (!sc_core::sc_end_of_simulation_invoked()) {
+    if (!sc_core::sc_end_of_simulation_invoked())
+    {
         SC_REPORT_INFO("sc_main", "Simulation stopped without explicit sc_stop()");
         sc_core::sc_stop();
     }

DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4400A.json

@@ -47,12 +47,12 @@
             "FAW_dlr": 0,    
             "WTR_L": 22,      
             "WTR_S": 6,      
-            "RFC_slr": 429,
+            "RFC1_slr": 429,
-            "RFC_slr": 286,            
+            "RFC2_slr": 286,            
-            "RFC_dlr": 0,
+            "RFC1_dlr": 0,
-            "RFC_dlr": 0,            
+            "RFC2_dlr": 0,            
-            "RFC_dpr": 0,
+            "RFC1_dpr": 0,
-            "RFC_dpr": 0,            
+            "RFC2_dpr": 0,            
             "RFCsb_slr": 253,  
             "RFCsb_dlr": 0,  
             "REFI1": 8580, 

README.md

@@ -312,48 +312,61 @@ An example follows.
     "mcconfig": {
         "PagePolicy": "Open", 
         "Scheduler": "Fifo", 
+        "SchedulerBuffer": "ReadWrite",
         "RequestBufferSize": 8, 
         "CmdMux": "Oldest", 
         "RespQueue": "Fifo", 
-        "RefreshPolicy": "Rankwise", 
+        "RefreshPolicy": "AllBank", 
         "RefreshMaxPostponed": 8, 
         "RefreshMaxPulledin": 8, 
         "PowerDownPolicy": "NoPowerDown", 
-        "PowerDownTimeout": 100
+        "Arbiter": "Fifo",
+        "MaxActiveTransactions": 128 
     }
 }
 ```
 
   - *PagePolicy* (string)
-      - "Open"
+      - "Open": no auto-precharge is performed after read or write commands
-      - "OpenAdaptive"
+      - "OpenAdaptive": auto-precharge after read or write commands is only performed if further requests for the targeted bank are stored in the scheduler and all the requests are row misses
-      - "Closed"
+      - "Closed": auto-precharge is performed after each read or write command
-      - "ClosedAdaptive"
+      - "ClosedAdaptive": auto-precharge after read or write commands is performed if all further requests for the targeted bank stored in the scheduler are row misses or if there are no further requests stored 
   - *Scheduler* (string)
-    - "Fifo": first in, first out
+    - all policies are applied locally to one bank, not globally to the whole channel
-    - "FrFcfs": first-ready - first-come, first-served
+    - "Fifo": first in, first out policy
-    - "FrFcfsGrp": first-ready - first-come, first-served with grouping of read and write requests
+    - "FrFcfs": first-ready - first-come, first-served policy (row hits are preferred to row misses)
-  - RequestBufferSize (unsigned int)
+    - "FrFcfsGrp": first-ready - first-come, first-served policy with additional grouping of read and write requests
-    - buffer size of the scheduler
+- *SchedulerBuffer* (string)
-  - *CmdMux* (string)
+     - "Bankwise": requests are stored in bankwise buffers
-      - "Oldest": oldest payload has the highest priority
+     - "ReadWrite": read and write requests are stored in different buffers
-      - "Strict": read and write commands are issued in the same order as their corresponding requests arrived at the channel controller (can only be combined with "Fifo" scheduler) 
+     - "Shared": all requests are stored in one shared buffer
-  - *RespQueue* (string)
+
-      - "Strict": outgoing responses are not reordered
+- *RequestBufferSize* (unsigned int)
-      - "Reorder": outgoing responses are reordered
+  - depth of a single scheduler buffer entity, total buffer depth depends on the selected scheduler buffer policy
-  - *RefreshPolicy* (string)
+- *CmdMux* (string)
-      - "NoRefresh": refresh disabled
+    - "Oldest": from all commands that are ready to be issued in the current clock cycle the one that belongs to the oldest transaction has the highest priority; commands from refresh managers have a higher priority than all other commands, commands from power down managers have a lower priority than all other commands
-      - "Rankwise": all-bank refresh commands, issued per rank
+    - "Strict": based on "Oldest", in addition, read and write commands are strictly issued in the order their corresponding requests arrived at the channel controller (can only be used in combination with the "Fifo" scheduler) 
-      - "Bankwise": per-bank refresh commands (only supported by LPDDR4, Wide I/O 2, GDDR5/5X/6, HBM2)
+- *RespQueue* (string)
-  - *RefreshMaxPostponed*
+    - "Fifo": the original request order is not restored for outgoing responses 
-      - maximum number of refresh commands that can be postponed (usually 8, with per-bank refresh the number is automatically multiplied by the number of banks)
+    - "Reorder": the original request order is restored for outgoing responses (only within the channel)
-  - *RefreshMaxPulledin*
+- *RefreshPolicy* (string)
-      - maximum number of refresh commands that can be pulled in (usually 8, with per-bank refresh the number is automatically multiplied by the number of banks)
+    - "NoRefresh": refresh is disabled
-  - *PowerDownPolicy* (string)
+    - "AllBank": all-bank refresh commands are issued (per rank)
-    - "NoPowerDown": power down disabled
+    - "PerBank": per-bank refresh commands are issued (only available in combination with LPDDR4, Wide I/O 2, GDDR5/5X/6 or HBM2)
-    - "Staggered": staggered power down policy [5]
+    - "SameBank": same-bank refresh commands are issued (only available in combination with DDR5)
-- PowerDownTimeout (unsigned int)
+- *RefreshMaxPostponed* (unsigned int)
-  - currently unused
+    - maximum number of refresh commands that can be postponed (with per-bank refresh the number is internally multiplied with the number of banks, with same-bank refresh the number is internally multiplied with the number of banks per bank group)
+- *RefreshMaxPulledin* (unsigned int)
+    - maximum number of refresh commands that can be pulled in (with per-bank refresh the number is internally multiplied with the number of banks, with same-bank refresh the number is internally multiplied with the number of banks per bank group)
+- *PowerDownPolicy* (string)
+  - "NoPowerDown": power down disabled
+  - "Staggered": staggered power down policy [5]
+- *Arbiter* (string)
+  - "Simple": simple forwarding of transactions to the right channel or initiator
+  - "Fifo": transactions can be buffered internally to achieve a higher throughput especially in multi-initiator-multi-channel configurations
+  - "Reorder": based on "Fifo", in addition, the original request order is restored for outgoing responses (separately for each initiator and globally to all channels)
+- *MaxActiveTransactions* (unsigned int)
+  - maximum number of active transactions per initiator (only applies to "Fifo" and "Reorder" arbiter policy)
 
 ## DRAMSys with Thermal Simulation