Intensive refactor of DRAMSys project structure and CMakeFiles
This commit is contained in:
Thomas Psota
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src/gem5/main.cpp
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239
src/gem5/main.cpp
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/*
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* Copyright (c) 2015, Technische Universität Kaiserslautern
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* Copyright (c) 2016, Dresden University of Technology (TU Dresden)
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
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* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Matthias Jung
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* Christian Menard
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* Abdul Mutaal Ahmad
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*/
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#include <iostream>
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#include <string>
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#include <cstdlib>
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#include <systemc>
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#include <tlm>
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#include <tlm_utils/simple_initiator_socket.h>
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#include <tlm_utils/simple_target_socket.h>
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#include "report_handler.hh"
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#include "sc_target.hh"
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#include "sim_control.hh"
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#include "slave_transactor.hh"
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#include "stats.hh"
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#include "Configuration.h"
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#include "simulation/DRAMSys.h"
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#ifdef RECORDING
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#include "simulation/DRAMSysRecordable.h"
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#endif
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using namespace sc_core;
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using namespace tlm;
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class Gem5SimControlDRAMsys : public Gem5SystemC::Gem5SimControl
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{
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public:
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Gem5SimControlDRAMsys(std::string configFile) :
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Gem5SystemC::Gem5SimControl("gem5", configFile, 0, "MemoryAccess")
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{}
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virtual void afterSimulate() override
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{
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sc_stop();
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}
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};
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class AddressOffset : sc_module
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{
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private:
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unsigned long long int offset;
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public:
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tlm_utils::simple_target_socket<AddressOffset> t_socket;
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tlm_utils::simple_initiator_socket<AddressOffset> i_socket;
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AddressOffset(sc_module_name, unsigned long long int o) : offset(o),
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t_socket("t_socket"), i_socket("i_socket")
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{
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t_socket.register_nb_transport_fw(this, &AddressOffset::nb_transport_fw);
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t_socket.register_transport_dbg(this, &AddressOffset::transport_dbg);
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t_socket.register_b_transport(this, &AddressOffset::b_transport);
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i_socket.register_nb_transport_bw(this, &AddressOffset::nb_transport_bw);
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}
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//Forward Interface
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tlm_sync_enum nb_transport_fw(tlm_generic_payload &trans, tlm_phase &phase,
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sc_time &delay)
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{
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//std::cout << "NB "<< this->name() <<": " << trans.get_address() << " -" << offset;
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trans.set_address(trans.get_address() - offset);
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//std::cout << " = " << trans.get_address() << std::endl;
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return i_socket->nb_transport_fw(trans, phase, delay);
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}
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unsigned int transport_dbg(tlm_generic_payload &trans)
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{
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// adjust address offset:
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//std::cout << "Debug "<< this->name() <<": " << trans.get_address() << " -" << offset;
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trans.set_address(trans.get_address() - offset);
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//std::cout << " = " << trans.get_address() << std::endl;
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return i_socket->transport_dbg(trans);
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}
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void b_transport(tlm_generic_payload &trans, sc_time &delay)
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{
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// adjust address offset:
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//std::cout << "B "<< this->name() <<": " << trans.get_address() << " -" << offset;
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trans.set_address(trans.get_address() - offset);
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//std::cout << " = " << trans.get_address() << std::endl;
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i_socket->b_transport(trans, delay);
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}
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//Backward Interface
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tlm_sync_enum nb_transport_bw(tlm_generic_payload &trans, tlm_phase &phase,
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sc_time &delay)
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{
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//trans.set_address(trans.get_address()+offset);
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return t_socket->nb_transport_bw(trans, phase, delay);
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}
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};
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std::string pathOfFile(std::string file)
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{
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return file.substr(0, file.find_last_of('/'));
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}
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int sc_main(int argc, char **argv)
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{
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SC_REPORT_INFO("sc_main", "Simulation Setup");
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std::string simulationJson;
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std::string gem5ConfigFile;
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std::string resources;
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unsigned int numTransactors;
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std::vector<std::unique_ptr<Gem5SystemC::Gem5SlaveTransactor>> transactors;
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if (argc == 4)
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{
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// Get path of resources:
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resources = pathOfFile(argv[0])
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+ std::string("/../../DRAMSys/library/resources/");
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simulationJson = argv[1];
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gem5ConfigFile = argv[2];
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numTransactors = static_cast<unsigned>(std::stoul(argv[3]));
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}
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else
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{
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SC_REPORT_FATAL("sc_main", "Please provide configuration files and number of ports");
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return EXIT_FAILURE;
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}
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DRAMSysConfiguration::Configuration configLib = DRAMSysConfiguration::from_path(simulationJson, resources);
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// Instantiate DRAMSys:
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std::unique_ptr<DRAMSys> dramSys;
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#ifdef RECORDING
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if (configLib.simConfig.databaseRecording.value_or(false))
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dramSys = std::make_unique<DRAMSysRecordable>("DRAMSys", configLib);
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else
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#endif
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dramSys = std::make_unique<DRAMSys>("DRAMSys", configLib);
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// Instantiate gem5:
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Gem5SimControlDRAMsys sim_control(gem5ConfigFile);
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// XXX: this code assumes:
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// - for a single port the port name is "transactor"
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// - for multiple ports names are transactor1, transactor2, ..., transactorN
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// Names generated here must match port names used by the gem5 config file, e.g., config.ini
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if (numTransactors == 1)
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{
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transactors.emplace_back(std::make_unique<Gem5SystemC::Gem5SlaveTransactor>("transactor", "transactor"));
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transactors.back().get()->socket.bind(dramSys->tSocket);
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transactors.back().get()->sim_control.bind(sim_control);
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}
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else
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{
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for (unsigned i = 0; i < numTransactors; i++)
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{
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// If there are two or more ports
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unsigned index = i + 1;
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std::string name = "transactor" + std::to_string(index);
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std::string portName = "transactor" + std::to_string(index);
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transactors.emplace_back(std::make_unique<Gem5SystemC::Gem5SlaveTransactor>(name.c_str(), portName.c_str()));
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transactors.back().get()->socket.bind(dramSys->tSocket);
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transactors.back().get()->sim_control.bind(sim_control);
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}
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}
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#ifdef CHOICE3
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// If for example two gem5 ports are used (NVM and DRAM) with
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// crazy address offsets:
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Gem5SystemC::Gem5SlaveTransactor dramInterface("transactor1", "transactor1");
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Gem5SystemC::Gem5SlaveTransactor nvmInterface("transactor2", "transactor2");
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AddressOffset nvmOffset("nvmOffset", 0);
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AddressOffset dramOffset("dramOffset", (2147483648 - 67108863)); //+67108863);
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dramInterface.socket.bind(dramOffset.t_socket);
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dramOffset.i_socket.bind(dramSys->tSocket); // ID0
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nvmInterface.socket.bind(nvmOffset.t_socket);
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nvmOffset.i_socket.bind(dramSys->tSocket);
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dramInterface.sim_control.bind(sim_control);
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nvmInterface.sim_control.bind(sim_control);
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#endif
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SC_REPORT_INFO("sc_main", "Start of Simulation");
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sc_core::sc_set_stop_mode(SC_STOP_FINISH_DELTA);
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sc_core::sc_start();
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if (!sc_core::sc_end_of_simulation_invoked())
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{
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SC_REPORT_INFO("sc_main", "Simulation stopped without explicit sc_stop()");
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sc_core::sc_stop();
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}
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//for (auto t : transactors)
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// delete t;
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SC_REPORT_INFO("sc_main", "End of Simulation");
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return EXIT_SUCCESS;
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}
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