From b272baa6f92d858166610e33d396d770fb3dc2eb Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Tue, 15 Feb 2022 15:04:20 +0100 Subject: [PATCH] Add length converter, add burst length checks. --- DRAMSys/library/src/common/dramExtensions.h | 10 +++++----- DRAMSys/library/src/common/utils.cpp | 4 ++-- .../src/configuration/memspec/MemSpec.cpp | 9 ++++++--- .../src/configuration/memspec/MemSpec.h | 6 ++++-- .../src/controller/checker/CheckerDDR3.cpp | 2 +- .../src/controller/checker/CheckerDDR4.cpp | 2 +- .../src/controller/checker/CheckerDDR5.cpp | 2 ++ .../src/controller/checker/CheckerGDDR5.cpp | 2 +- .../src/controller/checker/CheckerGDDR5X.cpp | 2 +- .../src/controller/checker/CheckerGDDR6.cpp | 2 +- .../src/controller/checker/CheckerHBM2.cpp | 2 +- .../src/controller/checker/CheckerLPDDR4.cpp | 4 +++- .../src/controller/checker/CheckerLPDDR5.cpp | 2 ++ .../src/controller/checker/CheckerSTTMRAM.cpp | 2 +- .../src/controller/checker/CheckerWideIO.cpp | 4 +++- .../src/controller/checker/CheckerWideIO2.cpp | 4 +++- DRAMSys/library/src/error/errormodel.cpp | 2 +- DRAMSys/library/src/simulation/dram/Dram.h | 1 - .../library/src/simulation/dram/DramDDR3.cpp | 2 +- .../library/src/simulation/dram/DramDDR4.cpp | 2 +- .../src/simulation/dram/DramWideIO.cpp | 10 +++++----- DRAMSys/simulator/CMakeLists.txt | 1 + .../LengthConverter.cpp | 0 .../LengthConverter.h | 0 DRAMSys/simulator/MemoryManager.cpp | 2 +- DRAMSys/simulator/StlPlayer.cpp | 6 ++---- DRAMSys/simulator/StlPlayer.h | 1 + DRAMSys/simulator/TraceSetup.cpp | 14 +++++++++---- DRAMSys/simulator/TrafficGenerator.cpp | 20 +++++++++---------- DRAMSys/simulator/TrafficGenerator.h | 3 +++ DRAMSys/simulator/TrafficInitiator.cpp | 16 +++++++-------- DRAMSys/simulator/TrafficInitiator.h | 8 ++++---- DRAMSys/simulator/main.cpp | 20 +++++++++++++++++-- 33 files changed, 103 insertions(+), 64 deletions(-) rename DRAMSys/{library/src/simulation => simulator}/LengthConverter.cpp (100%) rename DRAMSys/{library/src/simulation => simulator}/LengthConverter.h (100%) diff --git a/DRAMSys/library/src/common/dramExtensions.h b/DRAMSys/library/src/common/dramExtensions.h index f4a4a040..929495de 100644 --- a/DRAMSys/library/src/common/dramExtensions.h +++ b/DRAMSys/library/src/common/dramExtensions.h @@ -159,11 +159,6 @@ class DramExtension : public tlm::tlm_extension { public: DramExtension(); - DramExtension(Thread thread, Channel channel, Rank rank, - BankGroup bankGroup, Bank bank, Row row, - Column column, unsigned int burstLength, - uint64_t threadPayloadID, uint64_t channelPayloadID); - tlm::tlm_extension_base *clone() const override; void copy_from(const tlm::tlm_extension_base &ext) override; @@ -222,6 +217,11 @@ public: void incrementRow(); private: + DramExtension(Thread thread, Channel channel, Rank rank, + BankGroup bankGroup, Bank bank, Row row, + Column column, unsigned int burstLength, + uint64_t threadPayloadID, uint64_t channelPayloadID); + Thread thread; Channel channel; Rank rank; diff --git a/DRAMSys/library/src/common/utils.cpp b/DRAMSys/library/src/common/utils.cpp index 8427a84a..4dee2c5f 100644 --- a/DRAMSys/library/src/common/utils.cpp +++ b/DRAMSys/library/src/common/utils.cpp @@ -163,7 +163,7 @@ void setUpDummy(tlm_generic_payload &payload, uint64_t channelPayloadID, Rank ra payload.set_dmi_allowed(false); payload.set_byte_enable_length(0); payload.set_streaming_width(0); - payload.set_extension(new DramExtension(Thread(UINT_MAX), Channel(0), rank, bankGroup, - bank, Row(0), Column(0), 0, 0, channelPayloadID)); + DramExtension::setExtension(payload, Thread(UINT_MAX), Channel(0), rank, bankGroup, bank, Row(0), Column(0), + 0, 0, channelPayloadID); payload.set_extension(new GenerationExtension(SC_ZERO_TIME)); } diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp index ee7b511b..65714153 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp @@ -55,16 +55,19 @@ MemSpec::MemSpec(json &memspec, MemoryType memoryType, numberOfDevices(numberOfDevices), numberOfRows(parseUint(memspec["memarchitecturespec"], "nbrOfRows")), numberOfColumns(parseUint(memspec["memarchitecturespec"], "nbrOfColumns")), - burstLength(parseUint(memspec["memarchitecturespec"], "burstLength")), + defaultBurstLength(parseUint(memspec["memarchitecturespec"], "burstLength")), + maxBurstLength(memspec["memarchitecturespec"]["maxBurstLength"].is_number_unsigned() ? + static_cast(memspec["memarchitecturespec"]["maxBurstLength"]) : defaultBurstLength), dataRate(parseUint(memspec["memarchitecturespec"], "dataRate")), bitWidth(parseUint(memspec["memarchitecturespec"], "width")), dataBusWidth(bitWidth * numberOfDevices), - bytesPerBurst((burstLength * dataBusWidth) / 8), + defaultBytesPerBurst((defaultBurstLength * dataBusWidth) / 8), + maxBytesPerBurst((maxBurstLength * dataBusWidth) / 8), fCKMHz(parseUdouble(memspec["memtimingspec"], "clkMhz")), tCK(sc_time(1.0 / fCKMHz, SC_US)), memoryId(parseString(memspec, "memoryId")), memoryType(memoryType), - burstDuration(tCK * (static_cast(burstLength) / dataRate)), + burstDuration(tCK * (static_cast(defaultBurstLength) / dataRate)), memorySizeBytes(0) { commandLengthInCycles = std::vector(Command::numberOfCommands(), 1); diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.h b/DRAMSys/library/src/configuration/memspec/MemSpec.h index 7448a9e7..e1ada5a4 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.h @@ -60,11 +60,13 @@ public: const unsigned numberOfDevices; const unsigned numberOfRows; const unsigned numberOfColumns; - const unsigned burstLength; + const unsigned defaultBurstLength; + const unsigned maxBurstLength; const unsigned dataRate; const unsigned bitWidth; const unsigned dataBusWidth; - const unsigned bytesPerBurst; + const unsigned defaultBytesPerBurst; + const unsigned maxBytesPerBurst; // Clock const double fCKMHz; diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp index f4bc9bfe..e8c51245 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp @@ -54,7 +54,7 @@ CheckerDDR3::CheckerDDR3() lastCommandOnBus = sc_max_time(); last4Activates = std::vector>(memSpec->numberOfRanks); - tBURST = memSpec->burstLength / memSpec->dataRate * memSpec->tCK; + tBURST = memSpec->defaultBurstLength / memSpec->dataRate * memSpec->tCK; tRDWR = memSpec->tRL + tBURST + 2 * memSpec->tCK - memSpec->tWL; tRDWR_R = memSpec->tRL + tBURST + memSpec->tRTRS - memSpec->tWL; tWRRD = memSpec->tWL + tBURST + memSpec->tWTR - memSpec->tAL; diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp index ba0ad9a0..7ac477d3 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp @@ -56,7 +56,7 @@ CheckerDDR4::CheckerDDR4() lastCommandOnBus = sc_max_time(); last4Activates = std::vector>(memSpec->numberOfRanks); - tBURST = memSpec->burstLength / memSpec->dataRate * memSpec->tCK; + tBURST = memSpec->defaultBurstLength / memSpec->dataRate * memSpec->tCK; tRDWR = memSpec->tRL + tBURST + memSpec->tCK - memSpec->tWL + memSpec->tWPRE; tRDWR_R = memSpec->tRL + tBURST + memSpec->tRTRS - memSpec->tWL + memSpec->tWPRE; tWRRD_S = memSpec->tWL + tBURST + memSpec->tWTR_S - memSpec->tAL; diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR5.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR5.cpp index 95dcdf4c..59e55c49 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR5.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR5.cpp @@ -133,6 +133,7 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, tlm_generic_paylo unsigned burstLength = DramExtension::getBurstLength(payload); assert((burstLength == 16) || (burstLength == 32)); assert(!(burstLength == 32) || (memSpec->bitWidth == 4)); + assert(burstLength <= memSpec->maxBurstLength); lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != sc_max_time()) @@ -319,6 +320,7 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, tlm_generic_paylo unsigned burstLength = DramExtension::getBurstLength(payload); assert((burstLength == 16) || (burstLength == 32)); assert(!(burstLength == 32) || (memSpec->bitWidth == 4)); + assert(burstLength <= memSpec->maxBurstLength); lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != sc_max_time()) diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp b/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp index 008ede01..2f59f86e 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp @@ -59,7 +59,7 @@ CheckerGDDR5::CheckerGDDR5() bankwiseRefreshCounter = std::vector(memSpec->numberOfRanks); - tBURST = memSpec->burstLength / memSpec->dataRate * memSpec->tCK; + tBURST = memSpec->defaultBurstLength / memSpec->dataRate * memSpec->tCK; tRDSRE = memSpec->tCL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK + memSpec->tWCK2DQO + tBURST; tWRSRE = memSpec->tWL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK + memSpec->tWCK2DQI + tBURST; tRDWR_R = memSpec->tCL + tBURST + memSpec->tRTRS - memSpec->tWL; diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp b/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp index 9730d000..5cbfdc6a 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp @@ -59,7 +59,7 @@ CheckerGDDR5X::CheckerGDDR5X() bankwiseRefreshCounter = std::vector(memSpec->numberOfRanks); - tBURST = memSpec->burstLength / memSpec->dataRate * memSpec->tCK; + tBURST = memSpec->defaultBurstLength / memSpec->dataRate * memSpec->tCK; tRDSRE = memSpec->tRL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK + memSpec->tWCK2DQO + tBURST; tWRSRE = memSpec->tWL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK + memSpec->tWCK2DQI + tBURST; tRDWR_R = memSpec->tRL + tBURST + memSpec->tRTRS - memSpec->tWL; diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp b/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp index c098e7e8..57cf9e9c 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp @@ -58,7 +58,7 @@ CheckerGDDR6::CheckerGDDR6() bankwiseRefreshCounter = std::vector(memSpec->numberOfRanks); - tBURST = memSpec->burstLength / memSpec->dataRate * memSpec->tCK; + tBURST = memSpec->defaultBurstLength / memSpec->dataRate * memSpec->tCK; tRDSRE = memSpec->tRL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK + memSpec->tWCK2DQO + tBURST; tWRSRE = memSpec->tWL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK + memSpec->tWCK2DQI + tBURST; tRDWR_R = memSpec->tRL + tBURST + memSpec->tRTRS - memSpec->tWL; diff --git a/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp b/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp index ee22bbd0..dcdbb381 100644 --- a/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp @@ -59,7 +59,7 @@ CheckerHBM2::CheckerHBM2() bankwiseRefreshCounter = std::vector(memSpec->numberOfRanks); - tBURST = memSpec->burstLength / memSpec->dataRate * memSpec->tCK; + tBURST = memSpec->defaultBurstLength / memSpec->dataRate * memSpec->tCK; tRDPDE = memSpec->tRL + memSpec->tPL + tBURST + memSpec->tCK; tRDSRE = tRDPDE; tWRPRE = memSpec->tWL + tBURST + memSpec->tWR; diff --git a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp index 74b55670..1390bc05 100644 --- a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp @@ -54,7 +54,7 @@ CheckerLPDDR4::CheckerLPDDR4() lastCommandOnBus = sc_max_time(); last4Activates = std::vector>(memSpec->numberOfRanks); - tBURST = memSpec->burstLength / memSpec->dataRate * memSpec->tCK; + tBURST = memSpec->defaultBurstLength / memSpec->dataRate * memSpec->tCK; tRDWR = memSpec->tRL + memSpec->tDQSCK + tBURST - memSpec->tWL + memSpec->tWPRE + memSpec->tRPST; tRDWR_R = memSpec->tRL + tBURST + memSpec->tRTRS - memSpec->tWL; tWRRD = memSpec->tWL + memSpec->tCK + tBURST + memSpec->tWTR; @@ -83,6 +83,7 @@ sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, tlm_generic_pay { unsigned burstLength = DramExtension::getBurstLength(payload); assert((burstLength == 16) || (burstLength == 32)); // TODO: BL16/32 OTF + assert(burstLength <= memSpec->maxBurstLength); lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != sc_max_time()) @@ -135,6 +136,7 @@ sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, tlm_generic_pay { unsigned burstLength = DramExtension::getBurstLength(payload); assert((burstLength == 16) || (burstLength == 32)); + assert(burstLength <= memSpec->maxBurstLength); lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != sc_max_time()) diff --git a/DRAMSys/library/src/controller/checker/CheckerLPDDR5.cpp b/DRAMSys/library/src/controller/checker/CheckerLPDDR5.cpp index 8198ad2d..194e44cc 100644 --- a/DRAMSys/library/src/controller/checker/CheckerLPDDR5.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerLPDDR5.cpp @@ -85,6 +85,7 @@ sc_time CheckerLPDDR5::timeToSatisfyConstraints(Command command, tlm_generic_pay unsigned burstLength = DramExtension::getBurstLength(payload); assert(!(memSpec->bitWidth == 8) || (burstLength == 32)); // x8 device -> BL32 assert(!(memSpec->groupsPerRank > 1) || (burstLength == 16)); // BG mode -> BL16 (TODO: BL32) + assert(burstLength <= memSpec->maxBurstLength); lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != sc_max_time()) @@ -196,6 +197,7 @@ sc_time CheckerLPDDR5::timeToSatisfyConstraints(Command command, tlm_generic_pay unsigned burstLength = DramExtension::getBurstLength(payload); assert(!(memSpec->bitWidth == 8) || (burstLength == 32)); // x8 device -> BL32 assert(!(memSpec->groupsPerRank > 1) || (burstLength == 16)); // BG mode -> BL16 (TODO: BL32) + assert(burstLength <= memSpec->maxBurstLength); lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != sc_max_time()) diff --git a/DRAMSys/library/src/controller/checker/CheckerSTTMRAM.cpp b/DRAMSys/library/src/controller/checker/CheckerSTTMRAM.cpp index 8099d77f..070b0b42 100644 --- a/DRAMSys/library/src/controller/checker/CheckerSTTMRAM.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerSTTMRAM.cpp @@ -54,7 +54,7 @@ CheckerSTTMRAM::CheckerSTTMRAM() lastCommandOnBus = sc_max_time(); last4Activates = std::vector>(memSpec->numberOfRanks); - tBURST = memSpec->burstLength / memSpec->dataRate * memSpec->tCK; + tBURST = memSpec->defaultBurstLength / memSpec->dataRate * memSpec->tCK; tRDWR = memSpec->tRL + tBURST + 2 * memSpec->tCK - memSpec->tWL; tRDWR_R = memSpec->tRL + tBURST + memSpec->tRTRS - memSpec->tWL; tWRRD = memSpec->tWL + tBURST + memSpec->tWTR - memSpec->tAL; diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp b/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp index 4fff40d5..1e441f5c 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp @@ -54,7 +54,7 @@ CheckerWideIO::CheckerWideIO() lastCommandOnBus = sc_max_time(); last2Activates = std::vector>(memSpec->numberOfRanks); - tBURST = memSpec->burstLength * memSpec->tCK; + tBURST = memSpec->defaultBurstLength * memSpec->tCK; tRDWR = memSpec->tRL + tBURST + memSpec->tCK; tRDWR_R = memSpec->tRL + tBURST + memSpec->tRTRS - memSpec->tWL; tWRPRE = memSpec->tWL + tBURST - memSpec->tCK + memSpec->tWR; @@ -77,6 +77,7 @@ sc_time CheckerWideIO::timeToSatisfyConstraints(Command command, tlm_generic_pay { unsigned burstLength = DramExtension::getBurstLength(payload); assert((burstLength == 2) || (burstLength == 4)); + assert(burstLength <= memSpec->maxBurstLength); lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != sc_max_time()) @@ -129,6 +130,7 @@ sc_time CheckerWideIO::timeToSatisfyConstraints(Command command, tlm_generic_pay { unsigned burstLength = DramExtension::getBurstLength(payload); assert((burstLength == 2) || (burstLength == 4)); + assert(burstLength <= memSpec->maxBurstLength); lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != sc_max_time()) diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp b/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp index 8617b834..182916db 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp @@ -54,7 +54,7 @@ CheckerWideIO2::CheckerWideIO2() lastCommandOnBus = sc_max_time(); last4Activates = std::vector>(memSpec->numberOfRanks); - tBURST = memSpec->burstLength / memSpec->dataRate * memSpec->tCK; + tBURST = memSpec->defaultBurstLength / memSpec->dataRate * memSpec->tCK; tRDPRE = tBURST + std::max(2 * memSpec->tCK, memSpec->tRTP) - 2 * memSpec->tCK; tRDPDEN = memSpec->tRL + memSpec->tDQSCK + tBURST + memSpec->tCK; tRDWR = memSpec->tRL + memSpec->tDQSCK + tBURST + memSpec->tCK - memSpec->tWL; @@ -78,6 +78,7 @@ sc_time CheckerWideIO2::timeToSatisfyConstraints(Command command, tlm_generic_pa { unsigned burstLength = DramExtension::getBurstLength(payload); assert((burstLength == 4) || (burstLength == 8)); // TODO: BL4/8 OTF + assert(burstLength <= memSpec->maxBurstLength); lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != sc_max_time()) @@ -130,6 +131,7 @@ sc_time CheckerWideIO2::timeToSatisfyConstraints(Command command, tlm_generic_pa { unsigned burstLength = DramExtension::getBurstLength(payload); assert((burstLength == 4) || (burstLength == 8)); + assert(burstLength <= memSpec->maxBurstLength); lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != sc_max_time()) diff --git a/DRAMSys/library/src/error/errormodel.cpp b/DRAMSys/library/src/error/errormodel.cpp index 51e72a2b..46537bc1 100644 --- a/DRAMSys/library/src/error/errormodel.cpp +++ b/DRAMSys/library/src/error/errormodel.cpp @@ -53,7 +53,7 @@ void errorModel::init() powerAnalysis = Configuration::getInstance().powerAnalysis; thermalSim = Configuration::getInstance().thermalSimulation; // Get Configuration parameters: - burstLenght = Configuration::getInstance().memSpec->burstLength; + burstLenght = Configuration::getInstance().memSpec->defaultBurstLength; numberOfColumns = Configuration::getInstance().memSpec->numberOfColumns; bytesPerColumn = std::log2(Configuration::getInstance().memSpec->dataBusWidth); diff --git a/DRAMSys/library/src/simulation/dram/Dram.h b/DRAMSys/library/src/simulation/dram/Dram.h index 965f70a4..da7a0ede 100644 --- a/DRAMSys/library/src/simulation/dram/Dram.h +++ b/DRAMSys/library/src/simulation/dram/Dram.h @@ -50,7 +50,6 @@ class Dram : public sc_core::sc_module { private: - unsigned int bytesPerBurst = Configuration::getInstance().memSpec->bytesPerBurst; bool powerReported = false; protected: diff --git a/DRAMSys/library/src/simulation/dram/DramDDR3.cpp b/DRAMSys/library/src/simulation/dram/DramDDR3.cpp index 4b1cf98d..347fd817 100644 --- a/DRAMSys/library/src/simulation/dram/DramDDR3.cpp +++ b/DRAMSys/library/src/simulation/dram/DramDDR3.cpp @@ -53,7 +53,7 @@ DramDDR3::DramDDR3(const sc_module_name &name) : Dram(name) SC_REPORT_FATAL("DramDDR3", "Wrong MemSpec chosen"); MemArchitectureSpec memArchSpec; - memArchSpec.burstLength = memSpec->burstLength; + memArchSpec.burstLength = memSpec->defaultBurstLength; memArchSpec.dataRate = memSpec->dataRate; memArchSpec.nbrOfRows = memSpec->numberOfRows; memArchSpec.nbrOfBanks = memSpec->numberOfBanks; diff --git a/DRAMSys/library/src/simulation/dram/DramDDR4.cpp b/DRAMSys/library/src/simulation/dram/DramDDR4.cpp index 58b0970e..cbd5454f 100644 --- a/DRAMSys/library/src/simulation/dram/DramDDR4.cpp +++ b/DRAMSys/library/src/simulation/dram/DramDDR4.cpp @@ -53,7 +53,7 @@ DramDDR4::DramDDR4(const sc_module_name &name) : Dram(name) SC_REPORT_FATAL("DramDDR4", "Wrong MemSpec chosen"); MemArchitectureSpec memArchSpec; - memArchSpec.burstLength = memSpec->burstLength; + memArchSpec.burstLength = memSpec->defaultBurstLength; memArchSpec.dataRate = memSpec->dataRate; memArchSpec.nbrOfRows = memSpec->numberOfRows; memArchSpec.nbrOfBanks = memSpec->numberOfBanks; diff --git a/DRAMSys/library/src/simulation/dram/DramWideIO.cpp b/DRAMSys/library/src/simulation/dram/DramWideIO.cpp index 663f063d..dacd5ace 100644 --- a/DRAMSys/library/src/simulation/dram/DramWideIO.cpp +++ b/DRAMSys/library/src/simulation/dram/DramWideIO.cpp @@ -54,7 +54,7 @@ DramWideIO::DramWideIO(const sc_module_name &name) : Dram(name) SC_REPORT_FATAL("DramWideIO", "Wrong MemSpec chosen"); MemArchitectureSpec memArchSpec; - memArchSpec.burstLength = memSpec->burstLength; + memArchSpec.burstLength = memSpec->defaultBurstLength; memArchSpec.dataRate = memSpec->dataRate; memArchSpec.nbrOfRows = memSpec->numberOfRows; memArchSpec.nbrOfBanks = memSpec->numberOfBanks; @@ -74,9 +74,9 @@ DramWideIO::DramWideIO(const sc_module_name &name) : Dram(name) //FIXME: memTimingSpec.RRDB_L = memSpec->tRRD / memSpec->tCK; //FIXME: memTimingSpec.RRDB_S = memSpec->tRRD / memSpec->tCK; memTimingSpec.AL = 0; - memTimingSpec.CCD = memSpec->burstLength; - memTimingSpec.CCD_L = memSpec->burstLength; - memTimingSpec.CCD_S = memSpec->burstLength; + memTimingSpec.CCD = memSpec->defaultBurstLength; + memTimingSpec.CCD_L = memSpec->defaultBurstLength; + memTimingSpec.CCD_S = memSpec->defaultBurstLength; memTimingSpec.CKE = memSpec->tCKE / memSpec->tCK; memTimingSpec.CKESR = memSpec->tCKESR / memSpec->tCK; memTimingSpec.clkMhz = memSpec->fCKMHz; @@ -94,7 +94,7 @@ DramWideIO::DramWideIO(const sc_module_name &name) : Dram(name) memTimingSpec.RRD = memSpec->tRRD / memSpec->tCK; memTimingSpec.RRD_L = memSpec->tRRD / memSpec->tCK; memTimingSpec.RRD_S = memSpec->tRRD / memSpec->tCK; - memTimingSpec.RTP = memSpec->burstLength; + memTimingSpec.RTP = memSpec->defaultBurstLength; memTimingSpec.TAW = memSpec->tTAW / memSpec->tCK; memTimingSpec.WL = memSpec->tWL / memSpec->tCK; memTimingSpec.WR = memSpec->tWR / memSpec->tCK; diff --git a/DRAMSys/simulator/CMakeLists.txt b/DRAMSys/simulator/CMakeLists.txt index a938367c..43b59dd2 100644 --- a/DRAMSys/simulator/CMakeLists.txt +++ b/DRAMSys/simulator/CMakeLists.txt @@ -52,6 +52,7 @@ add_executable(DRAMSys TrafficGenerator.cpp TrafficInitiator.cpp TraceSetup.cpp + LengthConverter.cpp ) if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/../library/src/simulation/DRAMSysRecordable.cpp) diff --git a/DRAMSys/library/src/simulation/LengthConverter.cpp b/DRAMSys/simulator/LengthConverter.cpp similarity index 100% rename from DRAMSys/library/src/simulation/LengthConverter.cpp rename to DRAMSys/simulator/LengthConverter.cpp diff --git a/DRAMSys/library/src/simulation/LengthConverter.h b/DRAMSys/simulator/LengthConverter.h similarity index 100% rename from DRAMSys/library/src/simulation/LengthConverter.h rename to DRAMSys/simulator/LengthConverter.h diff --git a/DRAMSys/simulator/MemoryManager.cpp b/DRAMSys/simulator/MemoryManager.cpp index ad4036a3..eb941d01 100644 --- a/DRAMSys/simulator/MemoryManager.cpp +++ b/DRAMSys/simulator/MemoryManager.cpp @@ -79,7 +79,7 @@ tlm_generic_payload *MemoryManager::allocate() if (storageEnabled) { // Allocate a data buffer and initialize it with zeroes: - unsigned int dataLength = Configuration::getInstance().memSpec->bytesPerBurst; + unsigned int dataLength = Configuration::getInstance().memSpec->maxBytesPerBurst; unsigned char *data = new unsigned char[dataLength]; std::fill(data, data + dataLength, 0); payload->set_data_ptr(data); diff --git a/DRAMSys/simulator/StlPlayer.cpp b/DRAMSys/simulator/StlPlayer.cpp index fb309182..8aa727bf 100644 --- a/DRAMSys/simulator/StlPlayer.cpp +++ b/DRAMSys/simulator/StlPlayer.cpp @@ -48,9 +48,10 @@ StlPlayer::StlPlayer(const sc_module_name &name, const sc_time &playerClk, unsigned int maxPendingReadRequests, unsigned int maxPendingWriteRequests, + bool addLengthConverter, TraceSetup *setup, bool relative) : - TrafficInitiator(name, setup, maxPendingReadRequests, maxPendingWriteRequests), + TrafficInitiator(name, setup, maxPendingReadRequests, maxPendingWriteRequests, addLengthConverter), file(pathToTrace), relative(relative), playerClk(playerClk) { currentBuffer = &lineContents[0]; @@ -73,8 +74,6 @@ StlPlayer::StlPlayer(const sc_module_name &name, SC_REPORT_FATAL("StlPlayer", "Trace file is empty"); } - defaultDataLength = Configuration::getInstance().memSpec->bytesPerBurst; - currentBuffer->reserve(lineBufferSize); parseBuffer->reserve(lineBufferSize); @@ -187,7 +186,6 @@ void StlPlayer::parseTraceFile() } else content.dataLength = defaultDataLength; - std::cout << "Data length: " << content.dataLength << std::endl; if (element == "read") content.command = TLM_READ_COMMAND; diff --git a/DRAMSys/simulator/StlPlayer.h b/DRAMSys/simulator/StlPlayer.h index 8f6af2af..049c2034 100644 --- a/DRAMSys/simulator/StlPlayer.h +++ b/DRAMSys/simulator/StlPlayer.h @@ -69,6 +69,7 @@ public: const sc_core::sc_time &playerClk, unsigned int maxPendingReadRequests, unsigned int maxPendingWriteRequests, + bool addLengthConverter, TraceSetup *setup, bool relative); diff --git a/DRAMSys/simulator/TraceSetup.cpp b/DRAMSys/simulator/TraceSetup.cpp index b76ed6bf..76a78ffe 100644 --- a/DRAMSys/simulator/TraceSetup.cpp +++ b/DRAMSys/simulator/TraceSetup.cpp @@ -83,6 +83,10 @@ TraceSetup::TraceSetup(const std::string &uri, if (value["maxPendingWriteRequests"].is_number_unsigned()) maxPendingWriteRequests = value["maxPendingWriteRequests"]; + bool addLengthConverter = false; + if (value["addLengthConverter"].is_boolean()) + addLengthConverter = value["addLengthConverter"]; + std::string type; // Defaulting to type "player" when not specified @@ -112,10 +116,12 @@ TraceSetup::TraceSetup(const std::string &uri, StlPlayer *player; if (ext == "stl") player = new StlPlayer(moduleName.c_str(), stlFile, playerClk, - maxPendingReadRequests, maxPendingWriteRequests, this, false); + maxPendingReadRequests, maxPendingWriteRequests, + addLengthConverter, this, false); else if (ext == "rstl") player = new StlPlayer(moduleName.c_str(), stlFile, playerClk, - maxPendingReadRequests, maxPendingWriteRequests, this, true); + maxPendingReadRequests, maxPendingWriteRequests, + addLengthConverter, this, true); else throw std::runtime_error("Unsupported file extension in " + name); @@ -188,13 +194,13 @@ TraceSetup::TraceSetup(const std::string &uri, addressIncrement = value["addressIncrement"]; players.push_back(std::unique_ptr(new TrafficGeneratorSequential(name.c_str(), - playerClk, numRequests, maxPendingReadRequests, maxPendingWriteRequests, + playerClk, numRequests, maxPendingReadRequests, maxPendingWriteRequests, addLengthConverter, minAddress, maxAddress, rwRatio, addressIncrement, seed, this))); } else { players.push_back(std::unique_ptr(new TrafficGeneratorRandom(name.c_str(), - playerClk, numRequests, maxPendingReadRequests, maxPendingWriteRequests, + playerClk, numRequests, maxPendingReadRequests, maxPendingWriteRequests, addLengthConverter, minAddress, maxAddress, rwRatio, seed, this))); } diff --git a/DRAMSys/simulator/TrafficGenerator.cpp b/DRAMSys/simulator/TrafficGenerator.cpp index de18bc1a..959ad86d 100644 --- a/DRAMSys/simulator/TrafficGenerator.cpp +++ b/DRAMSys/simulator/TrafficGenerator.cpp @@ -46,16 +46,14 @@ TrafficGenerator::TrafficGenerator(const sc_module_name &name, uint64_t numRequests, unsigned int maxPendingReadRequests, unsigned int maxPendingWriteRequests, + bool addLengthConverter, float rwRatio, unsigned int seed, TraceSetup *setup) : - TrafficInitiator(name, setup, maxPendingReadRequests, maxPendingWriteRequests), - generatorClk(generatorClk), numRequests(numRequests), rwRatio(rwRatio) -{ - defaultDataLength = Configuration::getInstance().memSpec->bytesPerBurst; - - randomGenerator = std::default_random_engine(seed); -} + TrafficInitiator(name, setup, maxPendingReadRequests, maxPendingWriteRequests, addLengthConverter), + generatorClk(generatorClk), numRequests(numRequests), rwRatio(rwRatio), + randomGenerator(std::default_random_engine(seed)) +{} void TrafficGenerator::sendNextPayload() { @@ -109,13 +107,14 @@ TrafficGeneratorRandom::TrafficGeneratorRandom(const sc_core::sc_module_name &na uint64_t numRequests, unsigned int maxPendingReadRequests, unsigned int maxPendingWriteRequests, + bool addLengthConverter, uint64_t minAddress, uint64_t maxAddress, float rwRatio, unsigned int seed, TraceSetup *setup) : TrafficGenerator(name, generatorClk, numRequests, maxPendingReadRequests, maxPendingWriteRequests, - rwRatio, seed, setup) + addLengthConverter, rwRatio, seed, setup) { randomAddressDistribution = std::uniform_int_distribution (minAddress, maxAddress); } @@ -130,6 +129,7 @@ TrafficGeneratorSequential::TrafficGeneratorSequential(const sc_core::sc_module_ uint64_t numRequests, unsigned int maxPendingReadRequests, unsigned int maxPendingWriteRequests, + bool addLengthConverter, uint64_t minAddress, uint64_t maxAddress, float rwRatio, @@ -137,7 +137,7 @@ TrafficGeneratorSequential::TrafficGeneratorSequential(const sc_core::sc_module_ unsigned int seed, TraceSetup *setup) : TrafficGenerator(name, generatorClk, numRequests, maxPendingReadRequests, maxPendingWriteRequests, - rwRatio, seed, setup), + addLengthConverter, rwRatio, seed, setup), minAddress(minAddress), maxAddress(maxAddress), addressIncrement(addressIncrement), currentAddress(minAddress) { @@ -158,7 +158,7 @@ TrafficGeneratorHammer::TrafficGeneratorHammer(const sc_core::sc_module_name &na uint64_t numRequests, uint64_t rowIncrement, TraceSetup *setup) : - TrafficGenerator(name, generatorClk, numRequests, 1, 1, 1.0f, 1, setup), rowIncrement(rowIncrement) + TrafficGenerator(name, generatorClk, numRequests, 1, 1, false, 1.0f, 1, setup), rowIncrement(rowIncrement) { } diff --git a/DRAMSys/simulator/TrafficGenerator.h b/DRAMSys/simulator/TrafficGenerator.h index 394e1d81..ceb254a2 100644 --- a/DRAMSys/simulator/TrafficGenerator.h +++ b/DRAMSys/simulator/TrafficGenerator.h @@ -52,6 +52,7 @@ protected: uint64_t numRequests, unsigned int maxPendingReadRequests, unsigned int maxPendingWriteRequests, + bool addLengthConverter, float rwRatio, unsigned int seed, TraceSetup *setup); @@ -78,6 +79,7 @@ public: uint64_t numRequests, unsigned int maxPendingReadRequests, unsigned int maxPendingWriteRequests, + bool addLengthConverter, uint64_t minAddress, uint64_t maxAddress, float rwRatio, @@ -98,6 +100,7 @@ public: uint64_t numRequests, unsigned int maxPendingReadRequests, unsigned int maxPendingWriteRequests, + bool addLengthConverter, uint64_t minAddress, uint64_t maxAddress, float rwRatio, diff --git a/DRAMSys/simulator/TrafficInitiator.cpp b/DRAMSys/simulator/TrafficInitiator.cpp index 2a7c783e..10a5ff36 100644 --- a/DRAMSys/simulator/TrafficInitiator.cpp +++ b/DRAMSys/simulator/TrafficInitiator.cpp @@ -44,18 +44,18 @@ using namespace sc_core; using namespace tlm; TrafficInitiator::TrafficInitiator(const sc_module_name &name, TraceSetup *setup, - unsigned int maxPendingReadRequests, unsigned int maxPendingWriteRequests) : - sc_module(name), payloadEventQueue(this, &TrafficInitiator::peqCallback), + unsigned int maxPendingReadRequests, unsigned int maxPendingWriteRequests, bool addLengthConverter) : + sc_module(name), + payloadEventQueue(this, &TrafficInitiator::peqCallback), setup(setup), - maxPendingReadRequests(maxPendingReadRequests), maxPendingWriteRequests(maxPendingWriteRequests) + maxPendingReadRequests(maxPendingReadRequests), + maxPendingWriteRequests(maxPendingWriteRequests), + addLengthConverter(addLengthConverter), + defaultDataLength(Configuration::getInstance().memSpec->defaultBytesPerBurst), + storageEnabled(Configuration::getInstance().storeMode != Configuration::StoreMode::NoStorage) { SC_METHOD(sendNextPayload); iSocket.register_nb_transport_bw(this, &TrafficInitiator::nb_transport_bw); - - if (Configuration::getInstance().storeMode == Configuration::StoreMode::NoStorage) - storageEnabled = false; - else - storageEnabled = true; } void TrafficInitiator::terminate() diff --git a/DRAMSys/simulator/TrafficInitiator.h b/DRAMSys/simulator/TrafficInitiator.h index 91ca118d..df1f39d0 100644 --- a/DRAMSys/simulator/TrafficInitiator.h +++ b/DRAMSys/simulator/TrafficInitiator.h @@ -57,14 +57,14 @@ class TrafficInitiator : public sc_core::sc_module public: tlm_utils::simple_initiator_socket iSocket; TrafficInitiator(const sc_core::sc_module_name &name, TraceSetup *setup, - unsigned int maxPendingReadRequests, unsigned int maxPendingWriteRequests); + unsigned int maxPendingReadRequests, unsigned int maxPendingWriteRequests, bool addLengthConverter); SC_HAS_PROCESS(TrafficInitiator); virtual void sendNextPayload() = 0; + const bool addLengthConverter = false; protected: tlm_utils::peq_with_cb_and_phase payloadEventQueue; void terminate(); - bool storageEnabled = false; TraceSetup *setup; void sendToTarget(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase, const sc_core::sc_time &delay); @@ -77,8 +77,8 @@ protected: const unsigned int maxPendingWriteRequests = 0; bool payloadPostponed = false; bool finished = false; - - unsigned int defaultDataLength; + const unsigned int defaultDataLength = 64; + const bool storageEnabled = false; private: tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &payload, tlm::tlm_phase &phase, diff --git a/DRAMSys/simulator/main.cpp b/DRAMSys/simulator/main.cpp index 93539a0c..56a965ed 100644 --- a/DRAMSys/simulator/main.cpp +++ b/DRAMSys/simulator/main.cpp @@ -48,6 +48,7 @@ #include "simulation/DRAMSys.h" #include "TraceSetup.h" #include "TrafficInitiator.h" +#include "LengthConverter.h" #ifdef RECORDING #include "simulation/DRAMSysRecordable.h" @@ -98,6 +99,7 @@ int sc_main(int argc, char **argv) } std::vector> players; + std::vector> lengthConverters; // Instantiate DRAMSys: std::unique_ptr dramSys; @@ -106,7 +108,7 @@ int sc_main(int argc, char **argv) json simulatordoc = parseJSON(resources + "configs/simulator/" + std::string(simulationdoc["simulation"]["simconfig"])); - if (simulatordoc["simconfig"]["DatabaseRecording"]) + if (simulatordoc["simconfig"]["DatabaseRecording"].is_boolean() && simulatordoc["simconfig"]["DatabaseRecording"]) dramSys = std::unique_ptr(new DRAMSysRecordable("DRAMSys", simulationJson, resources)); else #endif @@ -117,7 +119,21 @@ int sc_main(int argc, char **argv) // Bind STL Players with DRAMSys: for (auto& player : players) - player->iSocket.bind(dramSys->tSocket); + { + if (player->addLengthConverter) + { + std::string converterName("Converter_"); + lengthConverters.emplace_back(new LengthConverter(converterName.append(player->name()).c_str(), + Configuration::getInstance().memSpec->maxBytesPerBurst, + Configuration::getInstance().storeMode != Configuration::StoreMode::NoStorage)); + player->iSocket.bind(lengthConverters.back()->tSocket); + lengthConverters.back()->iSocket.bind(dramSys->tSocket); + } + else + { + player->iSocket.bind(dramSys->tSocket); + } + } // Store the starting of the simulation in wallclock time: auto start = std::chrono::high_resolution_clock::now();