From b0d7e4a18bb6af5114e91a9c236c24b71c7797a6 Mon Sep 17 00:00:00 2001
From: Derek Christ <derek.christ@iese.fraunhofer.de>
Date: Mon, 30 Jan 2023 12:57:13 +0100
Subject: [PATCH] Add some cache test cases

---
 src/simulator/simulator/Cache.h             | 37 +++++++++++-----
 tests/tests_simulator/cache/tests_cache.cpp | 49 ++++++++++++++++++---
 2 files changed, 68 insertions(+), 18 deletions(-)

diff --git a/src/simulator/simulator/Cache.h b/src/simulator/simulator/Cache.h
index 0e64bf67..845986c9 100644
--- a/src/simulator/simulator/Cache.h
+++ b/src/simulator/simulator/Cache.h
@@ -68,10 +68,12 @@ public:
 private:
     void peqCallback(tlm::tlm_generic_payload &trans, const tlm::tlm_phase &phase);
 
-    tlm::tlm_sync_enum
-    nb_transport_fw(tlm::tlm_generic_payload &trans, tlm::tlm_phase &phase, sc_core::sc_time &fwDelay);
-    tlm::tlm_sync_enum
-    nb_transport_bw(tlm::tlm_generic_payload &trans, tlm::tlm_phase &phase, sc_core::sc_time &bwDelay);
+    tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &trans,
+                                       tlm::tlm_phase &phase,
+                                       sc_core::sc_time &fwDelay);
+    tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &trans,
+                                       tlm::tlm_phase &phase,
+                                       sc_core::sc_time &bwDelay);
     unsigned int transport_dbg(tlm::tlm_generic_payload &trans);
 
     void fetchLineAndSendEndRequest(tlm::tlm_generic_payload &trans);
@@ -118,9 +120,18 @@ private:
 
     bool isHit(index_t index, tag_t tag) const;
     bool isHit(std::uint64_t address) const;
-    void
-    writeLine(index_t index, tag_t tag, lineOffset_t lineOffset, unsigned int dataLength, const unsigned char *dataPtr);
-    void readLine(index_t index, tag_t tag, lineOffset_t lineOffset, unsigned int dataLength, unsigned char *dataPtr);
+
+    void writeLine(index_t index,
+                   tag_t tag,
+                   lineOffset_t lineOffset,
+                   unsigned int dataLength,
+                   const unsigned char *dataPtr);
+                   
+    void readLine(index_t index,
+                  tag_t tag,
+                  lineOffset_t lineOffset,
+                  unsigned int dataLength,
+                  unsigned char *dataPtr);
 
     CacheLine *evictLine(index_t index);
 
@@ -133,7 +144,10 @@ private:
         tag_t tag;
         tlm::tlm_generic_payload *trans;
 
-        BufferEntry(index_t index, tag_t tag, tlm::tlm_generic_payload *trans) : index(index), tag(tag), trans(trans) {}
+        BufferEntry(index_t index, tag_t tag, tlm::tlm_generic_payload *trans)
+            : index(index), tag(tag), trans(trans)
+        {
+        }
     };
 
     struct Mshr
@@ -155,7 +169,8 @@ private:
         /// delay when it is already being waited on.
         bool hitDelayStarted = false;
 
-        Mshr(index_t index, tag_t tag, tlm::tlm_generic_payload *request) : index(index), tag(tag), requestList{request}
+        Mshr(index_t index, tag_t tag, tlm::tlm_generic_payload *request)
+            : index(index), tag(tag), requestList{request}
         {
         }
     };
@@ -163,8 +178,8 @@ private:
     std::deque<Mshr> mshrQueue;
     std::deque<BufferEntry> hitQueue;
 
-    using writeBuffer_t = std::list<BufferEntry>;
-    writeBuffer_t writeBuffer;
+    using WriteBuffer = std::list<BufferEntry>;
+    WriteBuffer writeBuffer;
 
     uint64_t numberOfHits = 0;
     uint64_t numberOfPrimaryMisses = 0;
diff --git a/tests/tests_simulator/cache/tests_cache.cpp b/tests/tests_simulator/cache/tests_cache.cpp
index c8da5576..44d59737 100644
--- a/tests/tests_simulator/cache/tests_cache.cpp
+++ b/tests/tests_simulator/cache/tests_cache.cpp
@@ -78,16 +78,51 @@ protected:
     Cache cache;
 };
 
-TEST_F(DirectMappedCache, Hello)
+TEST_F(DirectMappedCache, Basic)
 {
+    using sc_core::SC_NS;
+    using sc_core::sc_time;
+    using Command = ListInitiator::TestTransactionData::Command;
+
     std::vector<ListInitiator::TestTransactionData> list{
-        {sc_core::sc_time(1000, sc_core::SC_NS),
-         sc_core::sc_time(1017, sc_core::SC_NS),
-         ListInitiator::TestTransactionData::Command::Read,
-         0x0,
-         4,
-         0x0}};
+        // Test miss
+        {sc_time(0, SC_NS), sc_time(17, SC_NS), Command::Read, 0x0, 4, 0x0},
+
+        // Test secondary miss
+        {sc_time(1, SC_NS), sc_time(18, SC_NS), Command::Read, 0x0, 4, 0x0},
+
+        // Test hit
+        {sc_time(100, SC_NS), sc_time(106, SC_NS), Command::Read, 0x0, 4, 0x0},
+
+        // Test write hit
+        {sc_time(200, SC_NS), sc_time(206, SC_NS), Command::Write, 0x0, 4, 0x8},
+
+        // Test eviction
+        {sc_time(300, SC_NS), sc_time(317, SC_NS), Command::Write, 1024 * 32, 4, 0x0}};
 
     initiator.appendTestTransactionList(list);
     sc_core::sc_start();
 }
+
+// Does not work yet
+// Unclear if a snoop should even happen when the line eviction fails
+// TEST_F(DirectMappedCache, WriteBufferSnooping)
+// {
+//     using sc_core::SC_NS;
+//     using sc_core::sc_time;
+//     using Command = ListInitiator::TestTransactionData::Command;
+
+//     std::vector<ListInitiator::TestTransactionData> list{
+//         // Allocate line
+//         {sc_time(0, SC_NS), sc_time(17, SC_NS), Command::Write, 0x0, 4, 0x0},
+
+//         // Evict line
+//         {sc_time(100, SC_NS), sc_time(117, SC_NS), Command::Read, 1024 * 32, 4, 0x0},
+
+//         // Snoop from write buffer
+//         {sc_time(102, SC_NS), sc_time(108, SC_NS), Command::Read, 0x0, 4, 0x0},
+//     };
+
+//     initiator.appendTestTransactionList(list);
+//     sc_core::sc_start();
+// }