diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp
index 8c049067..7cd28f80 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp
@@ -78,6 +78,11 @@ sc_time MemSpec::getCommandLength(Command command) const
     return tCK * commandLengthInCycles[command];
 }
 
+uint64_t MemSpec::getSimMemSizeInBytes() const
+{
+    return memorySizeBytes;
+}
+
 sc_time MemSpec::getRefreshIntervalAB() const
 {
     SC_REPORT_FATAL("MemSpec", "All bank refresh not supported");
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.h b/DRAMSys/library/src/configuration/memspec/MemSpec.h
index 3e5c0c1f..6596c388 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpec.h
+++ b/DRAMSys/library/src/configuration/memspec/MemSpec.h
@@ -84,7 +84,7 @@ public:
     virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const = 0;
 
     sc_time getCommandLength(Command) const;
-    virtual uint64_t getSimMemSizeInBytes() const = 0; 
+    uint64_t getSimMemSizeInBytes() const;
 
 protected:
     MemSpec(nlohmann::json &memspec, MemoryType memoryType,
@@ -97,6 +97,7 @@ protected:
     // Command lengths in cycles on bus, usually one clock cycle
     std::vector<unsigned> commandLengthInCycles;
     sc_time burstDuration;
+    uint64_t memorySizeBytes;
 };
 
 #endif // MEMSPEC_H
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp
index 5c566b46..e56f62f4 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp
@@ -88,7 +88,26 @@ MemSpecDDR3::MemSpecDDR3(json &memspec)
       iDD2P1   (parseUdouble(memspec["mempowerspec"]["idd2p1"], "idd2p1")),
       iDD3P0   (parseUdouble(memspec["mempowerspec"]["idd3p0"], "idd3p0")),
       iDD3P1   (parseUdouble(memspec["mempowerspec"]["idd3p1"], "idd3p1"))
-{}
+{
+    uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
+    uint64_t deviceSizeBytes = deviceSizeBits / 8;
+    memorySizeBytes = deviceSizeBytes * numberOfDevicesOnDIMM * numberOfRanks * numberOfChannels;
+
+    std::cout << headline << std::endl;
+    std::cout << "Memory Configuration:" << std::endl << std::endl;
+    std::cout << " Memory type:           " << "DDR3"                << std::endl;
+    std::cout << " Memory size in bytes:  " << memorySizeBytes       << std::endl;
+    std::cout << " Channels:              " << numberOfChannels      << std::endl;
+    std::cout << " Ranks per channel:     " << numberOfRanks         << std::endl;
+    std::cout << " Banks per rank:        " << banksPerRank          << std::endl;
+    std::cout << " Rows per bank:         " << numberOfRows          << std::endl;
+    std::cout << " Columns per row:       " << numberOfColumns       << std::endl;
+    std::cout << " Device width in bits:  " << bitWidth              << std::endl;
+    std::cout << " Device size in bits:   " << deviceSizeBits        << std::endl;
+    std::cout << " Device size in bytes:  " << deviceSizeBytes       << std::endl;
+    std::cout << " Devices on DIMM:       " << numberOfDevicesOnDIMM << std::endl;
+    std::cout << std::endl;
+}
 
 sc_time MemSpecDDR3::getRefreshIntervalAB() const
 {
@@ -132,27 +151,3 @@ TimeInterval MemSpecDDR3::getIntervalOnDataStrobe(Command command, const tlm::tl
         return TimeInterval();
     }
 }
-
-uint64_t MemSpecDDR3::getSimMemSizeInBytes() const
-{
-    uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
-    uint64_t deviceSizeBytes = deviceSizeBits / 8;
-    uint64_t memorySizeBytes = deviceSizeBytes * numberOfDevicesOnDIMM * numberOfRanks;
-
-    std::cout << headline << std::endl;
-    std::cout << "Per Channel Configuration:" << std::endl << std::endl;
-    std::cout << " Memory type:           " << "DDR3"                << std::endl;
-    std::cout << " Memory size in bytes:  " << memorySizeBytes       << std::endl;
-    std::cout << " Ranks:                 " << numberOfRanks         << std::endl;
-    std::cout << " Banks per rank:        " << banksPerRank          << std::endl;
-    std::cout << " Rows per bank:         " << numberOfRows          << std::endl;
-    std::cout << " Columns per row:       " << numberOfColumns       << std::endl;
-    std::cout << " Device width in bits:  " << bitWidth              << std::endl;
-    std::cout << " Device size in bits:   " << deviceSizeBits        << std::endl;
-    std::cout << " Device size in bytes:  " << deviceSizeBytes       << std::endl;
-    std::cout << " Devices on DIMM:       " << numberOfDevicesOnDIMM << std::endl;
-    std::cout << std::endl;
-
-    assert(memorySizeBytes > 0);
-    return memorySizeBytes;
-}
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h
index 370273b0..b0910bbd 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h
@@ -91,8 +91,6 @@ public:
 
     virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
     virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
-
-    virtual uint64_t getSimMemSizeInBytes() const override;
 };
 
 #endif // MEMSPECDDR3_H
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp
index 2b6e3bfb..3f705235 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp
@@ -107,7 +107,27 @@ MemSpecDDR4::MemSpecDDR4(json &memspec)
       iDD3P1   (parseUdouble(memspec["mempowerspec"]["idd3p1"], "idd3p1")),
       iDD62    (parseUdouble(memspec["mempowerspec"]["idd62"], "idd62")),
       vDD2     (parseUdouble(memspec["mempowerspec"]["vdd2"], "vdd2"))
-{}
+{
+    uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
+    uint64_t deviceSizeBytes = deviceSizeBits / 8;
+    memorySizeBytes = deviceSizeBytes * numberOfDevicesOnDIMM * numberOfRanks * numberOfChannels;
+
+    std::cout << headline << std::endl;
+    std::cout << "Memory Configuration:" << std::endl << std::endl;
+    std::cout << " Memory type:           " << "DDR4"                << std::endl;
+    std::cout << " Memory size in bytes:  " << memorySizeBytes       << std::endl;
+    std::cout << " Channels:              " << numberOfChannels      << std::endl;
+    std::cout << " Ranks per channel:     " << numberOfRanks         << std::endl;
+    std::cout << " Bank groups per rank:  " << groupsPerRank         << std::endl;
+    std::cout << " Banks per rank:        " << banksPerRank          << std::endl;
+    std::cout << " Rows per bank:         " << numberOfRows          << std::endl;
+    std::cout << " Columns per row:       " << numberOfColumns       << std::endl;
+    std::cout << " Device width in bits:  " << bitWidth              << std::endl;
+    std::cout << " Device size in bits:   " << deviceSizeBits        << std::endl;
+    std::cout << " Device size in bytes:  " << deviceSizeBytes       << std::endl;
+    std::cout << " Devices on DIMM:       " << numberOfDevicesOnDIMM << std::endl;
+    std::cout << std::endl;
+}
 
 sc_time MemSpecDDR4::getRefreshIntervalAB() const
 {
@@ -151,28 +171,3 @@ TimeInterval MemSpecDDR4::getIntervalOnDataStrobe(Command command, const tlm::tl
         return TimeInterval();
     }
 }
-
-uint64_t MemSpecDDR4::getSimMemSizeInBytes() const
-{
-    uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
-    uint64_t deviceSizeBytes = deviceSizeBits / 8;
-    uint64_t memorySizeBytes = deviceSizeBytes * numberOfDevicesOnDIMM * numberOfRanks;
-
-    std::cout << headline << std::endl;
-    std::cout << "Per Channel Configuration:" << std::endl << std::endl;
-    std::cout << " Memory type:           " << "DDR4"                << std::endl;
-    std::cout << " Memory size in bytes:  " << memorySizeBytes       << std::endl;
-    std::cout << " Ranks:                 " << numberOfRanks         << std::endl;
-    std::cout << " Bank groups per rank:  " << groupsPerRank         << std::endl;
-    std::cout << " Banks per rank:        " << banksPerRank          << std::endl;
-    std::cout << " Rows per bank:         " << numberOfRows          << std::endl;
-    std::cout << " Columns per row:       " << numberOfColumns       << std::endl;
-    std::cout << " Device width in bits:  " << bitWidth              << std::endl;
-    std::cout << " Device size in bits:   " << deviceSizeBits        << std::endl;
-    std::cout << " Device size in bytes:  " << deviceSizeBytes       << std::endl;
-    std::cout << " Devices on DIMM:       " << numberOfDevicesOnDIMM << std::endl;
-    std::cout << std::endl;
-
-    assert(memorySizeBytes > 0);
-    return memorySizeBytes;
-}
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h
index e3a5ed9b..5db3b3ea 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h
@@ -99,8 +99,6 @@ public:
 
     virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
     virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
-
-    virtual uint64_t getSimMemSizeInBytes() const override;
 };
 
 #endif // MEMSPECDDR4_H
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp
index 662464d2..990ea9d7 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp
@@ -146,6 +146,31 @@ MemSpecDDR5::MemSpecDDR5(json &memspec)
     if (!(refMode == 1 || refMode == 2))
         SC_REPORT_FATAL("MemSpecDDR5", "Invalid refresh mode! "
                 "Set 1 for normal or 2 for fine granularity refresh mode.");
+
+    uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows
+            * numberOfColumns * bitWidth * numberOfLogicalRanks;
+    uint64_t deviceSizeBytes = deviceSizeBits / 8;
+    memorySizeBytes = deviceSizeBytes * numberOfDevicesOnDIMM
+            * numberOfRanks / numberOfLogicalRanks * numberOfChannels;
+
+    std::cout << headline << std::endl;
+    std::cout << "Memory Configuration: " << std::endl << std::endl;
+    std::cout << " Memory type:              " << "DDR5"                      << std::endl;
+    std::cout << " Memory size in bytes:     " << memorySizeBytes             << std::endl;
+    std::cout << " Channels:                 " << numberOfChannels            << std::endl;
+    std::cout << " DIMMs per channel:        " << numberOfDIMMRanks           << std::endl;
+    std::cout << " Physical ranks per DIMM:  " << physicalRanksPerDIMMRank    << std::endl;
+    std::cout << " Logical ranks per device: " << logicalRanksPerPhysicalRank << std::endl;
+    std::cout << " Total ranks:              " << numberOfRanks               << std::endl;
+    std::cout << " Bank groups per rank:     " << groupsPerRank               << std::endl;
+    std::cout << " Banks per rank:           " << banksPerRank                << std::endl;
+    std::cout << " Rows per bank:            " << numberOfRows                << std::endl;
+    std::cout << " Columns per row:          " << numberOfColumns             << std::endl;
+    std::cout << " Device width in bits:     " << bitWidth                    << std::endl;
+    std::cout << " Device size in bits:      " << deviceSizeBits              << std::endl;
+    std::cout << " Device size in bytes:     " << deviceSizeBytes             << std::endl;
+    std::cout << " Devices on DIMM:          " << numberOfDevicesOnDIMM       << std::endl;
+    std::cout << std::endl;
 }
 
 sc_time MemSpecDDR5::getRefreshIntervalAB() const
@@ -222,31 +247,3 @@ TimeInterval MemSpecDDR5::getIntervalOnDataStrobe(Command command, const tlm_gen
         return TimeInterval();
     }
 }
-
-uint64_t MemSpecDDR5::getSimMemSizeInBytes() const
-{
-    uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
-    uint64_t deviceSizeBytes = deviceSizeBits / 8;
-    uint64_t memorySizeBytes = deviceSizeBytes * numberOfDevicesOnDIMM * numberOfRanks;
-
-    std::cout << headline << std::endl;
-    std::cout << "Per Channel Configuration: " << std::endl << std::endl;
-    std::cout << " Memory type:              " << "DDR5"                      << std::endl;
-    std::cout << " Memory size in bytes:     " << memorySizeBytes             << std::endl;
-    std::cout << " DIMMs:                    " << numberOfDIMMRanks           << std::endl;
-    std::cout << " Physical Ranks per DIMM:  " << physicalRanksPerDIMMRank    << std::endl;
-    std::cout << " Logical Ranks per device: " << logicalRanksPerPhysicalRank << std::endl;
-    std::cout << " Ranks:                    " << numberOfRanks               << std::endl;
-    std::cout << " Bank groups per rank:     " << groupsPerRank               << std::endl;
-    std::cout << " Banks per rank:           " << banksPerRank                << std::endl;
-    std::cout << " Rows per bank:            " << numberOfRows                << std::endl;
-    std::cout << " Columns per row:          " << numberOfColumns             << std::endl;
-    std::cout << " Device width in bits:     " << bitWidth                    << std::endl;
-    std::cout << " Device size in bits:      " << deviceSizeBits              << std::endl;
-    std::cout << " Device size in bytes:     " << deviceSizeBytes             << std::endl;
-    std::cout << " Devices on DIMM:          " << numberOfDevicesOnDIMM       << std::endl;
-    std::cout << std::endl;
-
-    assert(memorySizeBytes > 0);
-    return memorySizeBytes;
-}
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.h
index 40de44f1..95142700 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.h
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.h
@@ -114,8 +114,6 @@ public:
 
     virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
     virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
-
-    virtual uint64_t getSimMemSizeInBytes() const override;
 };
 
 #endif // MEMSPECDDR5_H
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp
index 4ae7bb17..de222b57 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp
@@ -85,7 +85,26 @@ MemSpecGDDR5::MemSpecGDDR5(json &memspec)
       tPPD       (tCK * parseUint(memspec["memtimingspec"]["PPD"], "PPD")),
       tLK        (tCK * parseUint(memspec["memtimingspec"]["LK"], "LK")),
       tRTRS      (tCK * parseUint(memspec["memtimingspec"]["RTRS"], "RTRS"))
-{}
+{
+    uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
+    uint64_t deviceSizeBytes = deviceSizeBits / 8;
+    memorySizeBytes = deviceSizeBytes * numberOfRanks * numberOfChannels;
+
+    std::cout << headline << std::endl;
+    std::cout << "Memory Configuration:" << std::endl << std::endl;
+    std::cout << " Memory type:           " << "GDDR5"               << std::endl;
+    std::cout << " Memory size in bytes:  " << memorySizeBytes       << std::endl;
+    std::cout << " Channels:              " << numberOfChannels      << std::endl;
+    std::cout << " Ranks per channel:     " << numberOfRanks         << std::endl;
+    std::cout << " Bank groups per rank:  " << groupsPerRank         << std::endl;
+    std::cout << " Banks per rank:        " << banksPerRank          << std::endl;
+    std::cout << " Rows per bank:         " << numberOfRows          << std::endl;
+    std::cout << " Columns per row:       " << numberOfColumns       << std::endl;
+    std::cout << " Device width in bits:  " << bitWidth              << std::endl;
+    std::cout << " Device size in bits:   " << deviceSizeBits        << std::endl;
+    std::cout << " Device size in bytes:  " << deviceSizeBytes       << std::endl;
+    std::cout << std::endl;
+}
 
 sc_time MemSpecGDDR5::getRefreshIntervalAB() const
 {
@@ -142,27 +161,3 @@ TimeInterval MemSpecGDDR5::getIntervalOnDataStrobe(Command command, const tlm_ge
         return TimeInterval();
     }
 }
-
-uint64_t MemSpecGDDR5::getSimMemSizeInBytes() const
-{
-    uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
-    uint64_t deviceSizeBytes = deviceSizeBits / 8;
-    uint64_t memorySizeBytes = deviceSizeBytes * numberOfRanks;
-
-    std::cout << headline << std::endl;
-    std::cout << "Per Channel Configuration:" << std::endl << std::endl;
-    std::cout << " Memory type:           " << "GDDR5"               << std::endl;
-    std::cout << " Memory size in bytes:  " << memorySizeBytes       << std::endl;
-    std::cout << " Ranks:                 " << numberOfRanks         << std::endl;
-    std::cout << " Bank groups per rank:  " << groupsPerRank         << std::endl;
-    std::cout << " Banks per rank:        " << banksPerRank          << std::endl;
-    std::cout << " Rows per bank:         " << numberOfRows          << std::endl;
-    std::cout << " Columns per row:       " << numberOfColumns       << std::endl;
-    std::cout << " Device width in bits:  " << bitWidth              << std::endl;
-    std::cout << " Device size in bits:   " << deviceSizeBits        << std::endl;
-    std::cout << " Device size in bytes:  " << deviceSizeBytes       << std::endl;
-    std::cout << std::endl;
-
-    assert(memorySizeBytes > 0);
-    return memorySizeBytes;
-}
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h
index cf584c98..6c607421 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h
@@ -90,8 +90,6 @@ public:
 
     virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
     virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
-
-    virtual uint64_t getSimMemSizeInBytes() const override;
 };
 
 #endif // MEMSPECGDDR5_H
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp
index 1c97fada..6667d00f 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp
@@ -85,7 +85,26 @@ MemSpecGDDR5X::MemSpecGDDR5X(json &memspec)
       tPPD       (tCK * parseUint(memspec["memtimingspec"]["PPD"], "PPD")),
       tLK        (tCK * parseUint(memspec["memtimingspec"]["LK"], "LK")),
       tRTRS      (tCK * parseUint(memspec["memtimingspec"]["RTRS"], "RTRS"))
-{}
+{
+    uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
+    uint64_t deviceSizeBytes = deviceSizeBits / 8;
+    memorySizeBytes = deviceSizeBytes * numberOfRanks * numberOfChannels;
+
+    std::cout << headline << std::endl;
+    std::cout << "Memory Configuration:" << std::endl << std::endl;
+    std::cout << " Memory type:           " << "GDDR5X"              << std::endl;
+    std::cout << " Memory size in bytes:  " << memorySizeBytes       << std::endl;
+    std::cout << " Channels:              " << numberOfChannels      << std::endl;
+    std::cout << " Ranks per channel:     " << numberOfRanks         << std::endl;
+    std::cout << " Bank groups per rank:  " << groupsPerRank         << std::endl;
+    std::cout << " Banks per rank:        " << banksPerRank          << std::endl;
+    std::cout << " Rows per bank:         " << numberOfRows          << std::endl;
+    std::cout << " Columns per row:       " << numberOfColumns       << std::endl;
+    std::cout << " Device width in bits:  " << bitWidth              << std::endl;
+    std::cout << " Device size in bits:   " << deviceSizeBits        << std::endl;
+    std::cout << " Device size in bytes:  " << deviceSizeBytes       << std::endl;
+    std::cout << std::endl;
+}
 
 sc_time MemSpecGDDR5X::getRefreshIntervalAB() const
 {
@@ -142,27 +161,3 @@ TimeInterval MemSpecGDDR5X::getIntervalOnDataStrobe(Command command, const tlm_g
         return TimeInterval();
     }
 }
-
-uint64_t MemSpecGDDR5X::getSimMemSizeInBytes() const
-{
-    uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
-    uint64_t deviceSizeBytes = deviceSizeBits / 8;
-    uint64_t memorySizeBytes = deviceSizeBytes * numberOfRanks;
-
-    std::cout << headline << std::endl;
-    std::cout << "Per Channel Configuration:" << std::endl << std::endl;
-    std::cout << " Memory type:           " << "GDDR5X"              << std::endl;
-    std::cout << " Memory size in bytes:  " << memorySizeBytes       << std::endl;
-    std::cout << " Ranks:                 " << numberOfRanks         << std::endl;
-    std::cout << " Bank groups per rank:  " << groupsPerRank         << std::endl;
-    std::cout << " Banks per rank:        " << banksPerRank          << std::endl;
-    std::cout << " Rows per bank:         " << numberOfRows          << std::endl;
-    std::cout << " Columns per row:       " << numberOfColumns       << std::endl;
-    std::cout << " Device width in bits:  " << bitWidth              << std::endl;
-    std::cout << " Device size in bits:   " << deviceSizeBits        << std::endl;
-    std::cout << " Device size in bytes:  " << deviceSizeBytes       << std::endl;
-    std::cout << std::endl;
-
-    assert(memorySizeBytes > 0);
-    return memorySizeBytes;
-}
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h
index f507232d..da79ad3b 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h
@@ -90,8 +90,6 @@ public:
 
     virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
     virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
-
-    virtual uint64_t getSimMemSizeInBytes() const override;
 };
 
 #endif // MEMSPECGDDR5X_H
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp
index c0dfd854..6107d89b 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp
@@ -87,7 +87,26 @@ MemSpecGDDR6::MemSpecGDDR6(json &memspec)
       tPREPDE    (tCK * parseUint(memspec["memtimingspec"]["PREPDE"], "PREPDE")),
       tREFPDE    (tCK * parseUint(memspec["memtimingspec"]["REFPDE"], "REFPDE")),
       tRTRS      (tCK * parseUint(memspec["memtimingspec"]["RTRS"], "RTRS"))
-{}
+{
+    uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
+    uint64_t deviceSizeBytes = deviceSizeBits / 8;
+    memorySizeBytes = deviceSizeBytes * numberOfRanks * numberOfChannels;
+
+    std::cout << headline << std::endl;
+    std::cout << "Memory Configuration:" << std::endl << std::endl;
+    std::cout << " Memory type:           " << "GDDR6"              << std::endl;
+    std::cout << " Memory size in bytes:  " << memorySizeBytes       << std::endl;
+    std::cout << " Channels:              " << numberOfChannels      << std::endl;
+    std::cout << " Ranks per channel:     " << numberOfRanks         << std::endl;
+    std::cout << " Bank groups per rank:  " << groupsPerRank         << std::endl;
+    std::cout << " Banks per rank:        " << banksPerRank          << std::endl;
+    std::cout << " Rows per bank:         " << numberOfRows          << std::endl;
+    std::cout << " Columns per row:       " << numberOfColumns       << std::endl;
+    std::cout << " Device width in bits:  " << bitWidth              << std::endl;
+    std::cout << " Device size in bits:   " << deviceSizeBits        << std::endl;
+    std::cout << " Device size in bytes:  " << deviceSizeBytes       << std::endl;
+    std::cout << std::endl;
+}
 
 sc_time MemSpecGDDR6::getRefreshIntervalAB() const
 {
@@ -144,27 +163,3 @@ TimeInterval MemSpecGDDR6::getIntervalOnDataStrobe(Command command, const tlm_ge
         return TimeInterval();
     }
 }
-
-uint64_t MemSpecGDDR6::getSimMemSizeInBytes() const
-{
-    uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
-    uint64_t deviceSizeBytes = deviceSizeBits / 8;
-    uint64_t memorySizeBytes = deviceSizeBytes * numberOfRanks;
-
-    std::cout << headline << std::endl;
-    std::cout << "Per Channel Configuration:" << std::endl << std::endl;
-    std::cout << " Memory type:           " << "GDDR6"               << std::endl;
-    std::cout << " Memory size in bytes:  " << memorySizeBytes       << std::endl;
-    std::cout << " Ranks:                 " << numberOfRanks         << std::endl;
-    std::cout << " Bank groups per rank:  " << groupsPerRank         << std::endl;
-    std::cout << " Banks per rank:        " << banksPerRank          << std::endl;
-    std::cout << " Rows per bank:         " << numberOfRows          << std::endl;
-    std::cout << " Columns per row:       " << numberOfColumns       << std::endl;
-    std::cout << " Device width in bits:  " << bitWidth              << std::endl;
-    std::cout << " Device size in bits:   " << deviceSizeBits        << std::endl;
-    std::cout << " Device size in bytes:  " << deviceSizeBytes       << std::endl;
-    std::cout << std::endl;
-
-    assert(memorySizeBytes > 0);
-    return memorySizeBytes;
-}
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h
index b6d86f8e..da13f143 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h
@@ -92,8 +92,6 @@ public:
 
     virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
     virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
-
-    virtual uint64_t getSimMemSizeInBytes() const override;
 };
 
 #endif // MEMSPECGDDR6_H
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp
index 25f77ef9..afc986a2 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp
@@ -82,6 +82,25 @@ MemSpecHBM2::MemSpecHBM2(json &memspec)
       tREFISB (tCK * parseUint(memspec["memtimingspec"]["REFISB"], "REFISB"))
 {
     commandLengthInCycles[Command::ACT] = 2;
+
+    uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
+    uint64_t deviceSizeBytes = deviceSizeBits / 8;
+    memorySizeBytes = deviceSizeBytes * numberOfRanks * numberOfChannels;
+
+    std::cout << headline << std::endl;
+    std::cout << "Memory Configuration:" << std::endl << std::endl;
+    std::cout << " Memory type:           " << "HBM2"              << std::endl;
+    std::cout << " Memory size in bytes:  " << memorySizeBytes       << std::endl;
+    std::cout << " Channels:              " << numberOfChannels      << std::endl;
+    std::cout << " Ranks per channel:     " << numberOfRanks         << std::endl;
+    std::cout << " Bank groups per rank:  " << groupsPerRank         << std::endl;
+    std::cout << " Banks per rank:        " << banksPerRank          << std::endl;
+    std::cout << " Rows per bank:         " << numberOfRows          << std::endl;
+    std::cout << " Columns per row:       " << numberOfColumns       << std::endl;
+    std::cout << " Device width in bits:  " << bitWidth              << std::endl;
+    std::cout << " Device size in bits:   " << deviceSizeBits        << std::endl;
+    std::cout << " Device size in bytes:  " << deviceSizeBytes       << std::endl;
+    std::cout << std::endl;
 }
 
 sc_time MemSpecHBM2::getRefreshIntervalAB() const
@@ -142,27 +161,3 @@ TimeInterval MemSpecHBM2::getIntervalOnDataStrobe(Command command, const tlm_gen
         return TimeInterval();
     }
 }
-
-uint64_t MemSpecHBM2::getSimMemSizeInBytes() const
-{
-    uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
-    uint64_t deviceSizeBytes = deviceSizeBits / 8;
-    uint64_t memorySizeBytes = deviceSizeBytes * numberOfRanks;
-
-    std::cout << headline << std::endl;
-    std::cout << "Per Channel Configuration:" << std::endl << std::endl;
-    std::cout << " Memory type:           " << "HBM2"               << std::endl;
-    std::cout << " Memory size in bytes:  " << memorySizeBytes       << std::endl;
-    std::cout << " Ranks:                 " << numberOfRanks         << std::endl;
-    std::cout << " Bank groups per rank:  " << groupsPerRank         << std::endl;
-    std::cout << " Banks per rank:        " << banksPerRank          << std::endl;
-    std::cout << " Rows per bank:         " << numberOfRows          << std::endl;
-    std::cout << " Columns per row:       " << numberOfColumns       << std::endl;
-    std::cout << " Device width in bits:  " << bitWidth              << std::endl;
-    std::cout << " Device size in bits:   " << deviceSizeBits        << std::endl;
-    std::cout << " Device size in bytes:  " << deviceSizeBytes       << std::endl;
-    std::cout << std::endl;
-
-    assert(memorySizeBytes > 0);
-    return memorySizeBytes;
-}
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h
index f5c0fbb0..9572a7a0 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h
@@ -87,8 +87,6 @@ public:
 
     virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
     virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
-
-    virtual uint64_t getSimMemSizeInBytes() const override;
 };
 
 #endif // MEMSPECHBM2_H
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp
index 9e181a0d..e24fbb67 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp
@@ -92,6 +92,24 @@ MemSpecLPDDR4::MemSpecLPDDR4(json &memspec)
     commandLengthInCycles[Command::REFB] = 2;
     commandLengthInCycles[Command::SREFEN] = 2;
     commandLengthInCycles[Command::SREFEX] = 2;
+
+    uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
+    uint64_t deviceSizeBytes = deviceSizeBits / 8;
+    memorySizeBytes = deviceSizeBytes * numberOfRanks * numberOfChannels;
+
+    std::cout << headline << std::endl;
+    std::cout << "Memory Configuration:" << std::endl << std::endl;
+    std::cout << " Memory type:           " << "LPDDR4"              << std::endl;
+    std::cout << " Memory size in bytes:  " << memorySizeBytes       << std::endl;
+    std::cout << " Channels:              " << numberOfChannels      << std::endl;
+    std::cout << " Ranks per channel:     " << numberOfRanks         << std::endl;
+    std::cout << " Banks per rank:        " << banksPerRank          << std::endl;
+    std::cout << " Rows per bank:         " << numberOfRows          << std::endl;
+    std::cout << " Columns per row:       " << numberOfColumns       << std::endl;
+    std::cout << " Device width in bits:  " << bitWidth              << std::endl;
+    std::cout << " Device size in bits:   " << deviceSizeBits        << std::endl;
+    std::cout << " Device size in bytes:  " << deviceSizeBytes       << std::endl;
+    std::cout << std::endl;
 }
 
 sc_time MemSpecLPDDR4::getRefreshIntervalAB() const
@@ -146,27 +164,3 @@ TimeInterval MemSpecLPDDR4::getIntervalOnDataStrobe(Command command, const tlm_g
         return TimeInterval();
     }
 }
-
-uint64_t MemSpecLPDDR4::getSimMemSizeInBytes() const
-{
-    uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
-    uint64_t deviceSizeBytes = deviceSizeBits / 8;
-    uint64_t memorySizeBytes = deviceSizeBytes * numberOfRanks;
-
-    std::cout << headline << std::endl;
-    std::cout << "Per Channel Configuration:" << std::endl << std::endl;
-    std::cout << " Memory type:           " << "LPDDR4"              << std::endl;
-    std::cout << " Memory size in bytes:  " << memorySizeBytes       << std::endl;
-    std::cout << " Ranks:                 " << numberOfRanks         << std::endl;
-    std::cout << " Banks per rank:        " << banksPerRank          << std::endl;
-    std::cout << " Rows per bank:         " << numberOfRows          << std::endl;
-    std::cout << " Columns per row:       " << numberOfColumns       << std::endl;
-    std::cout << " Device width in bits:  " << bitWidth              << std::endl;
-    std::cout << " Device size in bits:   " << deviceSizeBits        << std::endl;
-    std::cout << " Device size in bytes:  " << deviceSizeBytes       << std::endl;
-    std::cout << std::endl;
-
-    assert(memorySizeBytes > 0);
-    return memorySizeBytes;
-}
-
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h
index 8005422e..42e4e076 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h
@@ -85,8 +85,6 @@ public:
 
     virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
     virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
-
-    virtual uint64_t getSimMemSizeInBytes() const override;
 };
 
 #endif // MEMSPECLPDDR4_H
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.cpp
index 1d4d52c6..73b97171 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.cpp
@@ -73,7 +73,26 @@ MemSpecSTTMRAM::MemSpecSTTMRAM(json &memspec)
       tACTPDEN (tCK * parseUint(memspec["memtimingspec"]["ACTPDEN"], "ACTPDEN")),
       tPRPDEN  (tCK * parseUint(memspec["memtimingspec"]["PRPDEN"], "PRPDEN")),
       tRTRS    (tCK * parseUint(memspec["memtimingspec"]["RTRS"], "RTRS"))
-{}
+{
+    uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
+    uint64_t deviceSizeBytes = deviceSizeBits / 8;
+    memorySizeBytes = deviceSizeBytes * numberOfDevicesOnDIMM * numberOfRanks * numberOfChannels;
+
+    std::cout << headline << std::endl;
+    std::cout << "Memory Configuration:" << std::endl << std::endl;
+    std::cout << " Memory type:           " << "STT-MRAM"            << std::endl;
+    std::cout << " Memory size in bytes:  " << memorySizeBytes       << std::endl;
+    std::cout << " Channels:              " << numberOfChannels      << std::endl;
+    std::cout << " Ranks per channel:     " << numberOfRanks         << std::endl;
+    std::cout << " Banks per rank:        " << banksPerRank          << std::endl;
+    std::cout << " Rows per bank:         " << numberOfRows          << std::endl;
+    std::cout << " Columns per row:       " << numberOfColumns       << std::endl;
+    std::cout << " Device width in bits:  " << bitWidth              << std::endl;
+    std::cout << " Device size in bits:   " << deviceSizeBits        << std::endl;
+    std::cout << " Device size in bytes:  " << deviceSizeBytes       << std::endl;
+    std::cout << " Devices on DIMM:       " << numberOfDevicesOnDIMM << std::endl;
+    std::cout << std::endl;
+}
 
 // Returns the execution time for commands that have a fixed execution time
 sc_time MemSpecSTTMRAM::getExecutionTime(Command command, const tlm_generic_payload &) const
@@ -110,27 +129,3 @@ TimeInterval MemSpecSTTMRAM::getIntervalOnDataStrobe(Command command, const tlm:
         return TimeInterval();
     }
 }
-
-uint64_t MemSpecSTTMRAM::getSimMemSizeInBytes() const
-{
-    uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
-    uint64_t deviceSizeBytes = deviceSizeBits / 8;
-    uint64_t memorySizeBytes = deviceSizeBytes * numberOfDevicesOnDIMM * numberOfRanks;
-
-    std::cout << headline << std::endl;
-    std::cout << "Per Channel Configuration:" << std::endl << std::endl;
-    std::cout << " Memory type:           " << "STT-MRAM"            << std::endl;
-    std::cout << " Memory size in bytes:  " << memorySizeBytes       << std::endl;
-    std::cout << " Ranks:                 " << numberOfRanks         << std::endl;
-    std::cout << " Banks per rank:        " << banksPerRank          << std::endl;
-    std::cout << " Rows per bank:         " << numberOfRows          << std::endl;
-    std::cout << " Columns per row:       " << numberOfColumns       << std::endl;
-    std::cout << " Device width in bits:  " << bitWidth              << std::endl;
-    std::cout << " Device size in bits:   " << deviceSizeBits        << std::endl;
-    std::cout << " Device size in bytes:  " << deviceSizeBytes       << std::endl;
-    std::cout << " Devices on DIMM:       " << numberOfDevicesOnDIMM << std::endl;
-    std::cout << std::endl;
-
-    assert(memorySizeBytes > 0);
-    return memorySizeBytes;
-}
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.h b/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.h
index 0f29a5c1..323e8adb 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.h
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.h
@@ -75,8 +75,6 @@ public:
 
     virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
     virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
-
-    virtual uint64_t getSimMemSizeInBytes() const override;
 };
 
 #endif // MEMSPECSTTMRAM_H
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp
index dcbd1ae7..c88dde77 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp
@@ -94,7 +94,25 @@ MemSpecWideIO::MemSpecWideIO(json &memspec)
       iDD52   (parseUdouble(memspec["mempowerspec"]["idd52"], "idd52")),
       iDD62   (parseUdouble(memspec["mempowerspec"]["idd62"], "idd62")),
       vDD2    (parseUdouble(memspec["mempowerspec"]["vdd2"], "vdd2"))
-{}
+{
+    uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
+    uint64_t deviceSizeBytes = deviceSizeBits / 8;
+    memorySizeBytes = deviceSizeBytes * numberOfRanks * numberOfChannels;
+
+    std::cout << headline << std::endl;
+    std::cout << "Memory Configuration:" << std::endl << std::endl;
+    std::cout << " Memory type:           " << "Wide I/O"            << std::endl;
+    std::cout << " Memory size in bytes:  " << memorySizeBytes       << std::endl;
+    std::cout << " Channels:              " << numberOfChannels      << std::endl;
+    std::cout << " Ranks per channel:     " << numberOfRanks         << std::endl;
+    std::cout << " Banks per rank:        " << banksPerRank          << std::endl;
+    std::cout << " Rows per bank:         " << numberOfRows          << std::endl;
+    std::cout << " Columns per row:       " << numberOfColumns       << std::endl;
+    std::cout << " Device width in bits:  " << bitWidth              << std::endl;
+    std::cout << " Device size in bits:   " << deviceSizeBits        << std::endl;
+    std::cout << " Device size in bytes:  " << deviceSizeBytes       << std::endl;
+    std::cout << std::endl;
+}
 
 sc_time MemSpecWideIO::getRefreshIntervalAB() const
 {
@@ -138,26 +156,3 @@ TimeInterval MemSpecWideIO::getIntervalOnDataStrobe(Command command, const tlm_g
         return TimeInterval();
     }
 }
-
-uint64_t MemSpecWideIO::getSimMemSizeInBytes() const
-{
-    uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
-    uint64_t deviceSizeBytes = deviceSizeBits / 8;
-    uint64_t memorySizeBytes = deviceSizeBytes * numberOfRanks;
-
-    std::cout << headline << std::endl;
-    std::cout << "Per Channel Configuration:" << std::endl << std::endl;
-    std::cout << " Memory type:           " << "Wide I/O"            << std::endl;
-    std::cout << " Memory size in bytes:  " << memorySizeBytes       << std::endl;
-    std::cout << " Ranks:                 " << numberOfRanks         << std::endl;
-    std::cout << " Banks per rank:        " << banksPerRank          << std::endl;
-    std::cout << " Rows per bank:         " << numberOfRows          << std::endl;
-    std::cout << " Columns per row:       " << numberOfColumns       << std::endl;
-    std::cout << " Device width in bits:  " << bitWidth              << std::endl;
-    std::cout << " Device size in bits:   " << deviceSizeBits        << std::endl;
-    std::cout << " Device size in bytes:  " << deviceSizeBytes       << std::endl;
-    std::cout << std::endl;
-
-    assert(memorySizeBytes > 0);
-    return memorySizeBytes;
-}
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h
index 79b2818c..ad50ba1c 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h
@@ -97,8 +97,6 @@ public:
 
     virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
     virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
-
-    virtual uint64_t getSimMemSizeInBytes() const override;
 };
 
 #endif // MEMSPECWIDEIO_H
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp
index eb0efe10..4746b0ad 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp
@@ -76,7 +76,25 @@ MemSpecWideIO2::MemSpecWideIO2(json &memspec)
       tRFCab  (tCK * parseUint(memspec["memtimingspec"]["RFCAB"], "RFCAB")),
       tRFCpb  (tCK * parseUint(memspec["memtimingspec"]["RFCPB"], "RFCPB")),
       tRTRS   (tCK * parseUint(memspec["memtimingspec"]["RTRS"], "RTRS"))
-{}
+{
+    uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
+    uint64_t deviceSizeBytes = deviceSizeBits / 8;
+    memorySizeBytes = deviceSizeBytes * numberOfRanks * numberOfChannels;
+
+    std::cout << headline << std::endl;
+    std::cout << "Memory Configuration:" << std::endl << std::endl;
+    std::cout << " Memory type:           " << "Wide I/O 2"          << std::endl;
+    std::cout << " Memory size in bytes:  " << memorySizeBytes       << std::endl;
+    std::cout << " Channels:              " << numberOfChannels      << std::endl;
+    std::cout << " Ranks per channel:     " << numberOfRanks         << std::endl;
+    std::cout << " Banks per rank:        " << banksPerRank          << std::endl;
+    std::cout << " Rows per bank:         " << numberOfRows          << std::endl;
+    std::cout << " Columns per row:       " << numberOfColumns       << std::endl;
+    std::cout << " Device width in bits:  " << bitWidth              << std::endl;
+    std::cout << " Device size in bits:   " << deviceSizeBits        << std::endl;
+    std::cout << " Device size in bytes:  " << deviceSizeBytes       << std::endl;
+    std::cout << std::endl;
+}
 
 sc_time MemSpecWideIO2::getRefreshIntervalAB() const
 {
@@ -129,26 +147,3 @@ TimeInterval MemSpecWideIO2::getIntervalOnDataStrobe(Command command, const tlm_
         return TimeInterval();
     }
 }
-
-uint64_t MemSpecWideIO2::getSimMemSizeInBytes() const
-{
-    uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
-    uint64_t deviceSizeBytes = deviceSizeBits / 8;
-    uint64_t memorySizeBytes = deviceSizeBytes * numberOfRanks;
-
-    std::cout << headline << std::endl;
-    std::cout << "Per Channel Configuration:" << std::endl << std::endl;
-    std::cout << " Memory type:           " << "Wide I/O 2"          << std::endl;
-    std::cout << " Memory size in bytes:  " << memorySizeBytes       << std::endl;
-    std::cout << " Ranks:                 " << numberOfRanks         << std::endl;
-    std::cout << " Banks per rank:        " << banksPerRank          << std::endl;
-    std::cout << " Rows per bank:         " << numberOfRows          << std::endl;
-    std::cout << " Columns per row:       " << numberOfColumns       << std::endl;
-    std::cout << " Device width in bits:  " << bitWidth              << std::endl;
-    std::cout << " Device size in bits:   " << deviceSizeBits        << std::endl;
-    std::cout << " Device size in bytes:  " << deviceSizeBytes       << std::endl;
-    std::cout << std::endl;
-
-    assert(memorySizeBytes > 0);
-    return memorySizeBytes;
-}
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h
index 31b01a7d..494f8665 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h
@@ -79,8 +79,6 @@ public:
 
     virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
     virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
-
-    virtual uint64_t getSimMemSizeInBytes() const override;
 };
 
 #endif // MEMSPECWIDEIO2_H
diff --git a/DRAMSys/library/src/simulation/dram/Dram.cpp b/DRAMSys/library/src/simulation/dram/Dram.cpp
index 6622b557..8624b4c1 100644
--- a/DRAMSys/library/src/simulation/dram/Dram.cpp
+++ b/DRAMSys/library/src/simulation/dram/Dram.cpp
@@ -71,12 +71,12 @@ Dram::Dram(sc_module_name name) : sc_module(name), tSocket("socket")
 
     storeMode = config.storeMode;
 
-    uint64_t memorySize = config.memSpec->getSimMemSizeInBytes();
+    uint64_t channelSize = config.memSpec->getSimMemSizeInBytes() / config.memSpec->numberOfChannels;
     if (storeMode == Configuration::StoreMode::Store)
     {
         if (config.useMalloc)
         {
-            memory = (unsigned char *)malloc(memorySize);
+            memory = (unsigned char *)malloc(channelSize);
             if (!memory)
                 SC_REPORT_FATAL(this->name(), "Memory allocation failed");
         }
@@ -87,7 +87,7 @@ Dram::Dram(sc_module_name name) : sc_module(name), tSocket("socket")
                 SC_REPORT_FATAL("Dram", "On Windows Storage is not yet supported");
                 memory = 0; // FIXME
             #else
-                memory = (unsigned char *)mmap(NULL, memorySize, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON | MAP_NORESERVE, -1, 0);
+                memory = (unsigned char *)mmap(NULL, channelSize, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON | MAP_NORESERVE, -1, 0);
             #endif
         }
     }