From bd245a9d907a37bb0801c9aa80ccb1994e151575 Mon Sep 17 00:00:00 2001 From: Robert Gernhardt Date: Mon, 4 Aug 2014 18:27:33 +0200 Subject: [PATCH 1/6] reorder buffer --- analyzer/analyzer/paths.pro | 8 +- dram/dramSys/dramSys.pro | 13 +- .../configs/amconfigs/am_ddr4 (4th copy).xml | 27 --- dram/resources/simulations/sim-batch.xml | 17 +- dram/src/controller/Controller.h | 7 +- .../core/configuration/TimingConfiguration.h | 4 +- .../controller/scheduler/readwritegrouper.cpp | 32 +++- .../controller/scheduler/readwritegrouper.h | 6 +- dram/src/simulation/Arbiter.h | 41 +++-- dram/src/simulation/Arbiter.h.autosave | 163 ++++++++++++++++++ dram/src/simulation/Dram.h | 56 +++--- dram/src/simulation/ReorderBuffer.h | 121 +++++++++++++ dram/src/simulation/Simulation.cpp | 17 +- dram/src/simulation/Simulation.h | 1 + 14 files changed, 401 insertions(+), 112 deletions(-) delete mode 100755 dram/resources/configs/amconfigs/am_ddr4 (4th copy).xml create mode 100644 dram/src/simulation/Arbiter.h.autosave create mode 100644 dram/src/simulation/ReorderBuffer.h diff --git a/analyzer/analyzer/paths.pro b/analyzer/analyzer/paths.pro index 102db5af..b19fe4eb 100644 --- a/analyzer/analyzer/paths.pro +++ b/analyzer/analyzer/paths.pro @@ -8,8 +8,8 @@ CONFIG(qwt){ CONFIG(python){ -# LIBS += -L/opt/python/lib -lpython3.4m -# INCLUDEPATH += /opt/python/include/python3.4m - LIBS += -lpython3.3m - INCLUDEPATH += /usr/include/python3.3 + LIBS += -L/opt/python/lib -lpython3.4m + INCLUDEPATH += /opt/python/include/python3.4m +# LIBS += -lpython3.3m +# INCLUDEPATH += /usr/include/python3.3 } diff --git a/dram/dramSys/dramSys.pro b/dram/dramSys/dramSys.pro index f0052a93..9a679742 100644 --- a/dram/dramSys/dramSys.pro +++ b/dram/dramSys/dramSys.pro @@ -8,15 +8,15 @@ LIBS += -L/opt/systemc/lib-linux64 -lsystemc LIBS += -L/opt/boost/lib -lboost_filesystem -lboost_system LIBS += -L/opt/sqlite3/lib -lsqlite3 LIBS += -lpthread -LIBS += -lxerces-c -LIBS += -L../src/common/third_party/DRAMPower/src/ -ldrampowerxml -LIBS += -L../src/common/third_party/DRAMPower/src/ -ldrampower +#LIBS += -lxerces-c +#LIBS += -L../src/common/third_party/DRAMPower/src/ -ldrampowerxml +#LIBS += -L../src/common/third_party/DRAMPower/src/ -ldrampower INCLUDEPATH += /opt/systemc/include INCLUDEPATH += /opt/boost/include INCLUDEPATH += /opt/sqlite3/include -INCLUDEPATH += ../src/common/third_party/DRAMPower/src -INCLUDEPATH += ../src/common/third_party/DRAMPower/src/libdrampower +#INCLUDEPATH += ../src/common/third_party/DRAMPower/src +#INCLUDEPATH += ../src/common/third_party/DRAMPower/src/libdrampower DEFINES += TIXML_USE_STL DEFINES += SC_INCLUDE_DYNAMIC_PROCESSES @@ -121,5 +121,6 @@ HEADERS += \ ../src/simulation/Arbiter.h \ ../src/common/libDRAMPower.h \ ../src/controller/core/RowBufferStates.h \ - ../src/controller/scheduler/readwritegrouper.h + ../src/controller/scheduler/readwritegrouper.h \ + ../src/simulation/ReorderBuffer.h diff --git a/dram/resources/configs/amconfigs/am_ddr4 (4th copy).xml b/dram/resources/configs/amconfigs/am_ddr4 (4th copy).xml deleted file mode 100755 index 73d9cb36..00000000 --- a/dram/resources/configs/amconfigs/am_ddr4 (4th copy).xml +++ /dev/null @@ -1,27 +0,0 @@ - - - - - - - - - - - - - diff --git a/dram/resources/simulations/sim-batch.xml b/dram/resources/simulations/sim-batch.xml index 7b793ec0..21a24d7c 100644 --- a/dram/resources/simulations/sim-batch.xml +++ b/dram/resources/simulations/sim-batch.xml @@ -1,22 +1,17 @@ WideIO.xml - - am_wideio.xml - - fifo.xml - - + + fr_fcfs.xml + + - mediabench-epic_32.stl + test.stl diff --git a/dram/src/controller/Controller.h b/dram/src/controller/Controller.h index 34a1c4e8..814ffc56 100644 --- a/dram/src/controller/Controller.h +++ b/dram/src/controller/Controller.h @@ -120,9 +120,10 @@ void Controller::buildScheduler() if (selectedScheduler == "FR_FCFS") { - Scheduler* s = new FR_FCFS(*controllerCore, Configuration::getInstance().RefreshAwareScheduling, - Configuration::getInstance().AdaptiveOpenPagePolicy); - scheduler = new ReadWriteGrouper(s); + //Scheduler* s = new FR_FCFS(*controllerCore, Configuration::getInstance().RefreshAwareScheduling, + // Configuration::getInstance().AdaptiveOpenPagePolicy); + //scheduler = new ReadWriteGrouper(s); + scheduler = new FR_FCFS(*controllerCore, Configuration::getInstance().RefreshAwareScheduling,Configuration::getInstance().AdaptiveOpenPagePolicy); } else if (selectedScheduler == "PAR_BS") { diff --git a/dram/src/controller/core/configuration/TimingConfiguration.h b/dram/src/controller/core/configuration/TimingConfiguration.h index e990c6fd..cb080c94 100644 --- a/dram/src/controller/core/configuration/TimingConfiguration.h +++ b/dram/src/controller/core/configuration/TimingConfiguration.h @@ -15,8 +15,8 @@ namespace core{ struct RefreshTiming { - RefreshTiming() {}; - RefreshTiming(sc_time tRFC, sc_time tREFI) : tRFC(tRFC), tREFI(tREFI) {}; + RefreshTiming() {} + RefreshTiming(sc_time tRFC, sc_time tREFI) : tRFC(tRFC), tREFI(tREFI) {} sc_time tRFC; sc_time tREFI; }; diff --git a/dram/src/controller/scheduler/readwritegrouper.cpp b/dram/src/controller/scheduler/readwritegrouper.cpp index 5797fddb..efb202d4 100644 --- a/dram/src/controller/scheduler/readwritegrouper.cpp +++ b/dram/src/controller/scheduler/readwritegrouper.cpp @@ -1,13 +1,17 @@ #include "readwritegrouper.h" +#include "../../common/DebugManager.h" namespace scheduler{ using namespace tlm; +using namespace std; + +string ReadWriteGrouper::senderName = "ReadWriteGrouper"; ReadWriteGrouper::ReadWriteGrouper(Scheduler *scheduler): scheduler(scheduler), mode(Mode::read) { - + printDebugMessage("In read mode"); } ReadWriteGrouper::~ReadWriteGrouper() @@ -23,9 +27,9 @@ void ReadWriteGrouper::removePayload(gp *payload) //if scheduler is empty now if(!scheduler->hasPayloads()) { - if(mode == Mode::read && !writeQueue.empty()) - switchToWriteMode(); - else if(mode == Mode::readToWrite) + printDebugMessage("No more transactions in scheduler"); + + if((mode == Mode::read && !writeQueue.empty()) || mode == Mode::readToWrite) switchToWriteMode(); else switchToReadMode(); @@ -42,7 +46,7 @@ if(mode == Mode::read) if(command == TLM_READ_COMMAND) { //if scheduling the read would cause a hazard switch to readToWriteMode and put the read into the readQueue - if(schedulingReadCausesHazard(payload)) + if(schedulingReadCausesHazardWithQueuedWrite(payload)) { switchToReadToWriteMode(); readQueue.push_back(payload); @@ -50,7 +54,7 @@ if(mode == Mode::read) else scheduler->schedule(payload); } - else + else if(command == TLM_WRITE_COMMAND) { writeQueue.push_back(payload); if(!scheduler->hasPayloads()) @@ -62,14 +66,14 @@ else if(mode == Mode::readToWrite) { if(command == TLM_READ_COMMAND) readQueue.push_back(payload); - else + else if(command == TLM_WRITE_COMMAND) writeQueue.push_back(payload); } else if(mode == Mode::write) { if(command == TLM_READ_COMMAND) readQueue.push_back(payload); - else + else if(command == TLM_WRITE_COMMAND) scheduler->schedule(payload); } @@ -86,7 +90,7 @@ bool ReadWriteGrouper::hasPayloads() } -bool ReadWriteGrouper::schedulingReadCausesHazard(gp *payload) +bool ReadWriteGrouper::schedulingReadCausesHazardWithQueuedWrite(gp *payload) { sc_assert(payload->is_read()); for(gp* write: writeQueue) @@ -99,6 +103,8 @@ bool ReadWriteGrouper::schedulingReadCausesHazard(gp *payload) void ReadWriteGrouper::switchToReadMode() { + printDebugMessage("Switching to read mode"); + sc_assert(!scheduler->hasPayloads()); mode = Mode::read; for(gp* read: readQueue) scheduler->schedule(read); @@ -107,6 +113,8 @@ void ReadWriteGrouper::switchToReadMode() void ReadWriteGrouper::switchToWriteMode() { + printDebugMessage("Switching to write mode"); + sc_assert(!scheduler->hasPayloads()); mode = Mode::write; for(gp* write: writeQueue) scheduler->schedule(write); @@ -115,7 +123,13 @@ void ReadWriteGrouper::switchToWriteMode() void ReadWriteGrouper::switchToReadToWriteMode() { + printDebugMessage("Switching to read-to-write-mode"); mode = Mode::readToWrite; } +void printDebugMessage(string message) +{ + DebugManager::getInstance().printDebugMessage(ReadWriteGrouper::senderName, message); +} + } diff --git a/dram/src/controller/scheduler/readwritegrouper.h b/dram/src/controller/scheduler/readwritegrouper.h index 4e8b359f..9f5945f1 100644 --- a/dram/src/controller/scheduler/readwritegrouper.h +++ b/dram/src/controller/scheduler/readwritegrouper.h @@ -20,6 +20,8 @@ public: virtual gp* getNextPayload() override; virtual void removePayload(gp* payload) override; + static std::string senderName; + private: Scheduler *scheduler; std::vector readQueue, writeQueue; @@ -28,10 +30,12 @@ private: enum class Mode{read,readToWrite, write}; Mode mode; - bool schedulingReadCausesHazard(gp* payload); + bool schedulingReadCausesHazardWithQueuedWrite(gp* payload); void switchToReadMode(); void switchToWriteMode(); void switchToReadToWriteMode(); + void printDebugMessage(std::string message); + }; diff --git a/dram/src/simulation/Arbiter.h b/dram/src/simulation/Arbiter.h index 410ea46c..e21af2ec 100644 --- a/dram/src/simulation/Arbiter.h +++ b/dram/src/simulation/Arbiter.h @@ -45,10 +45,12 @@ public: private: tlm_utils::peq_with_cb_and_phase payloadEventQueue; bool channelIsFree; - deque backpressure; + //used to account for the request_accept_delay in the dram controllers + deque pendingRequests; + //used to account for the response_accept_delay in the initiators (traceplayer,core etc.) + deque pendingResponses[NUMBER_OF_THREADS]; - - // Initiated by dram + // Initiated by dram side tlm_sync_enum nb_transport_bw(tlm_generic_payload& payload, tlm_phase& phase, sc_time& bwDelay) { TlmRecorder::getInstance().recordPhase(payload, phase, bwDelay + sc_time_stamp()); @@ -56,7 +58,7 @@ private: return TLM_ACCEPTED; } - // Initiated by senders + // Initiated by initiator side tlm_sync_enum nb_transport_fw(int socketId, tlm_generic_payload& payload, tlm_phase& phase, sc_time& fwDelay) { @@ -66,7 +68,9 @@ private: payload.acquire(); } else if(phase == END_RESP) + { payload.release(); + } payloadEventQueue.notify(payload, phase, fwDelay); return TLM_ACCEPTED; @@ -74,6 +78,9 @@ private: void peqCallback(tlm_generic_payload& payload, const tlm_phase& phase) { + unsigned int initiatorSocket = DramExtension::getExtension(payload).getThread().ID()-1; + + //Phases initiated by intiator side if (phase == BEGIN_REQ) { @@ -84,32 +91,40 @@ private: } else { - backpressure.push_back(&payload); + pendingRequests.push_back(&payload); } } else if (phase == END_RESP) { - sendToChannel(payload, phase, SC_ZERO_TIME ); + sendToChannel(payload, phase, SC_ZERO_TIME); + pendingResponses[initiatorSocket].pop_front(); + if(!pendingResponses[initiatorSocket].empty()) + { + tlm_generic_payload* payloadToSend = pendingResponses[initiatorSocket].front(); + sendToInitiator(initiatorSocket,*payloadToSend,BEGIN_RESP,SC_ZERO_TIME); + } } //Phases initiated by dram side else if (phase == END_REQ) { channelIsFree = true; - sendToInitiator(DramExtension::getExtension(payload).getThread().ID()-1, payload, phase, SC_ZERO_TIME); + sendToInitiator(initiatorSocket, payload, phase, SC_ZERO_TIME); - if(!backpressure.empty()) + if(!pendingRequests.empty()) { - tlm_generic_payload* payloadToSend = backpressure.front(); - backpressure.pop_front(); + tlm_generic_payload* payloadToSend = pendingRequests.front(); + pendingRequests.pop_front(); sendToChannel(*payloadToSend, BEGIN_REQ, SC_ZERO_TIME ); channelIsFree = false; } } else if (phase == BEGIN_RESP) - { - sendToInitiator(DramExtension::getExtension(payload).getThread().ID()-1, payload, phase, SC_ZERO_TIME); + { + if(pendingResponses[initiatorSocket].empty()) + sendToInitiator(initiatorSocket, payload, phase, SC_ZERO_TIME); + pendingResponses[initiatorSocket].push_back(&payload); } else @@ -136,7 +151,7 @@ private: { unsigned int burstlength = payload.get_streaming_width(); DecodedAddress decodedAddress = xmlAddressDecoder::getInstance().decodeAddress(payload.get_address()); - DramExtension* extension = new DramExtension(Thread(socketId+1), Channel(decodedAddress.channel), Bank(decodedAddress.bank), + DramExtension* extension = new DramExtension(Thread(socketId+1), Channel(0), Bank(decodedAddress.bank), BankGroup(decodedAddress.bankgroup), Row(decodedAddress.row), Column(decodedAddress.column),burstlength); payload.set_auto_extension(extension); } diff --git a/dram/src/simulation/Arbiter.h.autosave b/dram/src/simulation/Arbiter.h.autosave new file mode 100644 index 00000000..b7421545 --- /dev/null +++ b/dram/src/simulation/Arbiter.h.autosave @@ -0,0 +1,163 @@ +/* + * arbiter.h + * + * Created on: Mar 16, 2014 + * Author: robert + */ + +#ifndef ARBITER_H_ +#define ARBITER_H_ + + +#include +#include +#include +#include +#include +#include +#include "../common/xmlAddressdecoder.h" +#include "../common/dramExtension.h" +#include "../controller/core/TimingCalculation.h" +#include + + +using namespace std; +using namespace tlm; + +template +struct Arbiter: public sc_module +{ +public: + tlm_utils::simple_initiator_socket iSocket; + tlm_utils::simple_target_socket_tagged tSockets[NUMBER_OF_THREADS]; + + SC_CTOR(Arbiter) : + payloadEventQueue(this, &Arbiter::peqCallback), channelIsFree(true) + { + iSocket.register_nb_transport_bw(this, &Arbiter::nb_transport_bw); + + for (unsigned int i = 0; i < NUMBER_OF_THREADS; ++i) + { + tSockets[i].register_nb_transport_fw(this, &Arbiter::nb_transport_fw, i); + } + } + +private: + tlm_utils::peq_with_cb_and_phase payloadEventQueue; + bool channelIsFree; + //used to account for the request_accept_delay in the dram controllers + deque pendingRequests; + //used to account for the response_accept_delay in the initiators (traceplayer,core etc.) + deque receivedResponses[NUMBER_OF_THREADS]; + + // Initiated by dram side + tlm_sync_enum nb_transport_bw(tlm_generic_payload& payload, tlm_phase& phase, sc_time& bwDelay) + { + TlmRecorder::getInstance().recordPhase(payload, phase, bwDelay + sc_time_stamp()); + payloadEventQueue.notify(payload, phase, bwDelay); + return TLM_ACCEPTED; + } + + // Initiated by initiator side + tlm_sync_enum nb_transport_fw(int socketId, tlm_generic_payload& payload, tlm_phase& phase, + sc_time& fwDelay) + { + if(phase == BEGIN_REQ) + { + appendDramExtension(socketId, payload); + payload.acquire(); + } + else if(phase == END_RESP) + { + payload.release(); + } + + payloadEventQueue.notify(payload, phase, fwDelay); + return TLM_ACCEPTED; + } + + void peqCallback(tlm_generic_payload& payload, const tlm_phase& phase) + { + unsigned int initiatorSocket = DramExtension::getExtension(payload).getThread().ID()-1; + + + //Phases initiated by intiator side + if (phase == BEGIN_REQ) + { + if(channelIsFree) + { + channelIsFree = false; + sendToChannel(payload, phase, SC_ZERO_TIME ); + } + else + { + pendingRequests.push_back(&payload); + } + } + + else if (phase == END_RESP) + { + sendToChannel(payload, phase, SC_ZERO_TIME); + receivedResponses[initiatorSocket].pop_front(); + if(!receivedResponses[initiatorSocket].empty()) + { + tlm_generic_payload* payloadToSend = receivedResponses[initiatorSocket].front(); + sendToInitiator(initiatorSocket,*payloadToSend,BEGIN_RESP,SC_ZERO_TIME); + } + } + + //Phases initiated by dram side + else if (phase == END_REQ) + { + channelIsFree = true; + sendToInitiator(initiatorSocket, payload, phase, SC_ZERO_TIME); + + if(!pendingRequests.empty()) + { + tlm_generic_payload* payloadToSend = pendingRequests.front(); + pendingRequests.pop_front(); + sendToChannel(*payloadToSend, BEGIN_REQ, SC_ZERO_TIME ); + channelIsFree = false; + } + } + else if (phase == BEGIN_RESP) + { + if(receivedResponses[initiatorSocket].empty()) + sendToInitiator(initiatorSocket, payload, phase, SC_ZERO_TIME); + receivedResponses[initiatorSocket].push_back(&payload); + } + + else + { + SC_REPORT_FATAL(0, "Payload event queue in arbiter was triggered with unknown phase"); + } + } + + void sendToChannel(tlm_generic_payload& payload, const tlm_phase& phase, const sc_time& delay) + { + tlm_phase TPhase = phase; + sc_time TDelay = delay; + iSocket->nb_transport_fw(payload, TPhase, TDelay); + } + + void sendToInitiator(unsigned int id, tlm_generic_payload& payload, const tlm_phase& phase, const sc_time& delay) + { + tlm_phase TPhase = phase; + sc_time TDelay = delay; + tSockets[id]->nb_transport_bw(payload, TPhase, TDelay); + } + + void appendDramExtension(int socketId, tlm_generic_payload& payload) + { + unsigned int burstlength = payload.get_streaming_width(); + DecodedAddress decodedAddress = xmlAddressDecoder::getInstance().decodeAddress(payload.get_address()); + DramExtension* extension = new DramExtension(Thread(socketId+1), Channel(0), Bank(decodedAddress.bank), + BankGroup(decodedAddress.bankgroup), Row(decodedAddress.row), Column(decodedAddress.column),burstlength); + payload.set_auto_extension(extension); + } +}; + + + + +#endif /* ARBITER_H_ */ diff --git a/dram/src/simulation/Dram.h b/dram/src/simulation/Dram.h index 69c882ba..f28b1749 100644 --- a/dram/src/simulation/Dram.h +++ b/dram/src/simulation/Dram.h @@ -19,38 +19,38 @@ #include "../common/protocol.h" #include "../common/Utils.h" #include "../common/TlmRecorder.h" -#include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" -#include "../common/third_party/DRAMPower/src/xmlparser/MemSpecParser.h" -#include "../common/third_party/DRAMPower/src/MemorySpecification.h" -#include "../common/third_party/DRAMPower/src/MemCommand.h" +//#include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" +//#include "../common/third_party/DRAMPower/src/xmlparser/MemSpecParser.h" +//#include "../common/third_party/DRAMPower/src/MemorySpecification.h" +//#include "../common/third_party/DRAMPower/src/MemCommand.h" using namespace std; using namespace tlm; using namespace core; -using namespace Data; +//using namespace Data; template struct Dram: sc_module { tlm_utils::simple_target_socket tSocket; - libDRAMPower *DRAMPower; + //libDRAMPower *DRAMPower; SC_CTOR(Dram) : tSocket("socket") { tSocket.register_nb_transport_fw(this, &Dram::nb_transport_fw); - MemorySpecification memSpec(MemSpecParser::getMemSpecFromXML(Configuration::getInstance().memspecUri)); - //MemorySpecification::getMemSpecFromXML(Configuration::getInstance().memspecUri)); - DRAMPower = new libDRAMPower( memSpec, 1,1,1,0,0 ); +// MemorySpecification memSpec(MemSpecParser::getMemSpecFromXML(Configuration::getInstance().memspecUri)); +// //MemorySpecification::getMemSpecFromXML(Configuration::getInstance().memspecUri)); +// DRAMPower = new libDRAMPower( memSpec, 1,1,1,0,0 ); } ~Dram() { - DRAMPower->updateCounters(true); - DRAMPower->getEnergy(); - cout << "Total Energy" << "\t" << DRAMPower->mpm.energy.total_energy << endl; - cout << "Average Power" << "\t" << DRAMPower->mpm.power.average_power << endl; +// DRAMPower->updateCounters(true); +// DRAMPower->getEnergy(); +// cout << "Total Energy" << "\t" << DRAMPower->mpm.energy.total_energy << endl; +// cout << "Average Power" << "\t" << DRAMPower->mpm.power.average_power << endl; } virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& payload, tlm::tlm_phase& phase, sc_time& delay) @@ -58,47 +58,47 @@ struct Dram: sc_module TlmRecorder::getInstance().recordPhase(payload, phase, sc_time_stamp() + delay); // This is only needed for power simulation: - unsigned long long cycle = sc_time_stamp().value()/Configuration::getInstance().Timings.clk.value(); + //unsigned long long cycle = sc_time_stamp().value()/Configuration::getInstance().Timings.clk.value(); unsigned int bank = DramExtension::getExtension(payload).getBank().ID(); if (phase == BEGIN_PRE) { - DRAMPower->doCommand(MemCommand::PRE, bank, cycle); + //DRAMPower->doCommand(MemCommand::PRE, bank, cycle); sendToController(payload, END_PRE, delay + getExecutionTime(Command::Precharge, payload)); } else if (phase == BEGIN_PRE_ALL) { - DRAMPower->doCommand(MemCommand::PREA, bank, cycle); + //DRAMPower->doCommand(MemCommand::PREA, bank, cycle); sendToController(payload, END_PRE_ALL,delay + getExecutionTime(Command::PrechargeAll, payload)); } else if (phase == BEGIN_ACT) { - DRAMPower->doCommand(MemCommand::ACT, bank, cycle); + //DRAMPower->doCommand(MemCommand::ACT, bank, cycle); sendToController(payload, END_ACT, delay + getExecutionTime(Command::Activate, payload)); } else if (phase == BEGIN_WR) { - DRAMPower->doCommand(MemCommand::WR, bank, cycle); + //DRAMPower->doCommand(MemCommand::WR, bank, cycle); sendToController(payload, END_WR, delay + getExecutionTime(Command::Write, payload)); } else if (phase == BEGIN_RD) { - DRAMPower->doCommand(MemCommand::RD, bank, cycle); + //DRAMPower->doCommand(MemCommand::RD, bank, cycle); sendToController(payload, END_RD, delay + getExecutionTime(Command::Read, payload)); } else if (phase == BEGIN_WRA) { - DRAMPower->doCommand(MemCommand::WRA, bank, cycle); + //DRAMPower->doCommand(MemCommand::WRA, bank, cycle); sendToController(payload, END_WRA, delay + getExecutionTime(Command::WriteA, payload)); } else if (phase == BEGIN_RDA) { - DRAMPower->doCommand(MemCommand::RDA, bank, cycle); + //DRAMPower->doCommand(MemCommand::RDA, bank, cycle); sendToController(payload, END_RDA, delay + getExecutionTime(Command::ReadA, payload)); } else if (phase == BEGIN_AUTO_REFRESH) { - DRAMPower->doCommand(MemCommand::REF, bank, cycle); + //DRAMPower->doCommand(MemCommand::REF, bank, cycle); sendToController(payload, END_AUTO_REFRESH, delay + getExecutionTime(Command::AutoRefresh, payload)); } @@ -109,7 +109,7 @@ struct Dram: sc_module { if(bank == 0) { - DRAMPower->doCommand(MemCommand::PDN_S_PRE, bank, cycle); + //DRAMPower->doCommand(MemCommand::PDN_S_PRE, bank, cycle); } } } @@ -119,7 +119,7 @@ struct Dram: sc_module { if(bank == 0) { - DRAMPower->doCommand(MemCommand::PUP_PRE, bank, cycle); + //DRAMPower->doCommand(MemCommand::PUP_PRE, bank, cycle); } } } @@ -129,7 +129,7 @@ struct Dram: sc_module { if(bank == 0) { - DRAMPower->doCommand(MemCommand::PDN_S_ACT, bank, cycle); + //DRAMPower->doCommand(MemCommand::PDN_S_ACT, bank, cycle); } } } @@ -139,17 +139,17 @@ struct Dram: sc_module { if(bank == 0) { - DRAMPower->doCommand(MemCommand::PUP_ACT, bank, cycle); + //DRAMPower->doCommand(MemCommand::PUP_ACT, bank, cycle); } } } else if (phase == BEGIN_SREF) { - DRAMPower->doCommand(MemCommand::SREN, bank, cycle); + //DRAMPower->doCommand(MemCommand::SREN, bank, cycle); } else if (phase == END_SREF) { - DRAMPower->doCommand(MemCommand::SREX, bank, cycle); + //DRAMPower->doCommand(MemCommand::SREX, bank, cycle); } else { diff --git a/dram/src/simulation/ReorderBuffer.h b/dram/src/simulation/ReorderBuffer.h new file mode 100644 index 00000000..d1ce1fff --- /dev/null +++ b/dram/src/simulation/ReorderBuffer.h @@ -0,0 +1,121 @@ +#ifndef REORDERBUFFER_H +#define REORDERBUFFER_H + +#include +#include +#include + +using namespace std; +using namespace tlm; + +template +struct ReorderBuffer: public sc_module +{ +public: + tlm_utils::simple_initiator_socket iSocket; + tlm_utils::simple_target_socket_tagged tSocket; + + SC_CTOR(ReorderBuffer) : + payloadEventQueue(this, &ReorderBuffer::peqCallback), responseIsPendingInInitator(false) + { + iSocket.register_nb_transport_bw(this, &ReorderBuffer::nb_transport_bw); + tSocket.register_nb_transport_fw(this, &ReorderBuffer::nb_transport_fw); + } + +private: + tlm_utils::peq_with_cb_and_phase payloadEventQueue; + deque requestsInOrder; + set receivedResponses; + + bool responseIsPendingInInitator; + + + // Initiated by dram side + tlm_sync_enum nb_transport_bw(tlm_generic_payload& payload, tlm_phase& phase, sc_time& bwDelay) + { + payloadEventQueue.notify(payload, phase, bwDelay); + return TLM_ACCEPTED; + } + + // Initiated by initator side (players) + tlm_sync_enum nb_transport_fw(tlm_generic_payload& payload, tlm_phase& phase, + sc_time& fwDelay) + { + if (phase == BEGIN_REQ) + { + payload.acquire(); + } + else if (phase == END_RESP) + { + payload.release(); + } + + payloadEventQueue.notify(payload, phase, fwDelay); + return TLM_ACCEPTED; + } + + void peqCallback(tlm_generic_payload& payload, const tlm_phase& phase) + { + //Phases initiated by initiator side + if (phase == BEGIN_REQ) + { + requestsInOrder.push_back(&payload); + sendToTarget(payload, phase, SC_ZERO_TIME ); + } + + else if (phase == END_RESP) + { + responseIsPendingInInitator = false; + sendNextResponse(); + } + + //Phases initiated by dram side + else if (phase == END_REQ) + { + sendToInitiator(payload, phase, SC_ZERO_TIME); + } + else if (phase == BEGIN_RESP) + { + sendToTarget(payload, END_RESP, SC_ZERO_TIME); + receivedResponses.emplace(&payload); + sendNextResponse(); + } + + else + { + SC_REPORT_FATAL(0, "Payload event queue in arbiter was triggered with unknown phase"); + } + } + + void sendToTarget(tlm_generic_payload& payload, const tlm_phase& phase, const sc_time& delay) + { + tlm_phase TPhase = phase; + sc_time TDelay = delay; + iSocket->nb_transport_fw(payload, TPhase, TDelay); + } + + void sendToInitiator(tlm_generic_payload& payload, const tlm_phase& phase, const sc_time& delay) + { + tlm_phase TPhase = phase; + sc_time TDelay = delay; + tSocket->nb_transport_bw(payload, TPhase, TDelay); + } + + void sendNextResponse() + { + if(!responseIsPendingInInitator && receivedResponses.count(requestsInOrder.front())) + { + tlm_generic_payload* payloadToSend = requestsInOrder.front(); + requestsInOrder.pop_front(); + receivedResponses.erase(payloadToSend); + responseIsPendingInInitator = true; + sendToInitiator(payloadToSend,BEGIN_RESP,SC_ZERO_TIME); + } + } + +}; + + + + +#endif // REORDERBUFFER_H diff --git a/dram/src/simulation/Simulation.cpp b/dram/src/simulation/Simulation.cpp index 31507a77..48158a40 100644 --- a/dram/src/simulation/Simulation.cpp +++ b/dram/src/simulation/Simulation.cpp @@ -44,14 +44,15 @@ void Simulation::setupDebugManager(const string& traceName) { auto& dbg = DebugManager::getInstance(); -// dbg.addToWhiteList(controller->name()); -// dbg.addToWhiteList(player2->name()); -// dbg.addToWhiteList(player1->name()); -// dbg.addToWhiteList(this->name()); -// dbg.addToWhiteList(Scheduler::sendername); -// dbg.addToWhiteList(TlmRecorder::senderName); -// dbg.addToWhiteList(ControllerCore::senderName); -// dbg.addToWhiteList(PowerDownManagerBankwise::senderName); + dbg.addToWhiteList(controller->name()); + dbg.addToWhiteList(player2->name()); + dbg.addToWhiteList(player1->name()); + dbg.addToWhiteList(this->name()); + dbg.addToWhiteList(Scheduler::sendername); + dbg.addToWhiteList(TlmRecorder::senderName); + dbg.addToWhiteList(ControllerCore::senderName); + dbg.addToWhiteList(PowerDownManagerBankwise::senderName); + dbg.addToWhiteList(ReadWriteGrouper::senderName); dbg.writeToConsole = true; dbg.writeToFile = true; diff --git a/dram/src/simulation/Simulation.h b/dram/src/simulation/Simulation.h index 1075291f..7e1017ed 100644 --- a/dram/src/simulation/Simulation.h +++ b/dram/src/simulation/Simulation.h @@ -11,6 +11,7 @@ #include "Dram.h" #include "Arbiter.h" #include "TracePlayer.h" +#include "ReorderBuffer.h" #include "../controller/Controller.h" #include "ISimulation.h" #include From 15f07b00176e084ae535af13e8b2ca88bf176445 Mon Sep 17 00:00:00 2001 From: Janik Schlemminger Date: Tue, 5 Aug 2014 19:33:16 +0200 Subject: [PATCH 2/6] precharge allchecker tRas, simulation memory --- dram/resources/simulations/sim-batch.xml | 3 +- .../checker/PrechargeAllChecker.cpp | 6 ++ dram/src/simulation/Dram.h | 67 ++++--------------- 3 files changed, 21 insertions(+), 55 deletions(-) diff --git a/dram/resources/simulations/sim-batch.xml b/dram/resources/simulations/sim-batch.xml index 89adea06..b1f47a18 100644 --- a/dram/resources/simulations/sim-batch.xml +++ b/dram/resources/simulations/sim-batch.xml @@ -16,7 +16,8 @@ - small.stl + + chstone-sha_32.stl diff --git a/dram/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp b/dram/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp index 112d4f90..92820e76 100644 --- a/dram/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp +++ b/dram/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp @@ -53,6 +53,12 @@ void PrechargeAllChecker::delayToSatisfyConstraints(ScheduledCommand& command) c } } + ScheduledCommand lastActivate = state.getLastCommand(Command::Activate, command.getBank()); + if (lastActivate.isValidCommand()) + { + command.delayToMeetConstraint(lastActivate.getStart(), config.Timings.tRAS); + } + state.bus.moveCommandToNextFreeSlot(command); } diff --git a/dram/src/simulation/Dram.h b/dram/src/simulation/Dram.h index 22e48d74..ba252c55 100644 --- a/dram/src/simulation/Dram.h +++ b/dram/src/simulation/Dram.h @@ -30,7 +30,7 @@ using namespace core; using namespace Data; -#define POWER +#define POWER //not better to define in simulation xml? also flag for storage simulation #ifdef POWER #define IFPOW(x) x @@ -39,43 +39,6 @@ using namespace Data; #endif -class column -{ - private: - - unsigned char * data; - unsigned int bytes; - - public: - - column() - { - bytes = 0; - data = NULL; - } - - column(int bytes) - { - this->bytes = bytes; - data = new unsigned char[bytes]; - } - - ~column() - { - delete data; - } - - void set(unsigned char * payloadDataPtr) - { - memcpy(data, payloadDataPtr, bytes); - } - - void get(unsigned char * payloadDataPtr) - { - memcpy(payloadDataPtr, data, bytes); - } -}; - template struct Dram: sc_module @@ -83,7 +46,7 @@ struct Dram: sc_module tlm_utils::simple_target_socket tSocket; IFPOW(libDRAMPower *DRAMPower); - map< unsigned long int, column * > memory; + map< unsigned long int, unsigned char[BUSWIDTH/2] > memory; SC_CTOR(Dram) : tSocket("socket") { @@ -128,28 +91,24 @@ struct Dram: sc_module else if (phase == BEGIN_WR) { IFPOW(DRAMPower->doCommand(MemCommand::WR, bank, cycle)); + //save data: + memcpy(&memory[payload.get_address()], payload.get_data_ptr(), BUSWIDTH/8); sendToController(payload, END_WR, delay + getExecutionTime(Command::Write, payload)); - - // Save: - //column * c = new column(16); - //c->set(payload.get_data_ptr()); - //memory[payload.get_address()] = c; } else if (phase == BEGIN_RD) { IFPOW(DRAMPower->doCommand(MemCommand::RD, bank, cycle)); sendToController(payload, END_RD, delay + getExecutionTime(Command::Read, payload)); - // Load: - //if(memory.count(payload.get_address()) == 1) - //{ - // column * c = memory[payload.get_address()]; - // c->get(payload.get_data_ptr()); - //} - //else - //{ - // SC_REPORT_WARNING ("DRAM", "Reading from an empty memory location"); - //} + // Load data: + if(memory.count(payload.get_address()) == 1) + { + memcpy(payload.get_data_ptr(), &memory[payload.get_address()], BUSWIDTH/8); + } + else + { + SC_REPORT_WARNING ("DRAM", "Reading from an empty memory location."); + } } else if (phase == BEGIN_WRA) { From 0bba004266cf186480110cf1b6efbc36eae4c15c Mon Sep 17 00:00:00 2001 From: Robert Gernhardt Date: Wed, 6 Aug 2014 09:37:42 +0200 Subject: [PATCH 3/6] modified rd/write grouper --- dram/dramSys/dramSys.pro | 10 +- dram/resources/configs/memconfigs/fr_fcfs.xml | 5 +- dram/resources/simulations/sim-batch.xml | 2 +- dram/src/controller/Controller.h | 11 +- dram/src/controller/scheduler/Fr_Fcfs.cpp | 13 ++ dram/src/controller/scheduler/Fr_Fcfs.h | 2 + .../controller/scheduler/readwritegrouper.cpp | 193 +++++++++--------- .../controller/scheduler/readwritegrouper.h | 33 ++- dram/src/simulation/Simulation.cpp | 1 - 9 files changed, 146 insertions(+), 124 deletions(-) diff --git a/dram/dramSys/dramSys.pro b/dram/dramSys/dramSys.pro index 6ba44ef5..b521d493 100644 --- a/dram/dramSys/dramSys.pro +++ b/dram/dramSys/dramSys.pro @@ -8,15 +8,15 @@ LIBS += -L/opt/systemc/lib-linux64 -lsystemc LIBS += -L/opt/boost/lib -lboost_filesystem -lboost_system LIBS += -L/opt/sqlite3/lib -lsqlite3 LIBS += -lpthread -#LIBS += -lxerces-c -#LIBS += -L../src/common/third_party/DRAMPower/src/ -ldrampowerxml -#LIBS += -L../src/common/third_party/DRAMPower/src/ -ldrampower +LIBS += -L/opt/xerces/lib -lxerces-c +LIBS += -L../src/common/third_party/DRAMPower/src/ -ldrampowerxml +LIBS += -L../src/common/third_party/DRAMPower/src/ -ldrampower INCLUDEPATH += /opt/systemc/include INCLUDEPATH += /opt/boost/include INCLUDEPATH += /opt/sqlite3/include -#INCLUDEPATH += ../src/common/third_party/DRAMPower/src -#INCLUDEPATH += ../src/common/third_party/DRAMPower/src/libdrampower +INCLUDEPATH += ../src/common/third_party/DRAMPower/src +INCLUDEPATH += ../src/common/third_party/DRAMPower/src/libdrampower DEFINES += TIXML_USE_STL DEFINES += SC_INCLUDE_DYNAMIC_PROCESSES diff --git a/dram/resources/configs/memconfigs/fr_fcfs.xml b/dram/resources/configs/memconfigs/fr_fcfs.xml index b126adb1..9dd3c80c 100644 --- a/dram/resources/configs/memconfigs/fr_fcfs.xml +++ b/dram/resources/configs/memconfigs/fr_fcfs.xml @@ -1,6 +1,6 @@ - + @@ -9,7 +9,6 @@ - - + diff --git a/dram/resources/simulations/sim-batch.xml b/dram/resources/simulations/sim-batch.xml index a9e88a0b..f0aa5a30 100644 --- a/dram/resources/simulations/sim-batch.xml +++ b/dram/resources/simulations/sim-batch.xml @@ -10,7 +10,7 @@ - chstone-sha_32.stl + mediabench-epic_32.stl diff --git a/dram/src/controller/Controller.h b/dram/src/controller/Controller.h index 4c0f5a7d..ea8adc02 100644 --- a/dram/src/controller/Controller.h +++ b/dram/src/controller/Controller.h @@ -116,13 +116,10 @@ template void Controller::buildScheduler() { string selectedScheduler = Configuration::getInstance().Scheduler; + //selectedScheduler == "ReadWriteGrouper"; if (selectedScheduler == "FR_FCFS") { - - //Scheduler* s = new FR_FCFS(*controllerCore, Configuration::getInstance().RefreshAwareScheduling, - // Configuration::getInstance().AdaptiveOpenPagePolicy); - //scheduler = new ReadWriteGrouper(s); scheduler = new FR_FCFS(*controllerCore, Configuration::getInstance().RefreshAwareScheduling,Configuration::getInstance().AdaptiveOpenPagePolicy); } else if (selectedScheduler == "PAR_BS") @@ -131,7 +128,13 @@ void Controller::buildScheduler() Configuration::getInstance().Capsize); } else if (selectedScheduler == "FIFO") + { scheduler = new Fifo(*controllerCore); + } + else if (selectedScheduler == "ReadWriteGrouper") + { + scheduler = new ReadWriteGrouper(*controllerCore); + } else reportFatal(name(), "unsupported scheduler: " + selectedScheduler); } diff --git a/dram/src/controller/scheduler/Fr_Fcfs.cpp b/dram/src/controller/scheduler/Fr_Fcfs.cpp index 5635cc33..b0b6c159 100644 --- a/dram/src/controller/scheduler/Fr_Fcfs.cpp +++ b/dram/src/controller/scheduler/Fr_Fcfs.cpp @@ -97,6 +97,19 @@ unsigned int FR_FCFS::getNumberOfQueuedPayloads() return numberOfQueuedPaylods; } +bool FR_FCFS::containsPayloadTragetingSameAddress(gp *payload) +{ + Bank bank = DramExtension::getExtension(payload).getBank(); + Row row = DramExtension::getExtension(payload).getRow(); + + for(gp* bufferedPayload: buffer[bank]) + { + if(DramExtension::getExtension(bufferedPayload).getRow() == row) + return true; + } + return false; +} + std::vector FR_FCFS::findRowHits(Bank bank, Row row) { vector found; diff --git a/dram/src/controller/scheduler/Fr_Fcfs.h b/dram/src/controller/scheduler/Fr_Fcfs.h index ccfbf718..39446120 100644 --- a/dram/src/controller/scheduler/Fr_Fcfs.h +++ b/dram/src/controller/scheduler/Fr_Fcfs.h @@ -25,6 +25,8 @@ public: gp* popOldest(Bank bank); unsigned int getNumberOfQueuedPayloads(); + //used by read/write grouper + bool containsPayloadTragetingSameAddress(gp* payload); private: std::vector findRowHits(Bank bank, Row row); std::map> buffer; diff --git a/dram/src/controller/scheduler/readwritegrouper.cpp b/dram/src/controller/scheduler/readwritegrouper.cpp index efb202d4..b28057db 100644 --- a/dram/src/controller/scheduler/readwritegrouper.cpp +++ b/dram/src/controller/scheduler/readwritegrouper.cpp @@ -6,130 +6,139 @@ namespace scheduler{ using namespace tlm; using namespace std; -string ReadWriteGrouper::senderName = "ReadWriteGrouper"; - -ReadWriteGrouper::ReadWriteGrouper(Scheduler *scheduler): - scheduler(scheduler), mode(Mode::read) +ReadWriteGrouper::ReadWriteGrouper(core::ControllerCore& controllerCore): controllerCore(controllerCore) { - printDebugMessage("In read mode"); + batches.push_back(shared_ptr(new FR_FCFS(controllerCore,true,false))); + batches.push_back(shared_ptr(new FR_FCFS(controllerCore,true,false))); } ReadWriteGrouper::~ReadWriteGrouper() { - delete scheduler; + +} + +void ReadWriteGrouper::schedule(gp *payload) +{ + tlm_command command = payload->get_command(); + printDebugMessage("Scheduling new payload"); + + if(batches.size() > 2) + { + if(command == TLM_READ_COMMAND) + { + if(schedulingReadCausesHazardWithQueuedWrite(payload)) + { + printDebugMessage("Scheduling read causes hazard with queued write"); + batches.push_back(shared_ptr(new FR_FCFS(controllerCore,true,false))); + batches.push_back(shared_ptr(new FR_FCFS(controllerCore,true,false))); + } + + getLatestReadBatch().schedule(payload); + } + else if(command == TLM_WRITE_COMMAND) + { + getLatestWriteBatch().schedule(payload); + } + } + else if(batches.size() == 2) + { + if(command == TLM_READ_COMMAND) + { + if(getLatestReadBatch().hasPayloads() && schedulingReadCausesHazardWithQueuedWrite(payload)) + { + printDebugMessage("Scheduling read causes hazard with queued write"); + batches.push_back(shared_ptr(new FR_FCFS(controllerCore,true,false))); + batches.push_back(shared_ptr(new FR_FCFS(controllerCore,true,false))); + } + else if(!getLatestReadBatch().hasPayloads() && getLatestWriteBatch().hasPayloads()) + { + batches.erase(batches.begin()); + batches.push_back(shared_ptr(new FR_FCFS(controllerCore,true,false))); + batches.push_back(shared_ptr(new FR_FCFS(controllerCore,true,false))); + } + getLatestReadBatch().schedule(payload); + + } + else if(command == TLM_WRITE_COMMAND) + { + getLatestWriteBatch().schedule(payload); + } + } + else + { + sc_assert(false); + } +} + +gp *ReadWriteGrouper::getNextPayload() +{ + if(batches.size() > 2) + { + return batches.front()->getNextPayload(); + } + else if(batches.size() == 2) + { + if(getLatestReadBatch().hasPayloads()) + return getLatestReadBatch().getNextPayload(); + else if(getLatestWriteBatch().hasPayloads()) + return getLatestWriteBatch().getNextPayload(); + else + return NULL; + } + else + { + sc_assert(false); + } } void ReadWriteGrouper::removePayload(gp *payload) { - scheduler->removePayload(payload); - - //if scheduler is empty now - if(!scheduler->hasPayloads()) + if(batches.size() > 2) { - printDebugMessage("No more transactions in scheduler"); - - if((mode == Mode::read && !writeQueue.empty()) || mode == Mode::readToWrite) - switchToWriteMode(); + batches.front()->removePayload(payload); + if(!batches.front()->hasPayloads()) + batches.erase(batches.begin()); + } + else if(batches.size() == 2) + { + if(payload->is_read()) + getLatestReadBatch().removePayload(payload); else - switchToReadMode(); + getLatestWriteBatch().removePayload(payload); } -} - -void ReadWriteGrouper::schedule(gp *payload) -{ -tlm_command command = payload->get_command(); - -//in read mode hazards could occur by letting a read pass a queued write -if(mode == Mode::read) -{ - if(command == TLM_READ_COMMAND) + else { - //if scheduling the read would cause a hazard switch to readToWriteMode and put the read into the readQueue - if(schedulingReadCausesHazardWithQueuedWrite(payload)) - { - switchToReadToWriteMode(); - readQueue.push_back(payload); - } - else - scheduler->schedule(payload); - } - else if(command == TLM_WRITE_COMMAND) - { - writeQueue.push_back(payload); - if(!scheduler->hasPayloads()) - //there are no reads in the scheduler, so switch directly to write mode - switchToWriteMode(); + sc_assert(false); } } -else if(mode == Mode::readToWrite) -{ - if(command == TLM_READ_COMMAND) - readQueue.push_back(payload); - else if(command == TLM_WRITE_COMMAND) - writeQueue.push_back(payload); -} -else if(mode == Mode::write) -{ - if(command == TLM_READ_COMMAND) - readQueue.push_back(payload); - else if(command == TLM_WRITE_COMMAND) - scheduler->schedule(payload); -} -} - -gp *ReadWriteGrouper::getNextPayload() -{ - return scheduler->getNextPayload(); -} bool ReadWriteGrouper::hasPayloads() { - return scheduler->hasPayloads(); + if(batches.size() > 2) + return true; + else if(batches.size() == 2) + return (getLatestReadBatch().hasPayloads() || getLatestWriteBatch().hasPayloads()); + else + sc_assert(false); } bool ReadWriteGrouper::schedulingReadCausesHazardWithQueuedWrite(gp *payload) { sc_assert(payload->is_read()); - for(gp* write: writeQueue) - { - if(payload->get_address()==write->get_address()) - return true; - } - return false; + return getLatestWriteBatch().containsPayloadTragetingSameAddress(payload); } -void ReadWriteGrouper::switchToReadMode() +FR_FCFS &ReadWriteGrouper::getLatestWriteBatch() { - printDebugMessage("Switching to read mode"); - sc_assert(!scheduler->hasPayloads()); - mode = Mode::read; - for(gp* read: readQueue) - scheduler->schedule(read); - readQueue.clear(); + return *batches[batches.size()-1]; } -void ReadWriteGrouper::switchToWriteMode() +FR_FCFS &ReadWriteGrouper::getLatestReadBatch() { - printDebugMessage("Switching to write mode"); - sc_assert(!scheduler->hasPayloads()); - mode = Mode::write; - for(gp* write: writeQueue) - scheduler->schedule(write); - writeQueue.clear(); -} - -void ReadWriteGrouper::switchToReadToWriteMode() -{ - printDebugMessage("Switching to read-to-write-mode"); - mode = Mode::readToWrite; -} - -void printDebugMessage(string message) -{ - DebugManager::getInstance().printDebugMessage(ReadWriteGrouper::senderName, message); + return *batches[batches.size()-2]; } } diff --git a/dram/src/controller/scheduler/readwritegrouper.h b/dram/src/controller/scheduler/readwritegrouper.h index 9f5945f1..dedd0c5d 100644 --- a/dram/src/controller/scheduler/readwritegrouper.h +++ b/dram/src/controller/scheduler/readwritegrouper.h @@ -1,40 +1,37 @@ #ifndef READWRITEGROUPER_H #define READWRITEGROUPER_H #include "Scheduler.h" +#include "Fr_Fcfs.h" +#include "../core/ControllerCore.h" +#include #include + namespace scheduler{ -/* Scheduler that batches reads and writes to reduce the overhead when switching from - * read to write mode (read-to-write constraints) - * The scheduler prioritizes reads. It switches to write mode, when stalling a write would induce a data-hazard - * or when there are no reads to process. - */ class ReadWriteGrouper : public Scheduler { public: - ReadWriteGrouper(Scheduler *scheduler); + ReadWriteGrouper(core::ControllerCore& controllerCore); ~ReadWriteGrouper(); virtual void schedule(gp* payload) override; virtual bool hasPayloads() override; virtual gp* getNextPayload() override; virtual void removePayload(gp* payload) override; - static std::string senderName; - private: - Scheduler *scheduler; - std::vector readQueue, writeQueue; - //Mode readToWrite is used to process the remaining reads in the readScheduler before - //switching to write mode (this is used when a potential hazard causes the scheduler to switch modes) - enum class Mode{read,readToWrite, write}; - Mode mode; + // contains batches of requests + // last element always contains writes + // next-to-last element always contains reads + // there are always at least two batches + // if there are more than two batches, batches[0] is never empty and + // getNextPayload and removePayload are forwarded to batches[0] + std::vector> batches; + core::ControllerCore& controllerCore; bool schedulingReadCausesHazardWithQueuedWrite(gp* payload); - void switchToReadMode(); - void switchToWriteMode(); - void switchToReadToWriteMode(); - void printDebugMessage(std::string message); + FR_FCFS& getLatestWriteBatch(); + FR_FCFS& getLatestReadBatch(); }; diff --git a/dram/src/simulation/Simulation.cpp b/dram/src/simulation/Simulation.cpp index 48158a40..7607bdbd 100644 --- a/dram/src/simulation/Simulation.cpp +++ b/dram/src/simulation/Simulation.cpp @@ -52,7 +52,6 @@ void Simulation::setupDebugManager(const string& traceName) dbg.addToWhiteList(TlmRecorder::senderName); dbg.addToWhiteList(ControllerCore::senderName); dbg.addToWhiteList(PowerDownManagerBankwise::senderName); - dbg.addToWhiteList(ReadWriteGrouper::senderName); dbg.writeToConsole = true; dbg.writeToFile = true; From 47580bcba370bc894c6cbe8383cf23ed22a2c4da Mon Sep 17 00:00:00 2001 From: Janik Schlemminger Date: Wed, 6 Aug 2014 10:30:49 +0200 Subject: [PATCH 4/6] added read/write grouper memconfig --- dram/resources/configs/memconfigs/fr_fcfs.xml | 2 +- dram/resources/simulations/sim-batch.xml | 3 ++- dram/src/controller/Controller.h | 3 +-- dram/src/controller/scheduler/Scheduler.cpp | 4 ++-- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/dram/resources/configs/memconfigs/fr_fcfs.xml b/dram/resources/configs/memconfigs/fr_fcfs.xml index 9dd3c80c..8aa70731 100644 --- a/dram/resources/configs/memconfigs/fr_fcfs.xml +++ b/dram/resources/configs/memconfigs/fr_fcfs.xml @@ -9,6 +9,6 @@ - + diff --git a/dram/resources/simulations/sim-batch.xml b/dram/resources/simulations/sim-batch.xml index a5a1c593..b8df13be 100644 --- a/dram/resources/simulations/sim-batch.xml +++ b/dram/resources/simulations/sim-batch.xml @@ -5,12 +5,13 @@ fr_fcfs.xml + grouper.xml - mediabench-epic_32.stl + mediabench-fractal_32.stl diff --git a/dram/src/controller/Controller.h b/dram/src/controller/Controller.h index a7505976..e40f8ade 100644 --- a/dram/src/controller/Controller.h +++ b/dram/src/controller/Controller.h @@ -116,7 +116,6 @@ template void Controller::buildScheduler() { string selectedScheduler = Configuration::getInstance().Scheduler; - selectedScheduler = "ReadWriteGrouper"; if (selectedScheduler == "FR_FCFS") { @@ -131,7 +130,7 @@ void Controller::buildScheduler() { scheduler = new Fifo(*controllerCore); } - else if (selectedScheduler == "ReadWriteGrouper") + else if (selectedScheduler == "Grouper") { scheduler = new ReadWriteGrouper(*controllerCore); } diff --git a/dram/src/controller/scheduler/Scheduler.cpp b/dram/src/controller/scheduler/Scheduler.cpp index f86a59d0..a872e821 100644 --- a/dram/src/controller/scheduler/Scheduler.cpp +++ b/dram/src/controller/scheduler/Scheduler.cpp @@ -10,7 +10,7 @@ std::string Scheduler::sendername = "scheduler"; void Scheduler::printDebugMessage(std::string message) { - cout << "scheduler: " << message << std::endl; - //DebugManager::getInstance().printDebugMessage(Scheduler::sendername, message); + //cout << "scheduler: " << message << std::endl; + DebugManager::getInstance().printDebugMessage(Scheduler::sendername, message); } From b1142c4796fdc1dcb04e2a1ed8d2a64f2337d608 Mon Sep 17 00:00:00 2001 From: Robert Gernhardt Date: Thu, 7 Aug 2014 12:06:04 +0200 Subject: [PATCH 5/6] traceplayer can now parse data of write commands. Reorder buffer inserted --- dram/resources/simulations/sim-batch.xml | 4 +- dram/src/simulation/Arbiter.h | 12 +- dram/src/simulation/Arbiter.h.autosave | 163 ------------------- dram/src/simulation/ReorderBuffer.h | 28 +++- dram/src/simulation/Simulation.cpp | 6 +- dram/src/simulation/Simulation.h | 1 + dram/src/simulation/TracePlayer.h | 192 ++++++++++++++++------- 7 files changed, 168 insertions(+), 238 deletions(-) delete mode 100644 dram/src/simulation/Arbiter.h.autosave diff --git a/dram/resources/simulations/sim-batch.xml b/dram/resources/simulations/sim-batch.xml index b8df13be..73734388 100644 --- a/dram/resources/simulations/sim-batch.xml +++ b/dram/resources/simulations/sim-batch.xml @@ -5,8 +5,8 @@ fr_fcfs.xml - grouper.xml - + diff --git a/dram/src/simulation/Arbiter.h b/dram/src/simulation/Arbiter.h index e21af2ec..b7421545 100644 --- a/dram/src/simulation/Arbiter.h +++ b/dram/src/simulation/Arbiter.h @@ -48,7 +48,7 @@ private: //used to account for the request_accept_delay in the dram controllers deque pendingRequests; //used to account for the response_accept_delay in the initiators (traceplayer,core etc.) - deque pendingResponses[NUMBER_OF_THREADS]; + deque receivedResponses[NUMBER_OF_THREADS]; // Initiated by dram side tlm_sync_enum nb_transport_bw(tlm_generic_payload& payload, tlm_phase& phase, sc_time& bwDelay) @@ -98,10 +98,10 @@ private: else if (phase == END_RESP) { sendToChannel(payload, phase, SC_ZERO_TIME); - pendingResponses[initiatorSocket].pop_front(); - if(!pendingResponses[initiatorSocket].empty()) + receivedResponses[initiatorSocket].pop_front(); + if(!receivedResponses[initiatorSocket].empty()) { - tlm_generic_payload* payloadToSend = pendingResponses[initiatorSocket].front(); + tlm_generic_payload* payloadToSend = receivedResponses[initiatorSocket].front(); sendToInitiator(initiatorSocket,*payloadToSend,BEGIN_RESP,SC_ZERO_TIME); } } @@ -122,9 +122,9 @@ private: } else if (phase == BEGIN_RESP) { - if(pendingResponses[initiatorSocket].empty()) + if(receivedResponses[initiatorSocket].empty()) sendToInitiator(initiatorSocket, payload, phase, SC_ZERO_TIME); - pendingResponses[initiatorSocket].push_back(&payload); + receivedResponses[initiatorSocket].push_back(&payload); } else diff --git a/dram/src/simulation/Arbiter.h.autosave b/dram/src/simulation/Arbiter.h.autosave deleted file mode 100644 index b7421545..00000000 --- a/dram/src/simulation/Arbiter.h.autosave +++ /dev/null @@ -1,163 +0,0 @@ -/* - * arbiter.h - * - * Created on: Mar 16, 2014 - * Author: robert - */ - -#ifndef ARBITER_H_ -#define ARBITER_H_ - - -#include -#include -#include -#include -#include -#include -#include "../common/xmlAddressdecoder.h" -#include "../common/dramExtension.h" -#include "../controller/core/TimingCalculation.h" -#include - - -using namespace std; -using namespace tlm; - -template -struct Arbiter: public sc_module -{ -public: - tlm_utils::simple_initiator_socket iSocket; - tlm_utils::simple_target_socket_tagged tSockets[NUMBER_OF_THREADS]; - - SC_CTOR(Arbiter) : - payloadEventQueue(this, &Arbiter::peqCallback), channelIsFree(true) - { - iSocket.register_nb_transport_bw(this, &Arbiter::nb_transport_bw); - - for (unsigned int i = 0; i < NUMBER_OF_THREADS; ++i) - { - tSockets[i].register_nb_transport_fw(this, &Arbiter::nb_transport_fw, i); - } - } - -private: - tlm_utils::peq_with_cb_and_phase payloadEventQueue; - bool channelIsFree; - //used to account for the request_accept_delay in the dram controllers - deque pendingRequests; - //used to account for the response_accept_delay in the initiators (traceplayer,core etc.) - deque receivedResponses[NUMBER_OF_THREADS]; - - // Initiated by dram side - tlm_sync_enum nb_transport_bw(tlm_generic_payload& payload, tlm_phase& phase, sc_time& bwDelay) - { - TlmRecorder::getInstance().recordPhase(payload, phase, bwDelay + sc_time_stamp()); - payloadEventQueue.notify(payload, phase, bwDelay); - return TLM_ACCEPTED; - } - - // Initiated by initiator side - tlm_sync_enum nb_transport_fw(int socketId, tlm_generic_payload& payload, tlm_phase& phase, - sc_time& fwDelay) - { - if(phase == BEGIN_REQ) - { - appendDramExtension(socketId, payload); - payload.acquire(); - } - else if(phase == END_RESP) - { - payload.release(); - } - - payloadEventQueue.notify(payload, phase, fwDelay); - return TLM_ACCEPTED; - } - - void peqCallback(tlm_generic_payload& payload, const tlm_phase& phase) - { - unsigned int initiatorSocket = DramExtension::getExtension(payload).getThread().ID()-1; - - - //Phases initiated by intiator side - if (phase == BEGIN_REQ) - { - if(channelIsFree) - { - channelIsFree = false; - sendToChannel(payload, phase, SC_ZERO_TIME ); - } - else - { - pendingRequests.push_back(&payload); - } - } - - else if (phase == END_RESP) - { - sendToChannel(payload, phase, SC_ZERO_TIME); - receivedResponses[initiatorSocket].pop_front(); - if(!receivedResponses[initiatorSocket].empty()) - { - tlm_generic_payload* payloadToSend = receivedResponses[initiatorSocket].front(); - sendToInitiator(initiatorSocket,*payloadToSend,BEGIN_RESP,SC_ZERO_TIME); - } - } - - //Phases initiated by dram side - else if (phase == END_REQ) - { - channelIsFree = true; - sendToInitiator(initiatorSocket, payload, phase, SC_ZERO_TIME); - - if(!pendingRequests.empty()) - { - tlm_generic_payload* payloadToSend = pendingRequests.front(); - pendingRequests.pop_front(); - sendToChannel(*payloadToSend, BEGIN_REQ, SC_ZERO_TIME ); - channelIsFree = false; - } - } - else if (phase == BEGIN_RESP) - { - if(receivedResponses[initiatorSocket].empty()) - sendToInitiator(initiatorSocket, payload, phase, SC_ZERO_TIME); - receivedResponses[initiatorSocket].push_back(&payload); - } - - else - { - SC_REPORT_FATAL(0, "Payload event queue in arbiter was triggered with unknown phase"); - } - } - - void sendToChannel(tlm_generic_payload& payload, const tlm_phase& phase, const sc_time& delay) - { - tlm_phase TPhase = phase; - sc_time TDelay = delay; - iSocket->nb_transport_fw(payload, TPhase, TDelay); - } - - void sendToInitiator(unsigned int id, tlm_generic_payload& payload, const tlm_phase& phase, const sc_time& delay) - { - tlm_phase TPhase = phase; - sc_time TDelay = delay; - tSockets[id]->nb_transport_bw(payload, TPhase, TDelay); - } - - void appendDramExtension(int socketId, tlm_generic_payload& payload) - { - unsigned int burstlength = payload.get_streaming_width(); - DecodedAddress decodedAddress = xmlAddressDecoder::getInstance().decodeAddress(payload.get_address()); - DramExtension* extension = new DramExtension(Thread(socketId+1), Channel(0), Bank(decodedAddress.bank), - BankGroup(decodedAddress.bankgroup), Row(decodedAddress.row), Column(decodedAddress.column),burstlength); - payload.set_auto_extension(extension); - } -}; - - - - -#endif /* ARBITER_H_ */ diff --git a/dram/src/simulation/ReorderBuffer.h b/dram/src/simulation/ReorderBuffer.h index d1ce1fff..82a74b4b 100644 --- a/dram/src/simulation/ReorderBuffer.h +++ b/dram/src/simulation/ReorderBuffer.h @@ -13,7 +13,7 @@ struct ReorderBuffer: public sc_module { public: tlm_utils::simple_initiator_socket iSocket; - tlm_utils::simple_target_socket_tagged tSocket; + tlm_utils::simple_target_socket tSocket; SC_CTOR(ReorderBuffer) : payloadEventQueue(this, &ReorderBuffer::peqCallback), responseIsPendingInInitator(false) @@ -24,7 +24,7 @@ public: private: tlm_utils::peq_with_cb_and_phase payloadEventQueue; - deque requestsInOrder; + deque pendingRequestsInOrder; set receivedResponses; bool responseIsPendingInInitator; @@ -59,13 +59,15 @@ private: //Phases initiated by initiator side if (phase == BEGIN_REQ) { - requestsInOrder.push_back(&payload); + pendingRequestsInOrder.push_back(&payload); sendToTarget(payload, phase, SC_ZERO_TIME ); } else if (phase == END_RESP) { responseIsPendingInInitator = false; + pendingRequestsInOrder.pop_front(); + receivedResponses.erase(&payload); sendNextResponse(); } @@ -81,6 +83,7 @@ private: sendNextResponse(); } + else { SC_REPORT_FATAL(0, "Payload event queue in arbiter was triggered with unknown phase"); @@ -96,6 +99,11 @@ private: void sendToInitiator(tlm_generic_payload& payload, const tlm_phase& phase, const sc_time& delay) { + + + sc_assert(phase == END_REQ || + (phase == BEGIN_RESP && pendingRequestsInOrder.front() == &payload && receivedResponses.count(&payload))); + tlm_phase TPhase = phase; sc_time TDelay = delay; tSocket->nb_transport_bw(payload, TPhase, TDelay); @@ -103,14 +111,18 @@ private: void sendNextResponse() { - if(!responseIsPendingInInitator && receivedResponses.count(requestsInOrder.front())) + //only send the next response when there response for the oldest pending request (requestsInOrder.front()) + //has been received + if(!responseIsPendingInInitator && receivedResponses.count(pendingRequestsInOrder.front())) { - tlm_generic_payload* payloadToSend = requestsInOrder.front(); - requestsInOrder.pop_front(); - receivedResponses.erase(payloadToSend); + tlm_generic_payload* payloadToSend = pendingRequestsInOrder.front(); responseIsPendingInInitator = true; - sendToInitiator(payloadToSend,BEGIN_RESP,SC_ZERO_TIME); + sendToInitiator(*payloadToSend,BEGIN_RESP,SC_ZERO_TIME); } +// else if(!responseIsPendingInInitator && receivedResponses.size()>0 && !receivedResponses.count(pendingRequestsInOrder.front())>0) +// { +// cout << "cant send this response, because we are still waiting for response of oldest pending request. Elemts in buffer: " << receivedResponses.size() << endl; +// } } }; diff --git a/dram/src/simulation/Simulation.cpp b/dram/src/simulation/Simulation.cpp index 7607bdbd..019fb56a 100644 --- a/dram/src/simulation/Simulation.cpp +++ b/dram/src/simulation/Simulation.cpp @@ -82,6 +82,7 @@ void Simulation::instantiateModules(const string &pathToResources, const std::ve dram = new Dram<>("dram"); arbiter = new Arbiter("arbiter"); controller = new Controller<>("controller"); + reorder = new ReorderBuffer<>("reorder"); player1 = new TracePlayer<>("player1", pathToResources + string("traces/") + devices[0].trace, devices[0].burstLength, devices[0].clkMhz, this); player2 = new TracePlayer<>("player2", pathToResources + string("traces/") + devices[1].trace, devices[1].burstLength, devices[1].clkMhz, this); @@ -91,7 +92,10 @@ void Simulation::instantiateModules(const string &pathToResources, const std::ve void Simulation::bindSockets() { - player1->iSocket.bind(arbiter->tSockets[0]); + //player1->iSocket.bind(arbiter->tSockets[0]); + player1->iSocket.bind(reorder->tSocket); + reorder->iSocket.bind(arbiter->tSockets[0]); + player2->iSocket.bind(arbiter->tSockets[1]); player3->iSocket.bind(arbiter->tSockets[2]); player4->iSocket.bind(arbiter->tSockets[3]); diff --git a/dram/src/simulation/Simulation.h b/dram/src/simulation/Simulation.h index 7e1017ed..8b4d5dc0 100644 --- a/dram/src/simulation/Simulation.h +++ b/dram/src/simulation/Simulation.h @@ -62,6 +62,7 @@ private: Dram<> *dram; Arbiter *arbiter; Controller<> *controller; + ReorderBuffer<> *reorder; TracePlayer<> *player1; TracePlayer<> *player2; diff --git a/dram/src/simulation/TracePlayer.h b/dram/src/simulation/TracePlayer.h index 0e604822..db699b53 100644 --- a/dram/src/simulation/TracePlayer.h +++ b/dram/src/simulation/TracePlayer.h @@ -33,7 +33,7 @@ struct TracePlayer: public sc_module public: tlm_utils::simple_initiator_socket iSocket; TracePlayer(sc_module_name /*name*/, string pathToTrace, unsigned int burstLength, unsigned int clkMhz, - simulation::ISimulation* simulationManager); + simulation::ISimulation* simulationManager); void start(); @@ -85,72 +85,148 @@ void TracePlayer::start() template void TracePlayer::generateNextPayload() { - if (file) + + if(file) { - string time, command, address, data; - file >> time >> command >> address; - - //if there is a newline at the end of the .stl - if (time.empty() || command.empty() || address.empty() ) - return; - - long parsedAdress = std::stoi(address.c_str(), 0, 16); - - gp* payload = memoryManager.allocate(); - payload->set_address(parsedAdress); - - // Set data pointer - unsigned char * dataElement = new unsigned char[16]; // TODO: column / burst breite - payload->set_data_length(16); // TODO: column / burst breite - payload->set_data_ptr(dataElement); - for(int i = 0; i < 16; i++) // TODO: column / burst breite - dataElement[i] = 0; - - if (command == "read") + string line; + if (std::getline(file, line)) { - payload->set_command(TLM_READ_COMMAND); - } - else if (command == "write") - { - payload->set_command(TLM_WRITE_COMMAND); + std::istringstream iss(line); + string time, command, address; + iss >> time >> command >> address; + if (time.empty() || command.empty() || address.empty() ) + return; + long parsedAdress = std::stoi(address.c_str(), 0, 16); - // Parse and set data -// file >> data; -// unsigned int counter = 0; -// for(int i = 0; i < 16*2-2; i=i+2) // TODO column / burst breite -// { -// std::string byteString = "0x"; -// byteString.append(data.substr(i+2, 2)); -// //cout << byteString << " " << std::stoi(byteString.c_str(), 0, 16) << endl; -// dataElement[counter++] = std::stoi(byteString.c_str(), 0, 16); -// } - } - else - { - SC_REPORT_FATAL(0, - (string("Corrupted tracefile, command ") + command + string(" unknown")).c_str()); - } + gp* payload = memoryManager.allocate(); + payload->set_address(parsedAdress); - payload->set_response_status(TLM_INCOMPLETE_RESPONSE); - payload->set_dmi_allowed(false); - payload->set_byte_enable_length(0); - payload->set_streaming_width(burstlenght); + // Set data pointer + unsigned char * dataElement = new unsigned char[16]; // TODO: column / burst breite + payload->set_data_length(16); // TODO: column / burst breite + payload->set_data_ptr(dataElement); + for(int i = 0; i < 16; i++) // TODO: column / burst breite + dataElement[i] = 0; - sc_time sendingTime = std::stoi(time.c_str())*clk; - GenerationExtension* genExtension = new GenerationExtension(sendingTime); - payload->set_auto_extension(genExtension); + if (command == "read") + { + payload->set_command(TLM_READ_COMMAND); + } + else if (command == "write") + { + payload->set_command(TLM_WRITE_COMMAND); + + // Parse and set data + string data; + iss >> data; + + if(!data.empty()) + { + //cout << "parsing write data: " << data << std::endl; + + for(int i = 0; i < 16; i++) // TODO column / burst breite + { + std::string byteString = "0x"; + byteString.append(data.substr(2*(i+1), 2)); + //cout << byteString << " " << std::stoi(byteString.c_str(), 0, 16) << endl; + dataElement[i] = std::stoi(byteString.c_str(), 0, 16); + } + } + } + else + { + SC_REPORT_FATAL(0, + (string("Corrupted tracefile, command ") + command + string(" unknown")).c_str()); + } + + payload->set_response_status(TLM_INCOMPLETE_RESPONSE); + payload->set_dmi_allowed(false); + payload->set_byte_enable_length(0); + payload->set_streaming_width(burstlenght); + + sc_time sendingTime = std::stoi(time.c_str())*clk; + GenerationExtension* genExtension = new GenerationExtension(sendingTime); + payload->set_auto_extension(genExtension); + + if (sendingTime <= sc_time_stamp()) + { + payloadEventQueue.notify(*payload, BEGIN_REQ, SC_ZERO_TIME); + } + else + { + payloadEventQueue.notify(*payload, BEGIN_REQ, sendingTime - sc_time_stamp()); + } + numberOfPendingTransactions++; - if (sendingTime <= sc_time_stamp()) - { - payloadEventQueue.notify(*payload, BEGIN_REQ, SC_ZERO_TIME); } - else - { - payloadEventQueue.notify(*payload, BEGIN_REQ, sendingTime - sc_time_stamp()); - } - numberOfPendingTransactions++; } } + // if (file) + // { + // string time, command, address, data; + // file >> time >> command >> address; + + // //if there is a newline at the end of the .stl + // if (time.empty() || command.empty() || address.empty() ) + // return; + + // long parsedAdress = std::stoi(address.c_str(), 0, 16); + + // gp* payload = memoryManager.allocate(); + // payload->set_address(parsedAdress); + + // // Set data pointer + // unsigned char * dataElement = new unsigned char[16]; // TODO: column / burst breite + // payload->set_data_length(16); // TODO: column / burst breite + // payload->set_data_ptr(dataElement); + // for(int i = 0; i < 16; i++) // TODO: column / burst breite + // dataElement[i] = 0; + + // if (command == "read") + // { + // payload->set_command(TLM_READ_COMMAND); + // } + // else if (command == "write") + // { + // payload->set_command(TLM_WRITE_COMMAND); + + // // Parse and set data + //// file >> data; + //// unsigned int counter = 0; + //// for(int i = 0; i < 16*2-2; i=i+2) // TODO column / burst breite + //// { + //// std::string byteString = "0x"; + //// byteString.append(data.substr(i+2, 2)); + //// //cout << byteString << " " << std::stoi(byteString.c_str(), 0, 16) << endl; + //// dataElement[counter++] = std::stoi(byteString.c_str(), 0, 16); + //// } + // } + // else + // { + // SC_REPORT_FATAL(0, + // (string("Corrupted tracefile, command ") + command + string(" unknown")).c_str()); + // } + + // payload->set_response_status(TLM_INCOMPLETE_RESPONSE); + // payload->set_dmi_allowed(false); + // payload->set_byte_enable_length(0); + // payload->set_streaming_width(burstlenght); + + // sc_time sendingTime = std::stoi(time.c_str())*clk; + // GenerationExtension* genExtension = new GenerationExtension(sendingTime); + // payload->set_auto_extension(genExtension); + + // if (sendingTime <= sc_time_stamp()) + // { + // payloadEventQueue.notify(*payload, BEGIN_REQ, SC_ZERO_TIME); + // } + // else + // { + // payloadEventQueue.notify(*payload, BEGIN_REQ, sendingTime - sc_time_stamp()); + // } + // numberOfPendingTransactions++; + // } +//} template tlm_sync_enum TracePlayer::nb_transport_bw(tlm_generic_payload &payload, tlm_phase &phase, sc_time &bwDelay) From 8e29063f76e7a7b72c960f261e2f8137964c57e6 Mon Sep 17 00:00:00 2001 From: Robert Gernhardt Date: Thu, 7 Aug 2014 12:11:48 +0200 Subject: [PATCH 6/6] added config for read/write grouper --- dram/resources/simulations/sim-batch.xml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/dram/resources/simulations/sim-batch.xml b/dram/resources/simulations/sim-batch.xml index 73734388..516578e6 100644 --- a/dram/resources/simulations/sim-batch.xml +++ b/dram/resources/simulations/sim-batch.xml @@ -4,9 +4,9 @@ am_wideio.xml - fr_fcfs.xml - + grouper.xml +