From addb7aae31c1be00845c96b705a39315c25ecc69 Mon Sep 17 00:00:00 2001 From: Iron Prando da Silva Date: Fri, 11 Mar 2022 10:00:24 +0100 Subject: [PATCH] Added DDR5 dependencies. Must be double checked. --- DRAMSys/traceAnalyzer/CMakeLists.txt | 4 + .../configurations/configurationfactory.cpp | 9 + .../configurations/configurationfactory.h | 1 + .../specialized/DDR5Configuration.cpp | 16 + .../specialized/DDR5Configuration.h | 14 + .../specialized/DDR5dbphaseentry.cpp | 55 +++ .../dbEntries/specialized/DDR5dbphaseentry.h | 18 + .../specialized/TimeDependenciesInfoDDR5.cpp | 373 ++++++++++++++++++ .../specialized/TimeDependenciesInfoDDR5.h | 109 +++++ .../phasedependenciestracker.cpp | 2 +- 10 files changed, 600 insertions(+), 1 deletion(-) create mode 100644 DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR5Configuration.cpp create mode 100644 DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR5Configuration.h create mode 100644 DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.cpp create mode 100644 DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.h create mode 100644 DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.cpp create mode 100644 DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.h diff --git a/DRAMSys/traceAnalyzer/CMakeLists.txt b/DRAMSys/traceAnalyzer/CMakeLists.txt index 13130e54..e9b0da4e 100644 --- a/DRAMSys/traceAnalyzer/CMakeLists.txt +++ b/DRAMSys/traceAnalyzer/CMakeLists.txt @@ -136,6 +136,10 @@ add_executable(TraceAnalyzer businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR4.cpp businessObjects/dramTimeDependencies/configurations/specialized/LPDDR4Configuration.cpp + businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.cpp + businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.cpp + businessObjects/dramTimeDependencies/configurations/specialized/DDR5Configuration.cpp + businessObjects/dramTimeDependencies/configurations/configurationfactory.cpp businessObjects/dramTimeDependencies/phasedependenciestracker.cpp diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationfactory.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationfactory.cpp index 6700934b..9d731976 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationfactory.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationfactory.cpp @@ -50,6 +50,9 @@ std::shared_ptr ConfigurationFactory::make(const TraceDB& tdb) } else if (deviceName == "LPDDR4") { return std::make_shared(tdb); + } else if (deviceName == "DDR5") { + return std::make_shared(tdb); + } else { // TODO maybe throw? throw std::invalid_argument("Could not find the device type '" + deviceName.toStdString() + '\''); @@ -74,6 +77,9 @@ const std::vector ConfigurationFactory::possiblePhases(const TraceDB& t } else if (deviceName == "LPDDR4") { return TimeDependenciesInfoLPDDR4::getPossiblePhases(); + } else if (deviceName == "DDR5") { + return TimeDependenciesInfoDDR5::getPossiblePhases(); + } else { // TODO maybe throw? // throw std::invalid_argument("Could not find the device type '" + deviceName.toStdString() + '\''); @@ -98,6 +104,9 @@ bool ConfigurationFactory::deviceSupported(const TraceDB& tdb) { } else if (deviceName == "LPDDR4") { return true; + } else if (deviceName == "DDR5") { + return true; + } else { return false; } diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationfactory.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationfactory.h index 4198a68a..7b252277 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationfactory.h +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationfactory.h @@ -43,6 +43,7 @@ #include "specialized/DDR4Configuration.h" #include "specialized/HBM2Configuration.h" #include "specialized/LPDDR4Configuration.h" +#include "specialized/DDR5Configuration.h" #include "data/tracedb.h" diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR5Configuration.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR5Configuration.cpp new file mode 100644 index 00000000..a5b412ee --- /dev/null +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR5Configuration.cpp @@ -0,0 +1,16 @@ + +#include "DDR5Configuration.h" +#include + +DDR5Configuration::DDR5Configuration(const TraceDB& tdb) { + mDeviceDeps = std::make_shared(std::forward(mGetMemspec(tdb)), mGetClk(tdb)); + +} + +std::shared_ptr DDR5Configuration::makePhaseEntry(const QSqlQuery& query) const { + auto phase = std::make_shared(query); + + std::dynamic_pointer_cast(mDeviceDeps)->rankIDToRankIDs(phase->tRank, phase->tLogicalRank, phase->tPhysicalRank, phase->tDIMMRank); + + return phase; +} diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR5Configuration.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR5Configuration.h new file mode 100644 index 00000000..e1ca0634 --- /dev/null +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR5Configuration.h @@ -0,0 +1,14 @@ + +#pragma once + +#include "businessObjects/dramTimeDependencies/configurations/configurationIF.h" +#include "businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.h" +#include "businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.h" + +class DDR5Configuration : public ConfigurationIF { + public: + DDR5Configuration(const TraceDB& tdb); + + std::shared_ptr makePhaseEntry(const QSqlQuery&) const override; + +}; diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.cpp new file mode 100644 index 00000000..b7533b8f --- /dev/null +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.cpp @@ -0,0 +1,55 @@ + +#include "DDR5dbphaseentry.h" + +DDR5DBPhaseEntry::DDR5DBPhaseEntry(const QSqlQuery& query) { + id = query.value(0).toLongLong(); + phaseName = StringMapper(query.value(1).toString()); + phaseBegin = query.value(2).toLongLong(); + phaseEnd = query.value(3).toLongLong(); + transact = query.value(4).toLongLong(); + tBank = query.value(5).toLongLong(); + tBankgroup = query.value(6).toLongLong(); + tRank = query.value(7).toLongLong(); +} + +bool DDR5DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) const { + auto other = std::dynamic_pointer_cast(otherPhase); + if (!other) return false; + + bool isCmdPool = dep.phaseDep == StringMapper::Identifier::CMD_BUS; + + bool const skipOnIntraBankAndDifferentBanks = { + dep.depType == DependencyType::IntraBank + && tBank != other->tBank + }; + bool const skipOnIntraBankgroupAndDifferentBankgroup = { + dep.depType == DependencyType::IntraBankGroup + && tBankgroup != other->tBankgroup + }; + bool const skipOnIntraLogRankAndDifferentRanks = { + dep.depType == DependencyType::IntraLogicalRank + && tLogicalRank != other->tLogicalRank + }; + bool const skipOnIntraPhysRankAndDifferentRanks = { + dep.depType == DependencyType::IntraPhysicalRank + && tPhysicalRank != other->tPhysicalRank + }; + bool const skipOnIntraDIMMRankAndDifferentRanks = { + dep.depType == DependencyType::IntraDIMMRank + && tDIMMRank != other->tDIMMRank + }; + bool const skipOnInterDIMMRankAndSameRank = { + dep.depType == DependencyType::InterDIMMRank + && tDIMMRank == other->tDIMMRank + && !isCmdPool + }; + + return !( + skipOnIntraBankAndDifferentBanks + || skipOnIntraBankgroupAndDifferentBankgroup + || skipOnIntraLogRankAndDifferentRanks + || skipOnIntraPhysRankAndDifferentRanks + || skipOnIntraDIMMRankAndDifferentRanks + || skipOnInterDIMMRankAndSameRank + ); +} diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.h new file mode 100644 index 00000000..19b35540 --- /dev/null +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.h @@ -0,0 +1,18 @@ + +#pragma once + +#include "businessObjects/dramTimeDependencies/dbEntries/dbphaseentryIF.h" + +class DDR5DBPhaseEntry : public DBPhaseEntryIF { + public: + DDR5DBPhaseEntry(const QSqlQuery&); + + size_t tBankgroup; + size_t tRank; + + size_t tLogicalRank; + size_t tPhysicalRank; + size_t tDIMMRank; + + bool potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) const override; +}; diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.cpp new file mode 100644 index 00000000..098b973d --- /dev/null +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.cpp @@ -0,0 +1,373 @@ +/* Generated by JetBrains MPS */ + +#include "TimeDependenciesInfoDDR5.h" +#include + +using namespace std; + +TimeDependenciesInfoDDR5::TimeDependenciesInfoDDR5(const QJsonObject& memspec, const uint tCK) : DRAMTimeDependenciesIF(memspec, tCK) { + mInitializeValues(); + + mBitsDIMMRanks = ceil(log2(mNumOfDIMMRanks)); + mBitsPhysicalRanks = ceil(log2(mNumOfPhysicalRanks)); + mBitsLogicalRanks = ceil(log2(mNumOfLogicalRanks)); + + mLogRankMask = (1 << mBitsLogicalRanks) - 1; + mPhysRankMask = ((1 << mBitsPhysicalRanks) - 1) << mBitsLogicalRanks; + mDIMMRankMask = ((1 << mBitsDIMMRanks) - 1) << mBitsPhysicalRanks << mBitsLogicalRanks; +} + +void TimeDependenciesInfoDDR5::rankIDToRankIDs(size_t rankID, size_t& dimmRID, size_t& physRID, size_t& logRID) const { + logRID = (rankID & mLogRankMask); + physRID = (rankID & mPhysRankMask) >> mBitsLogicalRanks; + dimmRID = (rankID & mDIMMRankMask) >> mBitsPhysicalRanks >> mBitsLogicalRanks; +} + +void TimeDependenciesInfoDDR5::mInitializeValues() { + mNumOfRanks = mMemspecJson["memarchitecturespec"].toObject()["nbrOfRanks"].toInt(); + mNumOfDIMMRanks = mMemspecJson["memarchitecturespec"].toObject()["nbrOfDIMMRanks"].toInt(); + mNumOfPhysicalRanks = mMemspecJson["memarchitecturespec"].toObject()["nbrOfPhysicalRanks"].toInt(); + mNumOfLogicalRanks = mMemspecJson["memarchitecturespec"].toObject()["nbrOfLogicalRanks"].toInt(); + + burstLength = mMemspecJson["memarchitecturespec"].toObject()["burstLength"].toInt(); + dataRate = mMemspecJson["memarchitecturespec"].toObject()["dataRate"].toInt(); + refMode = mMemspecJson["memarchitecturespec"].toObject()["refMode"].toInt(); + + mPools.insert({ + "CMD_BUS", { + 1, { + "ACT", + "RD", + "WR", + "RDA", + "WRA", + "PREPB", + "PREAB", + "REFAB", + } + } + }); + + mPools.insert({ + "FAW_LOGICAL", { + 4, { + "ACT", + } + } + }); + + mPools.insert({ + "FAW_PHYSICAL", { + 4, { + "ACT", + } + } + }); + + tRCD = tCK * mMemspecJson["memtimingspec"].toObject()["RCD"].toInt(); + tPPD = tCK * mMemspecJson["memtimingspec"].toObject()["PPD"].toInt(); + tRP = tCK * mMemspecJson["memtimingspec"].toObject()["RP"].toInt(); + tRAS = tCK * mMemspecJson["memtimingspec"].toObject()["RAS"].toInt(); + tRL = tCK * mMemspecJson["memtimingspec"].toObject()["RL"].toInt(); + RBL = tCK * mMemspecJson["memtimingspec"].toObject()["BL"].toInt(); + tRTP = tCK * mMemspecJson["memtimingspec"].toObject()["RTP"].toInt(); + tRPRE = tCK * mMemspecJson["memtimingspec"].toObject()["RPRE"].toInt(); + tRPST = tCK * mMemspecJson["memtimingspec"].toObject()["RPST"].toInt(); + tRDDQS = tCK * mMemspecJson["memtimingspec"].toObject()["RDDQS"].toInt(); + tWL = tCK * mMemspecJson["memtimingspec"].toObject()["WL"].toInt(); + WBL = tCK * mMemspecJson["memtimingspec"].toObject()["BL"].toInt(); + tWPRE = tCK * mMemspecJson["memtimingspec"].toObject()["WPRE"].toInt(); + tWPST = tCK * mMemspecJson["memtimingspec"].toObject()["WPST"].toInt(); + tWR = tCK * mMemspecJson["memtimingspec"].toObject()["WR"].toInt(); + tCCD_L_slr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_L_slr"].toInt(); + tCCD_L_WR_slr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_L_WR_slr"].toInt(); + tCCD_S_slr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_S_slr"].toInt(); + tCCD_S_WR_slr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_S_WR_slr"].toInt(); + tCCD_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_dlr"].toInt(); + tCCD_WR_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_WR_dlr"].toInt(); + tCCD_WR_dpr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_WR_dpr"].toInt(); + tRRD_S_slr = tCK * mMemspecJson["memtimingspec"].toObject()["RRD_S_slr"].toInt(); + tRRD_L_slr = tCK * mMemspecJson["memtimingspec"].toObject()["RRD_L_slr"].toInt(); + tRRD_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["RRD_dlr"].toInt(); + tFAW_slr = tCK * mMemspecJson["memtimingspec"].toObject()["FAW_slr"].toInt(); + tFAW_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["FAW_dlr"].toInt(); + tWTR_L = tCK * mMemspecJson["memtimingspec"].toObject()["WTR_L"].toInt(); + tWTR_S = tCK * mMemspecJson["memtimingspec"].toObject()["WTR_S"].toInt(); + tRFC_slr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC_slr"].toInt(); + tRFC_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC_dlr"].toInt(); + tRFC_dpr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC_dpr"].toInt(); + tRFCsb_slr = tCK * mMemspecJson["memtimingspec"].toObject()["RFCsb_slr"].toInt(); + tRFCsb_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["RFCsb_dlr"].toInt(); + tREFI = tCK * mMemspecJson["memtimingspec"].toObject()["REFI"].toInt(); + tREFSBRD_slr = tCK * mMemspecJson["memtimingspec"].toObject()["REFSBRD_slr"].toInt(); + tREFSBRD_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["REFSBRD_dlr"].toInt(); + tRTRS = tCK * mMemspecJson["memtimingspec"].toObject()["RTRS"].toInt(); + UNKNOWN = tCK * mMemspecJson["memtimingspec"].toObject()["NKNOWN"].toInt(); + tCPDED = tCK * mMemspecJson["memtimingspec"].toObject()["CPDED"].toInt(); + tPD = tCK * mMemspecJson["memtimingspec"].toObject()["PD"].toInt(); + tXP = tCK * mMemspecJson["memtimingspec"].toObject()["XP"].toInt(); + tACTPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["ACTPDEN"].toInt(); + tPRPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["PRPDEN"].toInt(); + tREFPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["REFPDEN"].toInt(); + + tRC = tRAS + tRP; + + if (refMode == 1) { + tRFC_slr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC1_slr"].toInt(); + tRFC_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC1_dlr"].toInt(); + tRFC_dpr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC1_dpr"].toInt(); + tREFI = tCK * mMemspecJson["memtimingspec"].toObject()["REFI1"].toInt(); + } else { + tRFC_slr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC2_slr"].toInt(); + tRFC_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC2_dlr"].toInt(); + tRFC_dpr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC2_dpr"].toInt(); + tREFI = tCK * mMemspecJson["memtimingspec"].toObject()["REFI2"].toInt(); + } + + tRD_BURST = (uint) (RBL / (float) dataRate) * tCK; + tWR_BURST = (uint) (WBL / (float) dataRate) * tCK; + tWTRA = tWR - tRTP; + tWRRDA = tWL + tWR_BURST + tWTRA; + tWRPRE = tWL + tWR_BURST + tWR; + tRDAACT = tRTP + tRP; + tWRAACT = tWRPRE + tRP; + tCCD_L_RTW_slr = tRL - tWL + tRD_BURST + 2 * tCK - tRDDQS + tRPST + tWPRE; + tCCD_S_RTW_slr = tRL - tWL + tRD_BURST + 2 * tCK - tRDDQS + tRPST + tWPRE; + tCCD_RTW_dlr = tRL - tWL + tRD_BURST + 2 * tCK - tRDDQS + tRPST + tWPRE; + tRDRD_dpr = tRD_BURST + tRTRS; + tRDRD_ddr = tRD_BURST + tRTRS; + tRDWR_dpr = tRL - tWL + tRD_BURST + tRTRS - tRDDQS + tRPST + tWPRE; + tRDWR_ddr = tRL - tWL + tRD_BURST + tRTRS - tRDDQS + tRPST + tWPRE; + tCCD_L_WTR_slr = tWL + tWR_BURST + tWTR_L; + tCCD_S_WTR_slr = tWL + tWR_BURST + tWTR_S; + tCCD_WTR_dlr = tWL + tWR_BURST + tWTR_S; + tWRWR_dpr = max(tCCD_WR_dpr, tWR_BURST + tRTRS); + tWRWR_ddr = tWR_BURST + tRTRS; + tWRRD_dpr = tWL - tRL + tWR_BURST + tRTRS + tRDDQS + tWPST + tRPRE; + tWRRD_ddr = tWL - tRL + tWR_BURST + tRTRS + tRDDQS + tWPST + tRPRE; + tRDPDEN = tRL + tRD_BURST + tCK; + tWRPDEN = tWL + tWR_BURST + tWR + tCK; + tWRAPDEN = tWL + tWR_BURST + tWR + tCK; + +} + +const std::vector TimeDependenciesInfoDDR5::getPossiblePhases() { + return { + "ACT", + "RD", + "WR", + "PREPB", + "RDA", + "WRA", + "REFAB", + "PREAB", + "PDEP", + "PDXP", + "SREFEN", + "SREFEX", + "PDEA", + "PDXA", + }; +} + +DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const { + DependencyMap dmap; + + dmap.emplace( + piecewise_construct, + forward_as_tuple("ACT"), + forward_as_tuple( + initializer_list{ + {tRC, "ACT", DependencyType::IntraBank, "tRC"}, + {tRRD_L_slr, "ACT", DependencyType::IntraBankGroup, "tRRD_L_slr"}, + {tRRD_S_slr, "ACT", DependencyType::IntraLogicalRank, "tRRD_S_slr"}, + {tRRD_dlr, "ACT", DependencyType::IntraPhysicalRank, "tRRD_dlr"}, + {tRDAACT, "RDA", DependencyType::IntraBank, "tRDAACT"}, + {tWRAACT, "WRA", DependencyType::IntraBank, "tWRAACT"}, + {tRP - tCK, "PREPB", DependencyType::IntraBank, "tRP - tCK"}, + {tRP - tCK, "PREAB", DependencyType::IntraLogicalRank, "tRP - tCK"}, + {tRFC_slr - tCK, "REFAB", DependencyType::IntraLogicalRank, "tRFC_slr - tCK"}, + {2 * tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"}, + {tFAW_slr, "FAW_LOGICAL", DependencyType::IntraLogicalRank, "tFAW_slr"}, + {tFAW_dlr, "FAW_PHYSICAL", DependencyType::IntraPhysicalRank, "tFAW_dlr"}, + } + ) + ); + + dmap.emplace( + piecewise_construct, + forward_as_tuple("RD"), + forward_as_tuple( + initializer_list{ + {tRCD, "ACT", DependencyType::IntraBank, "tRCD"}, + {tCCD_L_slr, "RD", DependencyType::IntraBankGroup, "tCCD_L_slr"}, + {tCCD_S_slr, "RD", DependencyType::IntraLogicalRank, "tCCD_S_slr"}, + {tCCD_dlr, "RD", DependencyType::IntraPhysicalRank, "tCCD_dlr"}, + {tRDRD_dpr, "RD", DependencyType::IntraDIMMRank, "tRDRD_dpr"}, + {tRDRD_ddr, "RD", DependencyType::InterDIMMRank, "tRDRD_ddr"}, + {tCCD_L_slr, "RDA", DependencyType::IntraBankGroup, "tCCD_L_slr"}, + {tCCD_S_slr, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_slr"}, + {tCCD_dlr, "RDA", DependencyType::IntraPhysicalRank, "tCCD_dlr"}, + {tRDRD_dpr, "RDA", DependencyType::IntraDIMMRank, "tRDRD_dpr"}, + {tRDRD_ddr, "RDA", DependencyType::InterDIMMRank, "tRDRD_ddr"}, + {tCCD_L_WTR_slr, "WR", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr"}, + {tCCD_S_WTR_slr, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr"}, + {tCCD_WTR_dlr, "WR", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr"}, + {tWRRD_dpr, "WR", DependencyType::IntraDIMMRank, "tWRRD_dpr"}, + {tWRRD_ddr, "WR", DependencyType::InterDIMMRank, "tWRRD_ddr"}, + {tCCD_L_WTR_slr, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr"}, + {tCCD_S_WTR_slr, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr"}, + {tCCD_WTR_dlr, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr"}, + {tWRRD_dpr, "WRA", DependencyType::IntraDIMMRank, "tWRRD_dpr"}, + {tWRRD_ddr, "WRA", DependencyType::InterDIMMRank, "tWRRD_ddr"}, + {2 * tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"}, + } + ) + ); + + dmap.emplace( + piecewise_construct, + forward_as_tuple("WR"), + forward_as_tuple( + initializer_list{ + {tRCD, "ACT", DependencyType::IntraBank, "tRCD"}, + {tCCD_L_RTW_slr, "RD", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr"}, + {tCCD_S_RTW_slr, "RD", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr"}, + {tCCD_RTW_dlr, "RD", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr"}, + {tRDWR_dpr, "RD", DependencyType::IntraDIMMRank, "tRDWR_dpr"}, + {tRDWR_ddr, "RD", DependencyType::InterDIMMRank, "tRDWR_ddr"}, + {tCCD_L_RTW_slr, "RDA", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr"}, + {tCCD_S_RTW_slr, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr"}, + {tCCD_RTW_dlr, "RDA", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr"}, + {tRDWR_dpr, "RDA", DependencyType::IntraDIMMRank, "tRDWR_dpr"}, + {tRDWR_ddr, "RDA", DependencyType::InterDIMMRank, "tRDWR_ddr"}, + {tCCD_L_WR_slr, "WR", DependencyType::IntraBankGroup, "tCCD_L_WR_slr"}, + {tCCD_S_WR_slr, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WR_slr"}, + {tCCD_WR_dlr, "WR", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr"}, + {tWRWR_dpr, "WR", DependencyType::IntraDIMMRank, "tWRWR_dpr"}, + {tWRWR_ddr, "WR", DependencyType::InterDIMMRank, "tWRWR_ddr"}, + {tCCD_L_WR_slr, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR_slr"}, + {tCCD_S_WR_slr, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WR_slr"}, + {tCCD_WR_dlr, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr"}, + {tWRWR_dpr, "WRA", DependencyType::IntraDIMMRank, "tWRWR_dpr"}, + {tWRWR_ddr, "WRA", DependencyType::InterDIMMRank, "tWRWR_ddr"}, + {2 * tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"}, + } + ) + ); + + dmap.emplace( + piecewise_construct, + forward_as_tuple("PREPB"), + forward_as_tuple( + initializer_list{ + {tRAS + tCK, "ACT", DependencyType::IntraBank, "tRAS + tCK"}, + {tRTP + tCK, "RD", DependencyType::IntraBank, "tRTP + tCK"}, + {tWRPRE + tCK, "WR", DependencyType::IntraBank, "tWRPRE + tCK"}, + {tPPD, "PREPB", DependencyType::IntraPhysicalRank, "tPPD"}, + {tPPD, "PREAB", DependencyType::IntraPhysicalRank, "tPPD"}, + {tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"}, + } + ) + ); + + dmap.emplace( + piecewise_construct, + forward_as_tuple("RDA"), + forward_as_tuple( + initializer_list{ + {tRCD, "ACT", DependencyType::IntraBank, "tRCD"}, + {tCCD_L_slr, "RD", DependencyType::IntraBankGroup, "tCCD_L_slr"}, + {tCCD_S_slr, "RD", DependencyType::IntraLogicalRank, "tCCD_S_slr"}, + {tCCD_dlr, "RD", DependencyType::IntraPhysicalRank, "tCCD_dlr"}, + {tRDRD_dpr, "RD", DependencyType::IntraDIMMRank, "tRDRD_dpr"}, + {tRDRD_ddr, "RD", DependencyType::InterDIMMRank, "tRDRD_ddr"}, + {tCCD_L_slr, "RDA", DependencyType::IntraBankGroup, "tCCD_L_slr"}, + {tCCD_S_slr, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_slr"}, + {tCCD_dlr, "RDA", DependencyType::IntraPhysicalRank, "tCCD_dlr"}, + {tRDRD_dpr, "RDA", DependencyType::IntraDIMMRank, "tRDRD_dpr"}, + {tRDRD_ddr, "RDA", DependencyType::InterDIMMRank, "tRDRD_ddr"}, + {tWRRDA, "WR", DependencyType::IntraBank, "tWRRDA"}, + {tCCD_L_WTR_slr, "WR", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr"}, + {tCCD_S_WTR_slr, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr"}, + {tCCD_WTR_dlr, "WR", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr"}, + {tWRRD_dpr, "WR", DependencyType::IntraDIMMRank, "tWRRD_dpr"}, + {tWRRD_ddr, "WR", DependencyType::InterDIMMRank, "tWRRD_ddr"}, + {tCCD_L_WTR_slr, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr"}, + {tCCD_S_WTR_slr, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr"}, + {tCCD_WTR_dlr, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr"}, + {tWRRD_dpr, "WRA", DependencyType::IntraDIMMRank, "tWRRD_dpr"}, + {tWRRD_ddr, "WRA", DependencyType::InterDIMMRank, "tWRRD_ddr"}, + {2 * tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"}, + } + ) + ); + + dmap.emplace( + piecewise_construct, + forward_as_tuple("WRA"), + forward_as_tuple( + initializer_list{ + {tRCD, "ACT", DependencyType::IntraBank, "tRCD"}, + {tCCD_L_RTW_slr, "RD", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr"}, + {tCCD_S_RTW_slr, "RD", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr"}, + {tCCD_RTW_dlr, "RD", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr"}, + {tRDWR_dpr, "RD", DependencyType::IntraDIMMRank, "tRDWR_dpr"}, + {tRDWR_ddr, "RD", DependencyType::InterDIMMRank, "tRDWR_ddr"}, + {tCCD_L_RTW_slr, "RDA", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr"}, + {tCCD_S_RTW_slr, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr"}, + {tCCD_RTW_dlr, "RDA", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr"}, + {tRDWR_dpr, "RDA", DependencyType::IntraDIMMRank, "tRDWR_dpr"}, + {tRDWR_ddr, "RDA", DependencyType::InterDIMMRank, "tRDWR_ddr"}, + {tCCD_L_WR_slr, "WR", DependencyType::IntraBankGroup, "tCCD_L_WR_slr"}, + {tCCD_S_WR_slr, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WR_slr"}, + {tCCD_WR_dlr, "WR", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr"}, + {tWRWR_dpr, "WR", DependencyType::IntraDIMMRank, "tWRWR_dpr"}, + {tWRWR_ddr, "WR", DependencyType::InterDIMMRank, "tWRWR_ddr"}, + {tCCD_L_WR_slr, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR_slr"}, + {tCCD_S_WR_slr, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WR_slr"}, + {tCCD_WR_dlr, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr"}, + {tWRWR_dpr, "WRA", DependencyType::IntraDIMMRank, "tWRWR_dpr"}, + {tWRWR_ddr, "WRA", DependencyType::InterDIMMRank, "tWRWR_ddr"}, + {2 * tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"}, + } + ) + ); + + dmap.emplace( + piecewise_construct, + forward_as_tuple("REFAB"), + forward_as_tuple( + initializer_list{ + {tRC + tCK, "ACT", DependencyType::IntraLogicalRank, "tRC + tCK"}, + {tRDAACT + tCK, "RDA", DependencyType::IntraPhysicalRank, "tRDAACT + tCK"}, + {tWRPRE + tRP + tCK, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tRP + tCK"}, + {tRP, "PREPB", DependencyType::IntraLogicalRank, "tRP"}, + {tRP, "PREAB", DependencyType::IntraLogicalRank, "tRP"}, + {tRFC_slr, "REFAB", DependencyType::IntraLogicalRank, "tRFC_slr"}, + {tRFC_dlr, "REFAB", DependencyType::IntraPhysicalRank, "tRFC_dlr"}, + {tRFC_dpr, "REFAB", DependencyType::IntraDIMMRank, "tRFC_dpr"}, + {tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"}, + } + ) + ); + + dmap.emplace( + piecewise_construct, + forward_as_tuple("PREAB"), + forward_as_tuple( + initializer_list{ + {tRAS + tCK, "ACT", DependencyType::IntraLogicalRank, "tRAS + tCK"}, + {tRTP + tCK, "RD", DependencyType::IntraLogicalRank, "tRTP + tCK"}, + {tRTP + tCK, "RDA", DependencyType::IntraLogicalRank, "tRTP + tCK"}, + {tWRPRE + tCK, "WR", DependencyType::IntraLogicalRank, "tWRPRE + tCK"}, + {tWRPRE + tCK, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tCK"}, + {tPPD, "PREPB", DependencyType::IntraPhysicalRank, "tPPD"}, + {tPPD, "PREAB", DependencyType::IntraPhysicalRank, "tPPD"}, + {tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"}, + } + ) + ); + + return dmap; +} diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.h new file mode 100644 index 00000000..a243090e --- /dev/null +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.h @@ -0,0 +1,109 @@ +/* Generated by JetBrains MPS */ + +#pragma once + +#include "../dramtimedependenciesIF.h" + +class TimeDependenciesInfoDDR5 final : public DRAMTimeDependenciesIF { + public: + TimeDependenciesInfoDDR5(const QJsonObject& memspec, const uint clk); + + static const std::vector getPossiblePhases(); + + void rankIDToRankIDs(size_t rankID, size_t& dimmRID, size_t& physRID, size_t& logRID) const; + + protected: + void mInitializeValues() override; + DependencyMap mSpecializedGetDependencies() const override; + + protected: + uint mNumOfRanks; + uint mNumOfDIMMRanks; + uint mNumOfPhysicalRanks; + uint mNumOfLogicalRanks; + + uint burstLength; + uint dataRate; + uint refMode; + + uint tRCD; + uint tPPD; + uint tRP; + uint tRAS; + uint tRC; + uint tRL; + uint RBL; + uint tRTP; + uint tRPRE; + uint tRPST; + uint tRDDQS; + uint tWL; + uint WBL; + uint tWPRE; + uint tWPST; + uint tWR; + uint tCCD_L_slr; + uint tCCD_L_WR_slr; + uint tCCD_S_slr; + uint tCCD_S_WR_slr; + uint tCCD_dlr; + uint tCCD_WR_dlr; + uint tCCD_WR_dpr; + uint tRRD_S_slr; + uint tRRD_L_slr; + uint tRRD_dlr; + uint tFAW_slr; + uint tFAW_dlr; + uint tWTR_L; + uint tWTR_S; + uint tRFC_slr; + uint tRFC_dlr; + uint tRFC_dpr; + uint tRFCsb_slr; + uint tRFCsb_dlr; + uint tREFI; + uint tREFSBRD_slr; + uint tREFSBRD_dlr; + uint tRTRS; + uint UNKNOWN; + uint tCPDED; + uint tPD; + uint tXP; + uint tACTPDEN; + uint tPRPDEN; + uint tREFPDEN; + + uint tRD_BURST; + uint tWR_BURST; + uint tWTRA; + uint tWRRDA; + uint tWRPRE; + uint tRDAACT; + uint tWRAACT; + uint tCCD_L_RTW_slr; + uint tCCD_S_RTW_slr; + uint tCCD_RTW_dlr; + uint tRDRD_dpr; + uint tRDRD_ddr; + uint tRDWR_dpr; + uint tRDWR_ddr; + uint tCCD_L_WTR_slr; + uint tCCD_S_WTR_slr; + uint tCCD_WTR_dlr; + uint tWRWR_dpr; + uint tWRWR_ddr; + uint tWRRD_dpr; + uint tWRRD_ddr; + uint tRDPDEN; + uint tWRPDEN; + uint tWRAPDEN; + + protected: + uint mBitsDIMMRanks; + uint mBitsPhysicalRanks; + uint mBitsLogicalRanks; + uint mLogRankMask; + uint mPhysRankMask; + uint mDIMMRankMask; + +}; diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/phasedependenciestracker.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/phasedependenciestracker.cpp index 9c0fb5fe..a5334f19 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/phasedependenciestracker.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/phasedependenciestracker.cpp @@ -212,7 +212,7 @@ PhaseDependenciesTracker::mCalculateDependencies(const std::shared_ptrgetDependencies(commands); + const DependencyMap deviceDependencies = deviceConfig->getDependencies(commands); // Tries to find all timing dependencies for each phase on the trace PoolControllerMap poolController = deviceConfig->getPools();