Set up testing infrastructure for Cache
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231
tests/tests_simulator/cache/TargetMemory.cpp
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231
tests/tests_simulator/cache/TargetMemory.cpp
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/*
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* Copyright (c) 2023, Technische Universität Kaiserslautern
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
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* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors:
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* Derek Christ
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*/
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#include "TargetMemory.h"
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#include <algorithm>
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#include <cstddef>
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#include <iomanip>
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#include <iostream>
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DECLARE_EXTENDED_PHASE(INTERNAL);
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TargetMemory::TargetMemory(const sc_core::sc_module_name &name,
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sc_core::sc_time acceptDelay,
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sc_core::sc_time memoryLatency,
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std::size_t bufferSize)
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: sc_core::sc_module(name),
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tSocket("tSocket"),
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bufferSize(bufferSize),
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peq(this, &TargetMemory::peqCallback),
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acceptDelay(acceptDelay),
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memoryLatency(memoryLatency)
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{
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tSocket.register_nb_transport_fw(this, &TargetMemory::nb_transport_fw);
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memory.reserve(SIZE);
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std::fill(memory.begin(), memory.end(), 0);
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}
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tlm::tlm_sync_enum TargetMemory::nb_transport_fw(tlm::tlm_generic_payload &trans,
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tlm::tlm_phase &phase,
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sc_core::sc_time &delay)
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{
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peq.notify(trans, phase, delay);
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return tlm::TLM_ACCEPTED;
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}
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void TargetMemory::printBuffer(int max, int n)
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{
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std::cout << "\033[1;35m(" << name() << ")@" << std::setfill(' ') << std::setw(12)
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<< sc_core::sc_time_stamp() << " Target Buffer: "
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<< "[";
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for (int i = 0; i < n; i++)
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{
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std::cout << "█";
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}
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for (int i = 0; i < max - n; i++)
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{
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std::cout << " ";
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}
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std::cout << "]"
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<< " (Max:" << max << ") "
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<< "\033[0m" << std::endl;
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std::cout.flush();
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}
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void TargetMemory::peqCallback(tlm::tlm_generic_payload &trans, const tlm::tlm_phase &phase)
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{
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sc_core::sc_time delay;
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if (phase == tlm::BEGIN_REQ)
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{
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trans.acquire();
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if (currentTransactions < bufferSize)
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{
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sendEndRequest(trans);
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}
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else
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{
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endRequestPending = &trans;
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}
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}
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else if (phase == tlm::END_RESP)
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{
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if (!responseInProgress)
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{
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SC_REPORT_FATAL(name(), "Illegal transaction phase END_RESP received by target");
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}
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currentTransactions--;
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printBuffer(bufferSize, currentTransactions);
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responseInProgress = false;
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if (!responseQueue.empty())
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{
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tlm::tlm_generic_payload *next = responseQueue.front();
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responseQueue.pop();
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sendResponse(*next);
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}
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if (endRequestPending != nullptr)
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{
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sendEndRequest(*endRequestPending);
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endRequestPending = nullptr;
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}
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}
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else if (phase == INTERNAL)
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{
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executeTransaction(trans);
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if (responseInProgress)
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{
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responseQueue.push(&trans);
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}
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else
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{
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sendResponse(trans);
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}
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}
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else // tlm::END_REQ or tlm::BEGIN_RESP
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{
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SC_REPORT_FATAL(name(), "Illegal transaction phase received");
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}
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}
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void TargetMemory::sendEndRequest(tlm::tlm_generic_payload &trans)
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{
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tlm::tlm_phase bw_phase;
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sc_core::sc_time delay;
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// Queue the acceptance and the response with the appropriate latency
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bw_phase = tlm::END_REQ;
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delay = acceptDelay;
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tlm::tlm_sync_enum status = tSocket->nb_transport_bw(trans, bw_phase, delay);
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// Queue internal event to mark beginning of response
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delay = delay + memoryLatency; // MEMORY Latency
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peq.notify(trans, INTERNAL, delay);
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currentTransactions++;
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printBuffer(bufferSize, currentTransactions);
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}
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void TargetMemory::sendResponse(tlm::tlm_generic_payload &trans)
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{
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sc_assert(responseInProgress == false);
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responseInProgress = true;
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tlm::tlm_phase bw_phase = tlm::BEGIN_RESP;
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sc_core::sc_time delay = sc_core::SC_ZERO_TIME;
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tlm::tlm_sync_enum status = tSocket->nb_transport_bw(trans, bw_phase, delay);
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if (status == tlm::TLM_UPDATED)
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{
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peq.notify(trans, bw_phase, delay);
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}
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else if (status == tlm::TLM_COMPLETED)
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{
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SC_REPORT_FATAL(name(), "This transition is deprecated since TLM2.0.1");
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}
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trans.release();
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}
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void TargetMemory::executeTransaction(tlm::tlm_generic_payload &trans)
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{
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tlm::tlm_command command = trans.get_command();
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sc_dt::uint64 address = trans.get_address();
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unsigned char *data_ptr = trans.get_data_ptr();
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unsigned int data_length = trans.get_data_length();
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unsigned char *byte_enable_ptr = trans.get_byte_enable_ptr();
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unsigned int streaming_width = trans.get_streaming_width();
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if (address >= SIZE - 64)
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{
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trans.set_response_status(tlm::TLM_ADDRESS_ERROR_RESPONSE);
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return;
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}
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if (byte_enable_ptr != nullptr)
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{
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trans.set_response_status(tlm::TLM_BYTE_ENABLE_ERROR_RESPONSE);
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return;
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}
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if (data_length > 64 || streaming_width < data_length)
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{
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trans.set_response_status(tlm::TLM_BURST_ERROR_RESPONSE);
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return;
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}
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if (command == tlm::TLM_READ_COMMAND)
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{
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std::memcpy(trans.get_data_ptr(), &memory[trans.get_address()], trans.get_data_length());
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}
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else if (command == tlm::TLM_WRITE_COMMAND)
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{
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memcpy(&memory[trans.get_address()], trans.get_data_ptr(), trans.get_data_length());
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}
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std::cout << "\033[1;32m(" << name() << ")@" << std::setfill(' ') << std::setw(12)
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<< sc_core::sc_time_stamp() << ": " << std::setw(12)
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<< (command == tlm::TLM_WRITE_COMMAND ? "Exec. Write " : "Exec. Read ")
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<< "Addr = " << std::setfill('0') << std::setw(8) << std::dec << address << " Data = "
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<< "0x" << std::setfill('0') << std::setw(8) << std::hex
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<< *reinterpret_cast<int *>(data_ptr) << "\033[0m" << std::endl;
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trans.set_response_status(tlm::TLM_OK_RESPONSE);
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}
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