From a4bd237418c7f48af87eb7b1f558d34e68982f56 Mon Sep 17 00:00:00 2001 From: Ana Mativi Date: Mon, 7 Aug 2017 18:12:16 +0200 Subject: [PATCH] Patch for Postpone Ref Implementation --- DRAMSys/simulator/resources/resources.pri | 6 ++++-- .../simulations/ddr3_postpone_test.xml | 2 +- .../src/controller/core/ControllerCore.cpp | 10 +++++++++ .../src/controller/core/ControllerCore.h | 1 + .../core/refresh/RefreshManager.cpp | 21 ++++++++----------- .../controller/core/refresh/RefreshManager.h | 1 - 6 files changed, 25 insertions(+), 16 deletions(-) diff --git a/DRAMSys/simulator/resources/resources.pri b/DRAMSys/simulator/resources/resources.pri index 71cc54aa..3de5ec6a 100644 --- a/DRAMSys/simulator/resources/resources.pri +++ b/DRAMSys/simulator/resources/resources.pri @@ -70,7 +70,9 @@ OTHER_FILES += resources/traces/sms_t1.stl OTHER_FILES += resources/traces/sms_t2.stl OTHER_FILES += resources/traces/sms_t3.stl OTHER_FILES += resources/traces/sms_t4.stl -OTHER_FILES += resources/traces/ddr3_postpone_test.stl +OTHER_FILES += resources/traces/ddr3_postpone_ref_test_1.stl +OTHER_FILES += resources/traces/ddr3_postpone_ref_test_2.stl +OTHER_FILES += resources/traces/ddr3_postpone_ref_test_3.stl # Memory Controller Configs OTHER_FILES += resources/configs/mcconfigs/fifoStrict.xml @@ -156,4 +158,4 @@ OTHER_FILES += resources/error/wideio.csv DISTFILES += \ $$PWD/traces/read_write_switch.stl \ $$PWD/configs/mcconfigs/fr_fcfs_rp.xml \ - $$PWD/configs/mcconfigs/fr_fcfs_grp.xml + $$PWD/configs/mcconfigs/fr_fcfs_grp.xml \ diff --git a/DRAMSys/simulator/resources/simulations/ddr3_postpone_test.xml b/DRAMSys/simulator/resources/simulations/ddr3_postpone_test.xml index bcaee4bf..3778baec 100644 --- a/DRAMSys/simulator/resources/simulations/ddr3_postpone_test.xml +++ b/DRAMSys/simulator/resources/simulations/ddr3_postpone_test.xml @@ -14,6 +14,6 @@ In library mode e.g. in Platform Architect the trace setup is ignored. --> - ddr3_postpone_test.stl + ddr3_postpone_ref_test_3.stl diff --git a/DRAMSys/simulator/src/controller/core/ControllerCore.cpp b/DRAMSys/simulator/src/controller/core/ControllerCore.cpp index 45b3bd47..6fc50917 100644 --- a/DRAMSys/simulator/src/controller/core/ControllerCore.cpp +++ b/DRAMSys/simulator/src/controller/core/ControllerCore.cpp @@ -184,6 +184,16 @@ ScheduledCommand ControllerCore::schedule(Command command, sc_time start, return scheduledCommand; } +bool ControllerCore::hasPendingRequests() +{ + for (Bank bank : getBanks()) + { + if (numberOfPayloads[bank] != 0) + return true; + } + return false; +} + bool ControllerCore::bankIsBusy(Bank bank) { diff --git a/DRAMSys/simulator/src/controller/core/ControllerCore.h b/DRAMSys/simulator/src/controller/core/ControllerCore.h index 821c2944..b05a3788 100644 --- a/DRAMSys/simulator/src/controller/core/ControllerCore.h +++ b/DRAMSys/simulator/src/controller/core/ControllerCore.h @@ -63,6 +63,7 @@ public: const std::vector& getBanks(); std::vector getFreeBanks(); const RowBufferState& getRowBufferStates(){return *(state->rowBufferStates);} + bool hasPendingRequests(); bool bankIsBusy(Bank bank); ICommandChecker& getCommandChecker(Command command); diff --git a/DRAMSys/simulator/src/controller/core/refresh/RefreshManager.cpp b/DRAMSys/simulator/src/controller/core/refresh/RefreshManager.cpp index bb5a7a4e..d251d3f5 100644 --- a/DRAMSys/simulator/src/controller/core/refresh/RefreshManager.cpp +++ b/DRAMSys/simulator/src/controller/core/refresh/RefreshManager.cpp @@ -64,7 +64,14 @@ RefreshManager::~RefreshManager() //Check if a command will be scheduled during the next refresh period bool RefreshManager::hasCollision(const ScheduledCommand& command) { - return command.getStart() < controllerCore.state->getLastCommand(Command::AutoRefresh).getEnd() || command.getEnd() >= nextPlannedRefresh; + bool collisionWithPreviousRefEnd = command.getStart() < controllerCore.state->getLastCommand(Command::AutoRefresh).getEnd(); + bool collisionWithNextRefStart = command.getEnd() >= nextPlannedRefresh; + + if (controllerCore.config.ControllerCoreEnableRefPostpone && (arCmdCounter < maxpostpone)) // Flexible refresh is on and have "credits" to postpone + { + collisionWithNextRefStart = false; // Then there will not be a collision with next refresh because nextPlannedRefresh will be updated + } + return collisionWithPreviousRefEnd || collisionWithNextRefStart; } void RefreshManager::doRefresh(tlm::tlm_generic_payload& payload __attribute__((unused)), sc_time time) @@ -104,20 +111,10 @@ void RefreshManager::doRefresh(tlm::tlm_generic_payload& payload __attribute__(( controllerCore.controller.send(refreshAllMaster, refreshPayloads[Bank(0)]); } -bool RefreshManager::pendingRequests() -{ - for (Bank bank : controllerCore.getBanks()) - { - if (controllerCore.numberOfPayloads[bank] != 0) - return true; - } - return false; -} - //This function is sensitive to state transitions only. For multiple calls of this function we ensure that burst is only updated on a state change void RefreshManager::evaluateBurstState() { - bool pendingReq = pendingRequests(); + bool pendingReq = controllerCore.hasPendingRequests(); if ((arCmdCounter == maxpostpone) || ((!pendingReq&&!burst) && !controllerCore.config.ControllerCoreForceMaxRefPostpone)) { diff --git a/DRAMSys/simulator/src/controller/core/refresh/RefreshManager.h b/DRAMSys/simulator/src/controller/core/refresh/RefreshManager.h index ce89474f..2c701467 100644 --- a/DRAMSys/simulator/src/controller/core/refresh/RefreshManager.h +++ b/DRAMSys/simulator/src/controller/core/refresh/RefreshManager.h @@ -68,7 +68,6 @@ private: void doRefresh(tlm::tlm_generic_payload& payload, sc_time time); void planNextRefresh(sc_time time); void printDebugMessage(std::string message); - bool pendingRequests(); void burstRefresh(); void evaluateBurstState(); sc_time getNextRefTiming();