From a4342f71044d4801aff0cdd9f468a7eaaa9e2cab Mon Sep 17 00:00:00 2001
From: Derek Christ <derek.christ@iese.fraunhofer.de>
Date: Tue, 15 Aug 2023 11:28:03 +0200
Subject: [PATCH] Update expected traces for DDR5 and HBM3

---
 tests/tests_regression/CMakeLists.txt                       | 5 ++---
 tests/tests_regression/DDR5/ddr5-example.json               | 2 +-
 .../DDR5/expected/DRAMSys_ddr5-example_ddr5_ch0.tdb         | 4 ++--
 .../DDR5/expected/DRAMSys_ddr5-example_ddr5_ch1.tdb         | 2 +-
 .../HBM3/expected/DRAMSys_hbm3-example_hbm3_ch0.tdb         | 4 ++--
 tests/tests_regression/HBM3/hbm3-example.json               | 6 +++---
 6 files changed, 11 insertions(+), 12 deletions(-)

diff --git a/tests/tests_regression/CMakeLists.txt b/tests/tests_regression/CMakeLists.txt
index 1ed6addf..e1d97ebf 100644
--- a/tests/tests_regression/CMakeLists.txt
+++ b/tests/tests_regression/CMakeLists.txt
@@ -39,11 +39,10 @@ cmake_minimum_required(VERSION 3.1.0)
 
 project(tests_regression)
 
-find_program(Bash bash)
 find_program(SqlDiff sqldiff)
 
-if(NOT Bash OR NOT SqlDiff)
-    message(WARNING "Regression tests require bash and sqldiff to be installed")
+if(NOT SqlDiff)
+    message(WARNING "Regression tests require sqldiff to be installed")
     return()
 endif()
 
diff --git a/tests/tests_regression/DDR5/ddr5-example.json b/tests/tests_regression/DDR5/ddr5-example.json
index f6445f7c..3d2b0cbd 100644
--- a/tests/tests_regression/DDR5/ddr5-example.json
+++ b/tests/tests_regression/DDR5/ddr5-example.json
@@ -157,7 +157,7 @@
         "simulationid": "ddr5-example",
         "tracesetup": [
             {
-                "clkMhz": 933,
+                "clkMhz": 1600,
                 "name": "trace_test3.stl"
             }
         ]
diff --git a/tests/tests_regression/DDR5/expected/DRAMSys_ddr5-example_ddr5_ch0.tdb b/tests/tests_regression/DDR5/expected/DRAMSys_ddr5-example_ddr5_ch0.tdb
index 5705dd3e..f8d7441f 100644
--- a/tests/tests_regression/DDR5/expected/DRAMSys_ddr5-example_ddr5_ch0.tdb
+++ b/tests/tests_regression/DDR5/expected/DRAMSys_ddr5-example_ddr5_ch0.tdb
@@ -1,3 +1,3 @@
 version https://git-lfs.github.com/spec/v1
-oid sha256:655d10bfd7b648e0f8121cd6d78652a86d2abc899a2181aaac33e87b5bed4833
-size 6045696
+oid sha256:5e0c71bd6f04a8e5547ef4207740b00b5ca68e02c6a7b99d998365809b54fc9d
+size 6041600
diff --git a/tests/tests_regression/DDR5/expected/DRAMSys_ddr5-example_ddr5_ch1.tdb b/tests/tests_regression/DDR5/expected/DRAMSys_ddr5-example_ddr5_ch1.tdb
index d76dbe0a..7ebed659 100644
--- a/tests/tests_regression/DDR5/expected/DRAMSys_ddr5-example_ddr5_ch1.tdb
+++ b/tests/tests_regression/DDR5/expected/DRAMSys_ddr5-example_ddr5_ch1.tdb
@@ -1,3 +1,3 @@
 version https://git-lfs.github.com/spec/v1
-oid sha256:d919de55d4f608730cf65fe7fa58d61630dca3188f56748a461b57e6c154ca71
+oid sha256:efd6b710929d4d02b83950b5e4bc2b5fed39c66a6d6d850802902b8db3f8c17d
 size 94208
diff --git a/tests/tests_regression/HBM3/expected/DRAMSys_hbm3-example_hbm3_ch0.tdb b/tests/tests_regression/HBM3/expected/DRAMSys_hbm3-example_hbm3_ch0.tdb
index 1444f081..20997b20 100644
--- a/tests/tests_regression/HBM3/expected/DRAMSys_hbm3-example_hbm3_ch0.tdb
+++ b/tests/tests_regression/HBM3/expected/DRAMSys_hbm3-example_hbm3_ch0.tdb
@@ -1,3 +1,3 @@
 version https://git-lfs.github.com/spec/v1
-oid sha256:a83949f53b32360d25095f5a344c9aae5fdcfe5b8516b63adf779c405f06c1a0
-size 1462272
+oid sha256:7609241e093ada5c641a7ff1ddbb0227c735f08095cd29f093e83c600462ab7b
+size 1458176
diff --git a/tests/tests_regression/HBM3/hbm3-example.json b/tests/tests_regression/HBM3/hbm3-example.json
index a35e6a1e..fb1fb047 100644
--- a/tests/tests_regression/HBM3/hbm3-example.json
+++ b/tests/tests_regression/HBM3/hbm3-example.json
@@ -79,7 +79,7 @@
                 "CCDS": 2,
                 "CKE": 8,
                 "DQSCK": 1,
-                "FAW": 16, 
+                "FAW": 16,
                 "PL": 0,
                 "PPD": 2,
                 "RAS": 28,
@@ -126,11 +126,11 @@
         "simulationid": "hbm3-example",
         "tracesetup": [
             {
-                "clkMhz": 1000,
+                "clkMhz": 1600,
                 "name": "trace1_test4.stl"
             },
 	    {
-                "clkMhz": 1000,
+                "clkMhz": 1600,
                 "name": "trace2_test4.stl"
             }
         ]