diff --git a/dram/.cproject b/dram/.cproject index 362fbe05..4e75fe86 100644 --- a/dram/.cproject +++ b/dram/.cproject @@ -19,7 +19,7 @@ - + diff --git a/dram/.gitignore b/dram/.gitignore index c1bea3e6..3f6fb6f0 100644 --- a/dram/.gitignore +++ b/dram/.gitignore @@ -1,4 +1,5 @@ /build-simulation *.tdb *.tdb-journal -*.out \ No newline at end of file +*.out +*.txt \ No newline at end of file diff --git a/dram/resources/configs/memconfigs/fifo.xml b/dram/resources/configs/memconfigs/fifo.xml new file mode 100644 index 00000000..e0c9501c --- /dev/null +++ b/dram/resources/configs/memconfigs/fifo.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/dram/resources/configs/memconfigs/fr_fcfs.xml b/dram/resources/configs/memconfigs/fr_fcfs.xml new file mode 100644 index 00000000..ad54f1e4 --- /dev/null +++ b/dram/resources/configs/memconfigs/fr_fcfs.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/dram/resources/configs/memconfigs/fr_fcfs_unaware.xml b/dram/resources/configs/memconfigs/fr_fcfs_unaware.xml new file mode 100644 index 00000000..1da98872 --- /dev/null +++ b/dram/resources/configs/memconfigs/fr_fcfs_unaware.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/dram/resources/configs/memconfigs/par_bs.xml b/dram/resources/configs/memconfigs/par_bs.xml new file mode 100644 index 00000000..2cc90b3a --- /dev/null +++ b/dram/resources/configs/memconfigs/par_bs.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/dram/resources/configs/memconfigs/par_bs_unaware.xml b/dram/resources/configs/memconfigs/par_bs_unaware.xml new file mode 100644 index 00000000..f2e238a6 --- /dev/null +++ b/dram/resources/configs/memconfigs/par_bs_unaware.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/dram/resources/configs/memspecs/MatzesWideIO.xml b/dram/resources/configs/memspecs/MatzesWideIO.xml index 57599053..8679ff1c 100644 --- a/dram/resources/configs/memspecs/MatzesWideIO.xml +++ b/dram/resources/configs/memspecs/MatzesWideIO.xml @@ -28,7 +28,7 @@ - + diff --git a/dram/src/common/DebugManager.cpp b/dram/src/common/DebugManager.cpp index e11e42c8..819c9195 100644 --- a/dram/src/common/DebugManager.cpp +++ b/dram/src/common/DebugManager.cpp @@ -23,7 +23,7 @@ void DebugManager::printDebugMessage(string sender, string message) cout << " at " << sc_time_stamp() << "\t in " << sender << "\t: " << message << endl; if (writeToFile) - debugFile << " at " << sc_time_stamp().to_default_time_units() << " in " << sender << "\t: " << message << "\n"; + debugFile << " at " << sc_time_stamp() << " in " << sender << "\t: " << message << "\n"; } } diff --git a/dram/src/simulation/Controller.h b/dram/src/simulation/Controller.h index 3b0ee8d1..6d209219 100644 --- a/dram/src/simulation/Controller.h +++ b/dram/src/simulation/Controller.h @@ -65,6 +65,11 @@ public: if (selectedScheduler == "FR_FCFS") { + if(Configuration::getInstance().RefreshAwareScheduling) + cout << "Building refresh aware scheduler" << std::endl; + else + cout << "Building refresh un-aware scheduler" << std::endl; + scheduler = new FR_FCFS(controller->state.bankStates, Configuration::getInstance().RefreshAwareScheduling, Configuration::getInstance().AdaptiveOpenPagePolicy); diff --git a/dram/src/simulation/SimulationManager.cpp b/dram/src/simulation/SimulationManager.cpp index 00ac55c8..fb3f69b2 100644 --- a/dram/src/simulation/SimulationManager.cpp +++ b/dram/src/simulation/SimulationManager.cpp @@ -39,7 +39,6 @@ Simulation::Simulation(sc_module_name name, string pathToResources, string trace arbiter = new Arbiter("arbiter"); controller = new Controller<>("controller"); - player1 = new TracePlayer<>("player1", pathToResources + string("traces/") + devices[0].trace, devices[0].burstLength, this); player2 = new TracePlayer<>("player2", pathToResources + string("traces/") + devices[1].trace, @@ -78,8 +77,6 @@ Simulation::~Simulation() void Simulation::startSimulation() { - - clock_t begin = clock(); DebugManager::getInstance().printDebugMessage(name(), "Starting simulation"); diff --git a/dram/src/simulation/main.cpp b/dram/src/simulation/main.cpp index 15c51195..3bb3a07d 100644 --- a/dram/src/simulation/main.cpp +++ b/dram/src/simulation/main.cpp @@ -19,6 +19,7 @@ using namespace std; using namespace simulation; string resources; +bool silent = true; string pathOfFile(string file) { @@ -32,13 +33,13 @@ void startTraceAnalyzer(string traceName) system(run_tpr.c_str()); } -bool runSimulation(string resources, string traceName, DramSetup setup, vector devices) +bool runSimulation(string traceName, DramSetup setup, vector devices) { int pid = fork(); int status = 0; if (pid == 0) { - Simulation simulation("sim", resources, traceName, setup, devices); + Simulation simulation("sim", resources, traceName, setup, devices,silent); simulation.startSimulation(); return true; } @@ -53,7 +54,7 @@ bool batchTraces(DramSetup setup, vector> tracePairs) { id++; string traceName = "traceBatch" + to_string(id) + ".tdb"; - if (runSimulation(resources, traceName, setup, { Device(pair.first), Device(pair.second) })) + if (runSimulation(traceName, setup, { Device(pair.first), Device(pair.second) })) return true; //kill child } } @@ -65,7 +66,7 @@ bool batchSetups(pair tracePair, vector setups) { id++; string traceName = "setupBatch" + to_string(id) + ".tdb"; - if (runSimulation(resources, traceName, setup, + if (runSimulation(traceName, setup, { Device(tracePair.first), Device(tracePair.second) })) return true; //kill child } @@ -76,21 +77,37 @@ int sc_main(int argc, char **argv) resources = pathOfFile(argv[0]) + string("/../resources/"); - DramSetup setup; - setup.memconfig = "memconfig.xml"; - setup.memspec = "MICRON_4Gb_DDR4-1866_8bit_A.xml"; - //setup.memspec = "MatzesWideIO.xml"; - - vector> tracePairs; - tracePairs.push_back(pair("chstone-mips_32.stl", "chstone-motion_32.stl")); - - batchTraces(setup, tracePairs); +// DramSetup setup; +// setup.memconfig = "memconfig.xml"; +// //setup.memspec = "MICRON_4Gb_DDR4-1866_8bit_A.xml"; +// setup.memspec = "MatzesWideIO.xml"; +// +// vector> tracePairs; +// tracePairs.push_back(pair("chstone-mips_32.stl", "chstone-motion_32.stl")); +// +// batchTraces(setup, tracePairs); // DramSetup setup2; // setup2.memconfig = "memconfig.xml"; // setup2.memspec = "MICRON_4Gb_DDR4-1866_8bit_A.xml"; //batchSetups(tracePairs[0], { setup, setup2 }); + Device d1("mediabench-c-ray-1.1_32.stl",4); + Device d2("mediabench-fractal_32.stl",4); + string dramSpec = "MatzesWideIO.xml"; + + if(runSimulation("fifo.tdb",DramSetup("fifo.xml",dramSpec),{d1,d2})) + return 0; + if(runSimulation("fr_fcfs.tdb",DramSetup("fr_fcfs.xml",dramSpec),{d1,d2})) + return 0; + if(runSimulation("fr_fcfs_unaware.tdb",DramSetup("fr_fcfs_unaware.xml",dramSpec),{d1,d2})) + return 0; + if(runSimulation("par_bs.tdb",DramSetup("par_bs.xml",dramSpec),{d1,d2})) + return 0; + if(runSimulation("par_bs_unaware.tdb",DramSetup("par_bs_unaware.xml",dramSpec),{d1,d2})) + return 0; + + startTraceAnalyzer("fifo.tdb fr_fcfs.tdb fr_fcfs_unaware.tdb par_bs.tdb par_bs_unaware.tdb"); return 0; }