From a101d80f44dcc81f6935a870ee2b8ba7dd380a6d Mon Sep 17 00:00:00 2001
From: Lukas Steiner <lsteiner@rhrk.uni-kl.de>
Date: Wed, 1 Sep 2021 12:08:48 +0200
Subject: [PATCH] Add simulation example with 2 ranks and 32 banks.

---
 .../am_ddr5_2x2x8x4Gbx4_dimm_p1KB_rbc.json    | 54 +++++++++++++
 .../JEDEC_2x2x8x4Gbx4_DDR5-3200A.json         | 77 +++++++++++++++++++
 .../resources/simulations/ddr5-rfm.json       | 24 ++++++
 3 files changed, 155 insertions(+)
 create mode 100644 DRAMSys/library/resources/configs/amconfigs/am_ddr5_2x2x8x4Gbx4_dimm_p1KB_rbc.json
 create mode 100644 DRAMSys/library/resources/configs/memspecs/JEDEC_2x2x8x4Gbx4_DDR5-3200A.json
 create mode 100644 DRAMSys/library/resources/simulations/ddr5-rfm.json

diff --git a/DRAMSys/library/resources/configs/amconfigs/am_ddr5_2x2x8x4Gbx4_dimm_p1KB_rbc.json b/DRAMSys/library/resources/configs/amconfigs/am_ddr5_2x2x8x4Gbx4_dimm_p1KB_rbc.json
new file mode 100644
index 00000000..5e42017b
--- /dev/null
+++ b/DRAMSys/library/resources/configs/amconfigs/am_ddr5_2x2x8x4Gbx4_dimm_p1KB_rbc.json
@@ -0,0 +1,54 @@
+{
+    "CONGEN": {
+        "BYTE_BIT": [
+            0,
+            1
+        ],
+        "COLUMN_BIT": [
+            2,
+            3,
+            4,
+            5,
+            6,
+            7,
+            8,
+            9,
+            10,
+            11,
+            12
+        ],
+        "BANKGROUP_BIT": [
+            13,
+            14,
+            15
+        ],
+        "BANK_BIT": [
+            16,
+            17
+        ],
+        "ROW_BIT": [
+            18,
+            19,
+            20,
+            21,
+            22,
+            23,
+            24,
+            25,
+            26,
+            27,
+            28,
+            29,
+            30,
+            31,
+            32,
+            33
+        ],
+        "CHANNEL_BIT": [
+            34
+        ],
+        "RANK_BIT": [
+            35
+        ]
+    }
+}
diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x2x8x4Gbx4_DDR5-3200A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x2x8x4Gbx4_DDR5-3200A.json
new file mode 100644
index 00000000..e3dc6461
--- /dev/null
+++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x2x8x4Gbx4_DDR5-3200A.json
@@ -0,0 +1,77 @@
+{
+    "memspec": {
+        "memarchitecturespec": {
+            "burstLength": 16,
+            "dataRate": 2,
+            "nbrOfBankGroups": 8,
+            "nbrOfBanks": 32,
+            "nbrOfColumns": 2048,
+            "nbrOfRanks": 2,
+            "nbrOfDIMMRanks": 1,
+            "nbrOfPhysicalRanks": 2,
+            "nbrOfLogicalRanks": 1,
+            "nbrOfRows": 65536,
+            "width": 4,
+            "nbrOfDevicesOnDIMM": 8,
+            "nbrOfChannels": 2,
+            "cmdMode": 1,
+            "refMode": 1,
+            "RAAIMT" : 3,
+            "RAAMMT" : 1,
+            "RAADEC" : 3
+        },
+        "memoryId": "JEDEC_2x8x2Gbx4_DDR5-3200A",
+        "memoryType": "DDR5",
+        "memtimingspec": {
+            "RCD": 22,
+            "PPD": 2,
+            "RP": 22,
+            "RAS": 52,
+            "RL": 22,
+            "RTP": 12,
+            "RPRE": 1,
+            "RPST": 0,
+            "RDDQS": 0,
+            "WL": 20,
+            "WPRE": 2,
+            "WPST": 0,
+            "WR": 48,
+            "CCD_L_slr": 8,
+            "CCD_L_WR_slr": 32,
+            "CCD_L_WR2_slr": 16,
+            "CCD_S_slr": 8,
+            "CCD_S_WR_slr": 8,
+            "CCD_dlr": 0,
+            "CCD_WR_dlr": 0,
+            "CCD_WR_dpr": 0,
+            "RRD_L_slr": 8,
+            "RRD_S_slr": 8,
+            "RRD_dlr": 0,
+            "FAW_slr": 32,
+            "FAW_dlr": 0,
+            "WTR_L": 16,
+            "WTR_S": 4,
+            "RFC1_slr": 312,
+            "RFC2_slr": 208,
+            "RFC1_dlr": 0,
+            "RFC2_dlr": 0,
+            "RFC1_dpr": 0,
+            "RFC2_dpr": 0,
+            "RFCsb_slr": 184,
+            "RFCsb_dlr": 0,
+            "REFI1": 6240,
+            "REFI2": 3120,
+            "REFISB": 1560,
+            "REFSBRD_slr": 48,
+            "REFSBRD_dlr": 0,
+            "RTRS": 2,
+            "CPDED": 8,
+            "PD": 12,
+            "XP": 12,
+            "ACTPDEN": 2,
+            "PRPDEN": 2,
+            "REFPDEN": 2,
+            "clkMhz": 1600
+        }
+    }
+}
diff --git a/DRAMSys/library/resources/simulations/ddr5-rfm.json b/DRAMSys/library/resources/simulations/ddr5-rfm.json
new file mode 100644
index 00000000..77dfdc27
--- /dev/null
+++ b/DRAMSys/library/resources/simulations/ddr5-rfm.json
@@ -0,0 +1,24 @@
+{
+    "simulation": {
+        "addressmapping": "am_ddr5_2x2x8x4Gbx4_dimm_p1KB_rbc.json",
+        "mcconfig": "fr_fcfs.json",
+        "memspec": "JEDEC_2x2x8x4Gbx4_DDR5-3200A.json",
+        "simconfig": "ddr5.json",
+        "simulationid": "ddr5-example",
+        "thermalconfig": "config.json",
+        "tracesetup": [
+            {
+                "clkMhz": 2000,
+                "type": "generator",
+                "name": "gen0",
+                "numRequests": 2000,
+                "rwRatio": 0.85,
+                "addressDistribution": "random",
+                "seed": 123456,
+                "maxPendingReadRequests": 8,
+                "maxPendingWriteRequests": 8
+            }
+
+        ]
+    }
+}