From a00cb68d01ccfa10211f8613f44079f1ed8f6930 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=C3=89der=20F=2E=20Zulian?= <zulian@eit.uni-kl.de>
Date: Mon, 3 Sep 2018 17:23:06 +0200
Subject: [PATCH] Elastic traces scripts and gem5 configs fixed.

Documentation improved.
---
 .../configs/dualElasticTraceReplay.dot.pdf    | Bin 0 -> 16457 bytes
 .../gem5/configs/dualElasticTraceReplay.ini   | 112 ++++++++++++------
 .../configs/singleElasticTraceReplay.dot.pdf  | Bin 0 -> 14694 bytes
 .../gem5/configs/singleElasticTraceReplay.ini |  59 +++++----
 .../singleElasticTraceReplayWithL2.dot.pdf    | Bin 0 -> 15663 bytes
 .../singleElasticTraceReplayWithL2.ini        |  84 ++++++++-----
 DRAMSys/gem5/examples/tlm_elastic_slave.py    |  11 +-
 .../examples/tlm_elastic_slave_mc_direct.py   |  14 ++-
 .../examples/tlm_elastic_slave_with_l2.py     |  17 +--
 README.md                                     |  15 +++
 10 files changed, 208 insertions(+), 104 deletions(-)
 create mode 100644 DRAMSys/gem5/configs/dualElasticTraceReplay.dot.pdf
 create mode 100644 DRAMSys/gem5/configs/singleElasticTraceReplay.dot.pdf
 create mode 100644 DRAMSys/gem5/configs/singleElasticTraceReplayWithL2.dot.pdf

diff --git a/DRAMSys/gem5/configs/dualElasticTraceReplay.dot.pdf b/DRAMSys/gem5/configs/dualElasticTraceReplay.dot.pdf
new file mode 100644
index 0000000000000000000000000000000000000000..723fe2030570cfa77f4ec1319eca90ad7443c559
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diff --git a/DRAMSys/gem5/configs/dualElasticTraceReplay.ini b/DRAMSys/gem5/configs/dualElasticTraceReplay.ini
index 4f459d3e..154e7c8d 100644
--- a/DRAMSys/gem5/configs/dualElasticTraceReplay.ini
+++ b/DRAMSys/gem5/configs/dualElasticTraceReplay.ini
@@ -21,7 +21,7 @@ init_param=0
 kernel=
 kernel_addr_check=true
 kernel_extras=
-load_addr_mask=1099511627775
+load_addr_mask=18446744073709551615
 load_offset=0
 mem_mode=timing
 mem_ranges=0:536870911:0:0:0:0
@@ -32,7 +32,7 @@ num_work_ids=16
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
-power_model=Null
+power_model=
 readfile=
 symbolfile=
 thermal_components=
@@ -60,7 +60,7 @@ children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
 checker=Null
 clk_domain=system.clk_domain
 cpu_id=0
-dataTraceFile=../../DRAMSys/gem5/etraces/system.cpu.traceListener.stream.data.gz
+dataTraceFile=../../DRAMSys/gem5/etraces/system.cpu.traceListener.data.gz
 default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
@@ -72,7 +72,7 @@ eventq_index=0
 freqMultiplier=1.0
 function_trace=false
 function_trace_start=0
-instTraceFile=../../DRAMSys/gem5/etraces/system.cpu.traceListener.stream.inst.gz
+instTraceFile=../../DRAMSys/gem5/etraces/system.cpu.traceListener.inst.gz
 interrupts=system.cpu0.interrupts
 isa=system.cpu0.isa
 istage2_mmu=system.cpu0.istage2_mmu
@@ -86,7 +86,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_gating_on_idle=false
-power_model=Null
+power_model=
 profile=0
 progressMsgInterval=0
 progress_interval=0
@@ -107,7 +107,7 @@ icache_port=system.cpu0.icache.cpu_side
 
 [system.cpu0.dcache]
 type=Cache
-children=tags
+children=replacement_policy tags
 addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.clk_domain
@@ -122,9 +122,10 @@ mshrs=4
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
-power_model=Null
+power_model=
 prefetch_on_access=false
 prefetcher=Null
+replacement_policy=system.cpu0.dcache.replacement_policy
 response_latency=2
 sequential_access=false
 size=32768
@@ -132,13 +133,18 @@ system=system
 tag_latency=2
 tags=system.cpu0.dcache.tags
 tgts_per_mshr=20
+warmup_percentage=0
 write_buffers=8
 writeback_clean=false
 cpu_side=system.cpu0.dcache_port
 mem_side=system.membus1.slave[2]
 
+[system.cpu0.dcache.replacement_policy]
+type=LRURP
+eventq_index=0
+
 [system.cpu0.dcache.tags]
-type=LRU
+type=BaseSetAssoc
 assoc=2
 block_size=64
 clk_domain=system.clk_domain
@@ -148,10 +154,12 @@ eventq_index=0
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
-power_model=Null
+power_model=
+replacement_policy=system.cpu0.dcache.replacement_policy
 sequential_access=false
 size=32768
 tag_latency=2
+warmup_percentage=0
 
 [system.cpu0.dstage2_mmu]
 type=ArmStage2MMU
@@ -180,7 +188,7 @@ num_squash_per_cycle=2
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
-power_model=Null
+power_model=
 sys=system
 
 [system.cpu0.dtb]
@@ -202,12 +210,12 @@ num_squash_per_cycle=2
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
-power_model=Null
+power_model=
 sys=system
 
 [system.cpu0.icache]
 type=Cache
-children=tags
+children=replacement_policy tags
 addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.clk_domain
@@ -222,9 +230,10 @@ mshrs=4
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
-power_model=Null
+power_model=
 prefetch_on_access=false
 prefetcher=Null
+replacement_policy=system.cpu0.icache.replacement_policy
 response_latency=2
 sequential_access=false
 size=32768
@@ -232,13 +241,18 @@ system=system
 tag_latency=2
 tags=system.cpu0.icache.tags
 tgts_per_mshr=20
+warmup_percentage=0
 write_buffers=8
 writeback_clean=true
 cpu_side=system.cpu0.icache_port
 mem_side=system.membus1.slave[1]
 
+[system.cpu0.icache.replacement_policy]
+type=LRURP
+eventq_index=0
+
 [system.cpu0.icache.tags]
-type=LRU
+type=BaseSetAssoc
 assoc=2
 block_size=64
 clk_domain=system.clk_domain
@@ -248,10 +262,12 @@ eventq_index=0
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
-power_model=Null
+power_model=
+replacement_policy=system.cpu0.icache.replacement_policy
 sequential_access=false
 size=32768
 tag_latency=2
+warmup_percentage=0
 
 [system.cpu0.interrupts]
 type=ArmInterrupts
@@ -280,6 +296,7 @@ id_mmfr0=270536963
 id_mmfr1=0
 id_mmfr2=19070976
 id_mmfr3=34611729
+impdef_nop=false
 midr=1091551472
 pmu=Null
 system=system
@@ -312,7 +329,7 @@ num_squash_per_cycle=2
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
-power_model=Null
+power_model=
 sys=system
 
 [system.cpu0.itb]
@@ -334,7 +351,7 @@ num_squash_per_cycle=2
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
-power_model=Null
+power_model=
 sys=system
 
 [system.cpu0.tracer]
@@ -347,7 +364,7 @@ children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
 checker=Null
 clk_domain=system.clk_domain
 cpu_id=1
-dataTraceFile=../../DRAMSys/gem5/etraces/system.cpu.traceListener.random.data.gz
+dataTraceFile=/home/eder/repos/dram.vp.system/DRAMSys/gem5/etraces/system.cpu.traceListener.data.gz
 default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
@@ -359,7 +376,7 @@ eventq_index=0
 freqMultiplier=1.0
 function_trace=false
 function_trace_start=0
-instTraceFile=../../DRAMSys/gem5/etraces/system.cpu.traceListener.random.inst.gz
+instTraceFile=/home/eder/repos/dram.vp.system/DRAMSys/gem5/etraces/system.cpu.traceListener.inst.gz
 interrupts=system.cpu1.interrupts
 isa=system.cpu1.isa
 istage2_mmu=system.cpu1.istage2_mmu
@@ -373,7 +390,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_gating_on_idle=false
-power_model=Null
+power_model=
 profile=0
 progressMsgInterval=0
 progress_interval=0
@@ -394,7 +411,7 @@ icache_port=system.cpu1.icache.cpu_side
 
 [system.cpu1.dcache]
 type=Cache
-children=tags
+children=replacement_policy tags
 addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.clk_domain
@@ -409,9 +426,10 @@ mshrs=4
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
-power_model=Null
+power_model=
 prefetch_on_access=false
 prefetcher=Null
+replacement_policy=system.cpu1.dcache.replacement_policy
 response_latency=2
 sequential_access=false
 size=32768
@@ -419,13 +437,18 @@ system=system
 tag_latency=2
 tags=system.cpu1.dcache.tags
 tgts_per_mshr=20
+warmup_percentage=0
 write_buffers=8
 writeback_clean=false
 cpu_side=system.cpu1.dcache_port
 mem_side=system.membus2.slave[1]
 
+[system.cpu1.dcache.replacement_policy]
+type=LRURP
+eventq_index=0
+
 [system.cpu1.dcache.tags]
-type=LRU
+type=BaseSetAssoc
 assoc=2
 block_size=64
 clk_domain=system.clk_domain
@@ -435,10 +458,12 @@ eventq_index=0
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
-power_model=Null
+power_model=
+replacement_policy=system.cpu1.dcache.replacement_policy
 sequential_access=false
 size=32768
 tag_latency=2
+warmup_percentage=0
 
 [system.cpu1.dstage2_mmu]
 type=ArmStage2MMU
@@ -467,7 +492,7 @@ num_squash_per_cycle=2
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
-power_model=Null
+power_model=
 sys=system
 
 [system.cpu1.dtb]
@@ -489,12 +514,12 @@ num_squash_per_cycle=2
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
-power_model=Null
+power_model=
 sys=system
 
 [system.cpu1.icache]
 type=Cache
-children=tags
+children=replacement_policy tags
 addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.clk_domain
@@ -509,9 +534,10 @@ mshrs=4
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
-power_model=Null
+power_model=
 prefetch_on_access=false
 prefetcher=Null
+replacement_policy=system.cpu1.icache.replacement_policy
 response_latency=2
 sequential_access=false
 size=32768
@@ -519,13 +545,18 @@ system=system
 tag_latency=2
 tags=system.cpu1.icache.tags
 tgts_per_mshr=20
+warmup_percentage=0
 write_buffers=8
 writeback_clean=true
 cpu_side=system.cpu1.icache_port
 mem_side=system.membus2.slave[0]
 
+[system.cpu1.icache.replacement_policy]
+type=LRURP
+eventq_index=0
+
 [system.cpu1.icache.tags]
-type=LRU
+type=BaseSetAssoc
 assoc=2
 block_size=64
 clk_domain=system.clk_domain
@@ -535,10 +566,12 @@ eventq_index=0
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
-power_model=Null
+power_model=
+replacement_policy=system.cpu1.icache.replacement_policy
 sequential_access=false
 size=32768
 tag_latency=2
+warmup_percentage=0
 
 [system.cpu1.interrupts]
 type=ArmInterrupts
@@ -567,6 +600,7 @@ id_mmfr0=270536963
 id_mmfr1=0
 id_mmfr2=19070976
 id_mmfr3=34611729
+impdef_nop=false
 midr=1091551472
 pmu=Null
 system=system
@@ -599,7 +633,7 @@ num_squash_per_cycle=2
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
-power_model=Null
+power_model=
 sys=system
 
 [system.cpu1.itb]
@@ -621,7 +655,7 @@ num_squash_per_cycle=2
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
-power_model=Null
+power_model=
 sys=system
 
 [system.cpu1.tracer]
@@ -639,7 +673,7 @@ voltage_domain=system.cpu_voltage_domain
 [system.cpu_voltage_domain]
 type=VoltageDomain
 eventq_index=0
-voltage=1.000000
+voltage=1.0
 
 [system.dvfs_handler]
 type=DVFSHandler
@@ -662,7 +696,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 point_of_coherency=true
 point_of_unification=true
-power_model=Null
+power_model=
 response_latency=2
 snoop_filter=system.membus1.snoop_filter
 snoop_response_latency=4
@@ -692,7 +726,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 point_of_coherency=true
 point_of_unification=true
-power_model=Null
+power_model=
 response_latency=2
 snoop_filter=system.membus2.snoop_filter
 snoop_response_latency=4
@@ -724,7 +758,7 @@ null=false
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
-power_model=Null
+power_model=
 range=0:134217727:0:0:0:0
 
 [system.tlm1]
@@ -738,7 +772,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 port_data=transactor1
 port_type=tlm_slave
-power_model=Null
+power_model=
 port=system.membus1.master[0]
 
 [system.tlm2]
@@ -752,11 +786,11 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 port_data=transactor2
 port_type=tlm_slave
-power_model=Null
+power_model=
 port=system.membus2.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
 eventq_index=0
-voltage=1.000000
+voltage=1.0
 
diff --git a/DRAMSys/gem5/configs/singleElasticTraceReplay.dot.pdf b/DRAMSys/gem5/configs/singleElasticTraceReplay.dot.pdf
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diff --git a/DRAMSys/gem5/configs/singleElasticTraceReplay.ini b/DRAMSys/gem5/configs/singleElasticTraceReplay.ini
index e213531c..cec31376 100644
--- a/DRAMSys/gem5/configs/singleElasticTraceReplay.ini
+++ b/DRAMSys/gem5/configs/singleElasticTraceReplay.ini
@@ -21,7 +21,7 @@ init_param=0
 kernel=
 kernel_addr_check=true
 kernel_extras=
-load_addr_mask=1099511627775
+load_addr_mask=18446744073709551615
 load_offset=0
 mem_mode=timing
 mem_ranges=0:536870911:0:0:0:0
@@ -32,7 +32,7 @@ num_work_ids=16
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
-power_model=Null
+power_model=
 readfile=
 symbolfile=
 thermal_components=
@@ -72,7 +72,7 @@ eventq_index=0
 freqMultiplier=1.0
 function_trace=false
 function_trace_start=0
-instTraceFile=../../DRAMSys/gem5/etraces/system.cpu.traceListener.random.inst.gz
+instTraceFile=../../DRAMSys/gem5/etraces/system.cpu.traceListener.inst.gz
 interrupts=system.cpu.interrupts
 isa=system.cpu.isa
 istage2_mmu=system.cpu.istage2_mmu
@@ -86,7 +86,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_gating_on_idle=false
-power_model=Null
+power_model=
 profile=0
 progressMsgInterval=0
 progress_interval=0
@@ -107,7 +107,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=Cache
-children=tags
+children=replacement_policy tags
 addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.clk_domain
@@ -122,9 +122,10 @@ mshrs=4
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
-power_model=Null
+power_model=
 prefetch_on_access=false
 prefetcher=Null
+replacement_policy=system.cpu.dcache.replacement_policy
 response_latency=2
 sequential_access=false
 size=32768
@@ -132,13 +133,18 @@ system=system
 tag_latency=2
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
+warmup_percentage=0
 write_buffers=8
 writeback_clean=false
 cpu_side=system.cpu.dcache_port
 mem_side=system.membus.slave[2]
 
+[system.cpu.dcache.replacement_policy]
+type=LRURP
+eventq_index=0
+
 [system.cpu.dcache.tags]
-type=LRU
+type=BaseSetAssoc
 assoc=2
 block_size=64
 clk_domain=system.clk_domain
@@ -148,10 +154,12 @@ eventq_index=0
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
-power_model=Null
+power_model=
+replacement_policy=system.cpu.dcache.replacement_policy
 sequential_access=false
 size=32768
 tag_latency=2
+warmup_percentage=0
 
 [system.cpu.dstage2_mmu]
 type=ArmStage2MMU
@@ -180,7 +188,7 @@ num_squash_per_cycle=2
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
-power_model=Null
+power_model=
 sys=system
 
 [system.cpu.dtb]
@@ -202,12 +210,12 @@ num_squash_per_cycle=2
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
-power_model=Null
+power_model=
 sys=system
 
 [system.cpu.icache]
 type=Cache
-children=tags
+children=replacement_policy tags
 addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.clk_domain
@@ -222,9 +230,10 @@ mshrs=4
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
-power_model=Null
+power_model=
 prefetch_on_access=false
 prefetcher=Null
+replacement_policy=system.cpu.icache.replacement_policy
 response_latency=2
 sequential_access=false
 size=32768
@@ -232,13 +241,18 @@ system=system
 tag_latency=2
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
+warmup_percentage=0
 write_buffers=8
 writeback_clean=true
 cpu_side=system.cpu.icache_port
 mem_side=system.membus.slave[1]
 
+[system.cpu.icache.replacement_policy]
+type=LRURP
+eventq_index=0
+
 [system.cpu.icache.tags]
-type=LRU
+type=BaseSetAssoc
 assoc=2
 block_size=64
 clk_domain=system.clk_domain
@@ -248,10 +262,12 @@ eventq_index=0
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
-power_model=Null
+power_model=
+replacement_policy=system.cpu.icache.replacement_policy
 sequential_access=false
 size=32768
 tag_latency=2
+warmup_percentage=0
 
 [system.cpu.interrupts]
 type=ArmInterrupts
@@ -280,6 +296,7 @@ id_mmfr0=270536963
 id_mmfr1=0
 id_mmfr2=19070976
 id_mmfr3=34611729
+impdef_nop=false
 midr=1091551472
 pmu=Null
 system=system
@@ -312,7 +329,7 @@ num_squash_per_cycle=2
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
-power_model=Null
+power_model=
 sys=system
 
 [system.cpu.itb]
@@ -334,7 +351,7 @@ num_squash_per_cycle=2
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
-power_model=Null
+power_model=
 sys=system
 
 [system.cpu.tracer]
@@ -352,7 +369,7 @@ voltage_domain=system.cpu_voltage_domain
 [system.cpu_voltage_domain]
 type=VoltageDomain
 eventq_index=0
-voltage=1.000000
+voltage=1.0
 
 [system.dvfs_handler]
 type=DVFSHandler
@@ -375,7 +392,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 point_of_coherency=true
 point_of_unification=true
-power_model=Null
+power_model=
 response_latency=2
 snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
@@ -407,7 +424,7 @@ null=false
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
-power_model=Null
+power_model=
 range=0:134217727:0:0:0:0
 
 [system.tlm]
@@ -421,11 +438,11 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 port_data=transactor
 port_type=tlm_slave
-power_model=Null
+power_model=
 port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
 eventq_index=0
-voltage=1.000000
+voltage=1.0
 
diff --git a/DRAMSys/gem5/configs/singleElasticTraceReplayWithL2.dot.pdf b/DRAMSys/gem5/configs/singleElasticTraceReplayWithL2.dot.pdf
new file mode 100644
index 0000000000000000000000000000000000000000..f7e3d3f9a7045e83f369269e99552320f9bcf49d
GIT binary patch
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diff --git a/DRAMSys/gem5/configs/singleElasticTraceReplayWithL2.ini b/DRAMSys/gem5/configs/singleElasticTraceReplayWithL2.ini
index 4b277f75..5e8ef16a 100644
--- a/DRAMSys/gem5/configs/singleElasticTraceReplayWithL2.ini
+++ b/DRAMSys/gem5/configs/singleElasticTraceReplayWithL2.ini
@@ -20,7 +20,8 @@ exit_on_work_items=false
 init_param=0
 kernel=
 kernel_addr_check=true
-load_addr_mask=1099511627775
+kernel_extras=
+load_addr_mask=18446744073709551615
 load_offset=0
 mem_mode=timing
 mem_ranges=0:1073741823:0:0:0:0
@@ -31,7 +32,7 @@ num_work_ids=16
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
-power_model=Null
+power_model=
 readfile=
 symbolfile=
 thermal_components=
@@ -59,7 +60,7 @@ children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
 checker=Null
 clk_domain=system.clk_domain
 cpu_id=0
-dataTraceFile=/Users/myzinsky/EMS/Programming/gem5.traces/2015_09_08/hpc_simpoints/hpcc-gups/l1-base_l2-none_l3-base_mem-simple1/system.cluster.cpu.ElasticTrace.data.itrc.gz
+dataTraceFile=../../DRAMSys/gem5/etraces/system.cpu.traceListener.data.gz
 default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
@@ -71,7 +72,7 @@ eventq_index=0
 freqMultiplier=1.0
 function_trace=false
 function_trace_start=0
-instTraceFile=/Users/myzinsky/EMS/Programming/gem5.traces/2015_09_08/hpc_simpoints/hpcc-gups/l1-base_l2-none_l3-base_mem-simple1/system.cluster.cpu.ElasticTrace.inst.ptrc.gz
+instTraceFile=../../DRAMSys/gem5/etraces/system.cpu.traceListener.inst.gz
 interrupts=system.cpu.interrupts
 isa=system.cpu.isa
 istage2_mmu=system.cpu.istage2_mmu
@@ -84,10 +85,12 @@ numThreads=1
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
-power_model=Null
+power_gating_on_idle=false
+power_model=
 profile=0
 progressMsgInterval=0
 progress_interval=0
+pwr_gating_latency=300
 simpoint_start_insts=
 sizeLoadBuffer=16
 sizeROB=40
@@ -104,7 +107,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=Cache
-children=tags
+children=replacement_policy tags
 addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.clk_domain
@@ -119,9 +122,10 @@ mshrs=4
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
-power_model=Null
+power_model=
 prefetch_on_access=false
 prefetcher=Null
+replacement_policy=system.cpu.dcache.replacement_policy
 response_latency=2
 sequential_access=false
 size=32768
@@ -129,13 +133,18 @@ system=system
 tag_latency=2
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
+warmup_percentage=0
 write_buffers=8
 writeback_clean=false
 cpu_side=system.cpu.dcache_port
 mem_side=system.tol2bus.slave[1]
 
+[system.cpu.dcache.replacement_policy]
+type=LRURP
+eventq_index=0
+
 [system.cpu.dcache.tags]
-type=LRU
+type=BaseSetAssoc
 assoc=2
 block_size=64
 clk_domain=system.clk_domain
@@ -145,10 +154,12 @@ eventq_index=0
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
-power_model=Null
+power_model=
+replacement_policy=system.cpu.dcache.replacement_policy
 sequential_access=false
 size=32768
 tag_latency=2
+warmup_percentage=0
 
 [system.cpu.dstage2_mmu]
 type=ArmStage2MMU
@@ -177,7 +188,7 @@ num_squash_per_cycle=2
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
-power_model=Null
+power_model=
 sys=system
 
 [system.cpu.dtb]
@@ -199,12 +210,12 @@ num_squash_per_cycle=2
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
-power_model=Null
+power_model=
 sys=system
 
 [system.cpu.icache]
 type=Cache
-children=tags
+children=replacement_policy tags
 addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.clk_domain
@@ -219,9 +230,10 @@ mshrs=4
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
-power_model=Null
+power_model=
 prefetch_on_access=false
 prefetcher=Null
+replacement_policy=system.cpu.icache.replacement_policy
 response_latency=2
 sequential_access=false
 size=32768
@@ -229,13 +241,18 @@ system=system
 tag_latency=2
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
+warmup_percentage=0
 write_buffers=8
 writeback_clean=true
 cpu_side=system.cpu.icache_port
 mem_side=system.tol2bus.slave[0]
 
+[system.cpu.icache.replacement_policy]
+type=LRURP
+eventq_index=0
+
 [system.cpu.icache.tags]
-type=LRU
+type=BaseSetAssoc
 assoc=2
 block_size=64
 clk_domain=system.clk_domain
@@ -245,10 +262,12 @@ eventq_index=0
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
-power_model=Null
+power_model=
+replacement_policy=system.cpu.icache.replacement_policy
 sequential_access=false
 size=32768
 tag_latency=2
+warmup_percentage=0
 
 [system.cpu.interrupts]
 type=ArmInterrupts
@@ -277,6 +296,7 @@ id_mmfr0=270536963
 id_mmfr1=0
 id_mmfr2=19070976
 id_mmfr3=34611729
+impdef_nop=false
 midr=1091551472
 pmu=Null
 system=system
@@ -309,7 +329,7 @@ num_squash_per_cycle=2
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
-power_model=Null
+power_model=
 sys=system
 
 [system.cpu.itb]
@@ -331,7 +351,7 @@ num_squash_per_cycle=2
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
-power_model=Null
+power_model=
 sys=system
 
 [system.cpu.tracer]
@@ -349,7 +369,7 @@ voltage_domain=system.cpu_voltage_domain
 [system.cpu_voltage_domain]
 type=VoltageDomain
 eventq_index=0
-voltage=1.000000
+voltage=1.0
 
 [system.dvfs_handler]
 type=DVFSHandler
@@ -361,7 +381,7 @@ transition_latency=100000000
 
 [system.l2cache]
 type=Cache
-children=tags
+children=replacement_policy tags
 addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.clk_domain
@@ -376,9 +396,10 @@ mshrs=20
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
-power_model=Null
+power_model=
 prefetch_on_access=false
 prefetcher=Null
+replacement_policy=system.l2cache.replacement_policy
 response_latency=20
 sequential_access=false
 size=1048576
@@ -386,13 +407,18 @@ system=system
 tag_latency=20
 tags=system.l2cache.tags
 tgts_per_mshr=12
+warmup_percentage=0
 write_buffers=8
 writeback_clean=false
 cpu_side=system.tol2bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.l2cache.replacement_policy]
+type=LRURP
+eventq_index=0
+
 [system.l2cache.tags]
-type=LRU
+type=BaseSetAssoc
 assoc=8
 block_size=64
 clk_domain=system.clk_domain
@@ -402,10 +428,12 @@ eventq_index=0
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
-power_model=Null
+power_model=
+replacement_policy=system.l2cache.replacement_policy
 sequential_access=false
 size=1048576
 tag_latency=20
+warmup_percentage=0
 
 [system.membus]
 type=CoherentXBar
@@ -419,7 +447,8 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 point_of_coherency=true
-power_model=Null
+point_of_unification=true
+power_model=
 response_latency=2
 snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
@@ -451,7 +480,7 @@ null=false
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
-power_model=Null
+power_model=
 range=0:134217727:0:0:0:0
 
 [system.tlm]
@@ -465,7 +494,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 port_data=transactor
 port_type=tlm_slave
-power_model=Null
+power_model=
 port=system.membus.master[0]
 
 [system.tol2bus]
@@ -480,7 +509,8 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 point_of_coherency=false
-power_model=Null
+point_of_unification=true
+power_model=
 response_latency=1
 snoop_filter=system.tol2bus.snoop_filter
 snoop_response_latency=1
@@ -500,5 +530,5 @@ system=system
 [system.voltage_domain]
 type=VoltageDomain
 eventq_index=0
-voltage=1.000000
+voltage=1.0
 
diff --git a/DRAMSys/gem5/examples/tlm_elastic_slave.py b/DRAMSys/gem5/examples/tlm_elastic_slave.py
index 6992bdf2..07f97fa0 100644
--- a/DRAMSys/gem5/examples/tlm_elastic_slave.py
+++ b/DRAMSys/gem5/examples/tlm_elastic_slave.py
@@ -80,6 +80,8 @@ system.voltage_domain = VoltageDomain()
 system.clk_domain = SrcClockDomain(clock =  '1GHz',
         voltage_domain = system.voltage_domain)
 
+system.cpu.createThreads()
+
 # Create a CPU voltage domain:
 system.cpu_voltage_domain = VoltageDomain()
 
@@ -95,9 +97,10 @@ system.cpu.dcache = L1_DCache(size="32kB")
 system.cpu.icache.cpu_side = system.cpu.icache_port
 system.cpu.dcache.cpu_side = system.cpu.dcache_port
 
-# Assign input trace files to the eTraceCPU:
-system.cpu.instTraceFile="system.cpu.traceListener.inst.gz"
-system.cpu.dataTraceFile="system.cpu.traceListener.data.gz"
+# XXX: Assign input trace files to the eTraceCPU (you have to set this path
+# properly before running gem5):
+system.cpu.instTraceFile="dram.vp.system/DRAMSys/gem5/etraces/system.cpu.traceListener.inst.gz"
+system.cpu.dataTraceFile="dram.vp.system/DRAMSys/gem5/etraces/system.cpu.traceListener.data.gz"
 
 # Setting up L1 BUS:
 system.membus = IOXBar(width = 16)
@@ -107,7 +110,7 @@ system.physmem = SimpleMemory() # This must be instantiated, even if not needed
 system.tlm = ExternalSlave()
 system.tlm.addr_ranges = [AddrRange('512MB')]
 system.tlm.port_type = "tlm_slave"
-system.tlm.port_data = "transactor1"
+system.tlm.port_data = "transactor"
 
 # Connect everything:
 system.membus = SystemXBar()
diff --git a/DRAMSys/gem5/examples/tlm_elastic_slave_mc_direct.py b/DRAMSys/gem5/examples/tlm_elastic_slave_mc_direct.py
index 2408b18b..58c0b632 100644
--- a/DRAMSys/gem5/examples/tlm_elastic_slave_mc_direct.py
+++ b/DRAMSys/gem5/examples/tlm_elastic_slave_mc_direct.py
@@ -94,19 +94,21 @@ system.cpu[0].icache = L1_ICache(size="32kB")
 system.cpu[0].dcache = L1_DCache(size="32kB")
 system.cpu[0].icache.cpu_side = system.cpu[0].icache_port
 system.cpu[0].dcache.cpu_side = system.cpu[0].dcache_port
+system.cpu[0].createThreads()
 
 system.cpu[1].createInterruptController()
 system.cpu[1].icache = L1_ICache(size="32kB")
 system.cpu[1].dcache = L1_DCache(size="32kB")
 system.cpu[1].icache.cpu_side = system.cpu[1].icache_port
 system.cpu[1].dcache.cpu_side = system.cpu[1].dcache_port
+system.cpu[1].createThreads()
 
-# Assign input trace files to the eTraceCPU:
-system.cpu[0].instTraceFile="system.cpu.traceListener.inst.gz"
-system.cpu[0].dataTraceFile="system.cpu.traceListener.data.gz"
-
-system.cpu[1].instTraceFile="system.cpu.traceListener.inst.gz"
-system.cpu[1].dataTraceFile="system.cpu.traceListener.data.gz"
+# XXX: Assign input trace files to the eTraceCPU (you have to set this path
+# properly before running gem5):
+system.cpu[0].instTraceFile="dram.vp.system/DRAMSys/gem5/etraces/system.cpu.traceListener.inst.gz"
+system.cpu[0].dataTraceFile="dram.vp.system/DRAMSys/gem5/etraces/system.cpu.traceListener.data.gz"
+system.cpu[1].instTraceFile="dram.vp.system/DRAMSys/gem5/etraces/system.cpu.traceListener.inst.gz"
+system.cpu[1].dataTraceFile="dram.vp.system/DRAMSys/gem5/etraces/system.cpu.traceListener.data.gz"
 
 # Setting up memory BUS:
 system.physmem = SimpleMemory() # This must be instantiated, even if not needed
diff --git a/DRAMSys/gem5/examples/tlm_elastic_slave_with_l2.py b/DRAMSys/gem5/examples/tlm_elastic_slave_with_l2.py
index f0142e53..8efd3c79 100644
--- a/DRAMSys/gem5/examples/tlm_elastic_slave_with_l2.py
+++ b/DRAMSys/gem5/examples/tlm_elastic_slave_with_l2.py
@@ -86,6 +86,8 @@ system.voltage_domain = VoltageDomain()
 system.clk_domain = SrcClockDomain(clock =  '1GHz',
         voltage_domain = system.voltage_domain)
 
+system.cpu.createThreads()
+
 # Create a CPU voltage domain:
 system.cpu_voltage_domain = VoltageDomain()
 
@@ -101,20 +103,21 @@ system.cpu.dcache = L1_DCache(size="32kB")
 system.cpu.icache.cpu_side = system.cpu.icache_port
 system.cpu.dcache.cpu_side = system.cpu.dcache_port
 
-# Assign input trace files to the eTraceCPU:
-system.cpu.instTraceFile="system.cpu.traceListener.inst.gz"
-system.cpu.dataTraceFile="system.cpu.traceListener.data.gz"
+# XXX: Assign input trace files to the eTraceCPU (you have to set this path
+# properly before running gem5):
+system.cpu.instTraceFile="dram.vp.system/DRAMSys/gem5/etraces/system.cpu.traceListener.inst.gz"
+system.cpu.dataTraceFile="dram.vp.system/DRAMSys/gem5/etraces/system.cpu.traceListener.data.gz"
 
 # Setting up L1 BUS:
-system.tol2bus = L2XBar()#(width = 16)
+system.tol2bus = L2XBar()
 system.l2cache = L2Cache(size="1MB")
 system.physmem = SimpleMemory() # This must be instantiated, even if not needed
 
 # Create a external TLM port:
 system.tlm = ExternalSlave()
-system.tlm.addr_ranges = [AddrRange('4024MB')]
+system.tlm.addr_ranges = [AddrRange('4096MB')]
 system.tlm.port_type = "tlm_slave"
-system.tlm.port_data = "transactor1"
+system.tlm.port_data = "transactor"
 
 # Connect everything:
 system.membus = SystemXBar()
@@ -129,4 +132,4 @@ system.membus.master = system.tlm.port
 root = Root(full_system = False, system = system)
 root.system.mem_mode = 'timing'
 m5.instantiate()
-m5.simulate() #Simulation time specified later on commandline
+m5.simulate()
diff --git a/README.md b/README.md
index b7b0fc1c..20b7762b 100644
--- a/README.md
+++ b/README.md
@@ -1696,8 +1696,19 @@ This is an example for running an elastic trace:
 ./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.xml ../../DRAMSys/gem5/configs/singleElasticTraceReplay.ini
 ```
 
+An overview of the architcture being simulated is presented below:
+
+![arch](DRAMSys/docs/images/singleElasticTraceReplay.png)
+
+
 Note that the address offset is usually zero for elastic traces.
 
+Another example with L2 cache:
+
+```bash
+./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.xml ../../DRAMSys/gem5/configs/singleElasticTraceReplayWithL2.ini 
+```
+
 If two elastic traces should be used the main.cpp must be modified:
 
 ```c++
@@ -1712,6 +1723,10 @@ Run the simulation with the following example:
 ./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.xml ../../DRAMSys/gem5/configs/dualElasticTraceReplay.ini
 ```
 
+An overview of the architcture being simulated is presented below:
+
+![arch](DRAMSys/docs/images/dualElasticTraceReplay.png)
+
 For more spophisticated setups, even with l2 caches the proper ini file should be created.
 If you need help please contact Matthias Jung.