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Include elastic trace example, extend readme.

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This commit is contained in:
Lukas Steiner
2020-07-09 09:30:58 +02:00
parent 156bbb7442
commit 9fe7232d7f
3 changed files with 594 additions and 81 deletions
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18
DRAMSys/gem5/README.md
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@@ -14,7 +14,7 @@ $ scons --with-cxx-config --without-python --without-tcmalloc build/ARM/libgem5_
In order to use gem5 with DRAMSys export the `GEM5` environment variable (gem5 root directory) and add the path of the library to `LD_LIBRARY_PATH`, then rerun CMake and rebuild the DRAMSys project.
### DRAMSys with gem5 ARM SE mode
### DRAMSys with gem5 ARM SE Mode
All essential files for a functional example are provided. Execute a hello world application:
@@ -25,7 +25,7 @@ $ ./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json .
A **Hello world!** message should be printed to the standard output.
### DRAMSys with gem5 X86 SE mode
### DRAMSys with gem5 X86 SE Mode
Make sure you have built *gem5/build/X86/libgem5_opt.so*. Add the path of the library to `LD_LIBRARY_PATH` and remove the path of the ARM library.
@@ -38,7 +38,21 @@ $ ./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json .
A **Hello world!** message should be printed to the standard output.
### DRAMSys with gem5 TraceCPU and Elastic Traces
In order to understand elastic traces and their generation you should take a look at the [gem5 wiki](https://www.gem5.org/documentation/general_docs/cpu_models/TraceCPU) and the paper [2].
All essential files for a functional example are provided. The example can be executed as follows:
```bash
$ cd DRAMSys/build/gem5
$ ./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.json ../../DRAMSys/gem5/gem5_etrace/config.ini 1
```
## References
[1] System Simulation with gem5 and SystemC: The Keystone for Full Interoperability
C. Menard, M. Jung, J. Castrillon, N. Wehn. IEEE International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS), July, 2017, Samos Island, Greece.
[2] Exploring System Performance using Elastic Traces: Fast, Accurate and Portable
R. Jagtap, S. Diestelhorst, A. Hansson, M. Jung, N. Wehn. IEEE International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS), July, 2016, Samos Island, Greece.

448
DRAMSys/gem5/gem5_etrace/config.ini Normal file
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@@ -0,0 +1,448 @@
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler membus physmem tlm voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
kernel_extras=
load_addr_mask=18446744073709551615
load_offset=0
mem_mode=timing
mem_ranges=0:536870911:0:0:0:0
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=TraceCPU
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
checker=Null
clk_domain=system.clk_domain
cpu_id=0
dataTraceFile=../../DRAMSys/gem5/gem5_etrace/system.cpu.traceListener.data.gz
default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu.dstage2_mmu
dtb=system.cpu.dtb
enableEarlyExit=false
eventq_index=0
freqMultiplier=1.0
function_trace=false
function_trace_start=0
instTraceFile=../../DRAMSys/gem5/gem5_etrace/system.cpu.traceListener.inst.gz
interrupts=system.cpu.interrupts
isa=system.cpu.isa
istage2_mmu=system.cpu.istage2_mmu
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_gating_on_idle=false
power_model=
profile=0
progressMsgInterval=0
progress_interval=0
pwr_gating_latency=300
simpoint_start_insts=
sizeLoadBuffer=16
sizeROB=40
sizeStoreBuffer=16
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
wait_for_remote_gdb=false
workload=
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=Cache
children=replacement_policy tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
prefetch_on_access=false
prefetcher=Null
replacement_policy=system.cpu.dcache.replacement_policy
response_latency=2
sequential_access=false
size=32768
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
warmup_percentage=0
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.membus.slave[2]
[system.cpu.dcache.replacement_policy]
type=LRURP
eventq_index=0
[system.cpu.dcache.tags]
type=BaseSetAssoc
assoc=2
block_size=64
clk_domain=system.clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
replacement_policy=system.cpu.dcache.replacement_policy
sequential_access=false
size=32768
tag_latency=2
warmup_percentage=0
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
sys=system
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
[system.cpu.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
sys=system
[system.cpu.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
sys=system
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
sys=system
[system.cpu.icache]
type=Cache
children=replacement_policy tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=true
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
prefetch_on_access=false
prefetcher=Null
replacement_policy=system.cpu.icache.replacement_policy
response_latency=2
sequential_access=false
size=32768
system=system
tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
warmup_percentage=0
write_buffers=8
writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.membus.slave[1]
[system.cpu.icache.replacement_policy]
type=LRURP
eventq_index=0
[system.cpu.icache.tags]
type=BaseSetAssoc
assoc=2
block_size=64
clk_domain=system.clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
replacement_policy=system.cpu.icache.replacement_policy
sequential_access=false
size=32768
tag_latency=2
warmup_percentage=0
[system.cpu.interrupts]
type=ArmInterrupts
eventq_index=0
[system.cpu.isa]
type=ArmISA
decoderFlavour=Generic
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
impdef_nop=false
midr=1091551472
pmu=Null
system=system
vecRegRenameMode=Full
[system.cpu.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
sys=system
walker=system.cpu.istage2_mmu.stage2_tlb.walker
[system.cpu.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
sys=system
[system.cpu.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
sys=system
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
sys=system
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu_clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.cpu_voltage_domain
[system.cpu_voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.0
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
point_of_unification=true
power_model=
response_latency=2
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.tlm.port
slave=system.system_port system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
kvm_map=true
latency=30000
latency_var=0
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
range=0:134217727:0:0:0:0
[system.tlm]
type=ExternalSlave
addr_ranges=0:536870911:0:0:0:0
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
port_data=transactor
port_type=tlm_slave
power_model=
port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.0

205
README.md
View File

@@ -1,19 +1,31 @@
DRAMSys4.0
===========
**DRAMSys4.0** [1] [2] [3] is a flexible DRAM subsystem design space exploration framework that consists of models reflecting the DRAM functionality, power consumption, temperature behavior and retention time errors.
**DRAMSys4.0** [1] [2] [3] is a flexible DRAM subsystem design space exploration framework based on SystemC TLM-2.0.
Pipeline Status: [![pipeline status](https://git.eit.uni-kl.de/ems/astdm/dram.sys/badges/master/pipeline.svg)](https://git.eit.uni-kl.de/ems/astdm/dram.sys/commits/master)
[![Coverage report](https://git.eit.uni-kl.de/ems/astdm/dram.sys/badges/master/coverage.svg?job=coverage)](https://git.eit.uni-kl.de/ems/astdm/dram.sys/commits/master)
## Key Features
- **standalone** simulator with trace players, **gem5**-coupled simulator and **TLM-AT-compliant library**
- support for **DDR3/4**, **LPDDR4**, **Wide I/O 1/2**, **GDDR5/5X/6** and **HBM2**
- automatic source code generation for new JEDEC standards [3] [9] from the domain-specific language DRAMml
- FIFO, FR-FCFS and FR-FCFS with read/write grouping scheduling policies
- open, closed, open adaptive and closed adaptive page policy [8]
- all-bank refresh and per-bank refresh with pulled-in and postponed refresh commands
- staggered power down [5]
- coupling to **DRAMPower** [4] and **3D-ICE** [8] for power and thermal simulation
- **Trace Analyzer** for visual and metric-based result analysis
## Basic Setup
Start using DRAMSys by cloning the repository.
Use the *--recursive* flag to initialize all submodules within the repository, namely **DRAMPower** [4], **SystemC** and **nlohmann json**.
Use the *--recursive* flag to initialize all submodules within the repository, namely **DRAMPower**, **SystemC** and **nlohmann json**.
### Dependencies
DRAMSys is based on the SystemC library. SystemC is included as a submodule and will be build automatically with the DRAMSys project. If you want to use an external SystemC version you have to export the environment variables `SYSTEMC_HOME` (SystemC root directory), `SYSTEMC_TARGET_ARCH` (e.g. linux64) and add the path of the library to `LD_LIBRARY_PATH`.
DRAMSys is based on the SystemC library. SystemC is included as a submodule and will be build automatically with the DRAMSys project. If you want to use an external SystemC version, export the environment variables `SYSTEMC_HOME` (SystemC root directory) and `SYSTEMC_TARGET_ARCH` (e.g. linux64) and add the path of the library to `LD_LIBRARY_PATH`.
### Building DRAMSys
DRAMSys uses CMake for the build process, the minimum required version is **CMake 3.10**.
@@ -28,7 +40,7 @@ $ cmake ../DRAMSys/
$ make
```
If you plan to integrate DRAMSys into your own SystemC/TLM project you can build the DRAMSys library only:
If you plan to integrate DRAMSys into your own SystemC TLM-2.0 project you can build the DRAMSys library only:
```bash
$ cd DRAMSys
@@ -40,6 +52,8 @@ $ make
To build DRAMSys on Windows 10 we recommend to use the **Windows Subsystem for Linux (WSL)**.
Information on how to couple DRAMSys with **gem5** can be found [here](DRAMSys/gem5/README.md).
### Executing DRAMSys
From the build directory use the commands below to execute the DRAMSys standalone.
@@ -92,13 +106,13 @@ The JSON code below shows an example configuration:
}
```
Fields Description:
- "simulationid": Simulation file identifier
- "simconfig": Configuration file for the DRAMSys Simulator
- "thermalconfig": Temperature Simulator Configuration File
- "memspec": Memory Device Specification File
- "addressmapping": Addressmapping Configuration of the Memory Controller File.
- "mcconfig": Memory Controller Configuration File.
- "tracesetup": The trace setup is only used in standalone mode. In library mode the trace setup is ignored. Each device should be added as a json object inside the "tracesetup" array.
- "simulationid": simulation file identifier
- "simconfig": configuration file for the DRAMSys simulator
- "thermalconfig": thermal simulation configuration file
- "memspec": memory device configuration file
- "addressmapping": address mapping configuration file
- "mcconfig": memory controller configuration file
- "tracesetup": The trace setup is only used in standalone mode. In library mode or gem5 mode the trace setup is ignored. Each device should be added as a json object inside the "tracesetup" array.
Each **trace setup** device configuration consists of two parameters, **clkMhz** (operation frequency of the **trace player**) and a trace file **name**. Most configuration fields reference other JSON files which contain more specialized chunks of the configuration like a memory specification, an address mapping and a memory controller configuration.
@@ -109,11 +123,11 @@ A **trace file** is a prerecorded file containing memory transactions. Each memo
There are two different kinds of trace files. They differ in their timing behavior and are distinguished by their file extension.
##### STL Trace (.stl)
##### STL Traces (.stl)
The times tamp corresponds to the time the request is to be issued and it is given in cycles of the bus master device. Example: the device is an FPGA with a frequency of 200 MHz (clock period of 5 ns). If the time stamp is 10 it means that the request is to be issued when time is 50 ns.
The time stamp corresponds to the time the request is to be issued and it is given in cycles of the bus master device. Example: The device is an FPGA with a frequency of 200 MHz (clock period of 5 ns). If the time stamp is 10 the request is to be issued when time is 50 ns.
Here is an example syntax:
Syntax example:
```
# Comment lines begin with #
@@ -126,9 +140,9 @@ Here is an example syntax:
##### Relative STL Traces (.rstl)
The time stamp corresponds to the time the request is to be issued relative to the end of the transaction before or the beginning of the trace. This results in a simulation in which the trace player is able to react to possible delays due to DRAM bottlenecks.
The time stamp corresponds to the time the request is to be issued relative to the end of the previous transaction. This results in a simulation in which the trace player is able to react to possible delays due to DRAM bottlenecks.
Here is an example syntax:
Syntax example:
```
# Comment lines begin with #
@@ -139,15 +153,17 @@ Here is an example syntax:
25: read 0x400180
```
##### Elastic Traces
More information about elastic traces can be found in the [gem5 readme](DRAMSys/gem5/README.md).
#### Trace Player
A **trace player** is **equivalent** to a bus master **device** (processor, FPGA, etc.). It reads an input trace file and translates each line into a new memory request. By adding a new device element into the trace setup section one can specify a new trace player, its operating frequency and the trace file for that trace player.
A trace player is equivalent to a bus master device (processor, FPGA, etc.). It reads an input trace file and translates each line into a new memory request. By adding a new device element into the trace setup section one can specify a new trace player, its operating frequency and its trace file.
#### Configuration File Sections
The main configuration file is divided into self-contained sections. Each of these sections refers to sub-configuration files.
Below, the sub-configurations are listed and explained.
The main configuration file is divided into self-contained sections. Each of these sections refers to sub-configuration files. Below, the sub-configurations are listed and explained.
##### Simulator Configuration
@@ -217,64 +233,15 @@ The content of [ddr3.json](DRAMSys/library/resources/configs/simulator/ddr3.json
- "Store": store data without error model
- "ErrorModel": store data with error model [6]
##### Temperature Simulator Configuration
##### Thermal Simulation
The content of [config.json](DRAMSys/library/resources/configs/thermalsim/config.json) is presented below as an example.
```json
{
"thermalsimconfig": {
"TemperatureScale": "Celsius",
"StaticTemperatureDefaultValue": 89,
"ThermalSimPeriod": 100,
"ThermalSimUnit": "us",
"PowerInfoFile": "powerInfo.json",
"IceServerIp": "127.0.0.1",
"IceServerPort": 11880,
"SimPeriodAdjustFactor": 10,
"NPowStableCyclesToIncreasePeriod": 5,
"GenerateTemperatureMap": true,
"GeneratePowerMap": true
}
}
```
- *TemperatureScale* (string)
- "Celsius"
- "Fahrenheit"
- "Kelvin"
- *StaticTemperatureDefaultValue* (int)
- Temperature value for simulations with static temperature
- *ThermalSimPeriod* (double)
- Period of the thermal simulation
- *ThermalSimUnit* (string)
- "s": seconds
- "ms": millisecond
- "us": microseconds
- "ns": nanoseconds
- "ps": picoseconds
- "fs": femtoseconds
- *PowerInfoFile* (string)
- File containing power related information: devices identifiers, initial power values and power thresholds.
- *IceServerIp* (string)
- 3D-ICE server IP address
- *IceServerPort* (unsigned int)
- 3D-ICE server port
- *SimPeriodAdjustFactor* (unsigned int)
- When substantial changes in power occur (i.e., changes that exceed the thresholds), then the simulation period will be divided by this number causing the thermal simulation to be executed more often.
- *NPowStableCyclesToIncreasePeriod* (unsigned int)
- Wait this number of thermal simulation cycles with power stability (i.e., changes that do not exceed the thresholds) to start increasing the simulation period back to its configured value.
- *GenerateTemperatureMap* (boolean)
- true: generate temperature map files during thermal simulation
- false: do not generate temperature map files during thermal simulation
- *GeneratePowerMap* (boolean)
- true: generate power map files during thermal simulation
- false: do not generate power map files during thermal simulation
The thermal simulation configuration can be found [here](#thermal-simulation-configuration).
##### Memory Specification
A file with memory specifications. Timings and currents come from data sheets and measurements, and usually do not change.
The fields inside "mempowerspec" can be written directly as a **double** type. "memoryId" and "memoryType" are **string**. The others are **unsigned int**.
A file with memory specifications. Timings and currents come from data sheets and measurements and usually do not change.
The fields inside "mempowerspec" can be written directly as a **double** type, "memoryId" and "memoryType" are **string**, all other fields are **unsigned int**.
##### Address Mapping
@@ -308,7 +275,7 @@ Used fields:
```
##### Memory Controller Configuration
##### Memory Controller
An example follows.
@@ -461,13 +428,89 @@ $ cd DRAMSys/build/simulator/
$ ./DRAMSys ../../DRAMSys/library/resources/simulations/wideio-thermal.json
```
## DRAMSys with gem5
#### Thermal Simulation Configuration
Further information about the usage of DRAMSys with gem5 can be found [here](DRAMSys/gem5/README.md).
The content of [config.json](DRAMSys/library/resources/configs/thermalsim/config.json) is presented below as an example.
```json
{
"thermalsimconfig": {
"TemperatureScale": "Celsius",
"StaticTemperatureDefaultValue": 89,
"ThermalSimPeriod": 100,
"ThermalSimUnit": "us",
"PowerInfoFile": "powerInfo.json",
"IceServerIp": "127.0.0.1",
"IceServerPort": 11880,
"SimPeriodAdjustFactor": 10,
"NPowStableCyclesToIncreasePeriod": 5,
"GenerateTemperatureMap": true,
"GeneratePowerMap": true
}
}
```
- *TemperatureScale* (string)
- "Celsius"
- "Fahrenheit"
- "Kelvin"
- *StaticTemperatureDefaultValue* (int)
- Temperature value for simulations with static temperature
- *ThermalSimPeriod* (double)
- Period of the thermal simulation
- *ThermalSimUnit* (string)
- "s": seconds
- "ms": millisecond
- "us": microseconds
- "ns": nanoseconds
- "ps": picoseconds
- "fs": femtoseconds
- *PowerInfoFile* (string)
- File containing power related information: devices identifiers, initial power values and power thresholds.
- *IceServerIp* (string)
- 3D-ICE server IP address
- *IceServerPort* (unsigned int)
- 3D-ICE server port
- *SimPeriodAdjustFactor* (unsigned int)
- When substantial changes in power occur (i.e., changes that exceed the thresholds), then the simulation period will be divided by this number causing the thermal simulation to be executed more often.
- *NPowStableCyclesToIncreasePeriod* (unsigned int)
- Wait this number of thermal simulation cycles with power stability (i.e., changes that do not exceed the thresholds) to start increasing the simulation period back to its configured value.
- *GenerateTemperatureMap* (boolean)
- true: generate temperature map files during thermal simulation
- false: do not generate temperature map files during thermal simulation
- *GeneratePowerMap* (boolean)
- true: generate power map files during thermal simulation
- false: do not generate power map files during thermal simulation
## Trace Analyzer
If you want to use the database recording feature and the Trace Analyzer tool for result analysis please contact [Matthias Jung](mailto:matthias.jung@iese.fraunhofer.de).
To provide better analysis capabilities for DRAM subsystem design space exploration than the usual performance-related outputs to the console, DRAMSys offers the Trace Analyzer.
All requests, responses and DRAM commands can be recorded in an SQLite trace database during a simulation and visualized with the tool afterwards. An evaluation of the trace databases can be performed with the powerful Python interface of the Trace Analyzer. Different metrics are described as SQL statements and formulas in Python, which can be customized or extended without recompilation.
The Trace Analyzer's main window is shown below.
If you are interested in the database recording feature and the Trace Analyzer please contact [Matthias Jung](mailto:matthias.jung@iese.fraunhofer.de).
![Trace Analyzer Main Window](DRAMSys/docs/images/traceanalyzer.png)
## List of Contributors
Shama Bhosale
Luiza Correa
Peter Ehses
Johannes Feldmann
Robert Gernhardt
Doris Gulai
Matthias Jung
Frederik Lauer
Ana Mativi
Felipe S. Prado
Janik Schlemminger
Lukas Steiner
Thanh C. Tran
Tran Anh Quoc
Éder F. Zulian
## Disclaimer
@@ -475,6 +518,8 @@ This is the public read-only mirror of an internal DRAMSys repository. Pull requ
The user DOES NOT get ANY WARRANTIES when using this tool. This software is released under the BSD 3-Clause License. By using this software, the user implicitly agrees to the licensing terms.
If you decide to use DRAMSys in your research please cite the paper [3].
## References
[1] TLM Modelling of 3D Stacked Wide I/O DRAM Subsystems, A Virtual Platform for Memory Controller Design Space Exploration
@@ -497,3 +542,9 @@ C. Weis, M. Jung, P. Ehses, C. Santos, P. Vivet, S. Goossens, M. Koedam, N. Wehn
[7] ConGen: An Application Specific DRAM Memory Controller Generator
M. Jung, I. Heinrich, M. Natale, D. M. Mathew, C. Weis, S. Krumke, N. Wehn. International Symposium on Memory Systems (MEMSYS 2016), October, 2016, Washington, DC, USA.
[8] Simulating DRAM controllers for future system architecture exploration
A. Hansson, N. Agarwal, A. Kolli, T. Wenisch, A. N. Udipi. IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2014, Monterey, USA.
[9] Fast Validation of DRAM Protocols with Timed Petri Nets
M. Jung, K. Kraft, T. Soliman, C. Sudarshan, C. Weis, N. Wehn. ACM International Symposium on Memory Systems (MEMSYS 2019), October, 2019, Washington, DC, USA.