diff --git a/.gitignore b/.gitignore index da990e0b..97b2ac1b 100644 --- a/.gitignore +++ b/.gitignore @@ -24,3 +24,5 @@ DRAMSys/analyzer/scripts/__pycache__/ DRAMSys/gem5/boot_linux/linux-aarch32-ael.img DRAMSys/docs/doxygen /.vscode +/cmake-build* +/.idea diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-3200A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-3200A.json index 8bc5a428..75172a46 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-3200A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-3200A.json @@ -34,7 +34,8 @@ "WPST": 0, "WR": 48, "CCD_L_slr": 8, - "CCD_L_WR_slr": 16, + "CCD_L_WR_slr": 32, + "CCD_L_WR2_slr": 16, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -70,4 +71,4 @@ "clkMhz": 1600 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-3600A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-3600A.json index 639c16a9..e35d934f 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-3600A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-3600A.json @@ -34,7 +34,8 @@ "WPST": 0, "WR": 54, "CCD_L_slr": 9, - "CCD_L_WR_slr": 18, + "CCD_L_WR_slr": 36, + "CCD_L_WR2_slr": 18, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -70,4 +71,4 @@ "clkMhz": 1800 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4000A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4000A.json index 98d6a123..484ba99f 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4000A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4000A.json @@ -34,7 +34,8 @@ "WPST": 0, "WR": 60, "CCD_L_slr": 10, - "CCD_L_WR_slr": 20, + "CCD_L_WR_slr": 40, + "CCD_L_WR2_slr": 20, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -70,4 +71,4 @@ "clkMhz": 2000 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4400A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4400A.json index e27d625d..43b961e5 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4400A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4400A.json @@ -34,7 +34,8 @@ "WPST": 0, "WR": 66, "CCD_L_slr": 11, - "CCD_L_WR_slr": 22, + "CCD_L_WR_slr": 44, + "CCD_L_WR2_slr": 22, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -70,4 +71,4 @@ "clkMhz": 2200 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4800A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4800A.json index 5fef3321..eb4a3b8c 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4800A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4800A.json @@ -34,7 +34,8 @@ "WPST": 0, "WR": 72, "CCD_L_slr": 12, - "CCD_L_WR_slr": 24, + "CCD_L_WR_slr": 48, + "CCD_L_WR2_slr": 24, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -70,4 +71,4 @@ "clkMhz": 2400 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-5200A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-5200A.json index 358643b8..030f4e43 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-5200A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-5200A.json @@ -34,7 +34,8 @@ "WPST": 0, "WR": 78, "CCD_L_slr": 13, - "CCD_L_WR_slr": 26, + "CCD_L_WR_slr": 52, + "CCD_L_WR2_slr": 26, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -70,4 +71,4 @@ "clkMhz": 2600 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-5600A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-5600A.json index 766c837c..8de5c0f9 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-5600A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-5600A.json @@ -34,7 +34,8 @@ "WPST": 0, "WR": 84, "CCD_L_slr": 14, - "CCD_L_WR_slr": 28, + "CCD_L_WR_slr": 56, + "CCD_L_WR2_slr": 28, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -70,4 +71,4 @@ "clkMhz": 2800 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-6000A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-6000A.json index 9e387dc4..0bf780ec 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-6000A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-6000A.json @@ -34,7 +34,8 @@ "WPST": 0, "WR": 90, "CCD_L_slr": 15, - "CCD_L_WR_slr": 30, + "CCD_L_WR_slr": 60, + "CCD_L_WR2_slr": 30, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -70,4 +71,4 @@ "clkMhz": 3000 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-6400A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-6400A.json index 18caa618..70d03828 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-6400A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-6400A.json @@ -34,7 +34,8 @@ "WPST": 0, "WR": 96, "CCD_L_slr": 16, - "CCD_L_WR_slr": 32, + "CCD_L_WR_slr": 64, + "CCD_L_WR2_slr": 32, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -70,4 +71,4 @@ "clkMhz": 3200 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-3200A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-3200A.json index aa6e82b0..635cc6cf 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-3200A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-3200A.json @@ -35,6 +35,7 @@ "WR": 48, "CCD_L_slr": 8, "CCD_L_WR_slr": 32, + "CCD_L_WR2_slr": 16, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -70,4 +71,4 @@ "clkMhz": 1600 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-3600A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-3600A.json index 96359874..ac39be46 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-3600A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-3600A.json @@ -35,6 +35,7 @@ "WR": 54, "CCD_L_slr": 9, "CCD_L_WR_slr": 36, + "CCD_L_WR2_slr": 18, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -70,4 +71,4 @@ "clkMhz": 1800 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-4000A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-4000A.json index bf632566..9887512d 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-4000A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-4000A.json @@ -35,6 +35,7 @@ "WR": 60, "CCD_L_slr": 10, "CCD_L_WR_slr": 40, + "CCD_L_WR2_slr": 20, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -70,4 +71,4 @@ "clkMhz": 2000 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-4400A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-4400A.json index a343598b..cd9bdced 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-4400A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-4400A.json @@ -35,6 +35,7 @@ "WR": 66, "CCD_L_slr": 11, "CCD_L_WR_slr": 44, + "CCD_L_WR2_slr": 22, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -70,4 +71,4 @@ "clkMhz": 2200 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-4800A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-4800A.json index 46998d40..6215400d 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-4800A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-4800A.json @@ -35,6 +35,7 @@ "WR": 72, "CCD_L_slr": 12, "CCD_L_WR_slr": 48, + "CCD_L_WR2_slr": 24, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -70,4 +71,4 @@ "clkMhz": 2400 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-5200A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-5200A.json index 18e6c093..48d99a38 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-5200A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-5200A.json @@ -35,6 +35,7 @@ "WR": 78, "CCD_L_slr": 13, "CCD_L_WR_slr": 52, + "CCD_L_WR2_slr": 26, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -70,4 +71,4 @@ "clkMhz": 2600 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-5600A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-5600A.json index 4891bb1b..0a46d8ed 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-5600A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-5600A.json @@ -35,6 +35,7 @@ "WR": 84, "CCD_L_slr": 14, "CCD_L_WR_slr": 56, + "CCD_L_WR2_slr": 28, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -70,4 +71,4 @@ "clkMhz": 2800 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-6000A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-6000A.json index 3e26408e..ba5c81eb 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-6000A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-6000A.json @@ -35,6 +35,7 @@ "WR": 90, "CCD_L_slr": 15, "CCD_L_WR_slr": 60, + "CCD_L_WR2_slr": 30, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -70,4 +71,4 @@ "clkMhz": 3000 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-6400A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-6400A.json index ca9eac9b..ea3ec632 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-6400A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-6400A.json @@ -35,6 +35,7 @@ "WR": 96, "CCD_L_slr": 16, "CCD_L_WR_slr": 64, + "CCD_L_WR2_slr": 32, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -70,4 +71,4 @@ "clkMhz": 3200 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x8x2Gbx4_DDR5-3200A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x8x2Gbx4_DDR5-3200A.json index 315fb976..fbbe90fe 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x8x2Gbx4_DDR5-3200A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x8x2Gbx4_DDR5-3200A.json @@ -35,6 +35,7 @@ "WR": 48, "CCD_L_slr": 8, "CCD_L_WR_slr": 32, + "CCD_L_WR2_slr": 16, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 8, diff --git a/DRAMSys/library/src/common/TlmRecorder.cpp b/DRAMSys/library/src/common/TlmRecorder.cpp index 17b20a34..ca347381 100644 --- a/DRAMSys/library/src/common/TlmRecorder.cpp +++ b/DRAMSys/library/src/common/TlmRecorder.cpp @@ -162,7 +162,7 @@ void TlmRecorder::introduceTransactionSystem(tlm_generic_payload &trans) currentTransactionsInSystem[&trans].cmd = trans.get_command() == tlm::TLM_READ_COMMAND ? "R" : "W"; currentTransactionsInSystem[&trans].address = trans.get_address(); - currentTransactionsInSystem[&trans].burstlength = trans.get_streaming_width(); + currentTransactionsInSystem[&trans].burstLength = DramExtension::getBurstLength(trans); currentTransactionsInSystem[&trans].dramExtension = DramExtension::getExtension(trans); currentTransactionsInSystem[&trans].timeOfGeneration = GenerationExtension::getTimeOfGeneration(trans); @@ -406,7 +406,7 @@ void TlmRecorder::insertTransactionInDB(Transaction &recordingData) sqlite3_bind_int(insertTransactionStatement, 1, static_cast(recordingData.id)); sqlite3_bind_int(insertTransactionStatement, 2, static_cast(recordingData.id)); sqlite3_bind_int64(insertTransactionStatement, 3, static_cast(recordingData.address)); - sqlite3_bind_int(insertTransactionStatement, 4, static_cast(recordingData.burstlength)); + sqlite3_bind_int(insertTransactionStatement, 4, static_cast(recordingData.burstLength)); sqlite3_bind_int(insertTransactionStatement, 5, static_cast(recordingData.dramExtension.getThread().ID())); sqlite3_bind_int(insertTransactionStatement, 6, diff --git a/DRAMSys/library/src/common/TlmRecorder.h b/DRAMSys/library/src/common/TlmRecorder.h index d3974f1b..fd422987 100644 --- a/DRAMSys/library/src/common/TlmRecorder.h +++ b/DRAMSys/library/src/common/TlmRecorder.h @@ -92,7 +92,7 @@ private: uint64_t id; uint64_t address; - unsigned int burstlength; + unsigned int burstLength; std::string cmd; DramExtension dramExtension; sc_time timeOfGeneration; diff --git a/DRAMSys/library/src/common/dramExtensions.cpp b/DRAMSys/library/src/common/dramExtensions.cpp index 09a49be9..44910e22 100644 --- a/DRAMSys/library/src/common/dramExtensions.cpp +++ b/DRAMSys/library/src/common/dramExtensions.cpp @@ -44,21 +44,21 @@ using namespace tlm; DramExtension::DramExtension() : thread(0), channel(0), rank(0), bankgroup(0), bank(0), - row(0), column(0), burstlength(0), + row(0), column(0), burstLength(0), threadPayloadID(0), channelPayloadID(0) {} DramExtension::DramExtension(Thread thread, Channel channel, Rank rank, BankGroup bankgroup, Bank bank, Row row, - Column column, unsigned int burstlength, + Column column, unsigned int burstLength, uint64_t threadPayloadID, uint64_t channelPayloadID) : thread(thread), channel(channel), rank(rank), bankgroup(bankgroup), bank(bank), - row(row), column(column), burstlength(burstlength), + row(row), column(column), burstLength(burstLength), threadPayloadID(threadPayloadID), channelPayloadID(channelPayloadID) {} void DramExtension::setExtension(tlm::tlm_generic_payload *payload, Thread thread, Channel channel, Rank rank, BankGroup bankgroup, Bank bank, Row row, - Column column, unsigned int burstlength, + Column column, unsigned int burstLength, uint64_t threadPayloadID, uint64_t channelPayloadID) { DramExtension *extension = nullptr; @@ -73,14 +73,14 @@ void DramExtension::setExtension(tlm::tlm_generic_payload *payload, extension->bank = bank; extension->row = row; extension->column = column; - extension->burstlength = burstlength; + extension->burstLength = burstLength; extension->threadPayloadID = threadPayloadID; extension->channelPayloadID = channelPayloadID; } else { extension = new DramExtension(thread, channel, rank, bankgroup, - bank, row, column, burstlength, + bank, row, column, burstLength, threadPayloadID, channelPayloadID); payload->set_auto_extension(extension); } @@ -89,11 +89,11 @@ void DramExtension::setExtension(tlm::tlm_generic_payload *payload, void DramExtension::setExtension(tlm::tlm_generic_payload &payload, Thread thread, Channel channel, Rank rank, BankGroup bankgroup, Bank bank, Row row, - Column column, unsigned int burstlength, + Column column, unsigned int burstLength, uint64_t threadPayloadID, uint64_t channelPayloadID) { setExtension(&payload, thread, channel, rank, bankgroup, - bank, row, column, burstlength, + bank, row, column, burstLength, threadPayloadID, channelPayloadID); } @@ -194,6 +194,16 @@ Column DramExtension::getColumn(const tlm_generic_payload &payload) return DramExtension::getColumn(&payload); } +unsigned DramExtension::getBurstLength(const tlm_generic_payload *payload) +{ + return DramExtension::getExtension(payload).getBurstLength(); +} + +unsigned DramExtension::getBurstLength(const tlm_generic_payload &payload) +{ + return DramExtension::getBurstLength(&payload); +} + uint64_t DramExtension::getThreadPayloadID(const tlm_generic_payload *payload) { return DramExtension::getExtension(payload).getThreadPayloadID(); @@ -217,7 +227,7 @@ uint64_t DramExtension::getChannelPayloadID(const tlm_generic_payload &payload) tlm_extension_base *DramExtension::clone() const { return new DramExtension(thread, channel, rank, bankgroup, bank, row, column, - burstlength, threadPayloadID, channelPayloadID); + burstLength, threadPayloadID, channelPayloadID); } void DramExtension::copy_from(const tlm_extension_base &ext) @@ -230,7 +240,7 @@ void DramExtension::copy_from(const tlm_extension_base &ext) bank = cpyFrom.bank; row = cpyFrom.row; column = cpyFrom.column; - burstlength = cpyFrom.burstlength; + burstLength = cpyFrom.burstLength; } Thread DramExtension::getThread() const @@ -268,9 +278,9 @@ Column DramExtension::getColumn() const return column; } -unsigned int DramExtension::getBurstlength() const +unsigned int DramExtension::getBurstLength() const { - return burstlength; + return burstLength; } uint64_t DramExtension::getThreadPayloadID() const diff --git a/DRAMSys/library/src/common/dramExtensions.h b/DRAMSys/library/src/common/dramExtensions.h index 989bb079..462a61a8 100644 --- a/DRAMSys/library/src/common/dramExtensions.h +++ b/DRAMSys/library/src/common/dramExtensions.h @@ -165,7 +165,7 @@ public: DramExtension(); DramExtension(Thread thread, Channel channel, Rank rank, BankGroup bankgroup, Bank bank, Row row, - Column column, unsigned int burstlength, + Column column, unsigned int burstLength, uint64_t threadPayloadID, uint64_t channelPayloadID); virtual tlm::tlm_extension_base *clone() const; @@ -174,12 +174,12 @@ public: static void setExtension(tlm::tlm_generic_payload *payload, Thread thread, Channel channel, Rank rank, BankGroup bankgroup, Bank bank, Row row, - Column column, unsigned int burstlength, + Column column, unsigned int burstLength, uint64_t threadPayloadID, uint64_t channelPayloadID); static void setExtension(tlm::tlm_generic_payload &payload, Thread thread, Channel channel, Rank rank, BankGroup bankgroup, Bank bank, Row row, - Column column, unsigned int burstlength, + Column column, unsigned int burstLength, uint64_t threadPayloadID, uint64_t channelPayloadID); static DramExtension &getExtension(const tlm::tlm_generic_payload *payload); @@ -205,6 +205,8 @@ public: static Row getRow(const tlm::tlm_generic_payload &payload); static Column getColumn(const tlm::tlm_generic_payload *payload); static Column getColumn(const tlm::tlm_generic_payload &payload); + static unsigned getBurstLength(const tlm::tlm_generic_payload *payload); + static unsigned getBurstLength(const tlm::tlm_generic_payload &payload); static uint64_t getThreadPayloadID(const tlm::tlm_generic_payload *payload); static uint64_t getThreadPayloadID(const tlm::tlm_generic_payload &payload); static uint64_t getChannelPayloadID(const tlm::tlm_generic_payload *payload); @@ -218,7 +220,7 @@ public: Row getRow() const; Column getColumn() const; - unsigned int getBurstlength() const; + unsigned int getBurstLength() const; uint64_t getThreadPayloadID() const; uint64_t getChannelPayloadID() const; void incrementRow(); @@ -231,7 +233,7 @@ private: Bank bank; Row row; Column column; - unsigned int burstlength; + unsigned int burstLength; uint64_t threadPayloadID; uint64_t channelPayloadID; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.h b/DRAMSys/library/src/configuration/memspec/MemSpec.h index 4020a8ed..82c1987d 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.h @@ -79,8 +79,8 @@ public: virtual bool hasRasAndCasBus() const; - virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const = 0; - virtual TimeInterval getIntervalOnDataStrobe(Command) const = 0; + virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const = 0; + virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const = 0; sc_time getCommandLength(Command) const; virtual uint64_t getSimMemSizeInBytes() const = 0; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp index 2da79c88..5c566b46 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp @@ -120,7 +120,7 @@ sc_time MemSpecDDR3::getExecutionTime(Command command, const tlm_generic_payload } } -TimeInterval MemSpecDDR3::getIntervalOnDataStrobe(Command command) const +TimeInterval MemSpecDDR3::getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) return TimeInterval(tRL, tRL + burstDuration); diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h index 6c9174de..370273b0 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h @@ -89,8 +89,8 @@ public: virtual sc_time getRefreshIntervalAB() const override; - virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const override; - virtual TimeInterval getIntervalOnDataStrobe(Command) const override; + virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; virtual uint64_t getSimMemSizeInBytes() const override; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp index cd6daac4..2b6e3bfb 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp @@ -139,7 +139,7 @@ sc_time MemSpecDDR4::getExecutionTime(Command command, const tlm_generic_payload } } -TimeInterval MemSpecDDR4::getIntervalOnDataStrobe(Command command) const +TimeInterval MemSpecDDR4::getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) return TimeInterval(tRL, tRL + burstDuration); diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h index c63fb36f..e3a5ed9b 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h @@ -97,8 +97,8 @@ public: virtual sc_time getRefreshIntervalAB() const override; - virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const override; - virtual TimeInterval getIntervalOnDataStrobe(Command) const override; + virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; virtual uint64_t getSimMemSizeInBytes() const override; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp index 5d0353c8..662464d2 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp @@ -59,56 +59,59 @@ MemSpecDDR5::MemSpecDDR5(json &memspec) numberOfLogicalRanks(logicalRanksPerPhysicalRank * numberOfPhysicalRanks), cmdMode(parseUint(memspec["memarchitecturespec"]["cmdMode"], "cmdMode")), refMode(parseUint(memspec["memarchitecturespec"]["refMode"], "refMode")), - tRCD (tCK * parseUint(memspec["memtimingspec"]["RCD"], "RCD")), - tPPD (tCK * parseUint(memspec["memtimingspec"]["PPD"], "PPD")), - tRP (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")), - tRAS (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")), - tRC (tRAS + tRP), - tRL (tCK * parseUint(memspec["memtimingspec"]["RL"], "RL")), - tRTP (tCK * parseUint(memspec["memtimingspec"]["RTP"], "RTP")), - tRPRE (tCK * parseUint(memspec["memtimingspec"]["RPRE"], "RPRE")), - tRPST (tCK * parseUint(memspec["memtimingspec"]["RPST"], "RPST")), - tRDDQS (tCK * parseUint(memspec["memtimingspec"]["RDDQS"], "RDDQS")), - tWL (tCK * parseUint(memspec["memtimingspec"]["WL"], "WL")), - tWPRE (tCK * parseUint(memspec["memtimingspec"]["WPRE"], "WPRE")), - tWPST (tCK * parseUint(memspec["memtimingspec"]["WPST"], "WPST")), - tWR (tCK * parseUint(memspec["memtimingspec"]["WR"], "WR")), - tCCD_L_slr (tCK * parseUint(memspec["memtimingspec"]["CCD_L_slr"], "CCD_L_slr")), - tCCD_L_WR_slr (tCK * parseUint(memspec["memtimingspec"]["CCD_L_WR_slr"], "CCD_L_WR_slr")), - tCCD_S_slr (tCK * parseUint(memspec["memtimingspec"]["CCD_S_slr"], "CCD_S_slr")), - tCCD_S_WR_slr (tCK * parseUint(memspec["memtimingspec"]["CCD_S_WR_slr"], "CCD_S_WR_slr")), - tCCD_dlr (tCK * parseUint(memspec["memtimingspec"]["CCD_dlr"], "CCD_dlr")), - tCCD_WR_dlr (tCK * parseUint(memspec["memtimingspec"]["CCD_WR_dlr"], "CCD_WR_dlr")), - tCCD_WR_dpr (tCK * parseUint(memspec["memtimingspec"]["CCD_WR_dpr"], "CCD_WR_dpr")), - tRRD_L_slr (tCK * parseUint(memspec["memtimingspec"]["RRD_L_slr"], "RRD_L_slr")), - tRRD_S_slr (tCK * parseUint(memspec["memtimingspec"]["RRD_S_slr"], "RRD_S_slr")), - tRRD_dlr (tCK * parseUint(memspec["memtimingspec"]["RRD_dlr"], "RRD_dlr")), - tFAW_slr (tCK * parseUint(memspec["memtimingspec"]["FAW_slr"], "FAW_slr")), - tFAW_dlr (tCK * parseUint(memspec["memtimingspec"]["FAW_dlr"], "FAW_dlr")), - tWTR_L (tCK * parseUint(memspec["memtimingspec"]["WTR_L"], "WTR_L")), - tWTR_S (tCK * parseUint(memspec["memtimingspec"]["WTR_S"], "WTR_S")), - tRFC_slr ((refMode == 1) ? tCK * parseUint(memspec["memtimingspec"]["RFC1_slr"], "RFC1_slr") - : tCK * parseUint(memspec["memtimingspec"]["RFC2_slr"], "RFC2_slr")), - tRFC_dlr ((refMode == 1) ? tCK * parseUint(memspec["memtimingspec"]["RFC1_dlr"], "RFC1_dlr") - : tCK * parseUint(memspec["memtimingspec"]["RFC2_dlr"], "RFC2_dlr")), - tRFC_dpr ((refMode == 1) ? tCK * parseUint(memspec["memtimingspec"]["RFC1_dpr"], "RFC1_dpr") - : tCK * parseUint(memspec["memtimingspec"]["RFC2_dpr"], "RFC2_dpr")), - tRFCsb_slr (tCK * parseUint(memspec["memtimingspec"]["RFCsb_slr"], "RFCsb_slr")), - tRFCsb_dlr (tCK * parseUint(memspec["memtimingspec"]["RFCsb_dlr"], "RFCsb_dlr")), - tREFI ((refMode == 1) ? tCK * parseUint(memspec["memtimingspec"]["REFI1"], "REFI1") - : tCK * parseUint(memspec["memtimingspec"]["REFI2"], "REFI2")), - tREFIsb (tCK * parseUint(memspec["memtimingspec"]["REFISB"], "REFISB")), - tREFSBRD_slr (tCK * parseUint(memspec["memtimingspec"]["REFSBRD_slr"], "REFSBRD_slr")), - tREFSBRD_dlr (tCK * parseUint(memspec["memtimingspec"]["REFSBRD_dlr"], "REFSBRD_dlr")), - tRTRS (tCK * parseUint(memspec["memtimingspec"]["RTRS"], "RTRS")), - tCPDED (tCK * parseUint(memspec["memtimingspec"]["CPDED"], "CPDED")), - tPD (tCK * parseUint(memspec["memtimingspec"]["PD"], "PD")), - tXP (tCK * parseUint(memspec["memtimingspec"]["XP"], "XP")), - tACTPDEN (tCK * parseUint(memspec["memtimingspec"]["ACTPDEN"], "ACTPDEN")), - tPRPDEN (tCK * parseUint(memspec["memtimingspec"]["PRPDEN"], "PRPDEN")), - tREFPDEN (tCK * parseUint(memspec["memtimingspec"]["REFPDEN"], "REFPDEN")), - cmdOffset_S (cmdMode == 2 ? 1 * tCK : 0 * tCK), - cmdOffset_L (cmdMode == 2 ? 3 * tCK : 1 * tCK) + tRCD (tCK * parseUint(memspec["memtimingspec"]["RCD"], "RCD")), + tPPD (tCK * parseUint(memspec["memtimingspec"]["PPD"], "PPD")), + tRP (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")), + tRAS (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")), + tRC (tRAS + tRP), + tRL (tCK * parseUint(memspec["memtimingspec"]["RL"], "RL")), + tRTP (tCK * parseUint(memspec["memtimingspec"]["RTP"], "RTP")), + tRPRE (tCK * parseUint(memspec["memtimingspec"]["RPRE"], "RPRE")), + tRPST (tCK * parseUint(memspec["memtimingspec"]["RPST"], "RPST")), + tRDDQS (tCK * parseUint(memspec["memtimingspec"]["RDDQS"], "RDDQS")), + tWL (tCK * parseUint(memspec["memtimingspec"]["WL"], "WL")), + tWPRE (tCK * parseUint(memspec["memtimingspec"]["WPRE"], "WPRE")), + tWPST (tCK * parseUint(memspec["memtimingspec"]["WPST"], "WPST")), + tWR (tCK * parseUint(memspec["memtimingspec"]["WR"], "WR")), + tCCD_L_slr (tCK * parseUint(memspec["memtimingspec"]["CCD_L_slr"], "CCD_L_slr")), + tCCD_L_WR_slr (tCK * parseUint(memspec["memtimingspec"]["CCD_L_WR_slr"], "CCD_L_WR_slr")), + tCCD_L_WR2_slr (tCK * parseUint(memspec["memtimingspec"]["CCD_L_WR2_slr"], "CCD_L_WR2_slr")), + tCCD_S_slr (tCK * parseUint(memspec["memtimingspec"]["CCD_S_slr"], "CCD_S_slr")), + tCCD_S_WR_slr (tCK * parseUint(memspec["memtimingspec"]["CCD_S_WR_slr"], "CCD_S_WR_slr")), + tCCD_dlr (tCK * parseUint(memspec["memtimingspec"]["CCD_dlr"], "CCD_dlr")), + tCCD_WR_dlr (tCK * parseUint(memspec["memtimingspec"]["CCD_WR_dlr"], "CCD_WR_dlr")), + tCCD_WR_dpr (tCK * parseUint(memspec["memtimingspec"]["CCD_WR_dpr"], "CCD_WR_dpr")), + tRRD_L_slr (tCK * parseUint(memspec["memtimingspec"]["RRD_L_slr"], "RRD_L_slr")), + tRRD_S_slr (tCK * parseUint(memspec["memtimingspec"]["RRD_S_slr"], "RRD_S_slr")), + tRRD_dlr (tCK * parseUint(memspec["memtimingspec"]["RRD_dlr"], "RRD_dlr")), + tFAW_slr (tCK * parseUint(memspec["memtimingspec"]["FAW_slr"], "FAW_slr")), + tFAW_dlr (tCK * parseUint(memspec["memtimingspec"]["FAW_dlr"], "FAW_dlr")), + tWTR_L (tCK * parseUint(memspec["memtimingspec"]["WTR_L"], "WTR_L")), + tWTR_S (tCK * parseUint(memspec["memtimingspec"]["WTR_S"], "WTR_S")), + tRFC_slr ((refMode == 1) ? tCK * parseUint(memspec["memtimingspec"]["RFC1_slr"], "RFC1_slr") + : tCK * parseUint(memspec["memtimingspec"]["RFC2_slr"], "RFC2_slr")), + tRFC_dlr ((refMode == 1) ? tCK * parseUint(memspec["memtimingspec"]["RFC1_dlr"], "RFC1_dlr") + : tCK * parseUint(memspec["memtimingspec"]["RFC2_dlr"], "RFC2_dlr")), + tRFC_dpr ((refMode == 1) ? tCK * parseUint(memspec["memtimingspec"]["RFC1_dpr"], "RFC1_dpr") + : tCK * parseUint(memspec["memtimingspec"]["RFC2_dpr"], "RFC2_dpr")), + tRFCsb_slr (tCK * parseUint(memspec["memtimingspec"]["RFCsb_slr"], "RFCsb_slr")), + tRFCsb_dlr (tCK * parseUint(memspec["memtimingspec"]["RFCsb_dlr"], "RFCsb_dlr")), + tREFI ((refMode == 1) ? tCK * parseUint(memspec["memtimingspec"]["REFI1"], "REFI1") + : tCK * parseUint(memspec["memtimingspec"]["REFI2"], "REFI2")), + tREFIsb (tCK * parseUint(memspec["memtimingspec"]["REFISB"], "REFISB")), + tREFSBRD_slr (tCK * parseUint(memspec["memtimingspec"]["REFSBRD_slr"], "REFSBRD_slr")), + tREFSBRD_dlr (tCK * parseUint(memspec["memtimingspec"]["REFSBRD_dlr"], "REFSBRD_dlr")), + tRTRS (tCK * parseUint(memspec["memtimingspec"]["RTRS"], "RTRS")), + tCPDED (tCK * parseUint(memspec["memtimingspec"]["CPDED"], "CPDED")), + tPD (tCK * parseUint(memspec["memtimingspec"]["PD"], "PD")), + tXP (tCK * parseUint(memspec["memtimingspec"]["XP"], "XP")), + tACTPDEN (tCK * parseUint(memspec["memtimingspec"]["ACTPDEN"], "ACTPDEN")), + tPRPDEN (tCK * parseUint(memspec["memtimingspec"]["PRPDEN"], "PRPDEN")), + tREFPDEN (tCK * parseUint(memspec["memtimingspec"]["REFPDEN"], "REFPDEN")), + shortCmdOffset (cmdMode == 2 ? 1 * tCK : 0 * tCK), + longCmdOffset (cmdMode == 2 ? 3 * tCK : 1 * tCK), + tBURST16(tCK * 8), + tBURST32(tCK * 16) { if (cmdMode == 1) { @@ -156,24 +159,39 @@ sc_time MemSpecDDR5::getRefreshIntervalSB() const } // Returns the execution time for commands that have a fixed execution time -sc_time MemSpecDDR5::getExecutionTime(Command command, const tlm_generic_payload &) const +sc_time MemSpecDDR5::getExecutionTime(Command command, const tlm_generic_payload &payload) const { if (command == Command::PRE || command == Command::PREA || command == Command::PRESB) - return tRP + cmdOffset_S; + return tRP + shortCmdOffset; else if (command == Command::ACT) - return tRCD + cmdOffset_L; + return tRCD + longCmdOffset; else if (command == Command::RD) - return tRL + burstDuration + cmdOffset_L; + { + if (DramExtension::getBurstLength(payload) == 32) + return tRL + tBURST32 + longCmdOffset; + else + return tRL + tBURST16 + longCmdOffset; + } else if (command == Command::RDA) - return tRTP + tRP + cmdOffset_L; + return tRTP + tRP + longCmdOffset; else if (command == Command::WR) - return tWL + burstDuration + cmdOffset_L; + { + if (DramExtension::getBurstLength(payload) == 32) + return tWL + tBURST32 + longCmdOffset; + else + return tWL + tBURST16 + longCmdOffset; + } else if (command == Command::WRA) - return tWL + burstDuration + tWR + tRP + cmdOffset_L; + { + if (DramExtension::getBurstLength(payload) == 32) + return tWL + tBURST32 + tWR + tRP + longCmdOffset; + else + return tWL + tBURST16 + tWR + tRP + longCmdOffset; + } else if (command == Command::REFA) - return tRFC_slr + cmdOffset_S; + return tRFC_slr + shortCmdOffset; else if (command == Command::REFSB) - return tRFCsb_slr + cmdOffset_S; + return tRFCsb_slr + shortCmdOffset; else { SC_REPORT_FATAL("getExecutionTime", @@ -182,12 +200,22 @@ sc_time MemSpecDDR5::getExecutionTime(Command command, const tlm_generic_payload } } -TimeInterval MemSpecDDR5::getIntervalOnDataStrobe(Command command) const +TimeInterval MemSpecDDR5::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &payload) const { if (command == Command::RD || command == Command::RDA) - return TimeInterval(tRL + cmdOffset_L, tRL + burstDuration + cmdOffset_L); + { + if (DramExtension::getBurstLength(payload) == 32) + return TimeInterval(tRL + longCmdOffset, tRL + tBURST32 + longCmdOffset); + else + return TimeInterval(tRL + longCmdOffset, tRL + tBURST16 + longCmdOffset); + } else if (command == Command::WR || command == Command::WRA) - return TimeInterval(tWL + cmdOffset_L, tWL + burstDuration + cmdOffset_L); + { + if (DramExtension::getBurstLength(payload) == 32) + return TimeInterval(tWL + longCmdOffset, tWL + tBURST32 + longCmdOffset); + else + return TimeInterval(tWL + longCmdOffset, tWL + tBURST16 + longCmdOffset); + } else { SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.h index 13883326..40de44f1 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.h @@ -69,6 +69,7 @@ public: const sc_time tWR; const sc_time tCCD_L_slr; const sc_time tCCD_L_WR_slr; + const sc_time tCCD_L_WR2_slr; const sc_time tCCD_S_slr; const sc_time tCCD_S_WR_slr; const sc_time tCCD_dlr; @@ -99,8 +100,11 @@ public: const sc_time tPRPDEN; const sc_time tREFPDEN; - const sc_time cmdOffset_S; - const sc_time cmdOffset_L; + const sc_time shortCmdOffset; + const sc_time longCmdOffset; + + const sc_time tBURST16; + const sc_time tBURST32; // Currents and Voltages: // TODO: to be completed @@ -108,8 +112,8 @@ public: virtual sc_time getRefreshIntervalAB() const override; virtual sc_time getRefreshIntervalSB() const override; - virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const override; - virtual TimeInterval getIntervalOnDataStrobe(Command) const override; + virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; virtual uint64_t getSimMemSizeInBytes() const override; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp index 2c27dbc3..4ae7bb17 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp @@ -128,7 +128,7 @@ sc_time MemSpecGDDR5::getExecutionTime(Command command, const tlm_generic_payloa } } -TimeInterval MemSpecGDDR5::getIntervalOnDataStrobe(Command command) const +TimeInterval MemSpecGDDR5::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) return TimeInterval(tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h index 3abeb869..cf584c98 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h @@ -88,8 +88,8 @@ public: virtual sc_time getRefreshIntervalAB() const override; virtual sc_time getRefreshIntervalPB() const override; - virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const override; - virtual TimeInterval getIntervalOnDataStrobe(Command) const override; + virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; virtual uint64_t getSimMemSizeInBytes() const override; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp index ea1dc46e..1c97fada 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp @@ -128,7 +128,7 @@ sc_time MemSpecGDDR5X::getExecutionTime(Command command, const tlm_generic_paylo } } -TimeInterval MemSpecGDDR5X::getIntervalOnDataStrobe(Command command) const +TimeInterval MemSpecGDDR5X::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) return TimeInterval(tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h index 10fcd5b5..f507232d 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h @@ -88,8 +88,8 @@ public: virtual sc_time getRefreshIntervalAB() const override; virtual sc_time getRefreshIntervalPB() const override; - virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const override; - virtual TimeInterval getIntervalOnDataStrobe(Command) const override; + virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; virtual uint64_t getSimMemSizeInBytes() const override; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp index d296f887..c0dfd854 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp @@ -130,7 +130,7 @@ sc_time MemSpecGDDR6::getExecutionTime(Command command, const tlm_generic_payloa } } -TimeInterval MemSpecGDDR6::getIntervalOnDataStrobe(Command command) const +TimeInterval MemSpecGDDR6::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) return TimeInterval(tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h index c0f9f7d1..b6d86f8e 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h @@ -90,8 +90,8 @@ public: virtual sc_time getRefreshIntervalAB() const override; virtual sc_time getRefreshIntervalPB() const override; - virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const override; - virtual TimeInterval getIntervalOnDataStrobe(Command) const override; + virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; virtual uint64_t getSimMemSizeInBytes() const override; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp index c299f9d9..25f77ef9 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp @@ -130,7 +130,7 @@ sc_time MemSpecHBM2::getExecutionTime(Command command, const tlm_generic_payload } } -TimeInterval MemSpecHBM2::getIntervalOnDataStrobe(Command command) const +TimeInterval MemSpecHBM2::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) return TimeInterval(tRL + tDQSCK, tRL + tDQSCK + burstDuration); diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h index a56f18fb..f5c0fbb0 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h @@ -85,8 +85,8 @@ public: virtual bool hasRasAndCasBus() const override; - virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const override; - virtual TimeInterval getIntervalOnDataStrobe(Command) const override; + virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; virtual uint64_t getSimMemSizeInBytes() const override; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp index a046a7d7..9e181a0d 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp @@ -132,7 +132,7 @@ sc_time MemSpecLPDDR4::getExecutionTime(Command command, const tlm_generic_paylo } } -TimeInterval MemSpecLPDDR4::getIntervalOnDataStrobe(Command command) const +TimeInterval MemSpecLPDDR4::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) return TimeInterval(tRL + tDQSCK + 3 * tCK, diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h index 4c7d0d52..8005422e 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h @@ -83,8 +83,8 @@ public: virtual sc_time getRefreshIntervalAB() const override; virtual sc_time getRefreshIntervalPB() const override; - virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const override; - virtual TimeInterval getIntervalOnDataStrobe(Command) const override; + virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; virtual uint64_t getSimMemSizeInBytes() const override; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp index 91f9f1c8..dcbd1ae7 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp @@ -126,7 +126,7 @@ sc_time MemSpecWideIO::getExecutionTime(Command command, const tlm_generic_paylo } } -TimeInterval MemSpecWideIO::getIntervalOnDataStrobe(Command command) const +TimeInterval MemSpecWideIO::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) return TimeInterval(tRL + tAC, tRL + tAC + burstDuration); diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h index eb1ad7d7..79b2818c 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h @@ -95,8 +95,8 @@ public: virtual sc_time getRefreshIntervalAB() const override; - virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const override; - virtual TimeInterval getIntervalOnDataStrobe(Command) const override; + virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; virtual uint64_t getSimMemSizeInBytes() const override; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp index 2b93a0cc..eb0efe10 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp @@ -117,7 +117,7 @@ sc_time MemSpecWideIO2::getExecutionTime(Command command, const tlm_generic_payl } } -TimeInterval MemSpecWideIO2::getIntervalOnDataStrobe(Command command) const +TimeInterval MemSpecWideIO2::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) return TimeInterval(tRL + tDQSCK, tRL + tDQSCK + burstDuration); diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h index 35503a61..31b01a7d 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h @@ -77,8 +77,8 @@ public: virtual sc_time getRefreshIntervalAB() const override; virtual sc_time getRefreshIntervalPB() const override; - virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const override; - virtual TimeInterval getIntervalOnDataStrobe(Command) const override; + virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; virtual uint64_t getSimMemSizeInBytes() const override; }; diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index 0fab68d9..4fdecbb1 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -148,7 +148,8 @@ sc_time BankMachineOpen::start() else // row miss nextCommand = Command::PRE; } - timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, bankgroup, bank); + timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, + bankgroup, bank, DramExtension::getBurstLength(currentPayload)); } } return timeToSchedule; @@ -178,7 +179,8 @@ sc_time BankMachineClosed::start() else SC_REPORT_FATAL("BankMachine", "Wrong TLM command"); } - timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, bankgroup, bank); + timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, + bankgroup, bank, DramExtension::getBurstLength(currentPayload)); } } return timeToSchedule; @@ -225,7 +227,8 @@ sc_time BankMachineOpenAdaptive::start() else // row miss nextCommand = Command::PRE; } - timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, bankgroup, bank); + timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, + bankgroup, bank, DramExtension::getBurstLength(currentPayload)); } } return timeToSchedule; @@ -272,7 +275,8 @@ sc_time BankMachineClosedAdaptive::start() else // row miss, should never happen SC_REPORT_FATAL("BankMachine", "Should never be reached for this policy"); } - timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, bankgroup, bank); + timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, + bankgroup, bank, DramExtension::getBurstLength(currentPayload)); } } return timeToSchedule; diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index 21355bb1..45b04c39 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -287,6 +287,7 @@ void Controller::controllerMethod() Rank rank = DramExtension::getRank(payload); BankGroup bankgroup = DramExtension::getBankGroup(payload); Bank bank = DramExtension::getBank(payload); + unsigned burstLength = DramExtension::getBurstLength(payload); if (isRankCommand(command)) { @@ -304,7 +305,7 @@ void Controller::controllerMethod() refreshManagers[rank.ID()]->updateState(command); powerDownManagers[rank.ID()]->updateState(command); - checker->insert(command, rank, bankgroup, bank); + checker->insert(command, rank, bankgroup, bank, burstLength); if (isCasCommand(command)) { @@ -312,7 +313,7 @@ void Controller::controllerMethod() manageRequests(thinkDelayFw); respQueue->insertPayload(payload, sc_time_stamp() + thinkDelayFw + phyDelayFw - + memSpec->getIntervalOnDataStrobe(command).end + + memSpec->getIntervalOnDataStrobe(command, *payload).end + phyDelayBw + thinkDelayBw); sc_time triggerTime = respQueue->getTriggerTime(); @@ -437,9 +438,9 @@ void Controller::manageResponses() NDEBUG_UNUSED(uint64_t id) = DramExtension::getChannelPayloadID(transToRelease.payload); PRINTDEBUGMESSAGE(name(), "Payload " + std::to_string(id) + " left system."); + numberOfBeatsServed += DramExtension::getBurstLength(transToRelease.payload); transToRelease.payload->release(); transToRelease.payload = nullptr; - numberOfTransactionsServed++; totalNumberOfPayloads--; if (totalNumberOfPayloads == 0) diff --git a/DRAMSys/library/src/controller/ControllerIF.h b/DRAMSys/library/src/controller/ControllerIF.h index b23c3a2e..aebae208 100644 --- a/DRAMSys/library/src/controller/ControllerIF.h +++ b/DRAMSys/library/src/controller/ControllerIF.h @@ -55,8 +55,7 @@ public: // Destructor virtual ~ControllerIF() { - sc_time activeTime = numberOfTransactionsServed - * Configuration::getInstance().memSpec->burstLength + sc_time activeTime = numberOfBeatsServed / Configuration::getInstance().memSpec->dataRate * Configuration::getInstance().memSpec->tCK; @@ -143,7 +142,7 @@ protected: sc_time idleStart; } idleTimeCollector; - uint64_t numberOfTransactionsServed = 0; + uint64_t numberOfBeatsServed = 0; }; diff --git a/DRAMSys/library/src/controller/ControllerRecordable.cpp b/DRAMSys/library/src/controller/ControllerRecordable.cpp index bd548d50..34350af4 100644 --- a/DRAMSys/library/src/controller/ControllerRecordable.cpp +++ b/DRAMSys/library/src/controller/ControllerRecordable.cpp @@ -75,7 +75,7 @@ void ControllerRecordable::sendToDram(Command command, tlm_generic_payload *payl { if (isCasCommand(command)) { - TimeInterval dataStrobe = Configuration::getInstance().memSpec->getIntervalOnDataStrobe(command); + TimeInterval dataStrobe = Configuration::getInstance().memSpec->getIntervalOnDataStrobe(command, *payload); tlmRecorder->updateDataStrobe(sc_time_stamp() + delay + dataStrobe.start, sc_time_stamp() + delay + dataStrobe.end, *payload); } @@ -130,9 +130,9 @@ void ControllerRecordable::controllerMethod() Controller::controllerMethod(); - uint64_t windowNumberOfTransactionsServed = numberOfTransactionsServed - lastNumberOfTransactionsServed; - lastNumberOfTransactionsServed = numberOfTransactionsServed; - sc_time windowActiveTime = windowNumberOfTransactionsServed * activeTimeMultiplier; + uint64_t windowNumberOfBeatsServed = numberOfBeatsServed - lastNumberOfBeatsServed; + lastNumberOfBeatsServed = numberOfBeatsServed; + sc_time windowActiveTime = windowNumberOfBeatsServed * activeTimeMultiplier; double windowAverageBandwidth = windowActiveTime / windowSizeTime; tlmRecorder->recordBandwidth(sc_time_stamp().to_seconds(), windowAverageBandwidth); } diff --git a/DRAMSys/library/src/controller/ControllerRecordable.h b/DRAMSys/library/src/controller/ControllerRecordable.h index c2efa334..9459cd12 100644 --- a/DRAMSys/library/src/controller/ControllerRecordable.h +++ b/DRAMSys/library/src/controller/ControllerRecordable.h @@ -66,10 +66,9 @@ private: std::vector windowAverageBufferDepth; sc_time lastTimeCalled = SC_ZERO_TIME; - uint64_t lastNumberOfTransactionsServed = 0; - sc_time activeTimeMultiplier = Configuration::getInstance().memSpec->burstLength - / Configuration::getInstance().memSpec->dataRate - * Configuration::getInstance().memSpec->tCK; + uint64_t lastNumberOfBeatsServed = 0; + sc_time activeTimeMultiplier = Configuration::getInstance().memSpec->tCK + / Configuration::getInstance().memSpec->dataRate; }; #endif // CONTROLLERRECORDABLE_H diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp index 1e48ea04..0d52b904 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp @@ -60,7 +60,7 @@ CheckerDDR3::CheckerDDR3() tWRAPDEN = memSpec->tWL + tBURST + memSpec->tWR + memSpec->tCK; } -sc_time CheckerDDR3::timeToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank) const +sc_time CheckerDDR3::timeToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank, unsigned) const { sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); @@ -412,7 +412,7 @@ sc_time CheckerDDR3::timeToSatisfyConstraints(Command command, Rank rank, BankGr return earliestTimeToStart; } -void CheckerDDR3::insert(Command command, Rank rank, BankGroup, Bank bank) +void CheckerDDR3::insert(Command command, Rank rank, BankGroup, Bank bank, unsigned) { PRINTDEBUGMESSAGE("CheckerDDR3", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + commandToString(command)); diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.h b/DRAMSys/library/src/controller/checker/CheckerDDR3.h index efce001a..1eed6b48 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.h +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.h @@ -45,8 +45,9 @@ class CheckerDDR3 final : public CheckerIF { public: CheckerDDR3(); - virtual sc_time timeToSatisfyConstraints(Command, Rank, BankGroup, Bank) const override; - virtual void insert(Command, Rank, BankGroup, Bank) override; + virtual sc_time timeToSatisfyConstraints(Command, Rank = Rank(0), + BankGroup = BankGroup(0), Bank = Bank(0), unsigned burstLength = 0) const override; + virtual void insert(Command, Rank, BankGroup, Bank, unsigned) override; private: const MemSpecDDR3 *memSpec; diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp index 1dad1943..25544d7b 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp @@ -63,7 +63,7 @@ CheckerDDR4::CheckerDDR4() tWRAPDEN = memSpec->tWL + tBURST + memSpec->tCK + memSpec->tWR; } -sc_time CheckerDDR4::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank) const +sc_time CheckerDDR4::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank, unsigned) const { sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); @@ -443,7 +443,7 @@ sc_time CheckerDDR4::timeToSatisfyConstraints(Command command, Rank rank, BankGr return earliestTimeToStart; } -void CheckerDDR4::insert(Command command, Rank rank, BankGroup bankgroup, Bank bank) +void CheckerDDR4::insert(Command command, Rank rank, BankGroup bankgroup, Bank bank, unsigned) { PRINTDEBUGMESSAGE("CheckerDDR4", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + commandToString(command)); diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR4.h b/DRAMSys/library/src/controller/checker/CheckerDDR4.h index 694eecd4..d2befee3 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR4.h +++ b/DRAMSys/library/src/controller/checker/CheckerDDR4.h @@ -45,8 +45,9 @@ class CheckerDDR4 final : public CheckerIF { public: CheckerDDR4(); - virtual sc_time timeToSatisfyConstraints(Command, Rank, BankGroup, Bank) const override; - virtual void insert(Command, Rank, BankGroup, Bank) override; + virtual sc_time timeToSatisfyConstraints(Command, Rank = Rank(0), + BankGroup = BankGroup(0), Bank = Bank(0), unsigned burstLength = 0) const override; + virtual void insert(Command, Rank, BankGroup, Bank, unsigned) override; private: const MemSpecDDR4 *memSpec; diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR5.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR5.cpp index a5458a3d..775008aa 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR5.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR5.cpp @@ -41,7 +41,7 @@ CheckerDDR5::CheckerDDR5() if (memSpec == nullptr) SC_REPORT_FATAL("CheckerDDR5", "Wrong MemSpec chosen"); - lastScheduledByCommandAndDIMMRank = std::vector> + lastScheduledByCommandAndDimmRank = std::vector> (numberOfCommands(), std::vector(memSpec->numberOfDIMMRanks, sc_max_time())); lastScheduledByCommandAndPhysicalRank = std::vector> (numberOfCommands(), std::vector(memSpec->numberOfPhysicalRanks, sc_max_time())); @@ -56,40 +56,63 @@ CheckerDDR5::CheckerDDR5() lastScheduledByCommandAndBankInGroup = std::vector>(numberOfCommands(), std::vector(memSpec->numberOfRanks * memSpec->banksPerGroup, sc_max_time())); lastCommandOnBus = sc_max_time(); + dummyCommandOnBus.start = sc_max_time(); + dummyCommandOnBus.end = sc_max_time(); + last4ActivatesLogical = std::vector>(memSpec->numberOfLogicalRanks); last4ActivatesPhysical = std::vector>(memSpec->numberOfPhysicalRanks); - cmdOffset = memSpec->cmdMode * memSpec->tCK; + lastBurstLengthByCommandAndDimmRank = std::vector> + (4, std::vector(memSpec->numberOfDIMMRanks)); + lastBurstLengthByCommandAndPhysicalRank = std::vector> + (4, std::vector(memSpec->numberOfPhysicalRanks)); + lastBurstLengthByCommandAndLogicalRank = std::vector> + (4, std::vector(memSpec->numberOfLogicalRanks)); + lastBurstLengthByCommandAndBankGroup = std::vector> + (4, std::vector(memSpec->numberOfBankGroups)); + lastBurstLengthByCommandAndBank = std::vector> + (4, std::vector(memSpec->numberOfBanks)); + lastBurstLengthByCommand = std::vector(4); + lastBurstLengthByCommandAndBankInGroup = std::vector> + (4, std::vector(memSpec->numberOfRanks * memSpec->banksPerGroup)); - tRD_BURST = memSpec->burstLength / memSpec->dataRate * memSpec->tCK; - tWR_BURST = memSpec->burstLength / memSpec->dataRate * memSpec->tCK; + cmdLengthDiff = memSpec->cmdMode * memSpec->tCK; + + tBURST16 = 8 * memSpec->tCK; + tBURST32 = 16 * memSpec->tCK; tWTRA = memSpec->tWR - memSpec->tRTP; - tWRRDA = memSpec->tWL + tWR_BURST + tWTRA; - tWRPRE = memSpec->tWL + tWR_BURST + memSpec->tWR; + tWRRDA = memSpec->tWL + tBURST16 + tWTRA; // tWTRA = tWR - tRTP + tWRPRE = memSpec->tWL + tBURST16 + memSpec->tWR; tRDAACT = memSpec->tRTP + memSpec->tRP; tWRAACT = tWRPRE + memSpec->tRP; - tCCD_L_RTW_slr = memSpec->tRL - memSpec->tWL + tRD_BURST + 2 * memSpec->tCK - memSpec->tRDDQS + memSpec->tRPST + memSpec->tWPRE; - tCCD_S_RTW_slr = memSpec->tRL - memSpec->tWL + tRD_BURST + 2 * memSpec->tCK - memSpec->tRDDQS + memSpec->tRPST + memSpec->tWPRE; - tCCD_RTW_dlr = memSpec->tRL - memSpec->tWL + tRD_BURST + 2 * memSpec->tCK - memSpec->tRDDQS + memSpec->tRPST + memSpec->tWPRE; - tRDRD_dpr = tRD_BURST + memSpec->tRTRS; - tRDRD_ddr = tRD_BURST + memSpec->tRTRS; - tRDWR_dpr = memSpec->tRL - memSpec->tWL + tRD_BURST + memSpec->tRTRS - memSpec->tRDDQS + memSpec->tRPST + memSpec->tWPRE; - tRDWR_ddr = memSpec->tRL - memSpec->tWL + tRD_BURST + memSpec->tRTRS - memSpec->tRDDQS + memSpec->tRPST + memSpec->tWPRE; - tCCD_L_WTR_slr = memSpec->tWL + tWR_BURST + memSpec->tWTR_L; - tCCD_S_WTR_slr = memSpec->tWL + tWR_BURST + memSpec->tWTR_S; - tCCD_WTR_dlr = memSpec->tWL + tWR_BURST + memSpec->tWTR_S; - tWRWR_dpr = std::max(memSpec->tCCD_WR_dpr, tWR_BURST + memSpec->tRTRS); - tWRWR_ddr = tWR_BURST + memSpec->tRTRS; - tWRRD_dpr = memSpec->tWL - memSpec->tRL + tWR_BURST + memSpec->tRTRS + memSpec->tRDDQS + memSpec->tWPST + memSpec->tRPRE; - tWRRD_ddr = memSpec->tWL - memSpec->tRL + tWR_BURST + memSpec->tRTRS + memSpec->tRDDQS + memSpec->tWPST + memSpec->tRPRE; - tRDPDEN = memSpec->tRL + tRD_BURST + cmdOffset; - tWRPDEN = memSpec->tWL + tWR_BURST + memSpec->tWR + cmdOffset; - tWRAPDEN = memSpec->tWL + tWR_BURST + memSpec->tWR + cmdOffset; - - // TODO: tRTP BL 32 (similar to LPDDR4) + tCCD_L_RTW_slr = memSpec->tRL - memSpec->tWL + tBURST16 + 2 * memSpec->tCK + - memSpec->tRDDQS + memSpec->tRPST + memSpec->tWPRE; + tCCD_S_RTW_slr = memSpec->tRL - memSpec->tWL + tBURST16 + 2 * memSpec->tCK + - memSpec->tRDDQS + memSpec->tRPST + memSpec->tWPRE; + tCCD_RTW_dlr = memSpec->tRL - memSpec->tWL + tBURST16 + 2 * memSpec->tCK + - memSpec->tRDDQS + memSpec->tRPST + memSpec->tWPRE; + tRDRD_dpr = tBURST16 + memSpec->tRTRS; + tRDRD_ddr = tBURST16 + memSpec->tRTRS; + tRDWR_dpr = memSpec->tRL - memSpec->tWL + tBURST16 + memSpec->tRTRS + - memSpec->tRDDQS + memSpec->tRPST + memSpec->tWPRE; + tRDWR_ddr = memSpec->tRL - memSpec->tWL + tBURST16 + memSpec->tRTRS + - memSpec->tRDDQS + memSpec->tRPST + memSpec->tWPRE; + tCCD_L_WTR_slr = memSpec->tWL + tBURST16 + memSpec->tWTR_L; + tCCD_S_WTR_slr = memSpec->tWL + tBURST16 + memSpec->tWTR_S; + tCCD_WTR_dlr = memSpec->tWL + tBURST16 + memSpec->tWTR_S; + tWRWR_dpr = std::max(memSpec->tCCD_WR_dpr, tBURST16 + memSpec->tRTRS); + tWRWR_ddr = tBURST16 + memSpec->tRTRS; + tWRRD_dpr = memSpec->tWL - memSpec->tRL + tBURST16 + memSpec->tRTRS + + memSpec->tRDDQS + memSpec->tWPST + memSpec->tRPRE; + tWRRD_ddr = memSpec->tWL - memSpec->tRL + tBURST16 + memSpec->tRTRS + + memSpec->tRDDQS + memSpec->tWPST + memSpec->tRPRE; + tRDPDEN = memSpec->tRL + tBURST16 + cmdLengthDiff; + tWRPDEN = memSpec->tWL + tBURST16 + memSpec->tWR + cmdLengthDiff; + tWRAPDEN = memSpec->tWL + tBURST16 + memSpec->tWR + cmdLengthDiff; } -sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank) const +sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank, + unsigned burstLength) const { sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); @@ -116,15 +139,30 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::RD][physicalrank.ID()]; if (lastCommandStart != sc_max_time()) + { + if (lastBurstLengthByCommandAndPhysicalRank[Command::RD][physicalrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST32); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_dlr); + } lastCommandStart = lastScheduledByCommand[Command::RD]; - if (lastCommandStart != lastScheduledByCommandAndPhysicalRank[Command::RD][physicalrank.ID()]) + if (lastCommandStart != lastScheduledByCommandAndPhysicalRank[Command::RD][physicalrank.ID()]) // different physical rank { - if (lastCommandStart == lastScheduledByCommandAndDIMMRank[Command::RD][dimmrank.ID()]) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDRD_dpr); - else - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDRD_ddr); + if (lastCommandStart == lastScheduledByCommandAndDimmRank[Command::RD][dimmrank.ID()]) // same DIMM + { + if (lastBurstLengthByCommandAndDimmRank[Command::RD][dimmrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDRD_dpr + tBURST16); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDRD_dpr); + } + else // different DIMM + { + if (lastBurstLengthByCommand[Command::RD] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDRD_ddr + tBURST16); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDRD_ddr); + } } lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankgroup.ID()]; @@ -137,64 +175,134 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::RDA][physicalrank.ID()]; if (lastCommandStart != sc_max_time()) + { + if (lastBurstLengthByCommandAndPhysicalRank[Command::RDA][physicalrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST32); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_dlr); + } lastCommandStart = lastScheduledByCommand[Command::RDA]; - if (lastCommandStart != lastScheduledByCommandAndPhysicalRank[Command::RDA][physicalrank.ID()]) + if (lastCommandStart != lastScheduledByCommandAndPhysicalRank[Command::RDA][physicalrank.ID()]) // different physical rank { - if (lastCommandStart == lastScheduledByCommandAndDIMMRank[Command::RDA][dimmrank.ID()]) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDRD_dpr); - else - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDRD_ddr); + if (lastCommandStart == lastScheduledByCommandAndDimmRank[Command::RDA][dimmrank.ID()]) // same DIMM + { + if (lastBurstLengthByCommandAndDimmRank[Command::RDA][dimmrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDRD_dpr + tBURST16); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDRD_dpr); + } + else // different DIMM + { + if (lastBurstLengthByCommand[Command::RDA] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDRD_ddr + tBURST16); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDRD_ddr); + } } if (command == Command::RDA) { lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRDA); + { + if (lastBurstLengthByCommandAndBank[Command::WR][bank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRDA + tBURST16); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRDA); + } } lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_WTR_slr); + { + if (lastBurstLengthByCommandAndBankGroup[Command::WR][bankgroup.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_WTR_slr + tBURST16); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_WTR_slr); + } lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::WR][logicalrank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_S_WTR_slr); + { + if (lastBurstLengthByCommandAndLogicalRank[Command::WR][logicalrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_S_WTR_slr + tBURST16); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_S_WTR_slr); + } lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::WR][physicalrank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_WTR_dlr); + { + if (lastBurstLengthByCommandAndPhysicalRank[Command::WR][physicalrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_WTR_dlr + tBURST16); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_WTR_dlr); + } lastCommandStart = lastScheduledByCommand[Command::WR]; - if (lastCommandStart != lastScheduledByCommandAndPhysicalRank[Command::WR][physicalrank.ID()]) + if (lastCommandStart != lastScheduledByCommandAndPhysicalRank[Command::WR][physicalrank.ID()]) // different physical rank { - if (lastCommandStart == lastScheduledByCommandAndDIMMRank[Command::WR][dimmrank.ID()]) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_dpr); - else - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_ddr); + if (lastCommandStart == lastScheduledByCommandAndDimmRank[Command::WR][dimmrank.ID()]) // same DIMM + { + if (lastBurstLengthByCommandAndDimmRank[Command::WR][dimmrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_dpr + tBURST16); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_dpr); + } + else // different DIMM + { + if (lastBurstLengthByCommand[Command::WR] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_ddr + tBURST16); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_ddr); + } } lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_WTR_slr); + { + if (lastBurstLengthByCommandAndBankGroup[Command::WRA][bankgroup.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_WTR_slr + tBURST16); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_WTR_slr); + } lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::WRA][logicalrank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_S_WTR_slr); + { + if (lastBurstLengthByCommandAndLogicalRank[Command::WRA][logicalrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_S_WTR_slr + tBURST16); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_S_WTR_slr); + } lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::WRA][physicalrank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_WTR_dlr); + { + if (lastBurstLengthByCommandAndPhysicalRank[Command::WRA][physicalrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_WTR_dlr + tBURST16); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_WTR_dlr); + } lastCommandStart = lastScheduledByCommand[Command::WRA]; - if (lastCommandStart != lastScheduledByCommandAndPhysicalRank[Command::WRA][physicalrank.ID()]) + if (lastCommandStart != lastScheduledByCommandAndPhysicalRank[Command::WRA][physicalrank.ID()]) // different physical rank { - if (lastCommandStart == lastScheduledByCommandAndDIMMRank[Command::WRA][dimmrank.ID()]) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_dpr); - else - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_ddr); + if (lastCommandStart == lastScheduledByCommandAndDimmRank[Command::WRA][dimmrank.ID()]) // same DIMM + { + if (lastBurstLengthByCommandAndDimmRank[Command::WRA][dimmrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_dpr + tBURST16); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_dpr); + } + else // different DIMM + { + if (lastBurstLengthByCommand[Command::WRA] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_ddr + tBURST16); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_ddr); + } } } else if (command == Command::WR || command == Command::WRA) @@ -205,49 +313,114 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankgroup.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_RTW_slr); + { + if (lastBurstLengthByCommandAndBankGroup[Command::RD][bankgroup.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_RTW_slr + tBURST16); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_RTW_slr); + } lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::RD][logicalrank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_S_RTW_slr); + { + if (lastBurstLengthByCommandAndLogicalRank[Command::RD][logicalrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_S_RTW_slr + tBURST16); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_S_RTW_slr); + } lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::RD][physicalrank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_RTW_dlr); + { + if (lastBurstLengthByCommandAndPhysicalRank[Command::RD][physicalrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_RTW_dlr + tBURST16); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_RTW_dlr); + } lastCommandStart = lastScheduledByCommand[Command::RD]; - if (lastCommandStart != lastScheduledByCommandAndPhysicalRank[Command::RD][physicalrank.ID()]) + if (lastCommandStart != lastScheduledByCommandAndPhysicalRank[Command::RD][physicalrank.ID()]) // different physical rank { - if (lastCommandStart == lastScheduledByCommandAndDIMMRank[Command::RD][dimmrank.ID()]) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR_dpr); - else - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR_ddr); + if (lastCommandStart == lastScheduledByCommandAndDimmRank[Command::RD][dimmrank.ID()]) // same DIMM + { + if (lastBurstLengthByCommandAndDimmRank[Command::RD][dimmrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR_dpr + tBURST16); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR_dpr); + } + else // different DIMM + { + if (lastBurstLengthByCommand[Command::RD] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR_ddr + tBURST16); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR_ddr); + } } lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankgroup.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_RTW_slr); + { + if (lastBurstLengthByCommandAndBankGroup[Command::RDA][bankgroup.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_RTW_slr + tBURST16); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_RTW_slr); + } lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::RDA][logicalrank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_S_RTW_slr); + { + if (lastBurstLengthByCommandAndLogicalRank[Command::RDA][logicalrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_S_RTW_slr + tBURST16); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_S_RTW_slr); + } lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::RDA][physicalrank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_RTW_dlr); + { + if (lastBurstLengthByCommandAndPhysicalRank[Command::RDA][physicalrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_RTW_dlr + tBURST16); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_RTW_dlr); + } lastCommandStart = lastScheduledByCommand[Command::RDA]; - if (lastCommandStart != lastScheduledByCommandAndPhysicalRank[Command::RDA][physicalrank.ID()]) + if (lastCommandStart != lastScheduledByCommandAndPhysicalRank[Command::RDA][physicalrank.ID()]) // different physical rank { - if (lastCommandStart == lastScheduledByCommandAndDIMMRank[Command::RDA][dimmrank.ID()]) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR_dpr); - else - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR_ddr); + if (lastCommandStart == lastScheduledByCommandAndDimmRank[Command::RDA][dimmrank.ID()]) // same DIMM + { + if (lastBurstLengthByCommandAndDimmRank[Command::RDA][dimmrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR_dpr + tBURST16); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR_dpr); + } + else // different DIMM + { + if (lastBurstLengthByCommand[Command::RDA] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR_ddr + tBURST16); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR_ddr); + } } lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L_WR_slr); + { + if (lastBurstLengthByCommandAndBankGroup[Command::WR][bankgroup.ID()] == 32) + { + if (burstLength == 16 && memSpec->bitWidth == 4) // second WR requires RMW + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST16 + memSpec->tCCD_L_WR_slr); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST16 + memSpec->tCCD_L_WR2_slr); + } + else + { + if (burstLength == 16 && memSpec->bitWidth == 4) // second WR requires RMW + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L_WR_slr); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L_WR2_slr); + } + } lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::WR][logicalrank.ID()]; if (lastCommandStart != sc_max_time()) @@ -255,20 +428,50 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::WR][physicalrank.ID()]; if (lastCommandStart != sc_max_time()) + { + if (lastBurstLengthByCommandAndPhysicalRank[Command::WR][physicalrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST32); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_WR_dlr); + } lastCommandStart = lastScheduledByCommand[Command::WR]; - if (lastCommandStart != lastScheduledByCommandAndPhysicalRank[Command::WR][physicalrank.ID()]) + if (lastCommandStart != lastScheduledByCommandAndPhysicalRank[Command::WR][physicalrank.ID()]) // different physical rank { - if (lastCommandStart == lastScheduledByCommandAndDIMMRank[Command::WR][dimmrank.ID()]) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRWR_dpr); - else - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRWR_ddr); + if (lastCommandStart == lastScheduledByCommandAndDimmRank[Command::WR][dimmrank.ID()]) // same DIMM + { + if (lastBurstLengthByCommandAndDimmRank[Command::WR][dimmrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRWR_dpr + tBURST16); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRWR_dpr); + } + else // different DIMM + { + if (lastBurstLengthByCommand[Command::WR] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRWR_ddr + tBURST16); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRWR_ddr); + } } lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L_WR_slr); + { + if (lastBurstLengthByCommandAndBankGroup[Command::WRA][bankgroup.ID()] == 32) + { + if (burstLength == 16 && memSpec->bitWidth == 4) // second WR requires RMW + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST16 + memSpec->tCCD_L_WR_slr); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST16 + memSpec->tCCD_L_WR2_slr); + } + else + { + if (burstLength == 16 && memSpec->bitWidth == 4) // second WR requires RMW + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L_WR_slr); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L_WR2_slr); + } + } lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::WRA][logicalrank.ID()]; if (lastCommandStart != sc_max_time()) @@ -276,15 +479,30 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::WRA][physicalrank.ID()]; if (lastCommandStart != sc_max_time()) + { + if (lastBurstLengthByCommandAndPhysicalRank[Command::WRA][physicalrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST32); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_WR_dlr); + } lastCommandStart = lastScheduledByCommand[Command::WRA]; - if (lastCommandStart != lastScheduledByCommandAndPhysicalRank[Command::WRA][physicalrank.ID()]) + if (lastCommandStart != lastScheduledByCommandAndPhysicalRank[Command::WRA][physicalrank.ID()]) // different physical rank { - if (lastCommandStart == lastScheduledByCommandAndDIMMRank[Command::WRA][dimmrank.ID()]) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRWR_dpr); - else - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRWR_ddr); + if (lastCommandStart == lastScheduledByCommandAndDimmRank[Command::WRA][dimmrank.ID()]) // same DIMM + { + if (lastBurstLengthByCommandAndDimmRank[Command::WRA][dimmrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRWR_dpr + tBURST16); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRWR_dpr); + } + else // different DIMM + { + if (lastBurstLengthByCommand[Command::WRA] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRWR_ddr + tBURST16); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRWR_ddr); + } } } else if (command == Command::ACT) @@ -311,61 +529,71 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRAACT); + { + if (lastBurstLengthByCommandAndBank[Command::WRA][bank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRAACT + tBURST16); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRAACT); + } lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP - cmdOffset); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP - cmdLengthDiff); lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::PREA][logicalrank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP - cmdOffset); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP - cmdLengthDiff); lastCommandStart = lastScheduledByCommandAndBankInGroup[Command::PRESB][bankInGroup.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP - cmdOffset); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP - cmdLengthDiff); lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::REFA][logicalrank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC_slr - cmdOffset); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC_slr - cmdLengthDiff); // TODO: No tRFC_dlr and tRFC_dpr between REFA and ACT? lastCommandStart = lastScheduledByCommandAndBankInGroup[Command::REFSB][bankInGroup.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCsb_slr - cmdOffset); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCsb_slr - cmdLengthDiff); // TODO: No tRFCsb_dlr between REFSB and ACT? lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::REFSB][logicalrank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tREFSBRD_slr - cmdOffset); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tREFSBRD_slr - cmdLengthDiff); lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::REFSB][physicalrank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tREFSBRD_dlr - cmdOffset); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tREFSBRD_dlr - cmdLengthDiff); if (last4ActivatesLogical[logicalrank.ID()].size() >= 4) earliestTimeToStart = std::max(earliestTimeToStart, last4ActivatesLogical[logicalrank.ID()].front() - + memSpec->tFAW_slr - memSpec->cmdOffset_L); + + memSpec->tFAW_slr - memSpec->longCmdOffset); if (last4ActivatesPhysical[physicalrank.ID()].size() >= 4) earliestTimeToStart = std::max(earliestTimeToStart, last4ActivatesPhysical[physicalrank.ID()].front() - + memSpec->tFAW_dlr - memSpec->cmdOffset_L); + + memSpec->tFAW_dlr - memSpec->longCmdOffset); } else if (command == Command::PRE) { lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + memSpec->tCK); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + cmdLengthDiff); lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tCK); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + cmdLengthDiff); lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tCK); + { + if (lastBurstLengthByCommandAndBank[Command::WR][bank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + tBURST16 + cmdLengthDiff); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + cmdLengthDiff); + } lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::PRE][physicalrank.ID()]; if (lastCommandStart != sc_max_time()) @@ -383,23 +611,33 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr { lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::ACT][logicalrank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + memSpec->tCK); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + cmdLengthDiff); lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::RD][logicalrank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tCK); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + cmdLengthDiff); lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::RDA][logicalrank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tCK); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + cmdLengthDiff); lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::WR][logicalrank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tCK); + { + if (lastBurstLengthByCommandAndLogicalRank[Command::WR][logicalrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + tBURST16 + cmdLengthDiff); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + cmdLengthDiff); + } lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::WRA][logicalrank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tCK); + { + if (lastBurstLengthByCommandAndLogicalRank[Command::WRA][logicalrank.ID()]) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + tBURST16 + cmdLengthDiff); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + cmdLengthDiff); + } lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::PRE][physicalrank.ID()]; if (lastCommandStart != sc_max_time()) @@ -415,23 +653,33 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr { lastCommandStart = lastScheduledByCommandAndBankInGroup[Command::ACT][bankInGroup.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + memSpec->tCK); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + cmdLengthDiff); lastCommandStart = lastScheduledByCommandAndBankInGroup[Command::RD][bankInGroup.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tCK); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + cmdLengthDiff); lastCommandStart = lastScheduledByCommandAndBankInGroup[Command::RDA][bankInGroup.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tCK); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + cmdLengthDiff); lastCommandStart = lastScheduledByCommandAndBankInGroup[Command::WR][bankInGroup.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tCK); + { + if (lastBurstLengthByCommandAndBankInGroup[Command::WR][bankInGroup.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + tBURST16 + cmdLengthDiff); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + cmdLengthDiff); + } lastCommandStart = lastScheduledByCommandAndBankInGroup[Command::WRA][bankInGroup.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tCK); + { + if (lastBurstLengthByCommandAndBankInGroup[Command::WRA][bankInGroup.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + tBURST16 + cmdLengthDiff); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + cmdLengthDiff); + } lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::PRE][physicalrank.ID()]; if (lastCommandStart != sc_max_time()) @@ -447,15 +695,20 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr { lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::ACT][logicalrank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC + memSpec->tCK); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC + cmdLengthDiff); lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::RDA][physicalrank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDAACT + memSpec->tCK); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDAACT + cmdLengthDiff); lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::WRA][logicalrank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tRP + memSpec->tCK); + { + if (lastBurstLengthByCommandAndLogicalRank[Command::WRA][logicalrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + tBURST16 + memSpec->tRP + cmdLengthDiff); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tRP + cmdLengthDiff); + } lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::PRE][logicalrank.ID()]; if (lastCommandStart != sc_max_time()) @@ -473,7 +726,7 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC_dlr); - lastCommandStart = lastScheduledByCommandAndDIMMRank[Command::REFA][dimmrank.ID()]; + lastCommandStart = lastScheduledByCommandAndDimmRank[Command::REFA][dimmrank.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC_dpr); @@ -484,19 +737,24 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr { lastCommandStart = lastScheduledByCommandAndBankInGroup[Command::ACT][bankInGroup.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC + memSpec->tCK); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC + cmdLengthDiff); lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::ACT][logicalrank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRD_L_slr + memSpec->tCK); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRD_L_slr + cmdLengthDiff); lastCommandStart = lastScheduledByCommandAndBankInGroup[Command::RDA][bankInGroup.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDAACT + memSpec->tCK); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDAACT + cmdLengthDiff); lastCommandStart = lastScheduledByCommandAndBankInGroup[Command::WRA][bankInGroup.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRAACT + memSpec->tCK); + { + if (lastBurstLengthByCommandAndBankInGroup[Command::WRA][bankInGroup.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRAACT + tBURST16 + cmdLengthDiff); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRAACT + cmdLengthDiff); + } lastCommandStart = lastScheduledByCommandAndBankInGroup[Command::PRE][bankInGroup.ID()]; if (lastCommandStart != sc_max_time()) @@ -518,7 +776,7 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC_dlr); // TODO: check this - lastCommandStart = lastScheduledByCommandAndDIMMRank[Command::REFA][dimmrank.ID()]; + lastCommandStart = lastScheduledByCommandAndDimmRank[Command::REFA][dimmrank.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC_dpr); @@ -532,11 +790,11 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr if (last4ActivatesLogical[logicalrank.ID()].size() >= 4) earliestTimeToStart = std::max(earliestTimeToStart, last4ActivatesLogical[logicalrank.ID()].front() - + memSpec->tFAW_slr - memSpec->cmdOffset_S); + + memSpec->tFAW_slr - memSpec->shortCmdOffset); if (last4ActivatesPhysical[physicalrank.ID()].size() >= 4) earliestTimeToStart = std::max(earliestTimeToStart, last4ActivatesPhysical[physicalrank.ID()].front() - + memSpec->tFAW_dlr - memSpec->cmdOffset_S); + + memSpec->tFAW_dlr - memSpec->shortCmdOffset); } else SC_REPORT_FATAL("CheckerDDR5", "Unknown command!"); @@ -544,38 +802,62 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr if (lastCommandOnBus != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->tCK); + if (dummyCommandOnBus.start != sc_max_time()) + { + TimeInterval currentCommandOnBus(earliestTimeToStart, + earliestTimeToStart + memSpec->getCommandLength(command)); + if (currentCommandOnBus.intersects(dummyCommandOnBus)) + earliestTimeToStart = dummyCommandOnBus.end; + } + return earliestTimeToStart; } -void CheckerDDR5::insert(Command command, Rank rank, BankGroup bankgroup, Bank bank) +void CheckerDDR5::insert(Command command, Rank rank, BankGroup bankgroup, Bank bank, unsigned burstLength) { PRINTDEBUGMESSAGE("CheckerDDR5", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + commandToString(command)); - Rank logicalrank = rank; - Rank physicalrank = Rank(logicalrank.ID() / memSpec->logicalRanksPerPhysicalRank); - Rank dimmrank = Rank(physicalrank.ID() / memSpec->physicalRanksPerDIMMRank); + Rank logicalRank = rank; + Rank physicalRank = Rank(logicalRank.ID() / memSpec->logicalRanksPerPhysicalRank); + Rank dimmRank = Rank(physicalRank.ID() / memSpec->physicalRanksPerDIMMRank); + Bank bankInGroup = Bank(rank.ID() * memSpec->banksPerGroup + bank.ID() % memSpec->banksPerGroup); - lastScheduledByCommandAndDIMMRank[command][dimmrank.ID()] = sc_time_stamp(); - lastScheduledByCommandAndPhysicalRank[command][physicalrank.ID()] = sc_time_stamp(); - lastScheduledByCommandAndLogicalRank[command][logicalrank.ID()] = sc_time_stamp(); + lastScheduledByCommandAndDimmRank[command][dimmRank.ID()] = sc_time_stamp(); + lastScheduledByCommandAndPhysicalRank[command][physicalRank.ID()] = sc_time_stamp(); + lastScheduledByCommandAndLogicalRank[command][logicalRank.ID()] = sc_time_stamp(); lastScheduledByCommandAndBankGroup[command][bankgroup.ID()] = sc_time_stamp(); lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp(); lastScheduledByCommand[command] = sc_time_stamp(); + lastScheduledByCommandAndBankInGroup[command][bankInGroup.ID()] = sc_time_stamp(); + + if (isCasCommand(command)) + { + lastBurstLengthByCommandAndDimmRank[command][dimmRank.ID()] = burstLength; + lastBurstLengthByCommandAndPhysicalRank[command][physicalRank.ID()] = burstLength; + lastBurstLengthByCommandAndLogicalRank[command][logicalRank.ID()] = burstLength; + lastBurstLengthByCommandAndBankGroup[command][bankgroup.ID()] = burstLength; + lastBurstLengthByCommandAndBank[command][bank.ID()] = burstLength; + lastBurstLengthByCommand[command] = burstLength; + lastBurstLengthByCommandAndBankInGroup[command][bankInGroup.ID()] = burstLength; + + if (burstLength == 32) + { + dummyCommandOnBus.start = sc_time_stamp() + tBURST16; + dummyCommandOnBus.end = sc_time_stamp() + tBURST16 + memSpec->getCommandLength(command); + } + } lastCommandOnBus = sc_time_stamp() + memSpec->getCommandLength(command) - memSpec->tCK; - lastScheduledByCommandAndBankInGroup[command][rank.ID() * memSpec->banksPerGroup - + bank.ID() % memSpec->banksPerGroup] = sc_time_stamp(); - if (command == Command::ACT || command == Command::REFSB) { - if (last4ActivatesLogical[logicalrank.ID()].size() == 4) - last4ActivatesLogical[logicalrank.ID()].pop(); - last4ActivatesLogical[logicalrank.ID()].push(lastCommandOnBus); + if (last4ActivatesLogical[logicalRank.ID()].size() == 4) + last4ActivatesLogical[logicalRank.ID()].pop(); + last4ActivatesLogical[logicalRank.ID()].push(lastCommandOnBus); - if (last4ActivatesPhysical[physicalrank.ID()].size() == 4) - last4ActivatesPhysical[physicalrank.ID()].pop(); - last4ActivatesPhysical[physicalrank.ID()].push(lastCommandOnBus); + if (last4ActivatesPhysical[physicalRank.ID()].size() == 4) + last4ActivatesPhysical[physicalRank.ID()].pop(); + last4ActivatesPhysical[physicalRank.ID()].push(lastCommandOnBus); } } diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR5.h b/DRAMSys/library/src/controller/checker/CheckerDDR5.h index caf04154..7717b052 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR5.h +++ b/DRAMSys/library/src/controller/checker/CheckerDDR5.h @@ -40,34 +40,48 @@ #include #include "../../configuration/memspec/MemSpecDDR5.h" #include "../../configuration/Configuration.h" +#include "../../common/utils.h" class CheckerDDR5 final : public CheckerIF { public: CheckerDDR5(); - virtual sc_time timeToSatisfyConstraints(Command, Rank, BankGroup, Bank) const override; - virtual void insert(Command, Rank, BankGroup, Bank) override; + virtual sc_time timeToSatisfyConstraints(Command, Rank = Rank(0), + BankGroup = BankGroup(0), Bank = Bank(0), unsigned burstLength = 0) const override; + virtual void insert(Command, Rank, BankGroup, Bank, unsigned) override; private: const MemSpecDDR5 *memSpec; - std::vector> lastScheduledByCommandAndDIMMRank; + std::vector> lastScheduledByCommandAndDimmRank; std::vector> lastScheduledByCommandAndPhysicalRank; std::vector> lastScheduledByCommandAndLogicalRank; std::vector> lastScheduledByCommandAndBankGroup; std::vector> lastScheduledByCommandAndBank; std::vector lastScheduledByCommand; sc_time lastCommandOnBus; + TimeInterval dummyCommandOnBus; std::vector> lastScheduledByCommandAndBankInGroup; std::vector> last4ActivatesPhysical; std::vector> last4ActivatesLogical; - sc_time cmdOffset; + std::vector> lastBurstLengthByCommandAndDimmRank; + std::vector> lastBurstLengthByCommandAndPhysicalRank; + std::vector> lastBurstLengthByCommandAndLogicalRank; + std::vector> lastBurstLengthByCommandAndBankGroup; + std::vector> lastBurstLengthByCommandAndBank; + std::vector lastBurstLengthByCommand; - sc_time tRD_BURST; - sc_time tWR_BURST; + std::vector> lastBurstLengthByCommandAndBankInGroup; + + // TODO: store BL of last RD and WR globally or for each hierarchy? + + sc_time cmdLengthDiff; + + sc_time tBURST16; + sc_time tBURST32; sc_time tWTRA; sc_time tWRRDA; sc_time tWRPRE; diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp b/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp index fe5fc00d..a32251f1 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp @@ -64,7 +64,7 @@ CheckerGDDR5::CheckerGDDR5() tWRPRE = memSpec->tWL + tBURST + memSpec->tWR; } -sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank) const +sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank, unsigned) const { sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); @@ -525,7 +525,7 @@ sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankG return earliestTimeToStart; } -void CheckerGDDR5::insert(Command command, Rank rank, BankGroup bankgroup, Bank bank) +void CheckerGDDR5::insert(Command command, Rank rank, BankGroup bankgroup, Bank bank, unsigned) { PRINTDEBUGMESSAGE("CheckerGDDR5", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + commandToString(command)); diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR5.h b/DRAMSys/library/src/controller/checker/CheckerGDDR5.h index 326dae75..30ab9287 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR5.h +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR5.h @@ -45,8 +45,9 @@ class CheckerGDDR5 final : public CheckerIF { public: CheckerGDDR5(); - virtual sc_time timeToSatisfyConstraints(Command, Rank, BankGroup, Bank) const override; - virtual void insert(Command, Rank, BankGroup, Bank) override; + virtual sc_time timeToSatisfyConstraints(Command, Rank = Rank(0), + BankGroup = BankGroup(0), Bank = Bank(0), unsigned burstLength = 0) const override; + virtual void insert(Command, Rank, BankGroup, Bank, unsigned) override; private: const MemSpecGDDR5 *memSpec; diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp b/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp index bb5679a9..487184a0 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp @@ -64,7 +64,7 @@ CheckerGDDR5X::CheckerGDDR5X() tWRPRE = memSpec->tWL + tBURST + memSpec->tWR; } -sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank) const +sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank, unsigned) const { sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); @@ -525,7 +525,7 @@ sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, Rank rank, Bank return earliestTimeToStart; } -void CheckerGDDR5X::insert(Command command, Rank rank, BankGroup bankgroup, Bank bank) +void CheckerGDDR5X::insert(Command command, Rank rank, BankGroup bankgroup, Bank bank, unsigned) { PRINTDEBUGMESSAGE("CheckerGDDR5X", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + commandToString(command)); diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR5X.h b/DRAMSys/library/src/controller/checker/CheckerGDDR5X.h index 39138be3..652de82b 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR5X.h +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR5X.h @@ -45,8 +45,9 @@ class CheckerGDDR5X final : public CheckerIF { public: CheckerGDDR5X(); - virtual sc_time timeToSatisfyConstraints(Command, Rank, BankGroup, Bank) const override; - virtual void insert(Command, Rank, BankGroup, Bank) override; + virtual sc_time timeToSatisfyConstraints(Command, Rank = Rank(0), + BankGroup = BankGroup(0), Bank = Bank(0), unsigned burstLength = 0) const override; + virtual void insert(Command, Rank, BankGroup, Bank, unsigned) override; private: const MemSpecGDDR5X *memSpec; diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp b/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp index f0f6fa54..f50504e6 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp @@ -63,7 +63,7 @@ CheckerGDDR6::CheckerGDDR6() tWRPRE = memSpec->tWL + tBURST + memSpec->tWR; } -sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank) const +sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank, unsigned) const { sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); @@ -546,7 +546,7 @@ sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, Rank rank, BankG return earliestTimeToStart; } -void CheckerGDDR6::insert(Command command, Rank rank, BankGroup bankgroup, Bank bank) +void CheckerGDDR6::insert(Command command, Rank rank, BankGroup bankgroup, Bank bank, unsigned) { PRINTDEBUGMESSAGE("CheckerGDDR6", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + commandToString(command)); diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR6.h b/DRAMSys/library/src/controller/checker/CheckerGDDR6.h index 202bd8d3..edd78a7c 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR6.h +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR6.h @@ -45,8 +45,9 @@ class CheckerGDDR6 final : public CheckerIF { public: CheckerGDDR6(); - virtual sc_time timeToSatisfyConstraints(Command, Rank, BankGroup, Bank) const override; - virtual void insert(Command, Rank, BankGroup, Bank) override; + virtual sc_time timeToSatisfyConstraints(Command, Rank = Rank(0), + BankGroup = BankGroup(0), Bank = Bank(0), unsigned burstLength = 0) const override; + virtual void insert(Command, Rank, BankGroup, Bank, unsigned) override; private: const MemSpecGDDR6 *memSpec; diff --git a/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp b/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp index 4ed20f3f..7472d0ad 100644 --- a/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp @@ -64,7 +64,7 @@ CheckerHBM2::CheckerHBM2() tWRRDL = memSpec->tWL + tBURST + memSpec->tWTRL; } -sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank) const +sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank, unsigned) const { sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); @@ -500,7 +500,7 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, Rank rank, BankGr return earliestTimeToStart; } -void CheckerHBM2::insert(Command command, Rank rank, BankGroup bankgroup, Bank bank) +void CheckerHBM2::insert(Command command, Rank rank, BankGroup bankgroup, Bank bank, unsigned) { PRINTDEBUGMESSAGE("CheckerHBM2", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + commandToString(command)); diff --git a/DRAMSys/library/src/controller/checker/CheckerHBM2.h b/DRAMSys/library/src/controller/checker/CheckerHBM2.h index 3578ee9b..a68a5f86 100644 --- a/DRAMSys/library/src/controller/checker/CheckerHBM2.h +++ b/DRAMSys/library/src/controller/checker/CheckerHBM2.h @@ -45,8 +45,9 @@ class CheckerHBM2 final : public CheckerIF { public: CheckerHBM2(); - virtual sc_time timeToSatisfyConstraints(Command, Rank, BankGroup, Bank) const override; - virtual void insert(Command, Rank, BankGroup, Bank) override; + virtual sc_time timeToSatisfyConstraints(Command, Rank = Rank(0), + BankGroup = BankGroup(0), Bank = Bank(0), unsigned burstLength = 0) const override; + virtual void insert(Command, Rank, BankGroup, Bank, unsigned) override; private: const MemSpecHBM2 *memSpec; diff --git a/DRAMSys/library/src/controller/checker/CheckerIF.h b/DRAMSys/library/src/controller/checker/CheckerIF.h index b5c4d9bb..a930d797 100644 --- a/DRAMSys/library/src/controller/checker/CheckerIF.h +++ b/DRAMSys/library/src/controller/checker/CheckerIF.h @@ -46,8 +46,9 @@ class CheckerIF public: virtual ~CheckerIF() {} - virtual sc_time timeToSatisfyConstraints(Command, Rank, BankGroup, Bank) const = 0; - virtual void insert(Command, Rank, BankGroup, Bank) = 0; + virtual sc_time timeToSatisfyConstraints(Command, Rank = Rank(0), + BankGroup = BankGroup(0), Bank = Bank(0), unsigned burstLength = 0) const = 0; + virtual void insert(Command, Rank, BankGroup, Bank, unsigned) = 0; }; #endif // CHECKERIF_H diff --git a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp index 366f9b1f..2dfc9456 100644 --- a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp @@ -66,7 +66,7 @@ CheckerLPDDR4::CheckerLPDDR4() tREFPDEN = memSpec->tCK + memSpec->tCMDCKE; } -sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank) const +sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank, unsigned) const { sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); @@ -496,7 +496,7 @@ sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, Rank rank, Bank return earliestTimeToStart; } -void CheckerLPDDR4::insert(Command command, Rank rank, BankGroup, Bank bank) +void CheckerLPDDR4::insert(Command command, Rank rank, BankGroup, Bank bank, unsigned) { PRINTDEBUGMESSAGE("CheckerLPDDR4", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + commandToString(command)); diff --git a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h index 5a73154a..3fe5e506 100644 --- a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h +++ b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h @@ -45,8 +45,9 @@ class CheckerLPDDR4 final : public CheckerIF { public: CheckerLPDDR4(); - virtual sc_time timeToSatisfyConstraints(Command, Rank, BankGroup, Bank) const override; - virtual void insert(Command, Rank, BankGroup, Bank) override; + virtual sc_time timeToSatisfyConstraints(Command, Rank = Rank(0), + BankGroup = BankGroup(0), Bank = Bank(0), unsigned burstLength = 0) const override; + virtual void insert(Command, Rank, BankGroup, Bank, unsigned) override; private: const MemSpecLPDDR4 *memSpec; diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp b/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp index 6f588494..16985f5d 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp @@ -60,7 +60,7 @@ CheckerWideIO::CheckerWideIO() tWRAPDEN = memSpec->tWL + tBURST + memSpec->tWR; // + memSpec->tCK; ?? } -sc_time CheckerWideIO::timeToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank) const +sc_time CheckerWideIO::timeToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank, unsigned) const { sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); @@ -385,7 +385,7 @@ sc_time CheckerWideIO::timeToSatisfyConstraints(Command command, Rank rank, Bank return earliestTimeToStart; } -void CheckerWideIO::insert(Command command, Rank rank, BankGroup, Bank bank) +void CheckerWideIO::insert(Command command, Rank rank, BankGroup, Bank bank, unsigned) { PRINTDEBUGMESSAGE("CheckerWideIO", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + commandToString(command)); diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO.h b/DRAMSys/library/src/controller/checker/CheckerWideIO.h index e5cdb430..c8b145a6 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO.h +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO.h @@ -45,8 +45,9 @@ class CheckerWideIO final : public CheckerIF { public: CheckerWideIO(); - virtual sc_time timeToSatisfyConstraints(Command, Rank, BankGroup, Bank) const override; - virtual void insert(Command, Rank, BankGroup, Bank) override; + virtual sc_time timeToSatisfyConstraints(Command, Rank = Rank(0), + BankGroup = BankGroup(0), Bank = Bank(0), unsigned burstLength = 0) const override; + virtual void insert(Command, Rank, BankGroup, Bank, unsigned) override; private: const MemSpecWideIO *memSpec; diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp b/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp index 14818bed..10e75682 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp @@ -61,7 +61,7 @@ CheckerWideIO2::CheckerWideIO2() tWRRD_R = memSpec->tWL + memSpec->tCK + tBURST + memSpec->tRTRS - memSpec->tRL; } -sc_time CheckerWideIO2::timeToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank) const +sc_time CheckerWideIO2::timeToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank, unsigned) const { sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); @@ -463,7 +463,7 @@ sc_time CheckerWideIO2::timeToSatisfyConstraints(Command command, Rank rank, Ban return earliestTimeToStart; } -void CheckerWideIO2::insert(Command command, Rank rank, BankGroup, Bank bank) +void CheckerWideIO2::insert(Command command, Rank rank, BankGroup, Bank bank, unsigned) { PRINTDEBUGMESSAGE("CheckerWideIO2", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + commandToString(command)); diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO2.h b/DRAMSys/library/src/controller/checker/CheckerWideIO2.h index 08d328b9..a1e32636 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO2.h +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO2.h @@ -45,8 +45,9 @@ class CheckerWideIO2 final : public CheckerIF { public: CheckerWideIO2(); - virtual sc_time timeToSatisfyConstraints(Command, Rank, BankGroup, Bank) const override; - virtual void insert(Command, Rank, BankGroup, Bank) override; + virtual sc_time timeToSatisfyConstraints(Command, Rank = Rank(0), + BankGroup = BankGroup(0), Bank = Bank(0), unsigned burstLength = 0) const override; + virtual void insert(Command, Rank, BankGroup, Bank, unsigned) override; private: const MemSpecWideIO2 *memSpec; diff --git a/DRAMSys/library/src/simulation/Arbiter.cpp b/DRAMSys/library/src/simulation/Arbiter.cpp index 753af435..a0de4bb6 100644 --- a/DRAMSys/library/src/simulation/Arbiter.cpp +++ b/DRAMSys/library/src/simulation/Arbiter.cpp @@ -54,6 +54,8 @@ Arbiter::Arbiter(sc_module_name name, std::string pathToAddressMapping) : addressDecoder = new AddressDecoder(pathToAddressMapping); addressDecoder->print(); + + bytesPerBeat = Configuration::getInstance().memSpec->dataBusWidth / 8; } ArbiterSimple::ArbiterSimple(sc_module_name name, std::string pathToAddressMapping) : @@ -141,7 +143,7 @@ tlm_sync_enum Arbiter::nb_transport_fw(int id, tlm_generic_payload &payload, Channel(decodedAddress.channel), Rank(decodedAddress.rank), BankGroup(decodedAddress.bankgroup), Bank(decodedAddress.bank), Row(decodedAddress.row), Column(decodedAddress.column), - payload.get_streaming_width(), 0, 0); + payload.get_data_length() / bytesPerBeat, 0, 0); payload.acquire(); } diff --git a/DRAMSys/library/src/simulation/Arbiter.h b/DRAMSys/library/src/simulation/Arbiter.h index d124c466..8b3f9b44 100644 --- a/DRAMSys/library/src/simulation/Arbiter.h +++ b/DRAMSys/library/src/simulation/Arbiter.h @@ -87,6 +87,8 @@ protected: sc_time tCK; sc_time arbitrationDelayFw; sc_time arbitrationDelayBw; + + unsigned bytesPerBeat; }; class ArbiterSimple final : public Arbiter diff --git a/DRAMSys/simulator/StlPlayer.cpp b/DRAMSys/simulator/StlPlayer.cpp index 8ff71bb0..1a85a6b3 100644 --- a/DRAMSys/simulator/StlPlayer.cpp +++ b/DRAMSys/simulator/StlPlayer.cpp @@ -55,7 +55,7 @@ StlPlayer::StlPlayer(sc_module_name name, SC_REPORT_FATAL("StlPlayer", (std::string("Could not open trace ") + pathToTrace).c_str()); this->playerClk = playerClk; - burstlength = Configuration::getInstance().memSpec->burstLength; + burstLength = Configuration::getInstance().memSpec->burstLength; dataLength = Configuration::getInstance().memSpec->bytesPerBurst; lineCnt = 0; @@ -96,7 +96,7 @@ void StlPlayer::nextPayload() payload->set_response_status(TLM_INCOMPLETE_RESPONSE); payload->set_dmi_allowed(false); payload->set_byte_enable_length(0); - payload->set_streaming_width(burstlength); + payload->set_streaming_width(burstLength); payload->set_data_length(dataLength); payload->set_command(lineIterator->cmd); std::copy(lineIterator->data.begin(), lineIterator->data.end(), payload->get_data_ptr()); diff --git a/DRAMSys/simulator/StlPlayer.h b/DRAMSys/simulator/StlPlayer.h index 27081d41..cacf37bf 100644 --- a/DRAMSys/simulator/StlPlayer.h +++ b/DRAMSys/simulator/StlPlayer.h @@ -75,7 +75,7 @@ private: std::ifstream file; uint64_t lineCnt; - unsigned int burstlength; + unsigned int burstLength; unsigned int dataLength; sc_time playerClk; // May be different from the memory clock!