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Update tCCD_M timings in memspecs for DDR5

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This commit is contained in:
Derek Christ
2023-04-11 14:27:26 +02:00
parent 60b2bcbffa
commit 949cf944bc
19 changed files with 58 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
configs/memspec/JEDEC_2x2x8x4Gbx4_DDR5-3200A.json
View File

@@ -39,6 +39,8 @@
"CCD_L_slr": 8,
"CCD_L_WR_slr": 32,
"CCD_L_WR2_slr": 16,
"CCD_M_slr": 8,
"CCD_M_WR_slr": 32,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 0,
@@ -50,6 +52,7 @@
"FAW_slr": 32,
"FAW_dlr": 0,
"WTR_L": 16,
"WTR_M": 16,
"WTR_S": 4,
"RFC1_slr": 312,
"RFC2_slr": 208,

3
configs/memspec/JEDEC_2x4x1Gbx8_DDR5-3200A.json
View File

@@ -39,6 +39,8 @@
"CCD_L_slr": 8,
"CCD_L_WR_slr": 32,
"CCD_L_WR2_slr": 16,
"CCD_M_slr": 8,
"CCD_M_WR_slr": 32,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 0,
@@ -50,6 +52,7 @@
"FAW_slr": 32,
"FAW_dlr": 0,
"WTR_L": 16,
"WTR_M": 16,
"WTR_S": 4,
"RFC1_slr": 312,
"RFC2_slr": 208,

3
configs/memspec/JEDEC_2x4x1Gbx8_DDR5-3600A.json
View File

@@ -39,6 +39,8 @@
"CCD_L_slr": 9,
"CCD_L_WR_slr": 36,
"CCD_L_WR2_slr": 18,
"CCD_M_slr": 9,
"CCD_M_WR_slr": 36,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 0,
@@ -50,6 +52,7 @@
"FAW_slr": 32,
"FAW_dlr": 0,
"WTR_L": 18,
"WTR_M": 18,
"WTR_S": 5,
"RFC1_slr": 351,
"RFC2_slr": 234,

3
configs/memspec/JEDEC_2x4x1Gbx8_DDR5-4000A.json
View File

@@ -39,6 +39,8 @@
"CCD_L_slr": 10,
"CCD_L_WR_slr": 40,
"CCD_L_WR2_slr": 20,
"CCD_M_slr": 10,
"CCD_M_WR_slr": 40,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 0,
@@ -50,6 +52,7 @@
"FAW_slr": 32,
"FAW_dlr": 0,
"WTR_L": 20,
"WTR_M": 20,
"WTR_S": 5,
"RFC1_slr": 390,
"RFC2_slr": 260,

3
configs/memspec/JEDEC_2x4x1Gbx8_DDR5-4400A.json
View File

@@ -39,6 +39,8 @@
"CCD_L_slr": 11,
"CCD_L_WR_slr": 44,
"CCD_L_WR2_slr": 22,
"CCD_M_slr": 11,
"CCD_M_WR_slr": 44,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 0,
@@ -50,6 +52,7 @@
"FAW_slr": 32,
"FAW_dlr": 0,
"WTR_L": 22,
"WTR_M": 22,
"WTR_S": 6,
"RFC1_slr": 429,
"RFC2_slr": 286,

3
configs/memspec/JEDEC_2x4x1Gbx8_DDR5-4800A.json
View File

@@ -39,6 +39,8 @@
"CCD_L_slr": 12,
"CCD_L_WR_slr": 48,
"CCD_L_WR2_slr": 24,
"CCD_M_slr": 12,
"CCD_M_WR_slr": 48,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 0,
@@ -50,6 +52,7 @@
"FAW_slr": 32,
"FAW_dlr": 0,
"WTR_L": 24,
"WTR_M": 24,
"WTR_S": 6,
"RFC1_slr": 468,
"RFC2_slr": 312,

3
configs/memspec/JEDEC_2x4x1Gbx8_DDR5-5200A.json
View File

@@ -39,6 +39,8 @@
"CCD_L_slr": 13,
"CCD_L_WR_slr": 52,
"CCD_L_WR2_slr": 26,
"CCD_M_slr": 13,
"CCD_M_WR_slr": 52,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 0,
@@ -50,6 +52,7 @@
"FAW_slr": 32,
"FAW_dlr": 0,
"WTR_L": 26,
"WTR_M": 26,
"WTR_S": 7,
"RFC1_slr": 507,
"RFC2_slr": 338,

3
configs/memspec/JEDEC_2x4x1Gbx8_DDR5-5600A.json
View File

@@ -39,6 +39,8 @@
"CCD_L_slr": 14,
"CCD_L_WR_slr": 56,
"CCD_L_WR2_slr": 28,
"CCD_M_slr": 14,
"CCD_M_WR_slr": 56,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 0,
@@ -50,6 +52,7 @@
"FAW_slr": 32,
"FAW_dlr": 0,
"WTR_L": 28,
"WTR_M": 28,
"WTR_S": 7,
"RFC1_slr": 546,
"RFC2_slr": 364,

3
configs/memspec/JEDEC_2x4x1Gbx8_DDR5-6000A.json
View File

@@ -39,6 +39,8 @@
"CCD_L_slr": 15,
"CCD_L_WR_slr": 60,
"CCD_L_WR2_slr": 30,
"CCD_M_slr": 15,
"CCD_M_WR_slr": 60,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 0,
@@ -50,6 +52,7 @@
"FAW_slr": 32,
"FAW_dlr": 0,
"WTR_L": 30,
"WTR_M": 30,
"WTR_S": 8,
"RFC1_slr": 585,
"RFC2_slr": 390,

3
configs/memspec/JEDEC_2x4x1Gbx8_DDR5-6400A.json
View File

@@ -39,6 +39,8 @@
"CCD_L_slr": 16,
"CCD_L_WR_slr": 64,
"CCD_L_WR2_slr": 32,
"CCD_M_slr": 16,
"CCD_M_WR_slr": 64,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 0,
@@ -50,6 +52,7 @@
"FAW_slr": 32,
"FAW_dlr": 0,
"WTR_L": 32,
"WTR_M": 32,
"WTR_S": 8,
"RFC1_slr": 624,
"RFC2_slr": 416,

3
configs/memspec/JEDEC_2x8x2Gbx4_DDR5-3600A.json
View File

@@ -39,6 +39,8 @@
"CCD_L_slr": 9,
"CCD_L_WR_slr": 36,
"CCD_L_WR2_slr": 18,
"CCD_M_slr": 9,
"CCD_M_WR_slr": 36,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 0,
@@ -50,6 +52,7 @@
"FAW_slr": 32,
"FAW_dlr": 0,
"WTR_L": 18,
"WTR_M": 18,
"WTR_S": 5,
"RFC1_slr": 351,
"RFC2_slr": 234,

3
configs/memspec/JEDEC_2x8x2Gbx4_DDR5-4000A.json
View File

@@ -39,6 +39,8 @@
"CCD_L_slr": 10,
"CCD_L_WR_slr": 40,
"CCD_L_WR2_slr": 20,
"CCD_M_slr": 10,
"CCD_M_WR_slr": 40,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 0,
@@ -50,6 +52,7 @@
"FAW_slr": 32,
"FAW_dlr": 0,
"WTR_L": 20,
"WTR_M": 20,
"WTR_S": 5,
"RFC1_slr": 390,
"RFC2_slr": 260,

3
configs/memspec/JEDEC_2x8x2Gbx4_DDR5-4400A.json
View File

@@ -39,6 +39,8 @@
"CCD_L_slr": 11,
"CCD_L_WR_slr": 44,
"CCD_L_WR2_slr": 22,
"CCD_M_slr": 11,
"CCD_M_WR_slr": 44,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 0,
@@ -50,6 +52,7 @@
"FAW_slr": 32,
"FAW_dlr": 0,
"WTR_L": 22,
"WTR_M": 22,
"WTR_S": 6,
"RFC1_slr": 429,
"RFC2_slr": 286,

3
configs/memspec/JEDEC_2x8x2Gbx4_DDR5-4800A.json
View File

@@ -39,6 +39,8 @@
"CCD_L_slr": 12,
"CCD_L_WR_slr": 48,
"CCD_L_WR2_slr": 24,
"CCD_M_slr": 12,
"CCD_M_WR_slr": 48,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 0,
@@ -50,6 +52,7 @@
"FAW_slr": 32,
"FAW_dlr": 0,
"WTR_L": 24,
"WTR_M": 24,
"WTR_S": 6,
"RFC1_slr": 468,
"RFC2_slr": 312,

3
configs/memspec/JEDEC_2x8x2Gbx4_DDR5-5200A.json
View File

@@ -39,6 +39,8 @@
"CCD_L_slr": 13,
"CCD_L_WR_slr": 52,
"CCD_L_WR2_slr": 26,
"CCD_M_slr": 13,
"CCD_M_WR_slr": 52,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 0,
@@ -50,6 +52,7 @@
"FAW_slr": 32,
"FAW_dlr": 0,
"WTR_L": 26,
"WTR_M": 26,
"WTR_S": 7,
"RFC1_slr": 507,
"RFC2_slr": 338,

3
configs/memspec/JEDEC_2x8x2Gbx4_DDR5-5600A.json
View File

@@ -39,6 +39,8 @@
"CCD_L_slr": 14,
"CCD_L_WR_slr": 56,
"CCD_L_WR2_slr": 28,
"CCD_M_slr": 14,
"CCD_M_WR_slr": 56,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 0,
@@ -50,6 +52,7 @@
"FAW_slr": 32,
"FAW_dlr": 0,
"WTR_L": 28,
"WTR_M": 28,
"WTR_S": 7,
"RFC1_slr": 546,
"RFC2_slr": 364,

3
configs/memspec/JEDEC_2x8x2Gbx4_DDR5-6000A.json
View File

@@ -39,6 +39,8 @@
"CCD_L_slr": 15,
"CCD_L_WR_slr": 60,
"CCD_L_WR2_slr": 30,
"CCD_M_slr": 15,
"CCD_M_WR_slr": 60,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 0,
@@ -50,6 +52,7 @@
"FAW_slr": 32,
"FAW_dlr": 0,
"WTR_L": 30,
"WTR_M": 30,
"WTR_S": 8,
"RFC1_slr": 585,
"RFC2_slr": 390,

3
configs/memspec/JEDEC_2x8x2Gbx4_DDR5-6400A.json
View File

@@ -39,6 +39,8 @@
"CCD_L_slr": 16,
"CCD_L_WR_slr": 64,
"CCD_L_WR2_slr": 32,
"CCD_M_slr": 16,
"CCD_M_WR_slr": 64,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 0,
@@ -50,6 +52,7 @@
"FAW_slr": 32,
"FAW_dlr": 0,
"WTR_L": 32,
"WTR_M": 32,
"WTR_S": 8,
"RFC1_slr": 624,
"RFC2_slr": 416,

5
configs/memspec/JEDEC_2x8x8x2Gbx4_DDR5-3200A.json
View File

@@ -39,6 +39,8 @@
"CCD_L_slr": 8,
"CCD_L_WR_slr": 32,
"CCD_L_WR2_slr": 16,
"CCD_M_slr": 8,
"CCD_M_WR_slr": 32,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 8,
@@ -49,7 +51,8 @@
"RRD_dlr": 4,
"FAW_slr": 32,
"FAW_dlr": 16,
"WTR_L": 16,
"WTR_L": 16,
"WTR_M": 16,
"WTR_S": 4,
"RFC1_slr": 312,
"RFC2_slr": 208,