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Remove hard-coded subdirectory paths for configs

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Previously, the subdirectories in which the sub-json files were searched
in were hardcoded. Now, DRAMSys simply searches in the directory of the
base config, making this approach more flexible.
This commit is contained in:
Derek Christ
2025-04-07 13:26:47 +02:00
parent a97b676b92
commit 939fc90f98
34 changed files with 61 additions and 285 deletions
Download Patch File Download Diff File Expand all files Collapse all files

46
configs/addressmapping/am_ranktest.json
View File

@@ -1,46 +0,0 @@
{
"addressmapping": {
"RANK_BIT":[
30,
31
],
"BANK_BIT": [
27,
28,
29
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26
]
}
}

10
configs/ddr3-example.json
View File

@@ -1,14 +1,14 @@
{
"simulation": {
"addressmapping": "am_ddr3_8x1Gbx8_dimm_p1KB_rbc.json",
"mcconfig": "fr_fcfs.json",
"memspec": "MICRON_1Gb_DDR3-1600_8bit_G.json",
"simconfig": "example.json",
"addressmapping": "addressmapping/am_ddr3_8x1Gbx8_dimm_p1KB_rbc.json",
"mcconfig": "mcconfig/fr_fcfs.json",
"memspec": "memspec/MICRON_1Gb_DDR3-1600_8bit_G.json",
"simconfig": "simconfig/example.json",
"simulationid": "ddr3-example",
"tracesetup": [
{
"clkMhz": 800,
"name": "example.stl"
"name": "traces/example.stl"
}
]
}

9
configs/ddr3-gem5-se.json
View File

@@ -1,9 +0,0 @@
{
"simulation": {
"addressmapping": "am_ddr3_8x1Gbx8_dimm_p1KB_brc.json",
"mcconfig": "fifoStrict.json",
"memspec": "MICRON_1Gb_DDR3-1600_8bit_G.json",
"simconfig": "gem5_se.json",
"simulationid": "ddr3-gem5-se"
}
}

10
configs/ddr4-example.json
View File

@@ -1,14 +1,14 @@
{
"simulation": {
"addressmapping": "am_ddr4_8x4Gbx8_dimm_p1KB_brc.json",
"mcconfig": "fr_fcfs.json",
"memspec": "JEDEC_4Gb_DDR4-1866_8bit_A.json",
"simconfig": "example.json",
"addressmapping": "addressmapping/am_ddr4_8x4Gbx8_dimm_p1KB_brc.json",
"mcconfig": "mcconfig/fr_fcfs.json",
"memspec": "memspec/JEDEC_4Gb_DDR4-1866_8bit_A.json",
"simconfig": "simconfig/example.json",
"simulationid": "ddr4-example",
"tracesetup": [
{
"clkMhz": 200,
"name": "example.stl"
"name": "traces/example.stl"
}
]
}

2
configs/ddr4-full-example.json
View File

@@ -147,7 +147,7 @@
"tracesetup": [
{
"clkMhz": 200,
"name": "example.stl"
"name": "traces/example.stl"
}
]
}

10
configs/ddr5-example.json
View File

@@ -1,14 +1,14 @@
{
"simulation": {
"addressmapping": "am_ddr5_2x8x2Gbx4_dimm_p1KB_rbc.json",
"mcconfig": "fr_fcfs.json",
"memspec": "JEDEC_2x8x2Gbx4_DDR5-3200A.json",
"simconfig": "example.json",
"addressmapping": "addressmapping/am_ddr5_2x8x2Gbx4_dimm_p1KB_rbc.json",
"mcconfig": "mcconfig/fr_fcfs.json",
"memspec": "memspec/JEDEC_2x8x2Gbx4_DDR5-3200A.json",
"simconfig": "simconfig/example.json",
"simulationid": "ddr5-example",
"tracesetup": [
{
"clkMhz": 2000,
"name": "example.stl"
"name": "traces/example.stl"
}
]
}

8
configs/ddr5-generator-example.json
View File

@@ -1,9 +1,9 @@
{
"simulation": {
"addressmapping": "am_ddr5_2x8x2Gbx4_dimm_p1KB_rbc.json",
"mcconfig": "fr_fcfs.json",
"memspec": "JEDEC_2x8x2Gbx4_DDR5-3200A.json",
"simconfig": "example.json",
"addressmapping": "addressmapping/am_ddr5_2x8x2Gbx4_dimm_p1KB_rbc.json",
"mcconfig": "mcconfig/fr_fcfs.json",
"memspec": "memspec/JEDEC_2x8x2Gbx4_DDR5-3200A.json",
"simconfig": "simconfig/example.json",
"simulationid": "ddr5-example",
"tracesetup": [
{

29
configs/ddr5-rfm.json
View File

@@ -1,29 +0,0 @@
{
"simulation": {
"addressmapping": "am_ddr5_2x2x8x4Gbx4_dimm_p1KB_rbc.json",
"mcconfig": "fr_fcfs_rfm.json",
"memspec": "JEDEC_2x2x8x4Gbx4_DDR5-3200A.json",
"simconfig": "example.json",
"simulationid": "ddr5-example",
"tracesetup": [
{
"clkMhz": 2000,
"type": "generator",
"name": "gen0",
"numRequests": 126000,
"rwRatio": 0.85,
"addressDistribution": "random",
"seed": 123456,
"maxPendingReadRequests": 24,
"maxPendingWriteRequests": 24
},
{
"clkMhz": 4000,
"type": "hammer",
"name": "ham0",
"numRequests": 4000,
"rowIncrement": 2097152
}
]
}
}

10
configs/hbm2-example.json
View File

@@ -1,14 +1,14 @@
{
"simulation": {
"addressmapping": "am_hbm2_8Gb_pc_brc.json",
"mcconfig": "fr_fcfs.json",
"memspec": "HBM2.json",
"simconfig": "example.json",
"addressmapping": "addressmapping/am_hbm2_8Gb_pc_brc.json",
"mcconfig": "mcconfig/fr_fcfs.json",
"memspec": "memspec/HBM2.json",
"simconfig": "simconfig/example.json",
"simulationid": "hbm2-example",
"tracesetup": [
{
"clkMhz": 1000,
"name": "example.stl"
"name": "traces/example.stl"
}
]
}

8
configs/hbm3-example.json
View File

@@ -1,9 +1,9 @@
{
"simulation": {
"addressmapping": "am_hbm3_8Gb_pc_brc.json",
"mcconfig": "fr_fcfs.json",
"memspec": "HBM3.json",
"simconfig": "example.json",
"addressmapping": "addressmapping/am_hbm3_8Gb_pc_brc.json",
"mcconfig": "mcconfig/fr_fcfs.json",
"memspec": "memspec/HBM3.json",
"simconfig": "simconfig/example.json",
"simulationid": "hbm3-example",
"tracesetup": [
{

10
configs/lpddr4-example.json
View File

@@ -1,14 +1,14 @@
{
"simulation": {
"addressmapping": "am_lpddr4_8Gbx16_brc.json",
"mcconfig": "fr_fcfs.json",
"memspec": "JEDEC_8Gb_LPDDR4-3200_16bit.json",
"simconfig": "example.json",
"addressmapping": "addressmapping/am_lpddr4_8Gbx16_brc.json",
"mcconfig": "mcconfig/fr_fcfs.json",
"memspec": "memspec/JEDEC_8Gb_LPDDR4-3200_16bit.json",
"simconfig": "simconfig/example.json",
"simulationid": "lpddr4-example",
"tracesetup": [
{
"clkMhz": 200,
"name": "example.stl"
"name": "traces/example.stl"
}
]
}

10
configs/lpddr5-example.json
View File

@@ -1,14 +1,14 @@
{
"simulation": {
"addressmapping": "am_lpddr5_1Gbx16_BG_rocobabg.json",
"mcconfig": "fr_fcfs_refp2b.json",
"memspec": "JEDEC_1Gbx16_BG_LPDDR5-6400.json",
"simconfig": "example.json",
"addressmapping": "addressmapping/am_lpddr5_1Gbx16_BG_rocobabg.json",
"mcconfig": "mcconfig/fr_fcfs_refp2b.json",
"memspec": "memspec/JEDEC_1Gbx16_BG_LPDDR5-6400.json",
"simconfig": "simconfig/example.json",
"simulationid": "lpddr5-example",
"tracesetup": [
{
"clkMhz": 200,
"name": "example.stl"
"name": "traces/example.stl"
}
]
}

61
configs/memspec/memspec_ranktest.json
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@@ -1,61 +0,0 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 8,
"dataRate": 2,
"nbrOfBanks": 8,
"nbrOfColumns": 1024,
"nbrOfRanks": 4,
"nbrOfRows": 16384,
"width": 8,
"nbrOfDevicesOnDIMM": 8,
"nbrOfChannels": 1
},
"memoryId": "MICRON_1Gb_DDR3-1600_8bit_G",
"memoryType": "DDR3",
"mempowerspec": {
"idd0": 70.0,
"idd2n": 45.0,
"idd2p0": 12.0,
"idd2p1": 30.0,
"idd3n": 45.0,
"idd3p0": 35.0,
"idd3p1": 35.0,
"idd4r": 140.0,
"idd4w": 145.0,
"idd5": 170.0,
"idd6": 8.0,
"vdd": 1.5
},
"memtimingspec": {
"AL": 0,
"CCD": 4,
"CKE": 3,
"CKESR": 4,
"CL": 10,
"DQSCK": 0,
"FAW": 24,
"RAS": 28,
"RC": 38,
"RCD": 10,
"REFI": 6240,
"RFC": 88,
"RL": 10,
"RP": 10,
"RRD": 5,
"RTP": 6,
"WL": 8,
"WR": 12,
"WTR": 6,
"XP": 6,
"XPDLL": 20,
"XS": 96,
"XSDLL": 512,
"ACTPDEN": 1,
"PRPDEN": 1,
"REFPDEN": 1,
"RTRS": 1,
"tCK": 1250
}
}
}

15
configs/ranktest.json
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@@ -1,15 +0,0 @@
{
"simulation": {
"addressmapping": "am_ranktest.json",
"mcconfig": "fr_fcfs.json",
"memspec": "memspec_ranktest.json",
"simconfig": "example.json",
"simulationid": "ranktest",
"tracesetup": [
{
"clkMhz": 200,
"name": "ranktest.stl"
}
]
}
}

10
configs/stt-mram-example.json
View File

@@ -1,14 +1,14 @@
{
"simulation": {
"addressmapping": "am_stt-mram_8x2Gbx8_dimm_p1KB_rbc.json",
"mcconfig": "fr_fcfs_noref.json",
"memspec": "STT-MRAM-1.2x.json",
"simconfig": "example.json",
"addressmapping": "addressmapping/am_stt-mram_8x2Gbx8_dimm_p1KB_rbc.json",
"mcconfig": "mcconfig/fr_fcfs_noref.json",
"memspec": "memspec/STT-MRAM-1.2x.json",
"simconfig": "simconfig/example.json",
"simulationid": "stt-mram-example",
"tracesetup": [
{
"clkMhz": 800,
"name": "example.stl"
"name": "traces/example.stl"
}
]
}

33
configs/traces/ranktest.stl
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@@ -1,33 +0,0 @@
0: write 0x00000000
1: write 0x08000000
2: write 0x10000000
3: write 0x18000000
4: write 0x20000000
5: write 0x28000000
6: write 0x30000000
7: write 0x38000000
8: write 0x40000000
9: write 0x48000000
10: write 0x50000000
11: write 0x58000000
12: write 0x60000000
13: write 0x68000000
14: write 0x70000000
15: write 0x78000000
16: write 0x80000000
17: write 0x88000000
18: write 0x90000000
19: write 0x98000000
20: write 0xA0000000
21: write 0xA8000000
22: write 0xB0000000
23: write 0xB8000000
24: write 0xC0000000
25: write 0xC8000000
26: write 0xD0000000
27: write 0xD8000000
28: write 0xE0000000
29: write 0xE8000000
30: write 0xF0000000
31: write 0xF8000000
32: write 0x00000000

15
configs/wideio-thermal.json
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@@ -1,15 +0,0 @@
{
"simulation": {
"addressmapping": "am_wideio_thermal.json",
"mcconfig": "fr_fcfs.json",
"memspec": "JEDEC_256Mb_WIDEIO-200_128bit.json",
"simconfig": "wideio_thermal.json",
"simulationid": "wideio-example",
"tracesetup": [
{
"clkMhz": 1000,
"name": "test_error.stl"
}
]
}
}