diff --git a/DRAMSys/library/resources/simulations/ddr3-example2.xml b/DRAMSys/library/resources/simulations/ddr3-example2.xml
new file mode 100644
index 00000000..e3af4615
--- /dev/null
+++ b/DRAMSys/library/resources/simulations/ddr3-example2.xml
@@ -0,0 +1,25 @@
+<simulation>
+    <!-- Simulation file identifier -->
+    <simulationid id="ddr3-example2"></simulationid>
+    <!-- Configuration for the DRAMSys Simulator -->
+    <simconfig src="ddr3.xml" />
+    <!-- Temperature Simulator Configuration -->
+    <thermalconfig src="config.xml" />
+    <!-- Memory Device Specification: Which Device is on the DDR3 DIMM -->
+    <memspec src="MICRON_1Gb_DDR3-1600_8bit_G.xml"></memspec>
+    <!-- Addressmapping Configuration of the Memory Controller -->
+    <addressmapping src="am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml"></addressmapping>
+    <!-- Memory Controller Configuration: -->
+    <mcconfig src="fifoStrict.xml"/>
+    <!--
+    The following trace setup is only used in standalone mode.
+    In library mode e.g. in Platform Architect the trace setup is ignored.
+    -->
+    <tracesetup>
+        <!--
+        This device mimics an image processing application
+        running on an FPGA with 200 Mhz.
+        -->
+        <device clkMhz="200">ddr3_example.stl</device>
+    </tracesetup>
+</simulation>
diff --git a/DRAMSys/library/resources/simulations/ddr3-example3.xml b/DRAMSys/library/resources/simulations/ddr3-example3.xml
new file mode 100644
index 00000000..3f9aac7e
--- /dev/null
+++ b/DRAMSys/library/resources/simulations/ddr3-example3.xml
@@ -0,0 +1,26 @@
+<simulation>
+    <!-- Simulation file identifier -->
+    <simulationid id="ddr3-example3"></simulationid>
+    <!-- Configuration for the DRAMSys Simulator -->
+    <simconfig src="ddr3.xml" />
+    <!-- Temperature Simulator Configuration -->
+    <thermalconfig src="config.xml" />
+    <!-- Memory Device Specification: Which Device is on the DDR3 DIMM -->
+    <memspec src="MICRON_1Gb_DDR3-1600_8bit_G.xml"></memspec>
+    <!-- Addressmapping Configuration of the Memory Controller -->
+    <addressmapping src="am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml"></addressmapping>
+    <!-- Memory Controller Configuration: -->
+    <mcconfig src="fifoStrict.xml"/>
+    <!--
+    The following trace setup is only used in standalone mode.
+    In library mode e.g. in Platform Architect the trace setup is ignored.
+    -->
+    <tracesetup>
+        <!--
+             Two memory bus master devices, one running at 300 MHz and the
+             other at 400 MHz.
+        -->
+        <device clkMhz="300">ddr3_example.stl</device>
+        <device clkMhz="400">ddr3_example.stl</device>
+    </tracesetup>
+</simulation>