diff --git a/DRAMSys/library/resources/configs/mcconfigs/rgrmccfg.xml b/DRAMSys/library/resources/configs/mcconfigs/rgrmccfg.xml
index f6b02b27..5f2adc2e 100644
--- a/DRAMSys/library/resources/configs/mcconfigs/rgrmccfg.xml
+++ b/DRAMSys/library/resources/configs/mcconfigs/rgrmccfg.xml
@@ -9,6 +9,8 @@
+
+
diff --git a/DRAMSys/library/src/controller/core/configuration/Configuration.cpp b/DRAMSys/library/src/controller/core/configuration/Configuration.cpp
index 42f17b21..6c726065 100644
--- a/DRAMSys/library/src/controller/core/configuration/Configuration.cpp
+++ b/DRAMSys/library/src/controller/core/configuration/Configuration.cpp
@@ -153,8 +153,7 @@ void Configuration::setParameter(std::string name, std::string value)
". This parameter must be between 0 and 100.").c_str());
} else {
SJFProbability = string2int(value);
- }
- else if (name == "RequestBufferSize")
+ } else if (name == "RequestBufferSize")
RequestBufferSize = string2int(value);
else if (name == "Capsize")
Capsize = string2int(value);
@@ -202,7 +201,12 @@ void Configuration::setParameter(std::string name, std::string value)
RowGranularRef = string2bool(value);
else if (name == "ControllerCoreRowGranularRefRowInc")RowInc = string2int(
value);
- else if (name == "ControllerCoreRowGranularRefNumAR")NumAR = string2int(value);
+ else if (name == "ControllerCoreRefMode") {
+ RefMode = string2int(value);
+ if (RefMode != 1 && RefMode != 2 && RefMode != 4)
+ SC_REPORT_FATAL("Configuration", (name + " invalid value.").c_str());
+ }
+ else if (name == "ControllerCoreRowGranularRefNumAR")NumAR = string2int(value);
else if (name == "ControllerCoreRowGranularRefB0")RGRB0 = string2bool(value);
else if (name == "ControllerCoreRowGranularRefB1")RGRB1 = string2bool(value);
else if (name == "ControllerCoreRowGranularRefB2")RGRB2 = string2bool(value);
@@ -235,20 +239,8 @@ void Configuration::setParameter(std::string name, std::string value)
ControllerCoreForceMaxRefBurst = string2bool(value);
else if (name == "ControllerCoreEnableRefPostpone") {
ControllerCoreEnableRefPostpone = string2bool(value);
- // Refresh postpone feature available for DDR3 only in the current
- // version of DRAMsys.
- if (ControllerCoreEnableRefPostpone && memSpec.MemoryType != "DDR3") {
- SC_REPORT_FATAL("Configuration",
- (name + " requires memory type DDR3.").c_str());
- }
} else if (name == "ControllerCoreEnableRefPullIn") {
ControllerCoreEnableRefPullIn = string2bool(value);
- // Refresh pull-in feature available for DDR3 only in the current
- // version of DRAMsys.
- if (ControllerCoreEnableRefPullIn && memSpec.MemoryType != "DDR3") {
- SC_REPORT_FATAL("Configuration",
- (name + " requires memory type DDR3.").c_str());
- }
} else if (name == "ControllerCoreMaxPostponedARCmd")
ControllerCoreMaxPostponedARCmd = string2int(value);
else if (name == "ControllerCoreMaxPulledInARCmd")
@@ -423,6 +415,11 @@ unsigned int Configuration::getRowInc(void)
return RowInc;
}
+unsigned int Configuration::getRefMode(void)
+{
+ return RefMode;
+}
+
// Changes the number of bytes depeding on the ECC Controller. This function is needed for modules which get data directly or indirectly from the ECC Controller
unsigned int Configuration::adjustNumBytesAfterECC(unsigned nBytes)
{
diff --git a/DRAMSys/library/src/controller/core/configuration/Configuration.h b/DRAMSys/library/src/controller/core/configuration/Configuration.h
index 99c9cb9e..28de22c7 100644
--- a/DRAMSys/library/src/controller/core/configuration/Configuration.h
+++ b/DRAMSys/library/src/controller/core/configuration/Configuration.h
@@ -116,10 +116,12 @@ struct Configuration {
bool RGRB14 = true;
bool RGRB15 = true;
unsigned int NumAR = 8192;
+ unsigned int RefMode = 1;
unsigned int RowInc = 1;
bool getRGRBank(unsigned int);
unsigned int getNumAR(void);
unsigned int getRowInc(void);
+ unsigned int getRefMode(void);
bool ControllerCoreForceMaxRefBurst = false;
bool ControllerCoreEnableRefPostpone = false;
bool ControllerCoreEnableRefPullIn = false;
diff --git a/DRAMSys/library/src/controller/core/refresh/RGR.cpp b/DRAMSys/library/src/controller/core/refresh/RGR.cpp
index 3be8eeee..3def058c 100644
--- a/DRAMSys/library/src/controller/core/refresh/RGR.cpp
+++ b/DRAMSys/library/src/controller/core/refresh/RGR.cpp
@@ -42,18 +42,17 @@ using namespace std;
RGR::RGR(sc_module_name, ControllerCore &ctrlcore) : ccore(ctrlcore),
timing(ctrlcore.config.memSpec.refreshTimings[ccore.getBanks()[0]])
{
- if (ccore.config.ControllerCoreEnableRefPostpone) {
- maxpostpone = ccore.config.ControllerCoreMaxPostponedARCmd;
- }
- if (ccore.config.ControllerCoreEnableRefPullIn) {
- maxpullin = ccore.config.ControllerCoreMaxPulledInARCmd;
- }
+ auto m = ccore.config.getRefMode();
+ tREFIx = timing.tREFI / m;
+ if (ccore.config.ControllerCoreEnableRefPostpone)
+ maxpostpone = ccore.config.ControllerCoreMaxPostponedARCmd * m;
+ if (ccore.config.ControllerCoreEnableRefPullIn)
+ maxpullin = ccore.config.ControllerCoreMaxPulledInARCmd * m;
#if 0
- if (Configuration::getInstance().BankwiseLogic) {
+ if (ccore.config.BankwiseLogic) {
for (Bank b : ccore.getBanks()) {
- sc_time refi = Configuration::getInstance().memSpec.refreshTimings[b].tREFI;
- nextPlannedRefreshs[b] = b.ID() * refi /
- Configuration::getInstance().memSpec.NumberOfBanks;
+ auto nbs = ccore.config.memSpec.NumberOfBanks;
+ nextPlannedRefreshs[b] = b.ID() * tREFIx / nbs;
}
}
#endif
@@ -66,12 +65,12 @@ RGR::RGR(sc_module_name, ControllerCore &ctrlcore) : ccore(ctrlcore),
nextState[b] = ST_REFRESH;
setUpDummy(rps[b], b);
}
- if (Configuration::getInstance().BankwiseLogic) {
+ if (ccore.config.BankwiseLogic) {
for (Bank b : ccore.getBanks()) {
- planNextRefresh(b, timing.tREFI);
+ planNextRefresh(b, tREFIx);
}
} else {
- planNextRefresh(ccore.getBanks()[0], timing.tREFI);
+ planNextRefresh(ccore.getBanks()[0], tREFIx);
}
}
@@ -83,16 +82,13 @@ bool RGR::hasCollision(const ScheduledCommand __attribute__((unused)) &cmd)
{
#if 0
bool r = false;
- nbs = Configuration::getInstance().memSpec.NumberOfBanks;
+ nbs = ccore.config.memSpec.NumberOfBanks;
for (unsigned b = 0; b < nbs; b++) {
if (cmd.getStart() < currentRefresh[b] && cmd.getEnd() > currentRefresh[b])
r = true;
-
- if (cmd.getStart() < nextPlannedRefreshs[b]
- && cmd.getEnd() > nextPlannedRefreshs[b])
+ if (cmd.getStart() < nextPlannedRefreshs[b] && cmd.getEnd() > nextPlannedRefreshs[b])
r = true;
}
-
return r;
#else
return false;
@@ -102,12 +98,13 @@ bool RGR::hasCollision(const ScheduledCommand __attribute__((unused)) &cmd)
void RGR::doRefresh(tlm::tlm_generic_payload &p, sc_time t)
{
sc_assert(!isInvalidated(p, t));
- auto nr = Configuration::getInstance().memSpec.NumberOfRows;
- auto nar = Configuration::getInstance().getNumAR();
- auto ri = Configuration::getInstance().getRowInc();
- assert((nr / nar) > 0);
+ auto nr = ccore.config.memSpec.NumberOfRows;
+ auto nar = ccore.config.getNumAR();
+ auto ri = ccore.config.getRowInc();
+ auto m = ccore.config.getRefMode();
+ assert(((nr / m) / nar) > 0);
Bank b = DramExtension::getExtension(p).getBank();
- bool bwl = Configuration::getInstance().BankwiseLogic;
+ bool bwl = ccore.config.BankwiseLogic;
bool o = ccore.state->rowBufferStates->rowBufferIsOpen(b);
bool ac = ccore.state->rowBufferStates->allRowBuffersAreClosed();
bool pre = !!(bwl ? o : (!ac));
@@ -123,28 +120,28 @@ void RGR::doRefresh(tlm::tlm_generic_payload &p, sc_time t)
if (pre) {
if (!bwl) {
for (Bank b : ccore.getBanks()) {
- auto rgrb = Configuration::getInstance().getRGRBank(b.ID());
+ auto rgrb = ccore.config.getRGRBank(b.ID());
if (ccore.state->rowBufferStates->rowBufferIsOpen(b) && rgrb) {
ccore.scheduleRequest(Command::PreB, rps[Bank(b)]);
}
}
} else {
- if (Configuration::getInstance().getRGRBank(b.ID())) {
+ if (ccore.config.getRGRBank(b.ID())) {
ccore.scheduleRequest(Command::PreB, rps[b]);
}
}
}
- for (unsigned r = 0; r < (nr / nar); r += ri) {
+ for (unsigned r = 0; r < ((nr / m) / nar); r += ri) {
if (!!bwl) {
- if (Configuration::getInstance().getRGRBank(b.ID())) {
+ if (ccore.config.getRGRBank(b.ID())) {
ccore.scheduleRequest(Command::ActB, rps[b]);
ccore.scheduleRequest(Command::PreB, rps[b]);
}
DramExtension::getExtension(p).incrementRow();
} else {
for (Bank b : ccore.getBanks()) {
- if (Configuration::getInstance().getRGRBank(b.ID())) {
+ if (ccore.config.getRGRBank(b.ID())) {
ccore.scheduleRequest(Command::ActB, rps[b]);
ccore.scheduleRequest(Command::PreB, rps[b]);
}
@@ -158,7 +155,7 @@ void RGR::scheduleRefresh(tlm::tlm_generic_payload &p, sc_time t)
{
sc_time nrt;
Bank b = DramExtension::getExtension(p).getBank();
- auto bwl = Configuration::getInstance().BankwiseLogic;
+ auto bwl = ccore.config.BankwiseLogic;
bool preq = bwl ? ccore.hasPendingRequests(b) : ccore.hasPendingRequests();
bool canPostpone = preq && (arCmdCounter[b] < maxpostpone);
bool canPullIn = !preq && (arCmdCounter[b] < maxpullin);
@@ -176,7 +173,7 @@ void RGR::scheduleRefresh(tlm::tlm_generic_payload &p, sc_time t)
nrt = SC_ZERO_TIME;
} else {
doRefresh(p, t);
- nrt = timing.tREFI;
+ nrt = tREFIx;
nextState[b] = ST_REFRESH;
}
break;
@@ -199,7 +196,7 @@ void RGR::scheduleRefresh(tlm::tlm_generic_payload &p, sc_time t)
nrt = SC_ZERO_TIME;
} else {
nextState[b] = ST_SKIP;
- nrt = timing.tREFI;
+ nrt = tREFIx;
}
break;
case ST_POSTPONE:
@@ -213,7 +210,7 @@ void RGR::scheduleRefresh(tlm::tlm_generic_payload &p, sc_time t)
} else {
arCmdCounter[b]++;
nextState[b] = ST_POSTPONE;
- nrt = timing.tREFI;
+ nrt = tREFIx;
}
break;
case ST_BURST:
@@ -229,10 +226,10 @@ void RGR::scheduleRefresh(tlm::tlm_generic_payload &p, sc_time t)
break;
case ST_ALIGN:
if (previousState[b] == ST_PULLIN) {
- nrt = timing.tREFI;
+ nrt = tREFIx;
nextState[b] = ST_SKIP;
} else {
- nrt = timing.tREFI;
+ nrt = tREFIx;
nextState[b] = ST_REFRESH;
}
break;
@@ -252,7 +249,7 @@ void RGR::planNextRefresh(Bank b, sc_time t)
void RGR::reInitialize(Bank b, sc_time t)
{
nextPlannedRefreshs[b] = clkAlign(t, Alignment::DOWN);
- planNextRefresh(b, timing.tREFI);
+ planNextRefresh(b, tREFIx);
}
bool RGR::isInvalidated(tlm::tlm_generic_payload &p, sc_time t)
@@ -264,3 +261,4 @@ void RGR::printDebugMessage(std::string msg)
{
DebugManager::getInstance().printDebugMessage(this->name(), msg);
}
+
diff --git a/DRAMSys/library/src/controller/core/refresh/RGR.h b/DRAMSys/library/src/controller/core/refresh/RGR.h
index 3cf31b10..212a0a63 100644
--- a/DRAMSys/library/src/controller/core/refresh/RGR.h
+++ b/DRAMSys/library/src/controller/core/refresh/RGR.h
@@ -49,6 +49,7 @@ public:
void reInitialize(Bank bank, sc_time time) override;
bool isInvalidated(tlm::tlm_generic_payload &payload, sc_time time) override;
private:
+ sc_time tREFIx;
ControllerCore &ccore;
RefreshTiming &timing;
std::map rps;
diff --git a/DRAMSys/library/src/controller/core/refresh/RefreshManager.cpp b/DRAMSys/library/src/controller/core/refresh/RefreshManager.cpp
index 78688699..4bbef8e9 100644
--- a/DRAMSys/library/src/controller/core/refresh/RefreshManager.cpp
+++ b/DRAMSys/library/src/controller/core/refresh/RefreshManager.cpp
@@ -50,16 +50,18 @@ RefreshManager::RefreshManager(sc_module_name /*name*/,
timing(controller.config.memSpec.refreshTimings[Bank(0)]),
nextPlannedRefresh(SC_ZERO_TIME)
{
+ auto m = controllerCore.config.getRefMode();
+ tREFIx = timing.tREFI / m;
if (controllerCore.config.ControllerCoreEnableRefPostpone) {
- maxpostpone = controllerCore.config.ControllerCoreMaxPostponedARCmd;
+ maxpostpone = controllerCore.config.ControllerCoreMaxPostponedARCmd * m;
}
if (controllerCore.config.ControllerCoreEnableRefPullIn) {
- maxpullin = controllerCore.config.ControllerCoreMaxPulledInARCmd;
+ maxpullin = controllerCore.config.ControllerCoreMaxPulledInARCmd * m;
}
for (Bank bank : controller.getBanks()) {
setUpDummy(refreshPayloads[bank], bank);
}
- planNextRefresh(timing.tREFI);
+ planNextRefresh(tREFIx);
}
RefreshManager::~RefreshManager()
@@ -138,9 +140,8 @@ void RefreshManager::scheduleRefresh(tlm::tlm_generic_payload &payload
switch (currentState) {
case ST_REFRESH:
// Regular Refresh. It's possible to migrate from this to the flexible refresh states
-
- assert(arCmdCounter ==
- 0); // The arCmdCounter should always be equal to zero here
+ // The arCmdCounter should always be equal to zero here
+ assert(arCmdCounter == 0);
if (canPostpone) {
nextState = ST_POSTPONE;
@@ -150,7 +151,7 @@ void RefreshManager::scheduleRefresh(tlm::tlm_generic_payload &payload
nextRefTiming = SC_ZERO_TIME; // Attempt to burst pull-in
} else {
doRefresh(payload, time);
- nextRefTiming = timing.tREFI;
+ nextRefTiming = tREFIx;
nextState = ST_REFRESH;
}
break;
@@ -179,7 +180,7 @@ void RefreshManager::scheduleRefresh(tlm::tlm_generic_payload &payload
nextRefTiming = SC_ZERO_TIME;
} else {
nextState = ST_SKIP;
- nextRefTiming = timing.tREFI;
+ nextRefTiming = tREFIx;
}
break;
@@ -199,7 +200,7 @@ void RefreshManager::scheduleRefresh(tlm::tlm_generic_payload &payload
} else {
arCmdCounter++;
nextState = ST_POSTPONE;
- nextRefTiming = timing.tREFI;
+ nextRefTiming = tREFIx;
}
break;
@@ -208,7 +209,7 @@ void RefreshManager::scheduleRefresh(tlm::tlm_generic_payload &payload
arCmdCounter--;
doRefresh(payload, time);
- if (arCmdCounter == 0) { // All bursts issued, next state will align to tREFI
+ if (arCmdCounter == 0) { // All bursts issued, next state will align to tREFIx
nextState = ST_ALIGN;
nextRefTiming = SC_ZERO_TIME;
} else {
@@ -218,13 +219,13 @@ void RefreshManager::scheduleRefresh(tlm::tlm_generic_payload &payload
break;
case ST_ALIGN:
- // Align Refresh. Adjusting the timing so the next REF timing will be a in a time multiple of tREFI
+ // Align Refresh. Adjusting the timing so the next REF timing will be a in a time multiple of tREFIx
if (previousState == ST_PULLIN) {
- nextRefTiming = timing.tREFI - (timing.tRFC * (alignValue));
+ nextRefTiming = tREFIx - (timing.tRFC * (alignValue));
nextState = ST_SKIP;
} else {
- nextRefTiming = timing.tREFI - (timing.tRFC * (alignValue - 1));
+ nextRefTiming = tREFIx - (timing.tRFC * (alignValue - 1));
nextState = ST_REFRESH;
}
break;
@@ -247,7 +248,7 @@ void RefreshManager::planNextRefresh(sc_time nextRefTiming)
void RefreshManager::reInitialize(Bank /*bank*/, sc_time time)
{
nextPlannedRefresh = clkAlign(time, Alignment::DOWN);
- planNextRefresh(timing.tREFI);
+ planNextRefresh(tREFIx);
}
bool RefreshManager::isInvalidated(tlm::tlm_generic_payload &payload
diff --git a/DRAMSys/library/src/controller/core/refresh/RefreshManager.h b/DRAMSys/library/src/controller/core/refresh/RefreshManager.h
index 2ec5792d..858d50b6 100644
--- a/DRAMSys/library/src/controller/core/refresh/RefreshManager.h
+++ b/DRAMSys/library/src/controller/core/refresh/RefreshManager.h
@@ -59,6 +59,7 @@ private:
ControllerCore &controllerCore;
RefreshTiming &timing;
sc_time nextPlannedRefresh;
+ sc_time tREFIx;
std::map refreshPayloads;
unsigned int maxpostpone = 0;
unsigned int maxpullin = 0;
diff --git a/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.cpp b/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.cpp
index 76e69453..9e7bdd3f 100644
--- a/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.cpp
+++ b/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.cpp
@@ -45,12 +45,12 @@ RefreshManagerBankwise::RefreshManagerBankwise(sc_module_name,
ControllerCore &controller) : controllerCore(controller),
timing(controller.config.memSpec.refreshTimings[Bank(0)])
{
- if (controllerCore.config.ControllerCoreEnableRefPostpone) {
- maxpostpone = controllerCore.config.ControllerCoreMaxPostponedARCmd;
- }
- if (controllerCore.config.ControllerCoreEnableRefPullIn) {
- maxpullin = controllerCore.config.ControllerCoreMaxPulledInARCmd;
- }
+ auto m = controllerCore.config.getRefMode();
+ tREFIx = timing.tREFI / m;
+ if (controllerCore.config.ControllerCoreEnableRefPostpone)
+ maxpostpone = controllerCore.config.ControllerCoreMaxPostponedARCmd * m;
+ if (controllerCore.config.ControllerCoreEnableRefPullIn)
+ maxpullin = controllerCore.config.ControllerCoreMaxPulledInARCmd * m;
for (Bank bank : controller.getBanks()) {
nextPlannedRefreshs[bank] = SC_ZERO_TIME;
arCmdCounter[bank] = 0;
@@ -59,7 +59,7 @@ RefreshManagerBankwise::RefreshManagerBankwise(sc_module_name,
previousState[bank] = ST_REFRESH;
nextState[bank] = ST_REFRESH;
setUpDummy(refreshPayloads[bank], bank);
- planNextRefresh(bank, timing.tREFI);
+ planNextRefresh(bank, tREFIx);
}
}
@@ -134,7 +134,7 @@ void RefreshManagerBankwise::scheduleRefresh(tlm::tlm_generic_payload &payload,
nextRefTiming = SC_ZERO_TIME; // Attempt to burst pull-in
} else {
doRefresh(payload, time);
- nextRefTiming = timing.tREFI;
+ nextRefTiming = tREFIx;
nextState[bank] = ST_REFRESH;
}
break;
@@ -165,7 +165,7 @@ void RefreshManagerBankwise::scheduleRefresh(tlm::tlm_generic_payload &payload,
nextRefTiming = SC_ZERO_TIME;
} else {
nextState[bank] = ST_SKIP;
- nextRefTiming = timing.tREFI;
+ nextRefTiming = tREFIx;
}
break;
@@ -190,7 +190,7 @@ void RefreshManagerBankwise::scheduleRefresh(tlm::tlm_generic_payload &payload,
} else {
arCmdCounter[bank]++;
nextState[bank] = ST_POSTPONE;
- nextRefTiming = timing.tREFI;
+ nextRefTiming = tREFIx;
}
break;
@@ -201,7 +201,7 @@ void RefreshManagerBankwise::scheduleRefresh(tlm::tlm_generic_payload &payload,
arCmdCounter[bank]--;
doRefresh(payload, time);
if (arCmdCounter[bank] == 0) {
- // All bursts issued, next state will align to tREFI
+ // All bursts issued, next state will align to tREFIx
nextState[bank] = ST_ALIGN;
nextRefTiming = SC_ZERO_TIME;
} else {
@@ -212,13 +212,13 @@ void RefreshManagerBankwise::scheduleRefresh(tlm::tlm_generic_payload &payload,
case ST_ALIGN:
// Align Refresh. Adjusting the timing so the next REF timing will be
- // a in a time multiple of tREFI.
+ // a in a time multiple of tREFIx.
if (previousState[bank] == ST_PULLIN) {
- nextRefTiming = timing.tREFI - (timing.tRFC * (alignValue[bank]));
+ nextRefTiming = tREFIx - (timing.tRFC * (alignValue[bank]));
nextState[bank] = ST_SKIP;
} else {
- nextRefTiming = timing.tREFI - (timing.tRFC * (alignValue[bank] - 1));
+ nextRefTiming = tREFIx - (timing.tRFC * (alignValue[bank] - 1));
nextState[bank] = ST_REFRESH;
}
break;
@@ -241,7 +241,7 @@ void RefreshManagerBankwise::planNextRefresh(Bank bank, sc_time nextRefTiming)
void RefreshManagerBankwise::reInitialize(Bank bank, sc_time time)
{
nextPlannedRefreshs[bank] = clkAlign(time, Alignment::DOWN);
- planNextRefresh(bank, timing.tREFI);
+ planNextRefresh(bank, tREFIx);
}
bool RefreshManagerBankwise::isInvalidated(tlm::tlm_generic_payload &payload,
diff --git a/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.h b/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.h
index b5c2fc80..b7be78e4 100644
--- a/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.h
+++ b/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.h
@@ -59,6 +59,7 @@ public:
private:
ControllerCore &controllerCore;
RefreshTiming &timing;
+ sc_time tREFIx;
std::map refreshPayloads;
std::map nextPlannedRefreshs;
unsigned int maxpostpone = 0;
diff --git a/README.md b/README.md
index 73078ec6..ea30a2b2 100644
--- a/README.md
+++ b/README.md
@@ -689,6 +689,8 @@ Below, the sub-configurations are listed and explained.
+
+
@@ -762,6 +764,8 @@ Below, the sub-configurations are listed and explained.
- *ControllerCoreDisableRefresh* (boolean)
- "1": disables refreshes
- "0": normal operation (refreshes enabled)
+ - ControllerCoreRefMode (unsigned int)
+ - Refresh mode. 1: 1X, 2: 2X, 4: 4X
- *ControllerCoreForceMaxRefBurst* (boolean)
- "1": always postpone, resulting in a ControllerCoreMaxPostponedARCmd burst
- "0": normal operation
@@ -772,75 +776,75 @@ Below, the sub-configurations are listed and explained.
- "1": enables the pull-in refresh feature
- "0": normal operation
- *ControllerCoreMaxPostponedARCmd* (unsigned int)
- - Max AR commands to be postponed.
+ - Max AR commands to be postponed. Refresh mode affects this config (multiplier).
- *ControllerCoreMaxPulledInARCmd* (unsigned int)
- - Max AR commands to be pulled-in.
- - *ControllerCoreRowGranularRef* (boolean)
+ - Max AR commands to be pulled-in. Refresh mode affects this config (multiplier).
+ - *ControllerCoreRowGranularRef* (boolean)
- "1": enables row granular refresh feature (RGR)
- "0": normal operation
- - *ControllerCoreRowGranularRefNumAR* (unsigned int)
+ - *ControllerCoreRowGranularRefNumAR* (unsigned int)
- Number of AR commands to to be issued in a refresh period tREFI
- - *ControllerCoreRowGranularRefRowInc* (unsigned int)
+ - *ControllerCoreRowGranularRefRowInc* (unsigned int)
- Row increment for each AR command (selective refresh)
- - *ControllerCoreRowGranularRefB0* (boolean)
+ - *ControllerCoreRowGranularRefB0* (boolean)
- "1": RGR this bank
- "0": skip this bank
- - *ControllerCoreRowGranularRefB1* (boolean)
+ - *ControllerCoreRowGranularRefB1* (boolean)
- "1": RGR this bank
- "0": skip this bank
- - *ControllerCoreRowGranularRefB2* (boolean)
+ - *ControllerCoreRowGranularRefB2* (boolean)
- "1": RGR this bank
- "0": skip this bank
- - *ControllerCoreRowGranularRefB3* (boolean)
+ - *ControllerCoreRowGranularRefB3* (boolean)
- "1": RGR this bank
- "0": skip this bank
- - *ControllerCoreRowGranularRefB4* (boolean)
+ - *ControllerCoreRowGranularRefB4* (boolean)
- "1": RGR this bank
- "0": skip this bank
- - *ControllerCoreRowGranularRefB5* (boolean)
+ - *ControllerCoreRowGranularRefB5* (boolean)
- "1": RGR this bank
- "0": skip this bank
- - *ControllerCoreRowGranularRefB6* (boolean)
+ - *ControllerCoreRowGranularRefB6* (boolean)
- "1": RGR this bank
- "0": skip this bank
- - *ControllerCoreRowGranularRefB7* (boolean)
+ - *ControllerCoreRowGranularRefB7* (boolean)
- "1": RGR this bank
- "0": skip this bank
- - *ControllerCoreRowGranularRefB8* (boolean)
+ - *ControllerCoreRowGranularRefB8* (boolean)
- "1": RGR this bank
- "0": skip this bank
- - *ControllerCoreRowGranularRefB9* (boolean)
+ - *ControllerCoreRowGranularRefB9* (boolean)
- "1": RGR this bank
- "0": skip this bank
- - *ControllerCoreRowGranularRefB10* (boolean)
+ - *ControllerCoreRowGranularRefB10* (boolean)
- "1": RGR this bank
- "0": skip this bank
- - *ControllerCoreRowGranularRefB11* (boolean)
+ - *ControllerCoreRowGranularRefB11* (boolean)
- "1": RGR this bank
- "0": skip this bank
- - *ControllerCoreRowGranularRefB12* (boolean)
+ - *ControllerCoreRowGranularRefB12* (boolean)
- "1": RGR this bank
- "0": skip this bank
- - *ControllerCoreRowGranularRefB13* (boolean)
+ - *ControllerCoreRowGranularRefB13* (boolean)
- "1": RGR this bank
- "0": skip this bank
- - *ControllerCoreRowGranularRefB14* (boolean)
+ - *ControllerCoreRowGranularRefB14* (boolean)
- "1": RGR this bank
- "0": skip this bank
- - *ControllerCoreRowGranularRefB15* (boolean)
+ - *ControllerCoreRowGranularRefB15* (boolean)
- "1": RGR this bank
- "0": skip this bank
- - *ControllerCoreRowGranularRefRASBInClkCycles* (unsigned int)
+ - *ControllerCoreRowGranularRefRASBInClkCycles* (unsigned int)
- Timing can be changed to explore optimum row granular refresh (ORGR)
- - *ControllerCoreRowGranularRefRRDB_LInClkCycles* (unsigned int)
+ - *ControllerCoreRowGranularRefRRDB_LInClkCycles* (unsigned int)
- Timing can be changed to explore optimum row granular refresh (ORGR)
- - *ControllerCoreRowGranularRefRRDB_SInClkCycles* (unsigned int)
+ - *ControllerCoreRowGranularRefRRDB_SInClkCycles* (unsigned int)
- Timing can be changed to explore optimum row granular refresh (ORGR)
- - *ControllerCoreRowGranularRefRPBInClkCycles* (unsigned int)
+ - *ControllerCoreRowGranularRefRPBInClkCycles* (unsigned int)
- Timing can be changed to explore optimum row granular refresh (ORGR)
- - *ControllerCoreRowGranularRefRCBInClkCycles* (unsigned int)
+ - *ControllerCoreRowGranularRefRCBInClkCycles* (unsigned int)
- Timing can be changed to explore optimum row granular refresh (ORGR)
- - *ControllerCoreRowGranularRefFAWBInClkCycles* (unsigned int)
+ - *ControllerCoreRowGranularRefFAWBInClkCycles* (unsigned int)
- Timing can be changed to explore optimum row granular refresh (ORGR)
- **Flexible Refresh**