From 8ddf7e4312ede66cf857fd10d0c092588b9cc82b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=C3=89der=20F=2E=20Zulian?= <zulian@eit.uni-kl.de>
Date: Thu, 30 Aug 2018 15:15:01 +0200
Subject: [PATCH] New configuration files

---
 .../configs/simulator/rgrsimcfg-gem5-se.xml   | 18 +++++++++++++++++
 .../resources/simulations/rgrsim-gem5-se.xml  | 20 +++++++++++++++++++
 2 files changed, 38 insertions(+)
 create mode 100644 DRAMSys/library/resources/configs/simulator/rgrsimcfg-gem5-se.xml
 create mode 100644 DRAMSys/library/resources/simulations/rgrsim-gem5-se.xml

diff --git a/DRAMSys/library/resources/configs/simulator/rgrsimcfg-gem5-se.xml b/DRAMSys/library/resources/configs/simulator/rgrsimcfg-gem5-se.xml
new file mode 100644
index 00000000..9ec65640
--- /dev/null
+++ b/DRAMSys/library/resources/configs/simulator/rgrsimcfg-gem5-se.xml
@@ -0,0 +1,18 @@
+<simconfig>
+    <SimulationName value="rgr" />
+    <Debug value="0" />
+    <DatabaseRecording value="1" />
+    <PowerAnalysis value="1" />
+    <EnableWindowing value = "1" />
+    <WindowSize value="1000" />
+    <ThermalSimulation value="0"/>
+    <SimulationProgressBar value="1"/>
+    <NumberOfMemChannels value="1"/>
+    <NumberOfDevicesOnDIMM value="4"/>
+    <CheckTLM2Protocol value = "0" />
+    <AddressOffset value = "0" />
+    <ECCControllerMode value = "Disabled" />
+    <ErrorChipSeed value="42" />
+    <ErrorCSVFile value="" />
+    <StoreMode value="Store" />
+</simconfig>
diff --git a/DRAMSys/library/resources/simulations/rgrsim-gem5-se.xml b/DRAMSys/library/resources/simulations/rgrsim-gem5-se.xml
new file mode 100644
index 00000000..aad4a74a
--- /dev/null
+++ b/DRAMSys/library/resources/simulations/rgrsim-gem5-se.xml
@@ -0,0 +1,20 @@
+<simulation>
+    <!-- Simulation file identifier -->
+    <simulationid id="rgrsim-gem5-se"></simulationid>
+    <!-- Configuration for the DRAMSys Simulator -->
+    <simconfig src="rgrsimcfg-gem5-se.xml" />
+    <!-- Temperature Simulator Configuration -->
+    <thermalconfig src="config.xml" />
+    <!-- Memory Device Specification -->
+    <memspec src="rgrspec.xml"></memspec>
+    <!-- Addressmapping Configuration of the Memory Controller -->
+    <addressmapping src="rgram.xml"></addressmapping>
+    <!-- Memory Controller Configuration -->
+    <mcconfig src="rgrmccfg.xml"/>
+    <!-- <tracesetup id="no_refresh_fr_fcfs_nbw_b16_ddr4_8b_1x"> -->
+    <!--
+    <tracesetup id="rgrsetup">
+        <device clkMhz="1000">1_720x1280_64-Pixelgroesse_imb3_str1_scram_ddr4_8b_same_clock.stl</device>
+    </tracesetup>
+    -->
+</simulation>