From c28c996271c7c921f26fc285be9eaf145b0067cf Mon Sep 17 00:00:00 2001 From: Thanh Tran Date: Mon, 7 Nov 2016 17:25:59 +0100 Subject: [PATCH 1/5] Fix hardcoded memory size (issue #128) Recalculate memory size using #Banks, #Rows, and #Columns from memory specs. --- DRAMSys/simulator/src/simulation/Dram.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/DRAMSys/simulator/src/simulation/Dram.h b/DRAMSys/simulator/src/simulation/Dram.h index 7db71f78..85dfdf8a 100644 --- a/DRAMSys/simulator/src/simulation/Dram.h +++ b/DRAMSys/simulator/src/simulation/Dram.h @@ -94,8 +94,11 @@ struct Dram : sc_module SC_CTOR(Dram) : tSocket("socket") { - // FIXME: memory size - unsigned int size = 1024 * 1024 * 1024; + // calculate memory size + unsigned int banks = Configuration::getInstance().memSpec.NumberOfBanks; + unsigned int rows = Configuration::getInstance().memSpec.NumberOfRows; + unsigned int columns = Configuration::getInstance().memSpec.NumberOfColumns; + unsigned int size = banks * rows * columns; memory = (unsigned char *)mmap(NULL, size, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON | MAP_NORESERVE, -1, 0); tSocket.register_nb_transport_fw(this, &Dram::nb_transport_fw); From 701152e0afbf51547c4f96d1f5fc4a183661ce5e Mon Sep 17 00:00:00 2001 From: Thanh Tran Date: Tue, 8 Nov 2016 00:04:00 +0100 Subject: [PATCH 2/5] Recalculate memory size, that take into account of bus width & #chips on a DIMM --- DRAMSys/simulator/src/simulation/Dram.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/DRAMSys/simulator/src/simulation/Dram.h b/DRAMSys/simulator/src/simulation/Dram.h index 85dfdf8a..db47d6cf 100644 --- a/DRAMSys/simulator/src/simulation/Dram.h +++ b/DRAMSys/simulator/src/simulation/Dram.h @@ -66,6 +66,8 @@ using namespace Data; struct Dram : sc_module { unsigned int burstLength = Configuration::getInstance().memSpec.BurstLength; + // All DRAM chips on a DIMM operate in lockstep, + // which constituing aggregate data bus width = chip's bus width * # locksteep-operated chips unsigned int busWidth = Configuration::getInstance().memSpec.BusWidth * Configuration::getInstance().NumberOfDevicesOnDIMM; unsigned int bytesPerBurst = burstLength * (busWidth / 8); @@ -94,11 +96,11 @@ struct Dram : sc_module SC_CTOR(Dram) : tSocket("socket") { - // calculate memory size + // calculate memory size (in Bytes) unsigned int banks = Configuration::getInstance().memSpec.NumberOfBanks; unsigned int rows = Configuration::getInstance().memSpec.NumberOfRows; unsigned int columns = Configuration::getInstance().memSpec.NumberOfColumns; - unsigned int size = banks * rows * columns; + unsigned int size = banks * rows * columns * (busWidth / 8); memory = (unsigned char *)mmap(NULL, size, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON | MAP_NORESERVE, -1, 0); tSocket.register_nb_transport_fw(this, &Dram::nb_transport_fw); From 79b624a88b957d0ca847c3c927a8a98e47a208a3 Mon Sep 17 00:00:00 2001 From: Thanh Tran Date: Tue, 8 Nov 2016 15:46:39 +0100 Subject: [PATCH 3/5] Add assertion when parsing Number of Device on DIMM --- .../src/controller/core/configuration/Configuration.cpp | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/DRAMSys/simulator/src/controller/core/configuration/Configuration.cpp b/DRAMSys/simulator/src/controller/core/configuration/Configuration.cpp index 4eba236d..82ab0e7b 100644 --- a/DRAMSys/simulator/src/controller/core/configuration/Configuration.cpp +++ b/DRAMSys/simulator/src/controller/core/configuration/Configuration.cpp @@ -167,6 +167,10 @@ void Configuration::setParameter(std::string name, std::string value) else if(name == "SimulationProgressBar") SimulationProgressBar = string2bool(value); else if(name == "NumberOfDevicesOnDIMM") + if (string2int(value) < 1) { + SC_REPORT_FATAL("Configuration", ("Invalid value for parameter " + name + ". This parameter must be at least one.").c_str()); + throw; + } else NumberOfDevicesOnDIMM = string2int(value); else if(name == "CheckTLM2Protocol") CheckTLM2Protocol = string2bool(value); From ac8982aa39a8c797fdf76a3afd8b8e2c4633fd50 Mon Sep 17 00:00:00 2001 From: Thanh Tran Date: Tue, 8 Nov 2016 15:49:45 +0100 Subject: [PATCH 4/5] Rename the data bit width of one DRAM chip to more significant one --- .../controller/core/configuration/ConfigurationLoader.cpp | 6 +++--- .../simulator/src/controller/core/configuration/MemSpec.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/DRAMSys/simulator/src/controller/core/configuration/ConfigurationLoader.cpp b/DRAMSys/simulator/src/controller/core/configuration/ConfigurationLoader.cpp index 0b44528a..afa05291 100644 --- a/DRAMSys/simulator/src/controller/core/configuration/ConfigurationLoader.cpp +++ b/DRAMSys/simulator/src/controller/core/configuration/ConfigurationLoader.cpp @@ -170,7 +170,7 @@ void ConfigurationLoader::loadDDR3(Configuration& config, XMLElement* memspec) config.memSpec.DataRate = queryUIntParameter(architecture, "dataRate"); config.memSpec.NumberOfRows = queryUIntParameter(architecture, "nbrOfRows"); config.memSpec.NumberOfColumns = queryUIntParameter(architecture, "nbrOfColumns"); - config.memSpec.BusWidth = queryUIntParameter(architecture, "width"); + config.memSpec.bitWidth = queryUIntParameter(architecture, "width"); config.memSpec.DLL = true; config.memSpec.termination = true; @@ -244,7 +244,7 @@ void ConfigurationLoader::loadDDR4(Configuration& config, XMLElement* memspec) config.memSpec.DataRate = queryUIntParameter(architecture, "dataRate"); config.memSpec.NumberOfRows = queryUIntParameter(architecture, "nbrOfRows"); config.memSpec.NumberOfColumns = queryUIntParameter(architecture, "nbrOfColumns"); - config.memSpec.BusWidth = queryUIntParameter(architecture, "width"); + config.memSpec.bitWidth = queryUIntParameter(architecture, "width"); config.memSpec.DLL = true; config.memSpec.termination = true; @@ -317,7 +317,7 @@ void ConfigurationLoader::loadWideIO(Configuration& config, XMLElement* memspec) config.memSpec.DataRate = queryUIntParameter(architecture, "dataRate"); config.memSpec.NumberOfRows = queryUIntParameter(architecture, "nbrOfRows"); config.memSpec.NumberOfColumns = queryUIntParameter(architecture, "nbrOfColumns"); - config.memSpec.BusWidth = queryUIntParameter(architecture, "width"); + config.memSpec.bitWidth = queryUIntParameter(architecture, "width"); config.memSpec.DLL = false; config.memSpec.termination = false; diff --git a/DRAMSys/simulator/src/controller/core/configuration/MemSpec.h b/DRAMSys/simulator/src/controller/core/configuration/MemSpec.h index 31226abc..dc93bec2 100644 --- a/DRAMSys/simulator/src/controller/core/configuration/MemSpec.h +++ b/DRAMSys/simulator/src/controller/core/configuration/MemSpec.h @@ -82,7 +82,7 @@ struct MemSpec unsigned int DataRate; unsigned int NumberOfRows; unsigned int NumberOfColumns; - unsigned int BusWidth; + unsigned int bitWidth; bool DLL; bool termination; From 989d00204b909d1a93ade8bcde9821b6dddc8dbe Mon Sep 17 00:00:00 2001 From: Thanh Tran Date: Tue, 8 Nov 2016 15:54:59 +0100 Subject: [PATCH 5/5] Reimplement calculation of Channel Memory Size to more readable and safer way --- DRAMSys/simulator/src/simulation/Dram.h | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/DRAMSys/simulator/src/simulation/Dram.h b/DRAMSys/simulator/src/simulation/Dram.h index db47d6cf..e84edd52 100644 --- a/DRAMSys/simulator/src/simulation/Dram.h +++ b/DRAMSys/simulator/src/simulation/Dram.h @@ -68,8 +68,8 @@ struct Dram : sc_module unsigned int burstLength = Configuration::getInstance().memSpec.BurstLength; // All DRAM chips on a DIMM operate in lockstep, // which constituing aggregate data bus width = chip's bus width * # locksteep-operated chips - unsigned int busWidth = Configuration::getInstance().memSpec.BusWidth * Configuration::getInstance().NumberOfDevicesOnDIMM; - unsigned int bytesPerBurst = burstLength * (busWidth / 8); + unsigned int dataBusWidth = Configuration::getInstance().memSpec.bitWidth * Configuration::getInstance().NumberOfDevicesOnDIMM; + unsigned int bytesPerBurst = burstLength * (dataBusWidth / 8); // TLM Related: tlm_utils::simple_target_socket tSocket; @@ -97,11 +97,20 @@ struct Dram : sc_module SC_CTOR(Dram) : tSocket("socket") { // calculate memory size (in Bytes) + // 1. Get number of banks, rows, columns and data width in bits unsigned int banks = Configuration::getInstance().memSpec.NumberOfBanks; unsigned int rows = Configuration::getInstance().memSpec.NumberOfRows; unsigned int columns = Configuration::getInstance().memSpec.NumberOfColumns; - unsigned int size = banks * rows * columns * (busWidth / 8); - memory = (unsigned char *)mmap(NULL, size, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON | MAP_NORESERVE, -1, 0); + unsigned int bitWidth = Configuration::getInstance().memSpec.bitWidth; + // 2. Calculate size of one DRAM chip in bits + unsigned int chipBitSize = banks * rows * columns * bitWidth; + // 3. Calculate size of one DRAM chip in bytes + unsigned int chipSize = chipBitSize / 8; + // 4. Total memory size in Bytes of one DIMM (with only support of 1 rank on a DIMM) + unsigned int memorySize = chipSize * Configuration::getInstance().NumberOfDevicesOnDIMM; + + // allocate and model storage of one DRAM channel using memory map + memory = (unsigned char *)mmap(NULL, memorySize, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON | MAP_NORESERVE, -1, 0); tSocket.register_nb_transport_fw(this, &Dram::nb_transport_fw); tSocket.register_transport_dbg(this,&Dram::transport_dbg); @@ -117,7 +126,7 @@ struct Dram : sc_module memArchSpec.nbrOfBanks = Configuration::getInstance().memSpec.NumberOfBanks; memArchSpec.nbrOfColumns = Configuration::getInstance().memSpec.NumberOfColumns; memArchSpec.nbrOfRanks = Configuration::getInstance().memSpec.NumberOfRanks; - memArchSpec.width = Configuration::getInstance().memSpec.BusWidth; + memArchSpec.width = Configuration::getInstance().memSpec.bitWidth; memArchSpec.nbrOfBankGroups = Configuration::getInstance().memSpec.NumberOfBankGroups; memArchSpec.twoVoltageDomains = (Configuration::getInstance().memSpec.vDD2 == 0 ? false : true); memArchSpec.dll = Configuration::getInstance().memSpec.DLL; @@ -239,7 +248,7 @@ struct Dram : sc_module double bandwidth = (activeTime/(endTime-startTime)*100); double bandwidth_IDLE = ((activeTime)/(endTime-startTime-idleTime)*100); // | clk in Mhz e.g. 800 [MHz] | * | DataRate e.g. 2 | * | BusWidth e.g. 8 | * | Number of devices on a DIMM e.g. 8 | / | 1024 | - double maxBandwidth = ( (1000000/Configuration::getInstance().memSpec.clk.to_double()) * Configuration::getInstance().memSpec.DataRate * Configuration::getInstance().memSpec.BusWidth * Configuration::getInstance().NumberOfDevicesOnDIMM ) / ( 1024 ); + double maxBandwidth = ( (1000000/Configuration::getInstance().memSpec.clk.to_double()) * Configuration::getInstance().memSpec.DataRate * Configuration::getInstance().memSpec.bitWidth * Configuration::getInstance().NumberOfDevicesOnDIMM ) / ( 1024 ); cout << name() << string("\tTotal Time: \t") <<(endTime-startTime).to_string() << endl; //cout << name() << string("\tTotal IDLE: \t") <