diff --git a/DRAMSys/simulator/src/controller/core/configuration/Configuration.cpp b/DRAMSys/simulator/src/controller/core/configuration/Configuration.cpp index 4eba236d..82ab0e7b 100644 --- a/DRAMSys/simulator/src/controller/core/configuration/Configuration.cpp +++ b/DRAMSys/simulator/src/controller/core/configuration/Configuration.cpp @@ -167,6 +167,10 @@ void Configuration::setParameter(std::string name, std::string value) else if(name == "SimulationProgressBar") SimulationProgressBar = string2bool(value); else if(name == "NumberOfDevicesOnDIMM") + if (string2int(value) < 1) { + SC_REPORT_FATAL("Configuration", ("Invalid value for parameter " + name + ". This parameter must be at least one.").c_str()); + throw; + } else NumberOfDevicesOnDIMM = string2int(value); else if(name == "CheckTLM2Protocol") CheckTLM2Protocol = string2bool(value); diff --git a/DRAMSys/simulator/src/controller/core/configuration/ConfigurationLoader.cpp b/DRAMSys/simulator/src/controller/core/configuration/ConfigurationLoader.cpp index 0b44528a..afa05291 100644 --- a/DRAMSys/simulator/src/controller/core/configuration/ConfigurationLoader.cpp +++ b/DRAMSys/simulator/src/controller/core/configuration/ConfigurationLoader.cpp @@ -170,7 +170,7 @@ void ConfigurationLoader::loadDDR3(Configuration& config, XMLElement* memspec) config.memSpec.DataRate = queryUIntParameter(architecture, "dataRate"); config.memSpec.NumberOfRows = queryUIntParameter(architecture, "nbrOfRows"); config.memSpec.NumberOfColumns = queryUIntParameter(architecture, "nbrOfColumns"); - config.memSpec.BusWidth = queryUIntParameter(architecture, "width"); + config.memSpec.bitWidth = queryUIntParameter(architecture, "width"); config.memSpec.DLL = true; config.memSpec.termination = true; @@ -244,7 +244,7 @@ void ConfigurationLoader::loadDDR4(Configuration& config, XMLElement* memspec) config.memSpec.DataRate = queryUIntParameter(architecture, "dataRate"); config.memSpec.NumberOfRows = queryUIntParameter(architecture, "nbrOfRows"); config.memSpec.NumberOfColumns = queryUIntParameter(architecture, "nbrOfColumns"); - config.memSpec.BusWidth = queryUIntParameter(architecture, "width"); + config.memSpec.bitWidth = queryUIntParameter(architecture, "width"); config.memSpec.DLL = true; config.memSpec.termination = true; @@ -317,7 +317,7 @@ void ConfigurationLoader::loadWideIO(Configuration& config, XMLElement* memspec) config.memSpec.DataRate = queryUIntParameter(architecture, "dataRate"); config.memSpec.NumberOfRows = queryUIntParameter(architecture, "nbrOfRows"); config.memSpec.NumberOfColumns = queryUIntParameter(architecture, "nbrOfColumns"); - config.memSpec.BusWidth = queryUIntParameter(architecture, "width"); + config.memSpec.bitWidth = queryUIntParameter(architecture, "width"); config.memSpec.DLL = false; config.memSpec.termination = false; diff --git a/DRAMSys/simulator/src/controller/core/configuration/MemSpec.h b/DRAMSys/simulator/src/controller/core/configuration/MemSpec.h index 31226abc..dc93bec2 100644 --- a/DRAMSys/simulator/src/controller/core/configuration/MemSpec.h +++ b/DRAMSys/simulator/src/controller/core/configuration/MemSpec.h @@ -82,7 +82,7 @@ struct MemSpec unsigned int DataRate; unsigned int NumberOfRows; unsigned int NumberOfColumns; - unsigned int BusWidth; + unsigned int bitWidth; bool DLL; bool termination; diff --git a/DRAMSys/simulator/src/simulation/Dram.h b/DRAMSys/simulator/src/simulation/Dram.h index 7db71f78..e84edd52 100644 --- a/DRAMSys/simulator/src/simulation/Dram.h +++ b/DRAMSys/simulator/src/simulation/Dram.h @@ -66,8 +66,10 @@ using namespace Data; struct Dram : sc_module { unsigned int burstLength = Configuration::getInstance().memSpec.BurstLength; - unsigned int busWidth = Configuration::getInstance().memSpec.BusWidth * Configuration::getInstance().NumberOfDevicesOnDIMM; - unsigned int bytesPerBurst = burstLength * (busWidth / 8); + // All DRAM chips on a DIMM operate in lockstep, + // which constituing aggregate data bus width = chip's bus width * # locksteep-operated chips + unsigned int dataBusWidth = Configuration::getInstance().memSpec.bitWidth * Configuration::getInstance().NumberOfDevicesOnDIMM; + unsigned int bytesPerBurst = burstLength * (dataBusWidth / 8); // TLM Related: tlm_utils::simple_target_socket tSocket; @@ -94,9 +96,21 @@ struct Dram : sc_module SC_CTOR(Dram) : tSocket("socket") { - // FIXME: memory size - unsigned int size = 1024 * 1024 * 1024; - memory = (unsigned char *)mmap(NULL, size, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON | MAP_NORESERVE, -1, 0); + // calculate memory size (in Bytes) + // 1. Get number of banks, rows, columns and data width in bits + unsigned int banks = Configuration::getInstance().memSpec.NumberOfBanks; + unsigned int rows = Configuration::getInstance().memSpec.NumberOfRows; + unsigned int columns = Configuration::getInstance().memSpec.NumberOfColumns; + unsigned int bitWidth = Configuration::getInstance().memSpec.bitWidth; + // 2. Calculate size of one DRAM chip in bits + unsigned int chipBitSize = banks * rows * columns * bitWidth; + // 3. Calculate size of one DRAM chip in bytes + unsigned int chipSize = chipBitSize / 8; + // 4. Total memory size in Bytes of one DIMM (with only support of 1 rank on a DIMM) + unsigned int memorySize = chipSize * Configuration::getInstance().NumberOfDevicesOnDIMM; + + // allocate and model storage of one DRAM channel using memory map + memory = (unsigned char *)mmap(NULL, memorySize, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON | MAP_NORESERVE, -1, 0); tSocket.register_nb_transport_fw(this, &Dram::nb_transport_fw); tSocket.register_transport_dbg(this,&Dram::transport_dbg); @@ -112,7 +126,7 @@ struct Dram : sc_module memArchSpec.nbrOfBanks = Configuration::getInstance().memSpec.NumberOfBanks; memArchSpec.nbrOfColumns = Configuration::getInstance().memSpec.NumberOfColumns; memArchSpec.nbrOfRanks = Configuration::getInstance().memSpec.NumberOfRanks; - memArchSpec.width = Configuration::getInstance().memSpec.BusWidth; + memArchSpec.width = Configuration::getInstance().memSpec.bitWidth; memArchSpec.nbrOfBankGroups = Configuration::getInstance().memSpec.NumberOfBankGroups; memArchSpec.twoVoltageDomains = (Configuration::getInstance().memSpec.vDD2 == 0 ? false : true); memArchSpec.dll = Configuration::getInstance().memSpec.DLL; @@ -234,7 +248,7 @@ struct Dram : sc_module double bandwidth = (activeTime/(endTime-startTime)*100); double bandwidth_IDLE = ((activeTime)/(endTime-startTime-idleTime)*100); // | clk in Mhz e.g. 800 [MHz] | * | DataRate e.g. 2 | * | BusWidth e.g. 8 | * | Number of devices on a DIMM e.g. 8 | / | 1024 | - double maxBandwidth = ( (1000000/Configuration::getInstance().memSpec.clk.to_double()) * Configuration::getInstance().memSpec.DataRate * Configuration::getInstance().memSpec.BusWidth * Configuration::getInstance().NumberOfDevicesOnDIMM ) / ( 1024 ); + double maxBandwidth = ( (1000000/Configuration::getInstance().memSpec.clk.to_double()) * Configuration::getInstance().memSpec.DataRate * Configuration::getInstance().memSpec.bitWidth * Configuration::getInstance().NumberOfDevicesOnDIMM ) / ( 1024 ); cout << name() << string("\tTotal Time: \t") <<(endTime-startTime).to_string() << endl; //cout << name() << string("\tTotal IDLE: \t") <