From 8aae7fbed345043c37e8d4a4b0742d11c2605a9b Mon Sep 17 00:00:00 2001
From: Matthias Jung <jungma@eit.uni-kl.de>
Date: Sun, 2 Aug 2015 13:51:29 +0200
Subject: [PATCH] each bank has its own error model

---
 DRAMSys/dramSys/src/error/errormodel.cpp | 22 +++++++++++++++---
 DRAMSys/dramSys/src/error/errormodel.h   |  2 +-
 DRAMSys/dramSys/src/simulation/Dram.h    | 29 +++++++++++++-----------
 3 files changed, 36 insertions(+), 17 deletions(-)

diff --git a/DRAMSys/dramSys/src/error/errormodel.cpp b/DRAMSys/dramSys/src/error/errormodel.cpp
index eeb312c1..3097ae4a 100644
--- a/DRAMSys/dramSys/src/error/errormodel.cpp
+++ b/DRAMSys/dramSys/src/error/errormodel.cpp
@@ -38,7 +38,7 @@
 #include <chrono>
 #include <bitset>
 
-errorModel::errorModel(const char * name)
+errorModel::errorModel()
 {
     // Get Configuration parameters:
     busWidth = Configuration::getInstance().Buswidth;
@@ -55,13 +55,19 @@ errorModel::errorModel(const char * name)
         lastRowAccess[i] = SC_ZERO_TIME;
     }
 
-    // Set name of parent component
-    this->name = name;
+    // The name is set when the context is clear.
+    name = "";
 
     // Parse data input:
     parseInputData();
     prepareWeakCells();
 
+    // Initialize context variables:
+    myChannel = -1;
+    myRank = -1;
+    myBankgroup = -1;
+    myBank = -1;
+
     // Test 1:
     // If you want to test the function that get the number
     // of bit errors for a given temperature and time
@@ -114,6 +120,14 @@ errorModel::~errorModel()
 
     // Clean list of weak cells:
     delete [] weakCells;
+
+    // If an access happened to a bank the numner of errors should be shown:
+    if(myChannel != -1 && myBank != -1 && myBankgroup != -1 && myRank != -1 )
+    {
+        std::cout << name
+                  << ": Number of Retention Error Events = " << numberOfBitErrorEvents
+                  << std::endl;
+    }
 }
 
 void errorModel::store(tlm::tlm_generic_payload &trans)
@@ -683,5 +697,7 @@ void errorModel::setContext(DecodedAddress addr)
         myBank = addr.bank;
         myBankgroup = addr.bankgroup;
         myRank = addr.rank;
+
+        name = "Channel_" + std::to_string(myChannel) + "_Bank_" + std::to_string(myBank);
     }
 }
diff --git a/DRAMSys/dramSys/src/error/errormodel.h b/DRAMSys/dramSys/src/error/errormodel.h
index 2a729eb8..08fc7e6a 100644
--- a/DRAMSys/dramSys/src/error/errormodel.h
+++ b/DRAMSys/dramSys/src/error/errormodel.h
@@ -43,7 +43,7 @@
 class errorModel
 {
   public:
-    errorModel(const char * name);
+    errorModel();
     ~errorModel();
 
     // Access Methods:
diff --git a/DRAMSys/dramSys/src/simulation/Dram.h b/DRAMSys/dramSys/src/simulation/Dram.h
index dd01065b..1c0b3979 100644
--- a/DRAMSys/dramSys/src/simulation/Dram.h
+++ b/DRAMSys/dramSys/src/simulation/Dram.h
@@ -69,7 +69,7 @@ struct Dram : sc_module
 
     // Error Model related:
     ErrorStorageMode ErrorStoreMode = Configuration::getInstance().ErrorStoreMode;
-    errorModel ememory = errorModel(name());
+    errorModel * ememory;
 
     // Data Storage:
     map< unsigned long int, unsigned char[BUSWIDTH/2] > memory;
@@ -165,6 +165,10 @@ struct Dram : sc_module
         }
 
         printDebugMessage(string("ErrorStorageMode: ") + EnumToString(ErrorStoreMode));
+        if(ErrorStoreMode == ErrorStorageMode::ErrorModel)
+        {
+            ememory = new errorModel[Configuration::getInstance().memSpec.NumberOfBanks];
+        }
     }
 
     ~Dram()
@@ -176,10 +180,9 @@ struct Dram : sc_module
             cout << name() << string("\tTotal Energy: \t") + to_string(DRAMPower->getEnergy().total_energy) << endl;
             cout << name() << string("\tAverage Power: \t") + to_string(DRAMPower->getPower().average_power) << endl;
         }
-        if(ErrorStoreMode == ErrorStorageMode::ErrorModel)
-        {
-            //cout << "BIT_ERRORS Bank: " <<b <<"="<< fmemory[b].BIT_ERR << endl;
-        }
+
+        // Clean up:
+        delete [] ememory;
         //std::cout << "Simulated Memory Size: " << memory.size() << endl; // TODO Aufrauemen
     }
 
@@ -213,7 +216,7 @@ struct Dram : sc_module
 
             if (ErrorStoreMode == ErrorStorageMode::ErrorModel)
             {
-                ememory.activate(row);
+                ememory[bank].activate(row);
             }
         }
         else if (phase == BEGIN_WR)
@@ -231,7 +234,7 @@ struct Dram : sc_module
             }
             else // == 2 Use Storage with Error Model
             {
-                ememory.store(payload);
+                ememory[bank].store(payload);
             }
             sendToController(payload, END_WR, delay +  getExecutionTime(Command::Write, payload));
         }
@@ -253,7 +256,7 @@ struct Dram : sc_module
             }
             else if(ErrorStoreMode == ErrorStorageMode::ErrorModel)// use ErrorStorageMode with errormodel
             {
-                ememory.load(payload);
+                ememory[bank].load(payload);
             }
 
             sendToController(payload, END_RD, delay +  getExecutionTime(Command::Read, payload));
@@ -273,7 +276,7 @@ struct Dram : sc_module
             }
             else // == 2 Use Storage with Error Model
             {
-                ememory.store(payload);
+                ememory[bank].store(payload);
             }
             sendToController(payload, END_WRA, delay +  getExecutionTime(Command::WriteA, payload));
         }
@@ -295,7 +298,7 @@ struct Dram : sc_module
             }
             else if(ErrorStoreMode == ErrorStorageMode::ErrorModel)// use ErrorStorageMode with errormodel
             {
-                ememory.load(payload);
+                ememory[bank].load(payload);
             }
 
             sendToController(payload, END_RDA, delay +  getExecutionTime(Command::ReadA, payload));
@@ -308,7 +311,7 @@ struct Dram : sc_module
 
             if (ErrorStoreMode == ErrorStorageMode::ErrorModel)
             {
-                ememory.refresh(row);
+                ememory[bank].refresh(row);
             }
         }
 
@@ -397,7 +400,7 @@ struct Dram : sc_module
                 }
                 else
                 {
-                    ememory.load(trans);
+                    ememory[bank].load(trans);
                 }
             }
             else if ( cmd == tlm::TLM_WRITE_COMMAND )
@@ -408,7 +411,7 @@ struct Dram : sc_module
                 }
                 else
                 {
-                    ememory.store(trans);
+                    ememory[bank].store(trans);
                 }
             }
             return len;