From 844eaa390a8e98518e10318cdb0ddfb949426fd5 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Wed, 27 Apr 2022 11:13:35 +0200 Subject: [PATCH] Integrate new extensions. --- DRAMSys/library/src/common/TlmRecorder.cpp | 50 +-- DRAMSys/library/src/common/TlmRecorder.h | 10 +- DRAMSys/library/src/common/dramExtensions.cpp | 307 +++++------------- DRAMSys/library/src/common/dramExtensions.h | 103 ++---- DRAMSys/library/src/common/utils.cpp | 5 +- .../src/configuration/memspec/MemSpec.cpp | 1 + .../src/configuration/memspec/MemSpec.h | 1 + .../src/configuration/memspec/MemSpecDDR5.cpp | 10 +- .../library/src/controller/BankMachine.cpp | 16 +- DRAMSys/library/src/controller/Controller.cpp | 29 +- DRAMSys/library/src/controller/Controller.h | 1 + .../src/controller/ControllerRecordable.cpp | 18 +- .../src/controller/checker/CheckerDDR3.cpp | 12 +- .../src/controller/checker/CheckerDDR4.cpp | 16 +- .../src/controller/checker/CheckerDDR5.cpp | 18 +- .../src/controller/checker/CheckerGDDR5.cpp | 16 +- .../src/controller/checker/CheckerGDDR5X.cpp | 16 +- .../src/controller/checker/CheckerGDDR6.cpp | 16 +- .../src/controller/checker/CheckerHBM2.cpp | 16 +- .../src/controller/checker/CheckerLPDDR4.cpp | 12 +- .../src/controller/checker/CheckerLPDDR5.cpp | 18 +- .../src/controller/checker/CheckerSTTMRAM.cpp | 12 +- .../src/controller/checker/CheckerWideIO.cpp | 12 +- .../src/controller/checker/CheckerWideIO2.cpp | 12 +- .../src/controller/cmdmux/CmdMuxOldest.cpp | 8 +- .../src/controller/cmdmux/CmdMuxStrict.cpp | 8 +- .../controller/respqueue/RespQueueReorder.cpp | 2 +- .../scheduler/BufferCounterBankwise.cpp | 4 +- .../controller/scheduler/SchedulerFifo.cpp | 6 +- .../controller/scheduler/SchedulerFrFcfs.cpp | 8 +- .../scheduler/SchedulerFrFcfsGrp.cpp | 8 +- .../scheduler/SchedulerGrpFrFcfs.cpp | 18 +- .../scheduler/SchedulerGrpFrFcfsWm.cpp | 14 +- DRAMSys/library/src/error/errormodel.cpp | 23 +- DRAMSys/library/src/simulation/Arbiter.cpp | 50 ++- DRAMSys/library/src/simulation/Arbiter.h | 2 +- DRAMSys/library/src/simulation/dram/Dram.cpp | 2 +- .../src/simulation/dram/DramRecordable.cpp | 12 +- .../src/simulation/dram/DramWideIO.cpp | 8 +- 39 files changed, 358 insertions(+), 542 deletions(-) diff --git a/DRAMSys/library/src/common/TlmRecorder.cpp b/DRAMSys/library/src/common/TlmRecorder.cpp index dd22ec4a..15ffc4da 100644 --- a/DRAMSys/library/src/common/TlmRecorder.cpp +++ b/DRAMSys/library/src/common/TlmRecorder.cpp @@ -123,16 +123,16 @@ void TlmRecorder::recordPhase(tlm_generic_payload &trans, if (phase == END_REQ || phase == END_RESP || phase >= END_PDNA) { - assert(getPhaseName(phase).substr(4) == currentTransactionsInSystem[&trans].recordedPhases.back().name); - currentTransactionsInSystem[&trans].recordedPhases.back().interval.end = time; + assert(getPhaseName(phase).substr(4) == currentTransactionsInSystem.at(&trans).recordedPhases.back().name); + currentTransactionsInSystem.at(&trans).recordedPhases.back().interval.end = time; } else { std::string phaseName = getPhaseName(phase).substr(6); // remove "BEGIN_" - currentTransactionsInSystem[&trans].recordedPhases.emplace_back(phaseName, time); + currentTransactionsInSystem.at(&trans).recordedPhases.emplace_back(phaseName, time); } - if (currentTransactionsInSystem[&trans].cmd == 'X') + if (currentTransactionsInSystem.at(&trans).cmd == 'X') { if (phase == END_REFAB || phase == END_RFMAB @@ -161,8 +161,8 @@ void TlmRecorder::updateDataStrobe(const sc_time &begin, const sc_time &end, tlm_generic_payload &trans) { assert(currentTransactionsInSystem.count(&trans) != 0); - currentTransactionsInSystem[&trans].timeOnDataStrobe.start = begin; - currentTransactionsInSystem[&trans].timeOnDataStrobe.end = end; + currentTransactionsInSystem.at(&trans).timeOnDataStrobe.start = begin; + currentTransactionsInSystem.at(&trans).timeOnDataStrobe.end = end; } @@ -177,21 +177,23 @@ void TlmRecorder::recordDebugMessage(const std::string &message, const sc_time & void TlmRecorder::introduceTransactionSystem(tlm_generic_payload &trans) { totalNumTransactions++; - currentTransactionsInSystem[&trans].id = totalNumTransactions; + currentTransactionsInSystem.insert({&trans, Transaction(totalNumTransactions, + ArbiterExtension::getExtension(trans), ControllerExtension::getExtension(trans))}); + currentTransactionsInSystem.at(&trans).id = totalNumTransactions; tlm_command command = trans.get_command(); if (command == TLM_READ_COMMAND) - currentTransactionsInSystem[&trans].cmd = 'R'; + currentTransactionsInSystem.at(&trans).cmd = 'R'; else if (command == TLM_WRITE_COMMAND) - currentTransactionsInSystem[&trans].cmd = 'W'; + currentTransactionsInSystem.at(&trans).cmd = 'W'; else - currentTransactionsInSystem[&trans].cmd = 'X'; - currentTransactionsInSystem[&trans].address = trans.get_address(); - currentTransactionsInSystem[&trans].burstLength = DramExtension::getBurstLength(trans); - currentTransactionsInSystem[&trans].dramExtension = DramExtension::getExtension(trans); - currentTransactionsInSystem[&trans].timeOfGeneration = GenerationExtension::getTimeOfGeneration(trans); + currentTransactionsInSystem.at(&trans).cmd = 'X'; + currentTransactionsInSystem.at(&trans).address = trans.get_address(); + currentTransactionsInSystem.at(&trans).burstLength = ControllerExtension::getBurstLength(trans); + currentTransactionsInSystem.at(&trans).controllerExtension = ControllerExtension::getExtension(trans); + currentTransactionsInSystem.at(&trans).timeOfGeneration = ArbiterExtension::getTimeOfGeneration(trans); PRINTDEBUGMESSAGE(name, "New transaction #" + std::to_string(totalNumTransactions) + " generation time " + - currentTransactionsInSystem[&trans].timeOfGeneration.to_string()); + currentTransactionsInSystem.at(&trans).timeOfGeneration.to_string()); } void TlmRecorder::removeTransactionFromSystem(tlm_generic_payload &trans) @@ -199,9 +201,9 @@ void TlmRecorder::removeTransactionFromSystem(tlm_generic_payload &trans) assert(currentTransactionsInSystem.count(&trans) != 0); PRINTDEBUGMESSAGE(name, "Removing transaction #" + - std::to_string(currentTransactionsInSystem[&trans].id)); + std::to_string(currentTransactionsInSystem.at(&trans).id)); - Transaction &recordingData = currentTransactionsInSystem[&trans]; + Transaction &recordingData = currentTransactionsInSystem.at(&trans); currentDataBuffer->push_back(recordingData); currentTransactionsInSystem.erase(&trans); @@ -413,19 +415,19 @@ void TlmRecorder::insertTransactionInDB(Transaction &recordingData) sqlite3_bind_int64(insertTransactionStatement, 3, static_cast(recordingData.address)); sqlite3_bind_int(insertTransactionStatement, 4, static_cast(recordingData.burstLength)); sqlite3_bind_int(insertTransactionStatement, 5, - static_cast(recordingData.dramExtension.getThread().ID())); + static_cast(recordingData.arbiterExtension.getThread().ID())); sqlite3_bind_int(insertTransactionStatement, 6, - static_cast(recordingData.dramExtension.getChannel().ID())); + static_cast(recordingData.arbiterExtension.getChannel().ID())); sqlite3_bind_int(insertTransactionStatement, 7, - static_cast(recordingData.dramExtension.getRank().ID())); + static_cast(recordingData.controllerExtension.getRank().ID())); sqlite3_bind_int(insertTransactionStatement, 8, - static_cast(recordingData.dramExtension.getBankGroup().ID())); + static_cast(recordingData.controllerExtension.getBankGroup().ID())); sqlite3_bind_int(insertTransactionStatement, 9, - static_cast(recordingData.dramExtension.getBank().ID())); + static_cast(recordingData.controllerExtension.getBank().ID())); sqlite3_bind_int(insertTransactionStatement, 10, - static_cast(recordingData.dramExtension.getRow().ID())); + static_cast(recordingData.controllerExtension.getRow().ID())); sqlite3_bind_int(insertTransactionStatement, 11, - static_cast(recordingData.dramExtension.getColumn().ID())); + static_cast(recordingData.controllerExtension.getColumn().ID())); sqlite3_bind_int64(insertTransactionStatement, 12, static_cast(recordingData.timeOnDataStrobe.start.value())); sqlite3_bind_int64(insertTransactionStatement, 13, diff --git a/DRAMSys/library/src/common/TlmRecorder.h b/DRAMSys/library/src/common/TlmRecorder.h index 1b63b41d..f531efd5 100644 --- a/DRAMSys/library/src/common/TlmRecorder.h +++ b/DRAMSys/library/src/common/TlmRecorder.h @@ -43,6 +43,7 @@ #include #include +#include #include #include @@ -89,14 +90,17 @@ private: struct Transaction { - Transaction() = default; - explicit Transaction(uint64_t id) : id(id) {} + //Transaction() = default; + Transaction(uint64_t id, ArbiterExtension arbiterExtension, ControllerExtension controllerExtension) : + id(id), arbiterExtension(std::move(arbiterExtension)), + controllerExtension(std::move(controllerExtension)) {} uint64_t id = 0; uint64_t address = 0; unsigned int burstLength = 0; char cmd = 'X'; - DramExtension dramExtension; + ArbiterExtension arbiterExtension; + ControllerExtension controllerExtension; sc_core::sc_time timeOfGeneration; TimeInterval timeOnDataStrobe; diff --git a/DRAMSys/library/src/common/dramExtensions.cpp b/DRAMSys/library/src/common/dramExtensions.cpp index bc4e45b2..3c486087 100644 --- a/DRAMSys/library/src/common/dramExtensions.cpp +++ b/DRAMSys/library/src/common/dramExtensions.cpp @@ -46,7 +46,7 @@ ArbiterExtension::ArbiterExtension(Thread thread, Channel channel, uint64_t thre thread(thread), channel(channel), threadPayloadID(threadPayloadID), timeOfGeneration(timeOfGeneration) {} -void ArbiterExtension::setExtension(tlm::tlm_generic_payload& trans, Thread thread, Channel channel) +void ArbiterExtension::setAutoExtension(tlm::tlm_generic_payload& trans, Thread thread, Channel channel) { auto* extension = trans.get_extension(); @@ -64,6 +64,14 @@ void ArbiterExtension::setExtension(tlm::tlm_generic_payload& trans, Thread thre } } +void ArbiterExtension::setExtension(tlm::tlm_generic_payload& trans, Thread thread, Channel channel, + uint64_t threadPayloadID, const sc_core::sc_time& timeOfGeneration) +{ + assert(trans.get_extension() == nullptr); + auto* extension = new ArbiterExtension(thread, channel, threadPayloadID, timeOfGeneration); + trans.set_extension(extension); +} + void ArbiterExtension::setIDAndTimeOfGeneration(tlm::tlm_generic_payload& trans, uint64_t threadPayloadID, const sc_core::sc_time& timeOfGeneration) { @@ -88,6 +96,31 @@ void ArbiterExtension::copy_from(const tlm_extension_base& ext) timeOfGeneration = cpyFrom.timeOfGeneration; } +Thread ArbiterExtension::getThread() const +{ + return thread; +} + +Channel ArbiterExtension::getChannel() const +{ + return channel; +} + +uint64_t ArbiterExtension::getThreadPayloadID() const +{ + return threadPayloadID; +} + +sc_core::sc_time ArbiterExtension::getTimeOfGeneration() const +{ + return timeOfGeneration; +} + +const ArbiterExtension& ArbiterExtension::getExtension(const tlm::tlm_generic_payload& trans) +{ + return *trans.get_extension(); +} + Thread ArbiterExtension::getThread(const tlm::tlm_generic_payload& trans) { return trans.get_extension()->thread; @@ -114,7 +147,7 @@ ControllerExtension::ControllerExtension(uint64_t channelPayloadID, Rank rank, B burstLength(burstLength) {} -void ControllerExtension::setExtension(tlm::tlm_generic_payload& trans, uint64_t channelPayloadID, Rank rank, +void ControllerExtension::setAutoExtension(tlm::tlm_generic_payload& trans, uint64_t channelPayloadID, Rank rank, BankGroup bankGroup, Bank bank, Row row, Column column, unsigned int burstLength) { auto* extension = trans.get_extension(); @@ -136,6 +169,14 @@ void ControllerExtension::setExtension(tlm::tlm_generic_payload& trans, uint64_t } } +void ControllerExtension::setExtension(tlm::tlm_generic_payload& trans, uint64_t channelPayloadID, Rank rank, + BankGroup bankGroup, Bank bank, Row row, Column column, unsigned int burstLength) +{ + assert(trans.get_extension() == nullptr); + auto* extension = new ControllerExtension(channelPayloadID, rank, bankGroup, bank, row, column, burstLength); + trans.set_extension(extension); +} + tlm_extension_base* ControllerExtension::clone() const { return new ControllerExtension(channelPayloadID, rank, bankGroup, bank, row, column, burstLength); @@ -153,6 +194,46 @@ void ControllerExtension::copy_from(const tlm_extension_base& ext) burstLength = cpyFrom.burstLength; } +uint64_t ControllerExtension::getChannelPayloadID() const +{ + return channelPayloadID; +} + +Rank ControllerExtension::getRank() const +{ + return rank; +} + +BankGroup ControllerExtension::getBankGroup() const +{ + return bankGroup; +} + +Bank ControllerExtension::getBank() const +{ + return bank; +} + +Row ControllerExtension::getRow() const +{ + return row; +} + +Column ControllerExtension::getColumn() const +{ + return column; +} + +unsigned ControllerExtension::getBurstLength() const +{ + return burstLength; +} + +const ControllerExtension& ControllerExtension::getExtension(const tlm::tlm_generic_payload& trans) +{ + return *trans.get_extension(); +} + uint64_t ControllerExtension::getChannelPayloadID(const tlm::tlm_generic_payload& trans) { return trans.get_extension()->channelPayloadID; @@ -188,228 +269,6 @@ unsigned ControllerExtension::getBurstLength(const tlm::tlm_generic_payload& tra return trans.get_extension()->burstLength; } -DramExtension::DramExtension() : - thread(0), channel(0), rank(0), bankGroup(0), bank(0), - row(0), column(0), burstLength(0), - threadPayloadID(0), channelPayloadID(0) {} - -DramExtension::DramExtension(Thread thread, Channel channel, Rank rank, - BankGroup bankGroup, Bank bank, Row row, - Column column, unsigned int burstLength, - uint64_t threadPayloadID, uint64_t channelPayloadID) : - thread(thread), channel(channel), rank(rank), bankGroup(bankGroup), bank(bank), - row(row), column(column), burstLength(burstLength), - threadPayloadID(threadPayloadID), channelPayloadID(channelPayloadID) {} - -void DramExtension::setExtension(tlm_generic_payload& payload, - Thread thread, Channel channel, Rank rank, - BankGroup bankGroup, Bank bank, Row row, - Column column, unsigned int burstLength, - uint64_t threadPayloadID, uint64_t channelPayloadID) -{ - DramExtension* extension = nullptr; - payload.get_extension(extension); - - if (extension != nullptr) - { - extension->thread = thread; - extension->channel = channel; - extension->rank = rank; - extension->bankGroup = bankGroup; - extension->bank = bank; - extension->row = row; - extension->column = column; - extension->burstLength = burstLength; - extension->threadPayloadID = threadPayloadID; - extension->channelPayloadID = channelPayloadID; - } - else - { - extension = new DramExtension(thread, channel, rank, bankGroup, - bank, row, column, burstLength, - threadPayloadID, channelPayloadID); - payload.set_auto_extension(extension); - } -} - -void DramExtension::setPayloadIDs(tlm_generic_payload& payload, uint64_t threadPayloadID, uint64_t channelPayloadID) -{ - DramExtension* extension = nullptr; - payload.get_extension(extension); - assert(extension != nullptr); - extension->threadPayloadID = threadPayloadID; - extension->channelPayloadID = channelPayloadID; -} - -DramExtension& DramExtension::getExtension(const tlm_generic_payload& payload) -{ - DramExtension* result = nullptr; - payload.get_extension(result); - assert(result != nullptr); - - return *result; -} - -Thread DramExtension::getThread(const tlm_generic_payload& payload) -{ - return DramExtension::getExtension(payload).getThread(); -} - -Channel DramExtension::getChannel(const tlm_generic_payload& payload) -{ - return DramExtension::getExtension(payload).getChannel(); -} - -Rank DramExtension::getRank(const tlm_generic_payload& payload) -{ - return DramExtension::getExtension(payload).getRank(); -} - -BankGroup DramExtension::getBankGroup(const tlm_generic_payload& payload) -{ - return DramExtension::getExtension(payload).getBankGroup(); -} - -Bank DramExtension::getBank(const tlm_generic_payload& payload) -{ - return DramExtension::getExtension(payload).getBank(); -} - -Row DramExtension::getRow(const tlm_generic_payload& payload) -{ - return DramExtension::getExtension(payload).getRow(); -} - -Column DramExtension::getColumn(const tlm_generic_payload& payload) -{ - return DramExtension::getExtension(payload).getColumn(); -} - -unsigned DramExtension::getBurstLength(const tlm_generic_payload& payload) -{ - return DramExtension::getExtension(payload).getBurstLength(); -} - -uint64_t DramExtension::getThreadPayloadID(const tlm_generic_payload& payload) -{ - return DramExtension::getExtension(payload).getThreadPayloadID(); -} - -uint64_t DramExtension::getChannelPayloadID(const tlm_generic_payload& payload) -{ - return DramExtension::getExtension(payload).getChannelPayloadID(); -} - -tlm_extension_base *DramExtension::clone() const -{ - return new DramExtension(thread, channel, rank, bankGroup, bank, row, column, - burstLength, threadPayloadID, channelPayloadID); -} - -void DramExtension::copy_from(const tlm_extension_base &ext) -{ - const auto &cpyFrom = dynamic_cast(ext); - thread = cpyFrom.thread; - channel = cpyFrom.channel; - rank = cpyFrom.rank; - bankGroup = cpyFrom.bankGroup; - bank = cpyFrom.bank; - row = cpyFrom.row; - column = cpyFrom.column; - burstLength = cpyFrom.burstLength; -} - -Thread DramExtension::getThread() const -{ - return thread; -} - -Channel DramExtension::getChannel() const -{ - return channel; -} - -Rank DramExtension::getRank() const -{ - return rank; -} - -BankGroup DramExtension::getBankGroup() const -{ - return bankGroup; -} - -Bank DramExtension::getBank() const -{ - return bank; -} - -Row DramExtension::getRow() const -{ - return row; -} - -Column DramExtension::getColumn() const -{ - return column; -} - -unsigned int DramExtension::getBurstLength() const -{ - return burstLength; -} - -uint64_t DramExtension::getThreadPayloadID() const -{ - return threadPayloadID; -} - -uint64_t DramExtension::getChannelPayloadID() const -{ - return channelPayloadID; -} - -tlm_extension_base *GenerationExtension::clone() const -{ - return new GenerationExtension(timeOfGeneration); -} - -void GenerationExtension::copy_from(const tlm_extension_base &ext) -{ - const auto &cpyFrom = dynamic_cast(ext); - timeOfGeneration = cpyFrom.timeOfGeneration; - -} - -void GenerationExtension::setExtension(tlm_generic_payload& payload, const sc_time& _timeOfGeneration) -{ - GenerationExtension* extension = nullptr; - payload.get_extension(extension); - - if (extension != nullptr) - { - extension->timeOfGeneration = _timeOfGeneration; - } - else - { - extension = new GenerationExtension(_timeOfGeneration); - payload.set_auto_extension(extension); - } -} - -GenerationExtension& GenerationExtension::getExtension(const tlm_generic_payload& payload) -{ - GenerationExtension* result = nullptr; - payload.get_extension(result); - assert(result != nullptr); - return *result; -} - -sc_time GenerationExtension::getTimeOfGeneration(const tlm_generic_payload& payload) -{ - return GenerationExtension::getExtension(payload).timeOfGeneration; -} - //THREAD bool operator ==(const Thread &lhs, const Thread &rhs) { diff --git a/DRAMSys/library/src/common/dramExtensions.h b/DRAMSys/library/src/common/dramExtensions.h index 27726bb7..7f164186 100644 --- a/DRAMSys/library/src/common/dramExtensions.h +++ b/DRAMSys/library/src/common/dramExtensions.h @@ -157,13 +157,21 @@ private: class ArbiterExtension : public tlm::tlm_extension { public: - static void setExtension(tlm::tlm_generic_payload& trans, Thread thread, Channel channel); + static void setAutoExtension(tlm::tlm_generic_payload& trans, Thread thread, Channel channel); + static void setExtension(tlm::tlm_generic_payload& trans, Thread thread, Channel channel, + uint64_t threadPayloadID, const sc_core::sc_time& timeOfGeneration); static void setIDAndTimeOfGeneration(tlm::tlm_generic_payload& trans, uint64_t threadPayloadID, const sc_core::sc_time& timeOfGeneration); tlm::tlm_extension_base* clone() const override; void copy_from(const tlm::tlm_extension_base& ext) override; + Thread getThread() const; + Channel getChannel() const; + uint64_t getThreadPayloadID() const; + sc_core::sc_time getTimeOfGeneration() const; + + static const ArbiterExtension& getExtension(const tlm::tlm_generic_payload& trans); static Thread getThread(const tlm::tlm_generic_payload& trans); static Channel getChannel(const tlm::tlm_generic_payload& trans); static uint64_t getThreadPayloadID(const tlm::tlm_generic_payload& trans); @@ -180,14 +188,26 @@ private: class ControllerExtension : public tlm::tlm_extension { public: - static void setExtension(tlm::tlm_generic_payload& trans, uint64_t channelPayloadID, Rank rank, BankGroup bankGroup, + static void setAutoExtension(tlm::tlm_generic_payload& trans, uint64_t channelPayloadID, Rank rank, BankGroup bankGroup, Bank bank, Row row, Column column, unsigned burstLength); + static void setExtension(tlm::tlm_generic_payload& trans, uint64_t channelPayloadID, Rank rank, BankGroup bankGroup, + Bank bank, Row row, Column column, unsigned burstLength); + //static ControllerExtension& getExtension(const tlm::tlm_generic_payload& trans); tlm::tlm_extension_base* clone() const override; void copy_from(const tlm::tlm_extension_base& ext) override; + uint64_t getChannelPayloadID() const; + Rank getRank() const; + BankGroup getBankGroup() const; + Bank getBank() const; + Row getRow() const; + Column getColumn() const; + unsigned getBurstLength() const; + + static const ControllerExtension& getExtension(const tlm::tlm_generic_payload& trans); static uint64_t getChannelPayloadID(const tlm::tlm_generic_payload& trans); static Rank getRank(const tlm::tlm_generic_payload& trans); static BankGroup getBankGroup(const tlm::tlm_generic_payload& trans); @@ -209,85 +229,6 @@ private: }; -class DramExtension : public tlm::tlm_extension -{ -public: - DramExtension(); - DramExtension(Thread thread, Channel channel, Rank rank, - BankGroup bankGroup, Bank bank, Row row, - Column column, unsigned int burstLength, - uint64_t threadPayloadID, uint64_t channelPayloadID); - tlm::tlm_extension_base *clone() const override; - void copy_from(const tlm::tlm_extension_base &ext) override; - - static void setExtension(tlm::tlm_generic_payload &payload, - Thread thread, Channel channel, Rank rank, - BankGroup bankGroup, Bank bank, Row row, - Column column, unsigned int burstLength, - uint64_t threadPayloadID, uint64_t channelPayloadID); - - static DramExtension &getExtension(const tlm::tlm_generic_payload &payload); - - static void setPayloadIDs(tlm::tlm_generic_payload &payload, - uint64_t threadPayloadID, uint64_t channelPayloadID); - - // Used for convenience, caller could also use getExtension(..) to access these field - static Thread getThread(const tlm::tlm_generic_payload &payload); - static Channel getChannel(const tlm::tlm_generic_payload &payload); - static Rank getRank(const tlm::tlm_generic_payload &payload); - static BankGroup getBankGroup(const tlm::tlm_generic_payload &payload); - static Bank getBank(const tlm::tlm_generic_payload &payload); - static Row getRow(const tlm::tlm_generic_payload &payload); - static Column getColumn(const tlm::tlm_generic_payload &payload); - static unsigned getBurstLength(const tlm::tlm_generic_payload &payload); - static uint64_t getThreadPayloadID(const tlm::tlm_generic_payload &payload); - static uint64_t getChannelPayloadID(const tlm::tlm_generic_payload &payload); - - Thread getThread() const; - Channel getChannel() const; - Rank getRank() const; - BankGroup getBankGroup() const; - Bank getBank() const; - Row getRow() const; - Column getColumn() const; - - unsigned int getBurstLength() const; - uint64_t getThreadPayloadID() const; - uint64_t getChannelPayloadID() const; - -private: - Thread thread; - Channel channel; - Rank rank; - BankGroup bankGroup; - Bank bank; - Row row; - Column column; - unsigned int burstLength; - uint64_t threadPayloadID; - uint64_t channelPayloadID; -}; - - -// Used to indicate the time when a payload is created (in a traceplayer or in a core) -// Note that this time can be different from the time the payload enters the DRAM system -//(at that time the phase BEGIN_REQ is recorded), so timeOfGeneration =< time(BEGIN_REQ) -class GenerationExtension : public tlm::tlm_extension -{ -public: - explicit GenerationExtension(const sc_core::sc_time &timeOfGeneration) - : timeOfGeneration(timeOfGeneration) {} - tlm::tlm_extension_base *clone() const override; - void copy_from(const tlm::tlm_extension_base &ext) override; - static void setExtension(tlm::tlm_generic_payload &payload, const sc_core::sc_time &_timeOfGeneration); - static GenerationExtension &getExtension(const tlm::tlm_generic_payload &payload); - static sc_core::sc_time getTimeOfGeneration(const tlm::tlm_generic_payload &payload); - -private: - sc_core::sc_time timeOfGeneration; -}; - - bool operator==(const Thread &lhs, const Thread &rhs); bool operator!=(const Thread &lhs, const Thread &rhs); bool operator<(const Thread &lhs, const Thread &rhs); diff --git a/DRAMSys/library/src/common/utils.cpp b/DRAMSys/library/src/common/utils.cpp index 81f7a565..9784289d 100644 --- a/DRAMSys/library/src/common/utils.cpp +++ b/DRAMSys/library/src/common/utils.cpp @@ -80,7 +80,6 @@ void setUpDummy(tlm_generic_payload &payload, uint64_t channelPayloadID, Rank ra payload.set_dmi_allowed(false); payload.set_byte_enable_length(0); payload.set_streaming_width(0); - payload.set_extension(new DramExtension(Thread(UINT_MAX), Channel(0), rank, - bankGroup, bank, Row(0), Column(0), 0, 0, channelPayloadID)); - payload.set_extension(new GenerationExtension(SC_ZERO_TIME)); + ControllerExtension::setExtension(payload, channelPayloadID, rank, bankGroup, bank, Row(0), Column(0), 0); + ArbiterExtension::setExtension(payload, Thread(UINT_MAX), Channel(0), 0, SC_ZERO_TIME); } diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp index 1b9f86f6..ffa85023 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp @@ -65,6 +65,7 @@ MemSpec::MemSpec(const DRAMSysConfiguration::MemSpec &memSpec, dataRate(memSpec.memArchitectureSpec.entries.at("dataRate")), bitWidth(memSpec.memArchitectureSpec.entries.at("width")), dataBusWidth(bitWidth * devicesPerRank), + bytesPerBeat(dataBusWidth / 8), defaultBytesPerBurst((defaultBurstLength * dataBusWidth) / 8), maxBytesPerBurst((maxBurstLength * dataBusWidth) / 8), fCKMHz(memSpec.memTimingSpec.entries.at("clkMhz")), diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.h b/DRAMSys/library/src/configuration/memspec/MemSpec.h index ac6fca08..bdf23cac 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.h @@ -66,6 +66,7 @@ public: const unsigned dataRate; const unsigned bitWidth; const unsigned dataBusWidth; + const unsigned bytesPerBeat; const unsigned defaultBytesPerBurst; const unsigned maxBytesPerBurst; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp index 259d8c7d..c8ff40ba 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp @@ -216,7 +216,7 @@ sc_time MemSpecDDR5::getExecutionTime(Command command, const tlm_generic_payload return tRCD + longCmdOffset; else if (command == Command::RD) { - if (DramExtension::getBurstLength(payload) == 32) + if (ControllerExtension::getBurstLength(payload) == 32) return tRL + tBURST32 + longCmdOffset; else return tRL + tBURST16 + longCmdOffset; @@ -225,14 +225,14 @@ sc_time MemSpecDDR5::getExecutionTime(Command command, const tlm_generic_payload return tRTP + tRP + longCmdOffset; else if (command == Command::WR) { - if (DramExtension::getBurstLength(payload) == 32) + if (ControllerExtension::getBurstLength(payload) == 32) return tWL + tBURST32 + longCmdOffset; else return tWL + tBURST16 + longCmdOffset; } else if (command == Command::WRA) { - if (DramExtension::getBurstLength(payload) == 32) + if (ControllerExtension::getBurstLength(payload) == 32) return tWL + tBURST32 + tWR + tRP + longCmdOffset; else return tWL + tBURST16 + tWR + tRP + longCmdOffset; @@ -253,14 +253,14 @@ TimeInterval MemSpecDDR5::getIntervalOnDataStrobe(Command command, const tlm_gen { if (command == Command::RD || command == Command::RDA) { - if (DramExtension::getBurstLength(payload) == 32) + if (ControllerExtension::getBurstLength(payload) == 32) return {tRL + longCmdOffset, tRL + tBURST32 + longCmdOffset}; else return {tRL + longCmdOffset, tRL + tBURST16 + longCmdOffset}; } else if (command == Command::WR || command == Command::WRA) { - if (DramExtension::getBurstLength(payload) == 32) + if (ControllerExtension::getBurstLength(payload) == 32) return {tWL + longCmdOffset, tWL + tBURST32 + longCmdOffset}; else return {tWL + longCmdOffset, tWL + tBURST16 + longCmdOffset}; diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index 10b29206..6316280a 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -57,7 +57,7 @@ void BankMachine::updateState(Command command) { case Command::ACT: state = State::Activated; - openRow = DramExtension::getRow(*currentPayload); + openRow = ControllerExtension::getRow(*currentPayload); keepTrans = true; refreshManagementCounter++; break; @@ -180,7 +180,7 @@ sc_time BankMachineOpen::start() assert(!keepTrans || currentPayload != nullptr); if (keepTrans) { - if (DramExtension::getRow(*newPayload) == openRow) + if (ControllerExtension::getRow(*newPayload) == openRow) currentPayload = newPayload; } else @@ -192,7 +192,7 @@ sc_time BankMachineOpen::start() nextCommand = Command::ACT; else if (state == State::Activated) { - if (DramExtension::getRow(*currentPayload) == openRow) // row hit + if (ControllerExtension::getRow(*currentPayload) == openRow) // row hit { assert(currentPayload->is_read() || currentPayload->is_write()); if (currentPayload->is_read()) @@ -232,7 +232,7 @@ sc_time BankMachineClosed::start() assert(!keepTrans || currentPayload != nullptr); if (keepTrans) { - if (DramExtension::getRow(*newPayload) == openRow) + if (ControllerExtension::getRow(*newPayload) == openRow) currentPayload = newPayload; } else @@ -279,7 +279,7 @@ sc_time BankMachineOpenAdaptive::start() assert(!keepTrans || currentPayload != nullptr); if (keepTrans) { - if (DramExtension::getRow(*newPayload) == openRow) + if (ControllerExtension::getRow(*newPayload) == openRow) currentPayload = newPayload; } else @@ -291,7 +291,7 @@ sc_time BankMachineOpenAdaptive::start() nextCommand = Command::ACT; else if (state == State::Activated) { - if (DramExtension::getRow(*currentPayload) == openRow) // row hit + if (ControllerExtension::getRow(*currentPayload) == openRow) // row hit { if (scheduler.hasFurtherRequest(bank, currentPayload->get_command()) && !scheduler.hasFurtherRowHit(bank, openRow, currentPayload->get_command())) @@ -343,7 +343,7 @@ sc_time BankMachineClosedAdaptive::start() assert(!keepTrans || currentPayload != nullptr); if (keepTrans) { - if (DramExtension::getRow(*newPayload) == openRow) + if (ControllerExtension::getRow(*newPayload) == openRow) currentPayload = newPayload; } else @@ -355,7 +355,7 @@ sc_time BankMachineClosedAdaptive::start() nextCommand = Command::ACT; else if (state == State::Activated) { - if (DramExtension::getRow(*currentPayload) == openRow) // row hit + if (ControllerExtension::getRow(*currentPayload) == openRow) // row hit { if (scheduler.hasFurtherRowHit(bank, openRow, currentPayload->get_command())) { diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index 08d9116e..4a410ebd 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -284,8 +284,8 @@ void Controller::controllerMethod() tlm_generic_payload *payload = std::get(commandTuple); if (command != Command::NOP) // can happen with FIFO strict { - Rank rank = DramExtension::getRank(*payload); - Bank bank = DramExtension::getBank(*payload); + Rank rank = ControllerExtension::getRank(*payload); + Bank bank = ControllerExtension::getBank(*payload); if (command.isRankCommand()) { @@ -369,6 +369,13 @@ tlm_sync_enum Controller::nb_transport_fw(tlm_generic_payload &trans, transToAcquire.payload = &trans; transToAcquire.time = sc_time_stamp() + delay; beginReqEvent.notify(delay); + + DecodedAddress decodedAddress = addressDecoder.decodeAddress(transToAcquire.payload->get_address()); + ControllerExtension::setAutoExtension(*transToAcquire.payload, nextChannelPayloadIDToAppend++, + Rank(decodedAddress.rank), BankGroup(decodedAddress.bankgroup), + Bank(decodedAddress.bank), Row(decodedAddress.row), + Column(decodedAddress.column), + transToAcquire.payload->get_data_length() / memSpec.bytesPerBeat); } else if (phase == END_RESP) { @@ -400,16 +407,24 @@ void Controller::manageRequests(const sc_time &delay) { if (transToAcquire.payload != nullptr && transToAcquire.time <= sc_time_stamp()) { + // Check size of transaction +// unsigned numSubTrans = transToAcquire.payload->get_data_length() / memSpec.maxBytesPerBurst; +// if (numSubTrans > 1) +// { +// // Split create child transactions +// // Address decoding!!! +// } + if (scheduler->hasBufferSpace()) { - NDEBUG_UNUSED(uint64_t id) = DramExtension::getChannelPayloadID(*transToAcquire.payload); + NDEBUG_UNUSED(uint64_t id) = ControllerExtension::getChannelPayloadID(*transToAcquire.payload); PRINTDEBUGMESSAGE(name(), "Payload " + std::to_string(id) + " entered system."); if (totalNumberOfPayloads == 0) idleTimeCollector.end(); totalNumberOfPayloads++; - Rank rank = DramExtension::getRank(*transToAcquire.payload); + Rank rank = ControllerExtension::getRank(*transToAcquire.payload); if (ranksNumberOfPayloads[rank.ID()] == 0) powerDownManagers[rank.ID()]->triggerExit(); @@ -418,7 +433,7 @@ void Controller::manageRequests(const sc_time &delay) scheduler->storeRequest(*transToAcquire.payload); transToAcquire.payload->acquire(); - Bank bank = DramExtension::getBank(*transToAcquire.payload); + Bank bank = ControllerExtension::getBank(*transToAcquire.payload); bankMachines[bank.ID()]->start(); transToAcquire.payload->set_response_status(TLM_OK_RESPONSE); @@ -441,10 +456,10 @@ void Controller::manageResponses() assert(transToRelease.time >= sc_time_stamp()); if (transToRelease.time == sc_time_stamp()) { - NDEBUG_UNUSED(uint64_t id) = DramExtension::getChannelPayloadID(*transToRelease.payload); + NDEBUG_UNUSED(uint64_t id) = ControllerExtension::getChannelPayloadID(*transToRelease.payload); PRINTDEBUGMESSAGE(name(), "Payload " + std::to_string(id) + " left system."); - numberOfBeatsServed += DramExtension::getBurstLength(*transToRelease.payload); + numberOfBeatsServed += ControllerExtension::getBurstLength(*transToRelease.payload); transToRelease.payload->release(); transToRelease.payload = nullptr; totalNumberOfPayloads--; diff --git a/DRAMSys/library/src/controller/Controller.h b/DRAMSys/library/src/controller/Controller.h index 4852f549..16e3d521 100644 --- a/DRAMSys/library/src/controller/Controller.h +++ b/DRAMSys/library/src/controller/Controller.h @@ -89,6 +89,7 @@ private: std::vector> powerDownManagers; const AddressDecoder& addressDecoder; + uint64_t nextChannelPayloadIDToAppend = 1; struct Transaction { diff --git a/DRAMSys/library/src/controller/ControllerRecordable.cpp b/DRAMSys/library/src/controller/ControllerRecordable.cpp index f7aa782a..6c188b71 100644 --- a/DRAMSys/library/src/controller/ControllerRecordable.cpp +++ b/DRAMSys/library/src/controller/ControllerRecordable.cpp @@ -58,8 +58,10 @@ ControllerRecordable::ControllerRecordable(const sc_module_name &name, const Con tlm_sync_enum ControllerRecordable::nb_transport_fw(tlm_generic_payload &trans, tlm_phase &phase, sc_time &delay) { + // Important: delay must not be increased by nb_transport_fw + tlm_sync_enum returnValue = Controller::nb_transport_fw(trans, phase, delay); recordPhase(trans, phase, delay); - return Controller::nb_transport_fw(trans, phase, delay); + return returnValue; } tlm_sync_enum ControllerRecordable::nb_transport_bw(tlm_generic_payload &, @@ -92,13 +94,13 @@ void ControllerRecordable::recordPhase(tlm_generic_payload &trans, const tlm_pha { sc_time recTime = delay + sc_time_stamp(); - NDEBUG_UNUSED(unsigned thr) = DramExtension::getExtension(trans).getThread().ID(); - NDEBUG_UNUSED(unsigned ch) = DramExtension::getExtension(trans).getChannel().ID(); - NDEBUG_UNUSED(unsigned bg) = DramExtension::getExtension(trans).getBankGroup().ID(); - NDEBUG_UNUSED(unsigned bank) = DramExtension::getExtension(trans).getBank().ID(); - NDEBUG_UNUSED(unsigned row) = DramExtension::getExtension(trans).getRow().ID(); - NDEBUG_UNUSED(unsigned col) = DramExtension::getExtension(trans).getColumn().ID(); - NDEBUG_UNUSED(uint64_t id) = DramExtension::getExtension(trans).getChannelPayloadID(); + NDEBUG_UNUSED(unsigned thr) = ArbiterExtension::getExtension(trans).getThread().ID(); + NDEBUG_UNUSED(unsigned ch) = ArbiterExtension::getExtension(trans).getChannel().ID(); + NDEBUG_UNUSED(unsigned bg) = ControllerExtension::getExtension(trans).getBankGroup().ID(); + NDEBUG_UNUSED(unsigned bank) = ControllerExtension::getExtension(trans).getBank().ID(); + NDEBUG_UNUSED(unsigned row) = ControllerExtension::getExtension(trans).getRow().ID(); + NDEBUG_UNUSED(unsigned col) = ControllerExtension::getExtension(trans).getColumn().ID(); + NDEBUG_UNUSED(uint64_t id) = ControllerExtension::getExtension(trans).getChannelPayloadID(); PRINTDEBUGMESSAGE(name(), "Recording " + getPhaseName(phase) + " thread " + std::to_string(thr) + " channel " + std::to_string(ch) + " bank group " + std::to_string( diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp index c440f244..4743ceb4 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp @@ -66,15 +66,15 @@ CheckerDDR3::CheckerDDR3(const Configuration& config) sc_time CheckerDDR3::timeToSatisfyConstraints(Command command, const tlm_generic_payload& payload) const { - Rank rank = DramExtension::getRank(payload); - Bank bank = DramExtension::getBank(payload); + Rank rank = ControllerExtension::getRank(payload); + Bank bank = ControllerExtension::getBank(payload); sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); if (command == Command::RD || command == Command::RDA) { - assert(DramExtension::getBurstLength(payload) == 8); + assert(ControllerExtension::getBurstLength(payload) == 8); lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != sc_max_time()) @@ -129,7 +129,7 @@ sc_time CheckerDDR3::timeToSatisfyConstraints(Command command, const tlm_generic } else if (command == Command::WR || command == Command::WRA) { - assert(DramExtension::getBurstLength(payload) == 8); + assert(ControllerExtension::getBurstLength(payload) == 8); lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != sc_max_time()) @@ -425,8 +425,8 @@ sc_time CheckerDDR3::timeToSatisfyConstraints(Command command, const tlm_generic void CheckerDDR3::insert(Command command, const tlm_generic_payload& payload) { - Rank rank = DramExtension::getRank(payload); - Bank bank = DramExtension::getBank(payload); + Rank rank = ControllerExtension::getRank(payload); + Bank bank = ControllerExtension::getBank(payload); PRINTDEBUGMESSAGE("CheckerDDR3", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + command.toString()); diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp index 421cac01..a15b8dfa 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp @@ -69,16 +69,16 @@ CheckerDDR4::CheckerDDR4(const Configuration& config) sc_time CheckerDDR4::timeToSatisfyConstraints(Command command, const tlm_generic_payload& payload) const { - Rank rank = DramExtension::getRank(payload); - BankGroup bankGroup = DramExtension::getBankGroup(payload); - Bank bank = DramExtension::getBank(payload); + Rank rank = ControllerExtension::getRank(payload); + BankGroup bankGroup = ControllerExtension::getBankGroup(payload); + Bank bank = ControllerExtension::getBank(payload); sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); if (command == Command::RD || command == Command::RDA) { - assert(DramExtension::getBurstLength(payload) == 8); + assert(ControllerExtension::getBurstLength(payload) == 8); lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != sc_max_time()) @@ -149,7 +149,7 @@ sc_time CheckerDDR4::timeToSatisfyConstraints(Command command, const tlm_generic } else if (command == Command::WR || command == Command::WRA) { - assert(DramExtension::getBurstLength(payload) == 8); + assert(ControllerExtension::getBurstLength(payload) == 8); lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != sc_max_time()) @@ -457,9 +457,9 @@ sc_time CheckerDDR4::timeToSatisfyConstraints(Command command, const tlm_generic void CheckerDDR4::insert(Command command, const tlm_generic_payload& payload) { - Rank rank = DramExtension::getRank(payload); - BankGroup bankGroup = DramExtension::getBankGroup(payload); - Bank bank = DramExtension::getBank(payload); + Rank rank = ControllerExtension::getRank(payload); + BankGroup bankGroup = ControllerExtension::getBankGroup(payload); + Bank bank = ControllerExtension::getBank(payload); PRINTDEBUGMESSAGE("CheckerDDR4", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + command.toString()); diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR5.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR5.cpp index 795c8857..5a6d92ef 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR5.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR5.cpp @@ -117,11 +117,11 @@ CheckerDDR5::CheckerDDR5(const Configuration& config) sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, const tlm_generic_payload& payload) const { - Rank logicalRank = DramExtension::getRank(payload); + Rank logicalRank = ControllerExtension::getRank(payload); Rank physicalRank = Rank(logicalRank.ID() / memSpec->logicalRanksPerPhysicalRank); Rank dimmRank = Rank(physicalRank.ID() / memSpec->physicalRanksPerDimmRank); - BankGroup bankGroup = DramExtension::getBankGroup(payload); - Bank bank = DramExtension::getBank(payload); + BankGroup bankGroup = ControllerExtension::getBankGroup(payload); + Bank bank = ControllerExtension::getBank(payload); Bank bankInGroup = Bank(logicalRank.ID() * memSpec->banksPerGroup + bank.ID() % memSpec->banksPerGroup); sc_time lastCommandStart; @@ -129,7 +129,7 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, const tlm_generic if (command == Command::RD || command == Command::RDA) { - unsigned burstLength = DramExtension::getBurstLength(payload); + unsigned burstLength = ControllerExtension::getBurstLength(payload); assert((burstLength == 16) || (burstLength == 32)); assert(!(burstLength == 32) || (memSpec->bitWidth == 4)); assert(burstLength <= memSpec->maxBurstLength); @@ -316,7 +316,7 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, const tlm_generic } else if (command == Command::WR || command == Command::WRA) { - unsigned burstLength = DramExtension::getBurstLength(payload); + unsigned burstLength = ControllerExtension::getBurstLength(payload); assert((burstLength == 16) || (burstLength == 32)); assert(!(burstLength == 32) || (memSpec->bitWidth == 4)); assert(burstLength <= memSpec->maxBurstLength); @@ -879,13 +879,13 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, const tlm_generic void CheckerDDR5::insert(Command command, const tlm_generic_payload& payload) { - Rank logicalRank = DramExtension::getRank(payload); + Rank logicalRank = ControllerExtension::getRank(payload); Rank physicalRank = Rank(logicalRank.ID() / memSpec->logicalRanksPerPhysicalRank); Rank dimmRank = Rank(physicalRank.ID() / memSpec->physicalRanksPerDimmRank); - BankGroup bankGroup = DramExtension::getBankGroup(payload); - Bank bank = DramExtension::getBank(payload); + BankGroup bankGroup = ControllerExtension::getBankGroup(payload); + Bank bank = ControllerExtension::getBank(payload); Bank bankInGroup = Bank(logicalRank.ID() * memSpec->banksPerGroup + bank.ID() % memSpec->banksPerGroup); - unsigned burstLength = DramExtension::getBurstLength(payload); + unsigned burstLength = ControllerExtension::getBurstLength(payload); PRINTDEBUGMESSAGE("CheckerDDR5", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + command.toString()); diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp b/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp index 9c9635b4..8ed0bf46 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp @@ -70,16 +70,16 @@ CheckerGDDR5::CheckerGDDR5(const Configuration& config) sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, const tlm_generic_payload& payload) const { - Rank rank = DramExtension::getRank(payload); - BankGroup bankGroup = DramExtension::getBankGroup(payload); - Bank bank = DramExtension::getBank(payload); + Rank rank = ControllerExtension::getRank(payload); + BankGroup bankGroup = ControllerExtension::getBankGroup(payload); + Bank bank = ControllerExtension::getBank(payload); sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); if (command == Command::RD || command == Command::RDA) { - assert(DramExtension::getBurstLength(payload) == 8); + assert(ControllerExtension::getBurstLength(payload) == 8); lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != sc_max_time()) @@ -150,7 +150,7 @@ sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, const tlm_generi } else if (command == Command::WR || command == Command::WRA) { - assert(DramExtension::getBurstLength(payload) == 8); + assert(ControllerExtension::getBurstLength(payload) == 8); lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != sc_max_time()) @@ -539,9 +539,9 @@ sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, const tlm_generi void CheckerGDDR5::insert(Command command, const tlm_generic_payload& payload) { - Rank rank = DramExtension::getRank(payload); - BankGroup bankGroup = DramExtension::getBankGroup(payload); - Bank bank = DramExtension::getBank(payload); + Rank rank = ControllerExtension::getRank(payload); + BankGroup bankGroup = ControllerExtension::getBankGroup(payload); + Bank bank = ControllerExtension::getBank(payload); PRINTDEBUGMESSAGE("CheckerGDDR5", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + command.toString()); diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp b/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp index 2c203b13..beb43e2f 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp @@ -70,16 +70,16 @@ CheckerGDDR5X::CheckerGDDR5X(const Configuration& config) sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, const tlm_generic_payload& payload) const { - Rank rank = DramExtension::getRank(payload); - BankGroup bankGroup = DramExtension::getBankGroup(payload); - Bank bank = DramExtension::getBank(payload); + Rank rank = ControllerExtension::getRank(payload); + BankGroup bankGroup = ControllerExtension::getBankGroup(payload); + Bank bank = ControllerExtension::getBank(payload); sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); if (command == Command::RD || command == Command::RDA) { - unsigned burstLength = DramExtension::getBurstLength(payload); + unsigned burstLength = ControllerExtension::getBurstLength(payload); assert(!(memSpec->dataRate == 4) || (burstLength == 8)); // DDR mode (QDR wrt CK) assert(!(memSpec->dataRate == 8) || (burstLength == 16)); // QDR mode (ODR wrt CK) @@ -152,7 +152,7 @@ sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, const tlm_gener } else if (command == Command::WR || command == Command::WRA) { - unsigned burstLength = DramExtension::getBurstLength(payload); + unsigned burstLength = ControllerExtension::getBurstLength(payload); assert(!(memSpec->dataRate == 4) || (burstLength == 8)); // DDR mode (QDR wrt CK) assert(!(memSpec->dataRate == 8) || (burstLength == 16)); // QDR mode (ODR wrt CK) @@ -543,9 +543,9 @@ sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, const tlm_gener void CheckerGDDR5X::insert(Command command, const tlm_generic_payload& payload) { - Rank rank = DramExtension::getRank(payload); - BankGroup bankGroup = DramExtension::getBankGroup(payload); - Bank bank = DramExtension::getBank(payload); + Rank rank = ControllerExtension::getRank(payload); + BankGroup bankGroup = ControllerExtension::getBankGroup(payload); + Bank bank = ControllerExtension::getBank(payload); PRINTDEBUGMESSAGE("CheckerGDDR5X", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + command.toString()); diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp b/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp index 2aaaa651..681f251d 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp @@ -69,16 +69,16 @@ CheckerGDDR6::CheckerGDDR6(const Configuration& config) sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, const tlm_generic_payload& payload) const { - Rank rank = DramExtension::getRank(payload); - BankGroup bankGroup = DramExtension::getBankGroup(payload); - Bank bank = DramExtension::getBank(payload); + Rank rank = ControllerExtension::getRank(payload); + BankGroup bankGroup = ControllerExtension::getBankGroup(payload); + Bank bank = ControllerExtension::getBank(payload); sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); if (command == Command::RD || command == Command::RDA) { - assert(DramExtension::getBurstLength(payload) == 16); + assert(ControllerExtension::getBurstLength(payload) == 16); lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != sc_max_time()) @@ -149,7 +149,7 @@ sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, const tlm_generi } else if (command == Command::WR || command == Command::WRA) { - assert(DramExtension::getBurstLength(payload) == 16); + assert(ControllerExtension::getBurstLength(payload) == 16); lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != sc_max_time()) @@ -560,9 +560,9 @@ sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, const tlm_generi void CheckerGDDR6::insert(Command command, const tlm_generic_payload& payload) { - Rank rank = DramExtension::getRank(payload); - BankGroup bankGroup = DramExtension::getBankGroup(payload); - Bank bank = DramExtension::getBank(payload); + Rank rank = ControllerExtension::getRank(payload); + BankGroup bankGroup = ControllerExtension::getBankGroup(payload); + Bank bank = ControllerExtension::getBank(payload); PRINTDEBUGMESSAGE("CheckerGDDR6", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + command.toString()); diff --git a/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp b/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp index 26b096a8..671dcb07 100644 --- a/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp @@ -70,16 +70,16 @@ CheckerHBM2::CheckerHBM2(const Configuration& config) sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, const tlm_generic_payload& payload) const { - Rank rank = DramExtension::getRank(payload); - BankGroup bankGroup = DramExtension::getBankGroup(payload); - Bank bank = DramExtension::getBank(payload); + Rank rank = ControllerExtension::getRank(payload); + BankGroup bankGroup = ControllerExtension::getBankGroup(payload); + Bank bank = ControllerExtension::getBank(payload); sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); if (command == Command::RD || command == Command::RDA) { - unsigned burstLength = DramExtension::getBurstLength(payload); + unsigned burstLength = ControllerExtension::getBurstLength(payload); assert(!(memSpec->ranksPerChannel == 1) || (burstLength == 2 || burstLength == 4)); // Legacy mode assert(!(memSpec->ranksPerChannel == 2) || (burstLength == 4)); // Pseudo-channel mode @@ -134,7 +134,7 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, const tlm_generic } else if (command == Command::WR || command == Command::WRA) { - unsigned burstLength = DramExtension::getBurstLength(payload); + unsigned burstLength = ControllerExtension::getBurstLength(payload); assert(!(memSpec->ranksPerChannel == 1) || (burstLength == 2)); // Legacy mode assert(!(memSpec->ranksPerChannel == 2) || (burstLength == 4)); // Pseudo-channel mode @@ -518,9 +518,9 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, const tlm_generic void CheckerHBM2::insert(Command command, const tlm_generic_payload& payload) { - Rank rank = DramExtension::getRank(payload); - BankGroup bankGroup = DramExtension::getBankGroup(payload); - Bank bank = DramExtension::getBank(payload); + Rank rank = ControllerExtension::getRank(payload); + BankGroup bankGroup = ControllerExtension::getBankGroup(payload); + Bank bank = ControllerExtension::getBank(payload); PRINTDEBUGMESSAGE("CheckerHBM2", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + command.toString()); diff --git a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp index cecfa592..eaa26001 100644 --- a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp @@ -72,15 +72,15 @@ CheckerLPDDR4::CheckerLPDDR4(const Configuration& config) sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, const tlm_generic_payload& payload) const { - Rank rank = DramExtension::getRank(payload); - Bank bank = DramExtension::getBank(payload); + Rank rank = ControllerExtension::getRank(payload); + Bank bank = ControllerExtension::getBank(payload); sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); if (command == Command::RD || command == Command::RDA) { - unsigned burstLength = DramExtension::getBurstLength(payload); + unsigned burstLength = ControllerExtension::getBurstLength(payload); assert((burstLength == 16) || (burstLength == 32)); // TODO: BL16/32 OTF assert(burstLength <= memSpec->maxBurstLength); @@ -133,7 +133,7 @@ sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, const tlm_gener } else if (command == Command::WR || command == Command::WRA) { - unsigned burstLength = DramExtension::getBurstLength(payload); + unsigned burstLength = ControllerExtension::getBurstLength(payload); assert((burstLength == 16) || (burstLength == 32)); assert(burstLength <= memSpec->maxBurstLength); @@ -513,8 +513,8 @@ sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, const tlm_gener void CheckerLPDDR4::insert(Command command, const tlm_generic_payload& payload) { - Rank rank = DramExtension::getRank(payload); - Bank bank = DramExtension::getBank(payload); + Rank rank = ControllerExtension::getRank(payload); + Bank bank = ControllerExtension::getBank(payload); PRINTDEBUGMESSAGE("CheckerLPDDR4", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + command.toString()); diff --git a/DRAMSys/library/src/controller/checker/CheckerLPDDR5.cpp b/DRAMSys/library/src/controller/checker/CheckerLPDDR5.cpp index 6b65980a..790a2d5a 100644 --- a/DRAMSys/library/src/controller/checker/CheckerLPDDR5.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerLPDDR5.cpp @@ -72,16 +72,16 @@ CheckerLPDDR5::CheckerLPDDR5(const Configuration& config) sc_time CheckerLPDDR5::timeToSatisfyConstraints(Command command, const tlm_generic_payload& payload) const { - Rank rank = DramExtension::getRank(payload); - BankGroup bankGroup = DramExtension::getBankGroup(payload); - Bank bank = DramExtension::getBank(payload); + Rank rank = ControllerExtension::getRank(payload); + BankGroup bankGroup = ControllerExtension::getBankGroup(payload); + Bank bank = ControllerExtension::getBank(payload); sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); if (command == Command::RD || command == Command::RDA) { - unsigned burstLength = DramExtension::getBurstLength(payload); + unsigned burstLength = ControllerExtension::getBurstLength(payload); assert(!(memSpec->bitWidth == 8) || (burstLength == 32)); // x8 device -> BL32 assert(!(memSpec->groupsPerRank > 1) || (burstLength == 16)); // BG mode -> BL16 (TODO: BL32) assert(burstLength <= memSpec->maxBurstLength); @@ -193,7 +193,7 @@ sc_time CheckerLPDDR5::timeToSatisfyConstraints(Command command, const tlm_gener } else if (command == Command::WR || command == Command::WRA) { - unsigned burstLength = DramExtension::getBurstLength(payload); + unsigned burstLength = ControllerExtension::getBurstLength(payload); assert(!(memSpec->bitWidth == 8) || (burstLength == 32)); // x8 device -> BL32 assert(!(memSpec->groupsPerRank > 1) || (burstLength == 16)); // BG mode -> BL16 (TODO: BL32) assert(burstLength <= memSpec->maxBurstLength); @@ -638,10 +638,10 @@ sc_time CheckerLPDDR5::timeToSatisfyConstraints(Command command, const tlm_gener void CheckerLPDDR5::insert(Command command, const tlm_generic_payload& payload) { - Rank rank = DramExtension::getRank(payload); - BankGroup bankGroup = DramExtension::getBankGroup(payload); - Bank bank = DramExtension::getBank(payload); - unsigned burstLength = DramExtension::getBurstLength(payload); + Rank rank = ControllerExtension::getRank(payload); + BankGroup bankGroup = ControllerExtension::getBankGroup(payload); + Bank bank = ControllerExtension::getBank(payload); + unsigned burstLength = ControllerExtension::getBurstLength(payload); PRINTDEBUGMESSAGE("CheckerLPDDR5", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + command.toString()); diff --git a/DRAMSys/library/src/controller/checker/CheckerSTTMRAM.cpp b/DRAMSys/library/src/controller/checker/CheckerSTTMRAM.cpp index 16f59a26..887c59a3 100644 --- a/DRAMSys/library/src/controller/checker/CheckerSTTMRAM.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerSTTMRAM.cpp @@ -66,15 +66,15 @@ CheckerSTTMRAM::CheckerSTTMRAM(const Configuration& config) sc_time CheckerSTTMRAM::timeToSatisfyConstraints(Command command, const tlm_generic_payload& payload) const { - Rank rank = DramExtension::getRank(payload); - Bank bank = DramExtension::getBank(payload); + Rank rank = ControllerExtension::getRank(payload); + Bank bank = ControllerExtension::getBank(payload); sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); if (command == Command::RD || command == Command::RDA) { - assert(DramExtension::getBurstLength(payload) == 8); + assert(ControllerExtension::getBurstLength(payload) == 8); lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != sc_max_time()) @@ -131,7 +131,7 @@ sc_time CheckerSTTMRAM::timeToSatisfyConstraints(Command command, const tlm_gene } else if (command == Command::WR || command == Command::WRA) { - assert(DramExtension::getBurstLength(payload) == 8); + assert(ControllerExtension::getBurstLength(payload) == 8); lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != sc_max_time()) @@ -381,8 +381,8 @@ sc_time CheckerSTTMRAM::timeToSatisfyConstraints(Command command, const tlm_gene void CheckerSTTMRAM::insert(Command command, const tlm_generic_payload& payload) { - Rank rank = DramExtension::getRank(payload); - Bank bank = DramExtension::getBank(payload); + Rank rank = ControllerExtension::getRank(payload); + Bank bank = ControllerExtension::getBank(payload); PRINTDEBUGMESSAGE("CheckerSTTMRAM", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + command.toString()); diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp b/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp index b6ce278e..76c0abbb 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp @@ -66,15 +66,15 @@ CheckerWideIO::CheckerWideIO(const Configuration& config) sc_time CheckerWideIO::timeToSatisfyConstraints(Command command, const tlm_generic_payload& payload) const { - Rank rank = DramExtension::getRank(payload); - Bank bank = DramExtension::getBank(payload); + Rank rank = ControllerExtension::getRank(payload); + Bank bank = ControllerExtension::getBank(payload); sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); if (command == Command::RD || command == Command::RDA) { - unsigned burstLength = DramExtension::getBurstLength(payload); + unsigned burstLength = ControllerExtension::getBurstLength(payload); assert((burstLength == 2) || (burstLength == 4)); assert(burstLength <= memSpec->maxBurstLength); @@ -127,7 +127,7 @@ sc_time CheckerWideIO::timeToSatisfyConstraints(Command command, const tlm_gener } else if (command == Command::WR || command == Command::WRA) { - unsigned burstLength = DramExtension::getBurstLength(payload); + unsigned burstLength = ControllerExtension::getBurstLength(payload); assert((burstLength == 2) || (burstLength == 4)); assert(burstLength <= memSpec->maxBurstLength); @@ -402,8 +402,8 @@ sc_time CheckerWideIO::timeToSatisfyConstraints(Command command, const tlm_gener void CheckerWideIO::insert(Command command, const tlm_generic_payload& payload) { - Rank rank = DramExtension::getRank(payload); - Bank bank = DramExtension::getBank(payload); + Rank rank = ControllerExtension::getRank(payload); + Bank bank = ControllerExtension::getBank(payload); PRINTDEBUGMESSAGE("CheckerWideIO", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + command.toString()); diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp b/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp index ab73abfb..ca42f0fd 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp @@ -67,15 +67,15 @@ CheckerWideIO2::CheckerWideIO2(const Configuration& config) sc_time CheckerWideIO2::timeToSatisfyConstraints(Command command, const tlm_generic_payload& payload) const { - Rank rank = DramExtension::getRank(payload); - Bank bank = DramExtension::getBank(payload); + Rank rank = ControllerExtension::getRank(payload); + Bank bank = ControllerExtension::getBank(payload); sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); if (command == Command::RD || command == Command::RDA) { - unsigned burstLength = DramExtension::getBurstLength(payload); + unsigned burstLength = ControllerExtension::getBurstLength(payload); assert((burstLength == 4) || (burstLength == 8)); // TODO: BL4/8 OTF assert(burstLength <= memSpec->maxBurstLength); @@ -128,7 +128,7 @@ sc_time CheckerWideIO2::timeToSatisfyConstraints(Command command, const tlm_gene } else if (command == Command::WR || command == Command::WRA) { - unsigned burstLength = DramExtension::getBurstLength(payload); + unsigned burstLength = ControllerExtension::getBurstLength(payload); assert((burstLength == 4) || (burstLength == 8)); assert(burstLength <= memSpec->maxBurstLength); @@ -480,8 +480,8 @@ sc_time CheckerWideIO2::timeToSatisfyConstraints(Command command, const tlm_gene void CheckerWideIO2::insert(Command command, const tlm_generic_payload& payload) { - Rank rank = DramExtension::getRank(payload); - Bank bank = DramExtension::getBank(payload); + Rank rank = ControllerExtension::getRank(payload); + Bank bank = ControllerExtension::getBank(payload); PRINTDEBUGMESSAGE("CheckerWideIO2", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + command.toString()); diff --git a/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.cpp b/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.cpp index 7ff7181c..151b34dc 100644 --- a/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.cpp +++ b/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.cpp @@ -52,7 +52,7 @@ CommandTuple::Type CmdMuxOldest::selectCommand(const ReadyCommands &readyCommand { newTimestamp = std::get(*it) + memSpec.getCommandLength(std::get(*it)); - newPayloadID = DramExtension::getChannelPayloadID(*std::get(*it)); + newPayloadID = ControllerExtension::getChannelPayloadID(*std::get(*it)); if (newTimestamp < lastTimestamp) { @@ -108,7 +108,7 @@ CommandTuple::Type CmdMuxOldestRasCas::selectCommand(const ReadyCommands &readyC { newTimestamp = std::get(*it) + memSpec.getCommandLength(std::get(*it)); - newPayloadID = DramExtension::getChannelPayloadID(*std::get(*it)); + newPayloadID = ControllerExtension::getChannelPayloadID(*std::get(*it)); if (newTimestamp < lastTimestamp) { @@ -130,7 +130,7 @@ CommandTuple::Type CmdMuxOldestRasCas::selectCommand(const ReadyCommands &readyC { newTimestamp = std::get(*it) + memSpec.getCommandLength(std::get(*it)); - newPayloadID = DramExtension::getChannelPayloadID(*std::get(*it)); + newPayloadID = ControllerExtension::getChannelPayloadID(*std::get(*it)); if (newTimestamp < lastTimestamp) { @@ -158,7 +158,7 @@ CommandTuple::Type CmdMuxOldestRasCas::selectCommand(const ReadyCommands &readyC for (auto it = readyRasCasCommands.cbegin(); it != readyRasCasCommands.cend(); it++) { newTimestamp = std::get(*it); - newPayloadID = DramExtension::getChannelPayloadID(*std::get(*it)); + newPayloadID = ControllerExtension::getChannelPayloadID(*std::get(*it)); if (newTimestamp < lastTimestamp) { diff --git a/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp b/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp index d046b161..9f3dd176 100644 --- a/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp +++ b/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp @@ -52,7 +52,7 @@ CommandTuple::Type CmdMuxStrict::selectCommand(const ReadyCommands &readyCommand { newTimestamp = std::get(*it) + memSpec.getCommandLength(std::get(*it)); - newPayloadID = DramExtension::getChannelPayloadID(*std::get(*it)); + newPayloadID = ControllerExtension::getChannelPayloadID(*std::get(*it)); if (newTimestamp < lastTimestamp) { @@ -118,7 +118,7 @@ CommandTuple::Type CmdMuxStrictRasCas::selectCommand(const ReadyCommands &readyC { newTimestamp = std::get(*it) + memSpec.getCommandLength(std::get(*it)); - newPayloadID = DramExtension::getChannelPayloadID(*std::get(*it)); + newPayloadID = ControllerExtension::getChannelPayloadID(*std::get(*it)); if (newTimestamp < lastTimestamp) { @@ -135,7 +135,7 @@ CommandTuple::Type CmdMuxStrictRasCas::selectCommand(const ReadyCommands &readyC for (auto it = readyCasCommands.cbegin(); it != readyCasCommands.cend(); it++) { - newPayloadID = DramExtension::getChannelPayloadID(*std::get(*it)); + newPayloadID = ControllerExtension::getChannelPayloadID(*std::get(*it)); if (newPayloadID == nextPayloadID) { @@ -157,7 +157,7 @@ CommandTuple::Type CmdMuxStrictRasCas::selectCommand(const ReadyCommands &readyC for (auto it = readyRasCasCommands.cbegin(); it != readyRasCasCommands.cend(); it++) { newTimestamp = std::get(*it); - newPayloadID = DramExtension::getChannelPayloadID(*std::get(*it)); + newPayloadID = ControllerExtension::getChannelPayloadID(*std::get(*it)); if (newTimestamp < lastTimestamp) { diff --git a/DRAMSys/library/src/controller/respqueue/RespQueueReorder.cpp b/DRAMSys/library/src/controller/respqueue/RespQueueReorder.cpp index 32793a6e..2ce372ad 100644 --- a/DRAMSys/library/src/controller/respqueue/RespQueueReorder.cpp +++ b/DRAMSys/library/src/controller/respqueue/RespQueueReorder.cpp @@ -40,7 +40,7 @@ using namespace tlm; void RespQueueReorder::insertPayload(tlm_generic_payload *payload, sc_time strobeEnd) { - buffer[DramExtension::getChannelPayloadID(*payload)] = {payload, strobeEnd}; + buffer[ControllerExtension::getChannelPayloadID(*payload)] = {payload, strobeEnd}; } tlm_generic_payload *RespQueueReorder::nextPayload() diff --git a/DRAMSys/library/src/controller/scheduler/BufferCounterBankwise.cpp b/DRAMSys/library/src/controller/scheduler/BufferCounterBankwise.cpp index a45baede..d31db7e6 100644 --- a/DRAMSys/library/src/controller/scheduler/BufferCounterBankwise.cpp +++ b/DRAMSys/library/src/controller/scheduler/BufferCounterBankwise.cpp @@ -50,7 +50,7 @@ bool BufferCounterBankwise::hasBufferSpace() const void BufferCounterBankwise::storeRequest(const tlm_generic_payload& trans) { - lastBankID = DramExtension::getBank(trans).ID(); + lastBankID = ControllerExtension::getBank(trans).ID(); numRequestsOnBank[lastBankID]++; if (trans.is_read()) numReadRequests++; @@ -60,7 +60,7 @@ void BufferCounterBankwise::storeRequest(const tlm_generic_payload& trans) void BufferCounterBankwise::removeRequest(const tlm_generic_payload& trans) { - numRequestsOnBank[DramExtension::getBank(trans).ID()]--; + numRequestsOnBank[ControllerExtension::getBank(trans).ID()]--; if (trans.is_read()) numReadRequests--; else diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp b/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp index 52cd08ed..9e1f9ede 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp @@ -59,13 +59,13 @@ bool SchedulerFifo::hasBufferSpace() const void SchedulerFifo::storeRequest(tlm_generic_payload& payload) { - buffer[DramExtension::getBank(payload).ID()].push_back(&payload); + buffer[ControllerExtension::getBank(payload).ID()].push_back(&payload); bufferCounter->storeRequest(payload); } void SchedulerFifo::removeRequest(tlm_generic_payload& payload) { - buffer[DramExtension::getBank(payload).ID()].pop_front(); + buffer[ControllerExtension::getBank(payload).ID()].pop_front(); bufferCounter->removeRequest(payload); } @@ -83,7 +83,7 @@ bool SchedulerFifo::hasFurtherRowHit(Bank bank, Row row, tlm_command command) co if (buffer[bank.ID()].size() >= 2) { tlm_generic_payload& nextRequest = *buffer[bank.ID()][1]; - if (DramExtension::getRow(nextRequest) == row) + if (ControllerExtension::getRow(nextRequest) == row) return true; } return false; diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp index 3c5d4587..dffdd224 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp @@ -59,14 +59,14 @@ bool SchedulerFrFcfs::hasBufferSpace() const void SchedulerFrFcfs::storeRequest(tlm_generic_payload& trans) { - buffer[DramExtension::getBank(trans).ID()].push_back(&trans); + buffer[ControllerExtension::getBank(trans).ID()].push_back(&trans); bufferCounter->storeRequest(trans); } void SchedulerFrFcfs::removeRequest(tlm_generic_payload& trans) { bufferCounter->removeRequest(trans); - unsigned bankID = DramExtension::getBank(trans).ID(); + unsigned bankID = ControllerExtension::getBank(trans).ID(); for (auto it = buffer[bankID].begin(); it != buffer[bankID].end(); it++) { if (*it == &trans) @@ -88,7 +88,7 @@ tlm_generic_payload *SchedulerFrFcfs::getNextRequest(const BankMachine& bankMach Row openRow = bankMachine.getOpenRow(); for (auto it : buffer[bankID]) { - if (DramExtension::getRow(*it) == openRow) + if (ControllerExtension::getRow(*it) == openRow) return it; } } @@ -103,7 +103,7 @@ bool SchedulerFrFcfs::hasFurtherRowHit(Bank bank, Row row, tlm_command command) unsigned rowHitCounter = 0; for (auto it : buffer[bank.ID()]) { - if (DramExtension::getRow(*it) == row) + if (ControllerExtension::getRow(*it) == row) { rowHitCounter++; if (rowHitCounter == 2) diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.cpp b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.cpp index b4b6320b..5d3a2b8e 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.cpp +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.cpp @@ -59,7 +59,7 @@ bool SchedulerFrFcfsGrp::hasBufferSpace() const void SchedulerFrFcfsGrp::storeRequest(tlm_generic_payload& trans) { - buffer[DramExtension::getBank(trans).ID()].push_back(&trans); + buffer[ControllerExtension::getBank(trans).ID()].push_back(&trans); bufferCounter->storeRequest(trans); } @@ -67,7 +67,7 @@ void SchedulerFrFcfsGrp::removeRequest(tlm_generic_payload& trans) { bufferCounter->removeRequest(trans); lastCommand = trans.get_command(); - unsigned bankID = DramExtension::getBank(trans).ID(); + unsigned bankID = ControllerExtension::getBank(trans).ID(); for (auto it = buffer[bankID].begin(); it != buffer[bankID].end(); it++) { if (*it == &trans) @@ -90,7 +90,7 @@ tlm_generic_payload *SchedulerFrFcfsGrp::getNextRequest(const BankMachine& bankM std::list rowHits; for (auto it : buffer[bankID]) { - if (DramExtension::getRow(*it) == openRow) + if (ControllerExtension::getRow(*it) == openRow) rowHits.push_back(it); } @@ -128,7 +128,7 @@ bool SchedulerFrFcfsGrp::hasFurtherRowHit(Bank bank, Row row, tlm_command comman unsigned rowHitCounter = 0; for (auto it : buffer[bank.ID()]) { - if (DramExtension::getRow(*it) == row) + if (ControllerExtension::getRow(*it) == row) { rowHitCounter++; if (rowHitCounter == 2) diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerGrpFrFcfs.cpp b/DRAMSys/library/src/controller/scheduler/SchedulerGrpFrFcfs.cpp index cd9f697c..35b7fa48 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerGrpFrFcfs.cpp +++ b/DRAMSys/library/src/controller/scheduler/SchedulerGrpFrFcfs.cpp @@ -63,9 +63,9 @@ bool SchedulerGrpFrFcfs::hasBufferSpace() const void SchedulerGrpFrFcfs::storeRequest(tlm_generic_payload& trans) { if (trans.is_read()) - readBuffer[DramExtension::getBank(trans).ID()].push_back(&trans); + readBuffer[ControllerExtension::getBank(trans).ID()].push_back(&trans); else - writeBuffer[DramExtension::getBank(trans).ID()].push_back(&trans); + writeBuffer[ControllerExtension::getBank(trans).ID()].push_back(&trans); bufferCounter->storeRequest(trans); } @@ -73,7 +73,7 @@ void SchedulerGrpFrFcfs::removeRequest(tlm_generic_payload& trans) { bufferCounter->removeRequest(trans); lastCommand = trans.get_command(); - unsigned bankID = DramExtension::getBank(trans).ID(); + unsigned bankID = ControllerExtension::getBank(trans).ID(); if (trans.is_read()) readBuffer[bankID].remove(&trans); @@ -97,7 +97,7 @@ tlm_generic_payload *SchedulerGrpFrFcfs::getNextRequest(const BankMachine& bankM Row openRow = bankMachine.getOpenRow(); for (auto it : readBuffer[bankID]) { - if (DramExtension::getRow(*it) == openRow) + if (ControllerExtension::getRow(*it) == openRow) return it; } } @@ -112,7 +112,7 @@ tlm_generic_payload *SchedulerGrpFrFcfs::getNextRequest(const BankMachine& bankM Row openRow = bankMachine.getOpenRow(); for (auto it : writeBuffer[bankID]) { - if (DramExtension::getRow(*it) == openRow) + if (ControllerExtension::getRow(*it) == openRow) return it; } } @@ -132,7 +132,7 @@ tlm_generic_payload *SchedulerGrpFrFcfs::getNextRequest(const BankMachine& bankM Row openRow = bankMachine.getOpenRow(); for (auto it : writeBuffer[bankID]) { - if (DramExtension::getRow(*it) == openRow) + if (ControllerExtension::getRow(*it) == openRow) return it; } } @@ -147,7 +147,7 @@ tlm_generic_payload *SchedulerGrpFrFcfs::getNextRequest(const BankMachine& bankM Row openRow = bankMachine.getOpenRow(); for (auto it : readBuffer[bankID]) { - if (DramExtension::getRow(*it) == openRow) + if (ControllerExtension::getRow(*it) == openRow) return it; } } @@ -167,7 +167,7 @@ bool SchedulerGrpFrFcfs::hasFurtherRowHit(Bank bank, Row row, tlm_command comman { for (auto it : readBuffer[bank.ID()]) { - if (DramExtension::getRow(*it) == row) + if (ControllerExtension::getRow(*it) == row) { rowHitCounter++; if (rowHitCounter == 2) @@ -180,7 +180,7 @@ bool SchedulerGrpFrFcfs::hasFurtherRowHit(Bank bank, Row row, tlm_command comman { for (auto it : writeBuffer[bank.ID()]) { - if (DramExtension::getRow(*it) == row) + if (ControllerExtension::getRow(*it) == row) { rowHitCounter++; if (rowHitCounter == 2) diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerGrpFrFcfsWm.cpp b/DRAMSys/library/src/controller/scheduler/SchedulerGrpFrFcfsWm.cpp index c6adda13..6a4a8971 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerGrpFrFcfsWm.cpp +++ b/DRAMSys/library/src/controller/scheduler/SchedulerGrpFrFcfsWm.cpp @@ -67,9 +67,9 @@ bool SchedulerGrpFrFcfsWm::hasBufferSpace() const void SchedulerGrpFrFcfsWm::storeRequest(tlm_generic_payload& trans) { if (trans.is_read()) - readBuffer[DramExtension::getBank(trans).ID()].push_back(&trans); + readBuffer[ControllerExtension::getBank(trans).ID()].push_back(&trans); else - writeBuffer[DramExtension::getBank(trans).ID()].push_back(&trans); + writeBuffer[ControllerExtension::getBank(trans).ID()].push_back(&trans); bufferCounter->storeRequest(trans); evaluateWriteMode(); } @@ -77,7 +77,7 @@ void SchedulerGrpFrFcfsWm::storeRequest(tlm_generic_payload& trans) void SchedulerGrpFrFcfsWm::removeRequest(tlm_generic_payload& trans) { bufferCounter->removeRequest(trans); - unsigned bankID = DramExtension::getBank(trans).ID(); + unsigned bankID = ControllerExtension::getBank(trans).ID(); if (trans.is_read()) readBuffer[bankID].remove(&trans); @@ -101,7 +101,7 @@ tlm_generic_payload *SchedulerGrpFrFcfsWm::getNextRequest(const BankMachine& ban Row openRow = bankMachine.getOpenRow(); for (auto it : readBuffer[bankID]) { - if (DramExtension::getRow(*it) == openRow) + if (ControllerExtension::getRow(*it) == openRow) return it; } } @@ -121,7 +121,7 @@ tlm_generic_payload *SchedulerGrpFrFcfsWm::getNextRequest(const BankMachine& ban Row openRow = bankMachine.getOpenRow(); for (auto it : writeBuffer[bankID]) { - if (DramExtension::getRow(*it) == openRow) + if (ControllerExtension::getRow(*it) == openRow) return it; } } @@ -140,7 +140,7 @@ bool SchedulerGrpFrFcfsWm::hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command { for (const auto* it : readBuffer[bank.ID()]) { - if (DramExtension::getRow(*it) == row) + if (ControllerExtension::getRow(*it) == row) { rowHitCounter++; if (rowHitCounter == 2) @@ -153,7 +153,7 @@ bool SchedulerGrpFrFcfsWm::hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command { for (auto it : writeBuffer[bank.ID()]) { - if (DramExtension::getRow(*it) == row) + if (ControllerExtension::getRow(*it) == row) { rowHitCounter++; if (rowHitCounter == 2) diff --git a/DRAMSys/library/src/error/errormodel.cpp b/DRAMSys/library/src/error/errormodel.cpp index ccbfde86..e9a6782f 100644 --- a/DRAMSys/library/src/error/errormodel.cpp +++ b/DRAMSys/library/src/error/errormodel.cpp @@ -158,11 +158,13 @@ void errorModel::store(tlm::tlm_generic_payload &trans) markBitFlips(); // Get the key for the dataMap from the transaction's dram extension: - DramExtension &ext = DramExtension::getExtension(trans); - DecodedAddress key = DecodedAddress(ext.getChannel().ID(), ext.getRank().ID(), - ext.getBankGroup().ID(), ext.getBank().ID(), - ext.getRow().ID(), ext.getColumn().ID(), 0); - // Set context: + // FIXME +// ControllerExtension &ext = ControllerExtension::getExtension(trans); +// DecodedAddress key = DecodedAddress(ext.getChannel().ID(), ext.getRank().ID(), +// ext.getBankGroup().ID(), ext.getBank().ID(), +// ext.getRow().ID(), ext.getColumn().ID(), 0); + DecodedAddress key; +// Set context: setContext(key); std::stringstream msg; @@ -226,11 +228,12 @@ void errorModel::load(tlm::tlm_generic_payload &trans) markBitFlips(); // Get the key for the dataMap from the transaction's dram extension: - DramExtension &ext = DramExtension::getExtension(trans); - DecodedAddress key = DecodedAddress(ext.getChannel().ID(), ext.getRank().ID(), - ext.getBankGroup().ID(), ext.getBank().ID(), - ext.getRow().ID(), ext.getColumn().ID(), 0); - + // FIXME +// DramExtension &ext = DramExtension::getExtension(trans); +// DecodedAddress key = DecodedAddress(ext.getChannel().ID(), ext.getRank().ID(), +// ext.getBankGroup().ID(), ext.getBank().ID(), +// ext.getRow().ID(), ext.getColumn().ID(), 0); + DecodedAddress key; // Set context: setContext(key); diff --git a/DRAMSys/library/src/simulation/Arbiter.cpp b/DRAMSys/library/src/simulation/Arbiter.cpp index 9bbf1992..57c545bf 100644 --- a/DRAMSys/library/src/simulation/Arbiter.cpp +++ b/DRAMSys/library/src/simulation/Arbiter.cpp @@ -138,12 +138,8 @@ tlm_sync_enum Arbiter::nb_transport_fw(int id, tlm_generic_payload &payload, uint64_t adjustedAddress = payload.get_address() - addressOffset; payload.set_address(adjustedAddress); - DecodedAddress decodedAddress = addressDecoder.decodeAddress(adjustedAddress); - DramExtension::setExtension(payload, Thread(static_cast(id)), Channel(decodedAddress.channel), - Rank(decodedAddress.rank), - BankGroup(decodedAddress.bankgroup), Bank(decodedAddress.bank), - Row(decodedAddress.row), Column(decodedAddress.column), - payload.get_data_length() / bytesPerBeat, 0, 0); + unsigned channel = addressDecoder.decodeChannel(adjustedAddress); + ArbiterExtension::setAutoExtension(payload, Thread(id), Channel(channel)); payload.acquire(); } @@ -172,14 +168,12 @@ unsigned int Arbiter::transport_dbg(int /*id*/, tlm::tlm_generic_payload &trans) void ArbiterSimple::peqCallback(tlm_generic_payload &cbPayload, const tlm_phase &cbPhase) { - unsigned int threadId = DramExtension::getExtension(cbPayload).getThread().ID(); - unsigned int channelId = DramExtension::getExtension(cbPayload).getChannel().ID(); + unsigned int threadId = ArbiterExtension::getThread(cbPayload).ID(); + unsigned int channelId = ArbiterExtension::getChannel(cbPayload).ID(); if (cbPhase == BEGIN_REQ) // from initiator { - GenerationExtension::setExtension(cbPayload, sc_time_stamp()); - DramExtension::setPayloadIDs(cbPayload, - nextThreadPayloadIDToAppend[threadId]++, nextChannelPayloadIDToAppend[channelId]++); + ArbiterExtension::setIDAndTimeOfGeneration(cbPayload, nextThreadPayloadIDToAppend[threadId]++, sc_time_stamp()); if (!channelIsBusy[channelId]) { @@ -263,8 +257,8 @@ void ArbiterSimple::peqCallback(tlm_generic_payload &cbPayload, const tlm_phase void ArbiterFifo::peqCallback(tlm_generic_payload &cbPayload, const tlm_phase &cbPhase) { - unsigned int threadId = DramExtension::getExtension(cbPayload).getThread().ID(); - unsigned int channelId = DramExtension::getExtension(cbPayload).getChannel().ID(); + unsigned int threadId = ArbiterExtension::getThread(cbPayload).ID(); + unsigned int channelId = ArbiterExtension::getChannel(cbPayload).ID(); if (cbPhase == BEGIN_REQ) // from initiator { @@ -272,9 +266,8 @@ void ArbiterFifo::peqCallback(tlm_generic_payload &cbPayload, const tlm_phase &c { activeTransactions[threadId]++; - GenerationExtension::setExtension(cbPayload, sc_time_stamp()); - DramExtension::setPayloadIDs(cbPayload, - nextThreadPayloadIDToAppend[threadId]++, nextChannelPayloadIDToAppend[channelId]++); + ArbiterExtension::setIDAndTimeOfGeneration(cbPayload, nextThreadPayloadIDToAppend[threadId]++, + sc_time_stamp()); tlm_phase tPhase = END_REQ; sc_time tDelay = SC_ZERO_TIME; @@ -325,11 +318,9 @@ void ArbiterFifo::peqCallback(tlm_generic_payload &cbPayload, const tlm_phase &c outstandingEndReq[threadId] = nullptr; tlm_phase tPhase = END_REQ; sc_time tDelay = SC_ZERO_TIME; - unsigned int tChannelId = DramExtension::getExtension(tPayload).getChannel().ID(); - GenerationExtension::setExtension(tPayload, sc_time_stamp()); - DramExtension::setPayloadIDs(tPayload, - nextThreadPayloadIDToAppend[threadId]++, nextChannelPayloadIDToAppend[tChannelId]++); + ArbiterExtension::setIDAndTimeOfGeneration(tPayload, nextThreadPayloadIDToAppend[threadId]++, + sc_time_stamp()); tSocket[static_cast(threadId)]->nb_transport_bw(tPayload, tPhase, tDelay); @@ -394,8 +385,8 @@ void ArbiterFifo::peqCallback(tlm_generic_payload &cbPayload, const tlm_phase &c void ArbiterReorder::peqCallback(tlm_generic_payload &cbPayload, const tlm_phase &cbPhase) { - unsigned int threadId = DramExtension::getExtension(cbPayload).getThread().ID(); - unsigned int channelId = DramExtension::getExtension(cbPayload).getChannel().ID(); + unsigned int threadId = ArbiterExtension::getThread(cbPayload).ID(); + unsigned int channelId = ArbiterExtension::getChannel(cbPayload).ID(); if (cbPhase == BEGIN_REQ) // from initiator { @@ -403,9 +394,8 @@ void ArbiterReorder::peqCallback(tlm_generic_payload &cbPayload, const tlm_phase { activeTransactions[threadId]++; - GenerationExtension::setExtension(cbPayload, sc_time_stamp()); - DramExtension::setPayloadIDs(cbPayload, - nextThreadPayloadIDToAppend[threadId]++, nextChannelPayloadIDToAppend[channelId]++); + ArbiterExtension::setIDAndTimeOfGeneration(cbPayload, nextThreadPayloadIDToAppend[threadId]++, + sc_time_stamp()); tlm_phase tPhase = END_REQ; sc_time tDelay = SC_ZERO_TIME; @@ -455,11 +445,9 @@ void ArbiterReorder::peqCallback(tlm_generic_payload &cbPayload, const tlm_phase outstandingEndReq[threadId] = nullptr; tlm_phase tPhase = END_REQ; sc_time tDelay = SC_ZERO_TIME; - unsigned int tChannelId = DramExtension::getExtension(tPayload).getChannel().ID(); - GenerationExtension::setExtension(tPayload, sc_time_stamp()); - DramExtension::setPayloadIDs(tPayload, - nextThreadPayloadIDToAppend[threadId]++, nextChannelPayloadIDToAppend[tChannelId]++); + ArbiterExtension::setIDAndTimeOfGeneration(tPayload, nextThreadPayloadIDToAppend[threadId]++, + sc_time_stamp()); tSocket[static_cast(threadId)]->nb_transport_bw(tPayload, tPhase, tDelay); @@ -471,7 +459,7 @@ void ArbiterReorder::peqCallback(tlm_generic_payload &cbPayload, const tlm_phase tlm_generic_payload &tPayload = **pendingResponses[threadId].begin(); if (!pendingResponses[threadId].empty() && - DramExtension::getThreadPayloadID(tPayload) == nextThreadPayloadIDToReturn[threadId]) + ArbiterExtension::getThreadPayloadID(tPayload) == nextThreadPayloadIDToReturn[threadId]) { nextThreadPayloadIDToReturn[threadId]++; pendingResponses[threadId].erase(pendingResponses[threadId].begin()); @@ -511,7 +499,7 @@ void ArbiterReorder::peqCallback(tlm_generic_payload &cbPayload, const tlm_phase { tlm_generic_payload &tPayload = **pendingResponses[threadId].begin(); - if (DramExtension::getThreadPayloadID(tPayload) == nextThreadPayloadIDToReturn[threadId]) + if (ArbiterExtension::getThreadPayloadID(tPayload) == nextThreadPayloadIDToReturn[threadId]) { threadIsBusy[threadId] = true; diff --git a/DRAMSys/library/src/simulation/Arbiter.h b/DRAMSys/library/src/simulation/Arbiter.h index 799ab27c..f99e997e 100644 --- a/DRAMSys/library/src/simulation/Arbiter.h +++ b/DRAMSys/library/src/simulation/Arbiter.h @@ -149,7 +149,7 @@ private: { bool operator() (const tlm::tlm_generic_payload *lhs, const tlm::tlm_generic_payload *rhs) const { - return DramExtension::getThreadPayloadID(*lhs) < DramExtension::getThreadPayloadID(*rhs); + return ArbiterExtension::getThreadPayloadID(*lhs) < ArbiterExtension::getThreadPayloadID(*rhs); } }; diff --git a/DRAMSys/library/src/simulation/dram/Dram.cpp b/DRAMSys/library/src/simulation/dram/Dram.cpp index e75096d8..d90fd06d 100644 --- a/DRAMSys/library/src/simulation/dram/Dram.cpp +++ b/DRAMSys/library/src/simulation/dram/Dram.cpp @@ -124,7 +124,7 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload, if (powerAnalysis) { - int bank = static_cast(DramExtension::getExtension(payload).getBank().ID()); + int bank = static_cast(ControllerExtension::getBank(payload).ID()); int64_t cycle = std::lround((sc_time_stamp() + delay) / memSpec.tCK); DRAMPower->doCommand(phaseToDRAMPowerCommand(phase), bank, cycle); } diff --git a/DRAMSys/library/src/simulation/dram/DramRecordable.cpp b/DRAMSys/library/src/simulation/dram/DramRecordable.cpp index 90c75dd2..a64e71c4 100644 --- a/DRAMSys/library/src/simulation/dram/DramRecordable.cpp +++ b/DRAMSys/library/src/simulation/dram/DramRecordable.cpp @@ -93,12 +93,12 @@ void DramRecordable::recordPhase(tlm_generic_payload &trans, const tlm if (phase == END_PDNA || phase == END_PDNP || phase == END_SREF) recTime += this->memSpec.getCommandLength(Command(phase)); - NDEBUG_UNUSED(unsigned thr) = DramExtension::getExtension(trans).getThread().ID(); - NDEBUG_UNUSED(unsigned ch) = DramExtension::getExtension(trans).getChannel().ID(); - NDEBUG_UNUSED(unsigned bg) = DramExtension::getExtension(trans).getBankGroup().ID(); - NDEBUG_UNUSED(unsigned bank) = DramExtension::getExtension(trans).getBank().ID(); - NDEBUG_UNUSED(unsigned row) = DramExtension::getExtension(trans).getRow().ID(); - NDEBUG_UNUSED(unsigned col) = DramExtension::getExtension(trans).getColumn().ID(); + NDEBUG_UNUSED(unsigned thr) = ArbiterExtension::getExtension(trans).getThread().ID(); + NDEBUG_UNUSED(unsigned ch) = ArbiterExtension::getExtension(trans).getChannel().ID(); + NDEBUG_UNUSED(unsigned bg) = ControllerExtension::getExtension(trans).getBankGroup().ID(); + NDEBUG_UNUSED(unsigned bank) = ControllerExtension::getExtension(trans).getBank().ID(); + NDEBUG_UNUSED(unsigned row) = ControllerExtension::getExtension(trans).getRow().ID(); + NDEBUG_UNUSED(unsigned col) = ControllerExtension::getExtension(trans).getColumn().ID(); PRINTDEBUGMESSAGE(this->name(), "Recording " + getPhaseName(phase) + " thread " + std::to_string(thr) + " channel " + std::to_string(ch) + " bank group " + std::to_string( diff --git a/DRAMSys/library/src/simulation/dram/DramWideIO.cpp b/DRAMSys/library/src/simulation/dram/DramWideIO.cpp index eb3b6f4e..e96e4760 100644 --- a/DRAMSys/library/src/simulation/dram/DramWideIO.cpp +++ b/DRAMSys/library/src/simulation/dram/DramWideIO.cpp @@ -176,7 +176,7 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, if (powerAnalysis) { - int bank = static_cast(DramExtension::getExtension(payload).getBank().ID()); + int bank = static_cast(ControllerExtension::getBank(payload).ID()); int64_t cycle = std::lround((sc_time_stamp() + delay) / memSpec.tCK); DRAMPower->doCommand(phaseToDRAMPowerCommand(phase), bank, cycle); } @@ -197,16 +197,16 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, else if (storeMode == Configuration::StoreMode::ErrorModel) { // TODO: delay should be considered here! - unsigned bank = DramExtension::getExtension(payload).getBank().ID(); + unsigned bank = ControllerExtension::getBank(payload).ID(); if (phase == BEGIN_ACT) - ememory[bank]->activate(DramExtension::getExtension(payload).getRow().ID()); + ememory[bank]->activate(ControllerExtension::getRow(payload).ID()); else if (phase == BEGIN_RD || phase == BEGIN_RDA) ememory[bank]->load(payload); else if (phase == BEGIN_WR || phase == BEGIN_WRA) ememory[bank]->store(payload); else if (phase == BEGIN_REFAB) - ememory[bank]->refresh(DramExtension::getExtension(payload).getRow().ID()); + ememory[bank]->refresh(ControllerExtension::getRow(payload).ID()); } return TLM_ACCEPTED;