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This commit is contained in:
Lukas Steiner
2023-09-21 16:50:59 +02:00
parent 7eea9c54e0
commit 8224e97abe
44 changed files with 1992 additions and 1097 deletions
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60
tests/tests_configuration/test_configuration.cpp
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@@ -46,12 +46,12 @@ using namespace DRAMSys::Config;
class ConfigurationTest : public ::testing::Test
{
protected:
ConfigurationTest()
: memSpec(createMemSpec()),
tracePlayer(createTracePlayer()),
traceGeneratorOneState(createTraceGeneratorOneState()),
traceGeneratorMultipleStates(createTraceGeneratorMultipleStates()),
traceHammer(createTraceHammer())
ConfigurationTest() :
memSpec(createMemSpec()),
tracePlayer(createTracePlayer()),
traceGeneratorOneState(createTraceGeneratorOneState()),
traceGeneratorMultipleStates(createTraceGeneratorMultipleStates()),
traceHammer(createTraceHammer())
{
}
@@ -118,38 +118,33 @@ protected:
DRAMSys::Config::TrafficGenerator traceGeneratorOneState;
DRAMSys::Config::TrafficGeneratorStateMachine traceGeneratorMultipleStates;
DRAMSys::Config::RowHammer traceHammer;
std::vector<DRAMSys::Config::Initiator> traceSetup{{tracePlayer, traceGeneratorOneState, traceGeneratorMultipleStates, traceHammer}};
std::vector<DRAMSys::Config::Initiator> traceSetup{
{tracePlayer, traceGeneratorOneState, traceGeneratorMultipleStates, traceHammer}};
DRAMSys::Config::Configuration configuration{
addressMapping,
mcConfig,
memSpec,
simConfig,
"std::string_simulationId",
traceSetup
};
addressMapping, mcConfig, memSpec, simConfig, "std::string_simulationId", traceSetup};
};
DRAMSys::Config::MemSpec ConfigurationTest::createMemSpec()
{
MemArchitectureSpecType memArchitectureSpec{{{"burstLength", 16},
{"dataRate", 2},
{"nbrOfBankGroups", 8},
{"nbrOfBanks", 16},
{"nbrOfColumns", 2048},
{"nbrOfRanks", 1},
{"nbrOfDIMMRanks", 1},
{"nbrOfPhysicalRanks", 1},
{"nbrOfLogicalRanks", 1},
{"nbrOfRows", 65536},
{"width", 4},
{"nbrOfDevices", 8},
{"nbrOfChannels", 2},
{"cmdMode", 1},
{"refMode", 1},
{"RAAIMT", 32},
{"RAAMMT", 96},
{"RAADEC", 1}}};
{"dataRate", 2},
{"nbrOfBankGroups", 8},
{"nbrOfBanks", 16},
{"nbrOfColumns", 2048},
{"nbrOfRanks", 1},
{"nbrOfDIMMRanks", 1},
{"nbrOfPhysicalRanks", 1},
{"nbrOfLogicalRanks", 1},
{"nbrOfRows", 65536},
{"width", 4},
{"nbrOfDevices", 8},
{"nbrOfChannels", 2},
{"cmdMode", 1},
{"refMode", 1},
{"RAAIMT", 32},
{"RAAMMT", 96},
{"RAADEC", 1}}};
MemTimingSpecType memTimingSpec{{{
{"RCD", 22}, {"PPD", 2}, {"RP", 22}, {"RAS", 52},
@@ -195,7 +190,8 @@ DRAMSys::Config::TrafficGenerator ConfigurationTest::createTraceGeneratorOneStat
return gen;
}
DRAMSys::Config::TrafficGeneratorStateMachine ConfigurationTest::createTraceGeneratorMultipleStates()
DRAMSys::Config::TrafficGeneratorStateMachine
ConfigurationTest::createTraceGeneratorMultipleStates()
{
DRAMSys::Config::TrafficGeneratorStateMachine gen;