diff --git a/DRAM/.cproject b/DRAM/.cproject index e0f0123c..256a525f 100644 --- a/DRAM/.cproject +++ b/DRAM/.cproject @@ -3,18 +3,23 @@ - + + + + + + + - - + @@ -25,8 +30,8 @@ @@ -64,7 +69,6 @@ - @@ -143,6 +147,75 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -170,6 +243,7 @@ + diff --git a/DRAM/.settings/language.settings.xml b/DRAM/.settings/language.settings.xml index 80ac5003..083c69ba 100644 --- a/DRAM/.settings/language.settings.xml +++ b/DRAM/.settings/language.settings.xml @@ -20,4 +20,14 @@ + + + + + + + + + + diff --git a/DRAM/src/core/CommandBus.cpp b/DRAM/src/core/CommandBus.cpp index 9db270d5..abc94be2 100644 --- a/DRAM/src/core/CommandBus.cpp +++ b/DRAM/src/core/CommandBus.cpp @@ -14,7 +14,8 @@ void CommandBus::schedule(const CommandSchedule& schedule) { const std::vector& commands = schedule.getScheduledCommands(); - for(std::vector::const_iterator it = commands.begin();it != commands.end();++it) + for (std::vector::const_iterator it = commands.begin(); it != commands.end(); + ++it) { scheduleCommand(*it); } @@ -27,112 +28,132 @@ void CommandBus::scheduleCommand(const ScheduledCommand& command) changeControllerState(command); pendingBusCommands.insert(command.getStart()); - wrapper.sendCommand(command.getStart(),command.getTransaction(),command.getCommand()); + notifyAllCheckersAboutScheduledCommand(command); + + wrapper.sendCommand(command.getStart(), command.getTransaction(), command.getCommand()); lastCommandsOnBus[command.getCommand()][command.getBank()] = command; lastCommandsOnBus[command.getCommand()][command.getBank()].invalidateTransaction(); +} +void CommandBus::notifyAllCheckersAboutScheduledCommand(const ScheduledCommand& command) +{ + for (std::vector::iterator it = checker.begin(); it != checker.end(); ++it) + { + (*it)->notifyAboutScheduledCommand(command); + } } void CommandBus::scheduleTrigger(const Trigger command, sc_time time) { - wrapper.sendTrigger(time,command); + wrapper.sendTrigger(time, command); } -ScheduledCommand& CommandBus::getLastCommand(Command command, Bank bank) +ScheduledCommand CommandBus::getLastCommand(Command command, Bank bank) { return lastCommandsOnBus[command][bank]; } -ScheduledCommand& CommandBus::getLastCommand(Command command) +ScheduledCommand CommandBus::getLastCommand(Command command) { - ScheduledCommand* max = &getLastCommand(command, Bank(0)); + ScheduledCommand max; for (unsigned int i = 0; i < config.numberOfBanks; ++i) { - ScheduledCommand* current = &getLastCommand(command, Bank(i)); - if (current->getStart() > max->getStart()) + const ScheduledCommand& current = getLastCommand(command, Bank(i)); + if (current.getStart() > max.getStart()) max = current; } - return *max; + return max; +} + +ScheduledCommand CommandBus::getLastCommand(Bank bank) +{ + ScheduledCommand lastCommand; + for(std::map >::iterator it = lastCommandsOnBus.begin(); it != lastCommandsOnBus.end(); ++it) + { + ScheduledCommand& current = lastCommandsOnBus[it->first][bank]; + if(current.getStart() > lastCommand.getStart()) + lastCommand = current; + } + return lastCommand; } bool CommandBus::notYetScheduled(Command command) const { - return (lastCommandsOnBus.count(command) == 0); +return (lastCommandsOnBus.count(command) == 0); } bool CommandBus::notYetScheduled(Command command, Bank bank) const { - return (notYetScheduled(command) || lastCommandsOnBus.find(command)->second.count(bank) == 0); +return (notYetScheduled(command) || lastCommandsOnBus.find(command)->second.count(bank) == 0); } sc_time CommandBus::getEarliestStartTime(const ScheduledCommand& command) const { - sc_time newStart = command.getStart(); - assert(isClkAligned(newStart, config.Timings.clk)); - std::set::iterator it = pendingBusCommands.begin(); - while (it != pendingBusCommands.end() && *it <= newStart) - { - if (*it == newStart) - newStart += config.Timings.clk; - ++it; - } - return newStart; +sc_time newStart = command.getStart(); +assert(isClkAligned(newStart, config.Timings.clk)); +std::set::iterator it = pendingBusCommands.begin(); +while (it != pendingBusCommands.end() && *it <= newStart) +{ + if (*it == newStart) + newStart += config.Timings.clk; + ++it; +} +return newStart; } void CommandBus::cleanUpBus(sc_time currentTime) { - pendingBusCommands.erase(pendingBusCommands.begin(), - pendingBusCommands.lower_bound(currentTime)); +pendingBusCommands.erase(pendingBusCommands.begin(), pendingBusCommands.lower_bound(currentTime)); } void CommandBus::changeControllerState(const ScheduledCommand& command) { - switch (command.getCommand()) - { - case Refresh: - refresh(command); - break; - case Activate: - activate(command); - break; - case Precharge: - precharge(command); - default: - break; - } +switch (command.getCommand()) +{ + case Refresh: + refresh(command); + break; + case Activate: + activate(command); + break; + case Precharge: + precharge(command); + default: + break; +} } void CommandBus::refresh(const ScheduledCommand& command) { - if(config.RefreshBankwise) - { - state.bankStates.closeRowBuffer(command.getBank()); - } - else - { - state.bankStates.closeAllRowBuffers(); - } +if (config.RefreshBankwise) +{ + state.bankStates.closeRowBuffer(command.getBank()); +} +else +{ + state.bankStates.closeAllRowBuffers(); +} } void CommandBus::precharge(const ScheduledCommand& command) { - if(command.getCommand() == Precharge) - { - state.bankStates.closeRowBuffer(command.getBank()); - } - else if(command.getCommand() == PrechargeAll) - { - state.bankStates.closeAllRowBuffers(); - } +if (command.getCommand() == Precharge) +{ + state.bankStates.closeRowBuffer(command.getBank()); +} +else if (command.getCommand() == PrechargeAll) +{ + state.bankStates.closeAllRowBuffers(); +} } void CommandBus::activate(const ScheduledCommand& command) { - if(command.getCommand() == Activate) - { - state.bankStates.openRowInRowBuffer(command.getBank(), command.getRow()); - } +if (command.getCommand() == Activate) +{ + state.bankStates.openRowInRowBuffer(command.getBank(), command.getRow()); +} } } /* namespace controller */ diff --git a/DRAM/src/core/CommandBus.h b/DRAM/src/core/CommandBus.h index e70a4b0d..7c7e9853 100644 --- a/DRAM/src/core/CommandBus.h +++ b/DRAM/src/core/CommandBus.h @@ -35,8 +35,10 @@ public: void cleanUpBus(sc_time currentTime); - ScheduledCommand& getLastCommand(Command command, Bank bank); //TODO simple way to make it const? - ScheduledCommand& getLastCommand(Command command); + ScheduledCommand getLastCommand(Command command, Bank bank); //TODO simple way to make it const? + ScheduledCommand getLastCommand(Command command); + ScheduledCommand getLastCommand(Bank bank); + bool notYetScheduled(Command command) const; bool notYetScheduled(Command command, Bank bank) const; sc_time getEarliestStartTime(const ScheduledCommand& command) const; @@ -55,6 +57,7 @@ private: std::map > lastCommandsOnBus; std::set pendingBusCommands; + void notifyAllCheckersAboutScheduledCommand(const ScheduledCommand& command); void changeControllerState(const ScheduledCommand& command); void refresh(const ScheduledCommand& command); void precharge(const ScheduledCommand& command); diff --git a/DRAM/src/core/Configuration.h b/DRAM/src/core/Configuration.h index df838d22..f5af040c 100644 --- a/DRAM/src/core/Configuration.h +++ b/DRAM/src/core/Configuration.h @@ -15,14 +15,14 @@ namespace core{ struct Configuration { - Configuration(): numberOfBanks(8),Timings(numberOfBanks), RefreshBankwise(false), - nActivate(4) + Configuration(): numberOfBanks(8),Timings(numberOfBanks), RefreshBankwise(false),buswidth(128), + nActivate(2) {} unsigned int numberOfBanks; TimingConfiguration Timings; bool RefreshBankwise; - + unsigned int buswidth; unsigned int nActivate; }; diff --git a/DRAM/src/core/TimingConfiguration.h b/DRAM/src/core/TimingConfiguration.h index 465f736f..05584260 100644 --- a/DRAM/src/core/TimingConfiguration.h +++ b/DRAM/src/core/TimingConfiguration.h @@ -38,9 +38,11 @@ struct TimingConfiguration tRC = tRP + tRAS; //RAS-cycle-time (min time bw 2 succesive ACT to same bank) tRRD = 2*clk; //(min time bw 2 succesive ACT to different banks) - tRCD = 5*clk; //act -> read/write + tRCD = 3*clk; //act -> read/write - tTAW = clkAlign(sc_time(50, SC_NS), clk); + tRL = 3*clk; //read latency (read command start to data strobe) + + tTAW = clkAlign(sc_time(50, SC_NS), clk); //two activate window } sc_time clk; @@ -50,6 +52,7 @@ struct TimingConfiguration sc_time tRRD; sc_time tRCD; sc_time tTAW; + sc_time tRL; std::vector refreshTimings; diff --git a/DRAM/src/core/scheduling/ScheduledCommand.h b/DRAM/src/core/scheduling/ScheduledCommand.h index d6c6a86a..8a5b271e 100644 --- a/DRAM/src/core/scheduling/ScheduledCommand.h +++ b/DRAM/src/core/scheduling/ScheduledCommand.h @@ -18,11 +18,11 @@ namespace core { class ScheduledCommand { public: - static const ScheduledCommand NoCommand; ScheduledCommand(tlm::tlm_generic_payload& transaction, Command command, sc_time time, sc_time executionTime) : - transaction(&transaction), command(command), start(time), executionTime(executionTime), extension(DramExtension::getExtension(&transaction)) + transaction(&transaction), command(command), start(time), executionTime(executionTime), extension( + DramExtension::getExtension(&transaction)) { } @@ -33,7 +33,12 @@ public: bool isNoCommand() const { - return (*this == NoCommand); + return (command == NOP && start == SC_ZERO_TIME && executionTime == SC_ZERO_TIME); + } + + bool isValidCommand() const + { + return !isNoCommand(); } const sc_time getStart() const diff --git a/DRAM/src/core/scheduling/checker/ActivateChecker.cpp b/DRAM/src/core/scheduling/checker/ActivateChecker.cpp index 4505d78f..69285125 100644 --- a/DRAM/src/core/scheduling/checker/ActivateChecker.cpp +++ b/DRAM/src/core/scheduling/checker/ActivateChecker.cpp @@ -10,7 +10,6 @@ #include "core/utils/Utils.h" #include "core/scheduling/checker/ActivateChecker.h" - namespace core { void ActivateChecker::check(ScheduledCommand& command) const @@ -34,12 +33,17 @@ void ActivateChecker::check_activateToActivate(ScheduledCommand& command) const if (bus.notYetScheduled(Activate)) return; - sc_time lastActivate = bus.getLastCommand(Activate).getStart(); - sc_time lastActivateOnBank = bus.getLastCommand(Activate, command.getBank()).getStart(); + ScheduledCommand lastActivate = bus.getLastCommand(Activate); + if (lastActivate.isValidCommand()) + command.delayStart( + delayByConstraint(lastActivate.getStart(), command.getStart(), + config.Timings.tRRD)); - command.delayStart(delayByConstraint(lastActivate, command.getStart(), config.Timings.tRRD)); - command.delayStart( - delayByConstraint(lastActivateOnBank, command.getStart(), config.Timings.tRC)); + ScheduledCommand lastActivateOnBank = bus.getLastCommand(Activate, command.getBank()); + if (lastActivateOnBank.isValidCommand()) + command.delayStart( + delayByConstraint(lastActivateOnBank.getStart(), command.getStart(), + config.Timings.tRC)); } void ActivateChecker::check_prechargeToActivate(ScheduledCommand& command) const @@ -65,7 +69,7 @@ void ActivateChecker::check_bus(ScheduledCommand& command) const command.delayStart(bus.getEarliestStartTime(command) - command.getStart()); } -void ActivateChecker::cb_IInternalScheduler(const ScheduledCommand& command) +void ActivateChecker::notifyAboutScheduledCommand(const ScheduledCommand& command) { if (command.getCommand() == Activate) { diff --git a/DRAM/src/core/scheduling/checker/ActivateChecker.h b/DRAM/src/core/scheduling/checker/ActivateChecker.h index a180bf30..e9844828 100644 --- a/DRAM/src/core/scheduling/checker/ActivateChecker.h +++ b/DRAM/src/core/scheduling/checker/ActivateChecker.h @@ -19,12 +19,12 @@ namespace core { class ActivateChecker: public core::ICommandChecker { public: - ActivateChecker(Configuration& config, CommandBus& commandBus) : config(config), bus(commandBus), nActivateWindow(config.nActivate - 1){} + ActivateChecker(Configuration& config, CommandBus& commandBus) : config(config), bus(commandBus), nActivateWindow(config.nActivate){} virtual ~ActivateChecker(){} virtual void check(ScheduledCommand& command) const; virtual sc_time getExecutionTime(const tlm::tlm_generic_payload& transaction, Command command) const; - virtual void cb_IInternalScheduler(const ScheduledCommand& command); + virtual void notifyAboutScheduledCommand(const ScheduledCommand& command); private: const Configuration& config; CommandBus& bus;//TODO should be const .. but fucking map access operator!!!! diff --git a/DRAM/src/core/scheduling/checker/ICommandChecker.h b/DRAM/src/core/scheduling/checker/ICommandChecker.h index 357ada50..05dbfd74 100644 --- a/DRAM/src/core/scheduling/checker/ICommandChecker.h +++ b/DRAM/src/core/scheduling/checker/ICommandChecker.h @@ -20,7 +20,7 @@ public: virtual void check(ScheduledCommand& command) const = 0; virtual sc_time getExecutionTime(const tlm::tlm_generic_payload& transaction, Command command) const = 0; - virtual void cb_IInternalScheduler(const ScheduledCommand& command) = 0; + virtual void notifyAboutScheduledCommand(const ScheduledCommand& command) = 0; }; } /* namespace controller */ diff --git a/DRAM/src/core/scheduling/checker/PrechargeChecker.cpp b/DRAM/src/core/scheduling/checker/PrechargeChecker.cpp index cb69d26f..39231b95 100644 --- a/DRAM/src/core/scheduling/checker/PrechargeChecker.cpp +++ b/DRAM/src/core/scheduling/checker/PrechargeChecker.cpp @@ -11,6 +11,11 @@ namespace core { void PrechargeChecker::check(ScheduledCommand& command) const { + ScheduledCommand lastCommand = bus.getLastCommand(command.getBank()); + if(lastCommand.isValidCommand() && lastCommand.getEnd() > command.getStart()) + { + command.delayStart(lastCommand.getEnd()-command.getStart()); + } } sc_time PrechargeChecker::getExecutionTime(const tlm::tlm_generic_payload& transaction, @@ -19,7 +24,7 @@ sc_time PrechargeChecker::getExecutionTime(const tlm::tlm_generic_payload& trans assert(command == Precharge || command == PrechargeAll); return config.Timings.tRP; } -void PrechargeChecker::cb_IInternalScheduler(const ScheduledCommand& command) +void PrechargeChecker::notifyAboutScheduledCommand(const ScheduledCommand& command) { } diff --git a/DRAM/src/core/scheduling/checker/PrechargeChecker.h b/DRAM/src/core/scheduling/checker/PrechargeChecker.h index 5e011650..7060f97e 100644 --- a/DRAM/src/core/scheduling/checker/PrechargeChecker.h +++ b/DRAM/src/core/scheduling/checker/PrechargeChecker.h @@ -17,15 +17,15 @@ namespace core { class PrechargeChecker: public core::ICommandChecker { public: - PrechargeChecker(const Configuration& config, const CommandBus& commandBus) : config(config), bus(commandBus) {} + PrechargeChecker(const Configuration& config, CommandBus& commandBus) : config(config), bus(commandBus) {} virtual ~PrechargeChecker() {} virtual void check(ScheduledCommand& command) const; virtual sc_time getExecutionTime(const tlm::tlm_generic_payload& transaction, Command command) const; - virtual void cb_IInternalScheduler(const ScheduledCommand& command); + virtual void notifyAboutScheduledCommand(const ScheduledCommand& command); private: const Configuration& config; - const CommandBus& bus; + CommandBus& bus; }; } /* namespace controller */ diff --git a/DRAM/src/core/scheduling/checker/ReadChecker.cpp b/DRAM/src/core/scheduling/checker/ReadChecker.cpp index 3934121e..6d42ba66 100644 --- a/DRAM/src/core/scheduling/checker/ReadChecker.cpp +++ b/DRAM/src/core/scheduling/checker/ReadChecker.cpp @@ -6,21 +6,28 @@ */ #include - +#include "core/utils/Utils.h" namespace core { void ReadChecker::check(ScheduledCommand& command) const { + ScheduledCommand lastCommand = bus.getLastCommand(command.getBank()); + if(lastCommand.isValidCommand() && lastCommand.getEnd() > command.getStart()) + { + command.delayStart(lastCommand.getEnd()-command.getStart()); + } + } sc_time ReadChecker::getExecutionTime(const tlm::tlm_generic_payload& transaction, Command command) const { assert(command == Read || command == ReadA); - return config.Timings.clk*8; + //return config.Timings.tRL + config.Timings.clk*getBurstLengthInBytes(transaction, config.buswidth); + return config.Timings.tRL + config.Timings.clk*2; } -void ReadChecker::cb_IInternalScheduler(const ScheduledCommand& command) +void ReadChecker::notifyAboutScheduledCommand(const ScheduledCommand& command) { } diff --git a/DRAM/src/core/scheduling/checker/ReadChecker.h b/DRAM/src/core/scheduling/checker/ReadChecker.h index 6232ca2d..20482ede 100644 --- a/DRAM/src/core/scheduling/checker/ReadChecker.h +++ b/DRAM/src/core/scheduling/checker/ReadChecker.h @@ -17,15 +17,15 @@ namespace core { class ReadChecker: public core::ICommandChecker { public: - ReadChecker(const Configuration& config, const CommandBus& commandBus) : config(config), bus(commandBus) {} + ReadChecker(const Configuration& config, CommandBus& commandBus) : config(config), bus(commandBus) {} virtual ~ReadChecker() {} virtual void check(ScheduledCommand& command) const; virtual sc_time getExecutionTime(const tlm::tlm_generic_payload& transaction, Command command) const; - virtual void cb_IInternalScheduler(const ScheduledCommand& command); + virtual void notifyAboutScheduledCommand(const ScheduledCommand& command); private: const Configuration& config; - const CommandBus& bus; + CommandBus& bus; }; } /* namespace controller */ diff --git a/DRAM/src/core/scheduling/checker/WriteChecker.cpp b/DRAM/src/core/scheduling/checker/WriteChecker.cpp index b8544407..88968cc1 100644 --- a/DRAM/src/core/scheduling/checker/WriteChecker.cpp +++ b/DRAM/src/core/scheduling/checker/WriteChecker.cpp @@ -20,7 +20,7 @@ sc_time WriteChecker::getExecutionTime(const tlm::tlm_generic_payload& transacti return config.Timings.clk*8; } -void WriteChecker::cb_IInternalScheduler(const ScheduledCommand& command) +void WriteChecker::notifyAboutScheduledCommand(const ScheduledCommand& command) { } diff --git a/DRAM/src/core/scheduling/checker/WriteChecker.h b/DRAM/src/core/scheduling/checker/WriteChecker.h index c4c471f2..7c3a2c2e 100644 --- a/DRAM/src/core/scheduling/checker/WriteChecker.h +++ b/DRAM/src/core/scheduling/checker/WriteChecker.h @@ -22,7 +22,7 @@ public: virtual void check(ScheduledCommand& command) const; virtual sc_time getExecutionTime(const tlm::tlm_generic_payload& transaction, Command command) const; - virtual void cb_IInternalScheduler(const ScheduledCommand& command); + virtual void notifyAboutScheduledCommand(const ScheduledCommand& command); private: const Configuration& config; const CommandBus& bus; diff --git a/DRAM/src/core/utils/Utils.cpp b/DRAM/src/core/utils/Utils.cpp index 4e9c1889..7efb74dc 100644 --- a/DRAM/src/core/utils/Utils.cpp +++ b/DRAM/src/core/utils/Utils.cpp @@ -12,6 +12,10 @@ unsigned int getStartAddress(Bank bank) return 0; } +unsigned int getBurstLengthInBytes(const tlm::tlm_generic_payload& payload, unsigned int buswidth) +{ + return payload.get_data_length() / (buswidth/8); +} sc_time delayByConstraint(sc_time previous, sc_time start, sc_time constraint) { if (previous + constraint > start) diff --git a/DRAM/src/core/utils/Utils.h b/DRAM/src/core/utils/Utils.h index 7de11b41..333dc58e 100644 --- a/DRAM/src/core/utils/Utils.h +++ b/DRAM/src/core/utils/Utils.h @@ -10,8 +10,10 @@ #include "common/dramExtension.h" #include +#include unsigned int getStartAddress(Bank bank); +unsigned int getBurstLengthInBytes(const tlm::tlm_generic_payload& payload, unsigned int buswidth); sc_time delayByConstraint(sc_time previous, sc_time start, sc_time constraint); diff --git a/DRAM/src/tlm/ControllerWrapper.h b/DRAM/src/tlm/ControllerWrapper.h deleted file mode 100644 index 240db21e..00000000 --- a/DRAM/src/tlm/ControllerWrapper.h +++ /dev/null @@ -1,188 +0,0 @@ -///* -// * ControllerWrapper.h -// * -// * Created on: Mar 15, 2014 -// * Author: gernhard -// */ -// -//#ifndef CONTROLLERWRAPPER_H_ -//#define CONTROLLERWRAPPER_H_ -// -//#include -//#include -//#include -//#include -//#include -// -//#include "common/protocol.h" -//#include "IControllerWrapper.h" -//#include "core/Controller.h" -// -//using namespace std; -//using namespace tlm; -//using namespace controller; -// -//template -//struct ControllerWrapper: public sc_module, public IControllerWrapper -//{ -//public: -// -// tlm_utils::simple_initiator_socket iSocket; -// tlm_utils::simple_target_socket tSocket; -// -// SC_CTOR(ControllerWrapper) : -// controller(*this), frontendPEQ(this, &ControllerWrapper::frontendPEQCallback), dramPEQ( -// this, &ControllerWrapper::dramPEQCallback), controllerPEQ(this, -// &ControllerWrapper::controllerPEQCallback), inputBufferDelay( -// controller.config.Timings.clk) -// { -// iSocket.register_nb_transport_bw(this, &ControllerWrapper::nb_transport_bw); -// tSocket.register_nb_transport_fw(this, &ControllerWrapper::nb_transport_fw); -// } -// -// ~ControllerWrapper() -// { -// } -// -// virtual void sendCommand(sc_time startTime, tlm::tlm_generic_payload& payload, -// controller::Command command) -// { -// assert(startTime >= sc_time_stamp()); -// sc_time delay = startTime - sc_time_stamp(); -// tlm::tlm_phase phase; -// switch (command) -// { -// case Read: -// phase = BEGIN_RD; -// break; -// case Write: -// phase = BEGIN_WR; -// break; -// case Refresh: -// phase = BEGIN_REFA; -// break; -// case Activate: -// phase = BEGIN_ACT; -// break; -// case Precharge: -// phase = BEGIN_PRE; -// break; -// default: -// SC_REPORT_FATAL(0, "unsupported command in controller wrapper"); -// break; -// } -// -// dramPEQ.notify(payload, phase, delay); -// } -// -// virtual void sendTrigger(sc_time time, controller::Trigger trigger) -// { -// assert(time >= sc_time_stamp()); -// sc_time delay = time - sc_time_stamp(); -// -// } -//private: -// Controller controller; -// tlm_utils::peq_with_cb_and_phase frontendPEQ; -// tlm_utils::peq_with_cb_and_phase dramPEQ; -// tlm_utils::peq_with_cb_and_phase controllerPEQ; -// -// sc_time inputBufferDelay; -// tlm::tlm_generic_payload triggerDummyPayload; -// -// // Initiated by dram -// tlm_sync_enum nb_transport_bw(tlm_generic_payload& payload, tlm_phase& phase, sc_time& bwDelay) -// { -// dramPEQ.notify(payload, phase, bwDelay); -// return TLM_ACCEPTED; -// } -// -// // Initiated by dram frontend -// tlm_sync_enum nb_transport_fw(tlm_generic_payload& payload, tlm_phase& phase, sc_time& fwDelay) -// { -// if (phase == BEGIN_REQ) -// payload.acquire(); -// else if (phase == END_RESP) -// payload.release(); -// -// frontendPEQ.notify(payload, phase, fwDelay); -// return TLM_ACCEPTED; -// } -// -// void frontendPEQCallback(tlm_generic_payload& payload, const tlm_phase& phase) -// { -// //todo : RECORDER -// -// if (phase == BEGIN_REQ) -// { -// controller.schedule(sc_time_stamp() + inputBufferDelay, payload); -// sendToFrontend(payload, END_REQ, inputBufferDelay); -// } -// else if (phase == BEGIN_RESP) -// { -// sendToFrontend(payload, phase, SC_ZERO_TIME); -// } -// else if (phase == END_RESP) -// { -// } -// -// else -// { -// SC_REPORT_FATAL(0, -// "Payload event queue in controller wrapper was triggered with unknown phase"); -// } -// } -// -// void dramPEQCallback(tlm_generic_payload& payload, const tlm_phase& phase) -// { -// //todo : RECORDER -// if (phase == BEGIN_RD || phase == BEGIN_WR || phase == BEGIN_REFA || phase == BEGIN_ACT -// || phase == BEGIN_PRE) -// { -// sendToDram(payload, phase, SC_ZERO_TIME); -// } -// else if (phase == END_RD || phase == END_WR) -// { -// frontendPEQ.notif(payload, BEGIN_RESP, SC_ZERO_TIME); -// } -// else if (phase == END_PRE || phase == END_ACT || phase == END_REFA) -// { -// -// } -// else -// { -// SC_REPORT_FATAL(0, -// "dramPEQCallback queue in controller wrapper was triggered with unknown phase"); -// } -// } -// -// void controllerPEQCallback(tlm_generic_payload& payload, const tlm_phase& phase) -// { -// if (phase == REFRESH_TRIGGER) -// { -// controller.refreshManager.scheduleRefresh(sc_time_stamp()); -// } -// else -// { -// SC_REPORT_FATAL(0, -// "controllerPEQCallback queue in controller wrapper was triggered with unknown phase"); -// } -// } -// -// void sendToDram(tlm_generic_payload& payload, const tlm_phase& phase, const sc_time& delay) -// { -// tlm_phase TPhase = phase; -// sc_time TDelay = delay; -// iSocket->nb_transport_fw(payload, TPhase, TDelay); -// } -// -// void sendToFrontend(tlm_generic_payload& payload, const tlm_phase& phase, const sc_time& delay) -// { -// tlm_phase TPhase = phase; -// sc_time TDelay = delay; -// tSocket->nb_transport_bw(payload, TPhase, TDelay); -// } -// -//}; -// -//#endif /* CONTROLLERWRAPPER_H_ */ diff --git a/DRAM/testing/Utils_test.cpp b/DRAM/testing/Utils_test.cpp index 841a147c..c2f0e023 100644 --- a/DRAM/testing/Utils_test.cpp +++ b/DRAM/testing/Utils_test.cpp @@ -72,5 +72,12 @@ TEST(UtilsTest, RingBufferWorks) EXPECT_TRUE(buffer.isFull()); } +TEST(UtilsTest,getBurstLengthInBytesWorks) +{ + tlm::tlm_generic_payload payload; + payload.set_data_length(4); + EXPECT_EQ(4,getBurstLengthInBytes(payload,128)); +} + } /* namespace controller */