From 7f049645cab551516df1e6109fc6525151ae749c Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Fri, 2 Oct 2020 15:16:42 +0200 Subject: [PATCH] Add DDR5 memspecs for different speed grades. --- .../am_ddr5_2x4x1Gbx8_dimm_p1KB_rbc.json | 49 +++++++++++++ .../memspecs/JEDEC_2x4x1Gbx8_DDR5-3200A.json | 68 +++++++++++++++++++ .../memspecs/JEDEC_2x4x1Gbx8_DDR5-3600A.json | 68 +++++++++++++++++++ .../memspecs/JEDEC_2x4x1Gbx8_DDR5-4000A.json | 68 +++++++++++++++++++ .../memspecs/JEDEC_2x4x1Gbx8_DDR5-4400A.json | 68 +++++++++++++++++++ .../memspecs/JEDEC_2x4x1Gbx8_DDR5-4800A.json | 68 +++++++++++++++++++ .../memspecs/JEDEC_2x4x1Gbx8_DDR5-5200A.json | 68 +++++++++++++++++++ .../memspecs/JEDEC_2x4x1Gbx8_DDR5-5600A.json | 68 +++++++++++++++++++ .../memspecs/JEDEC_2x4x1Gbx8_DDR5-6000A.json | 68 +++++++++++++++++++ .../memspecs/JEDEC_2x4x1Gbx8_DDR5-6400A.json | 68 +++++++++++++++++++ 10 files changed, 661 insertions(+) create mode 100644 DRAMSys/library/resources/configs/amconfigs/am_ddr5_2x4x1Gbx8_dimm_p1KB_rbc.json create mode 100644 DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-3200A.json create mode 100644 DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-3600A.json create mode 100644 DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4000A.json create mode 100644 DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4400A.json create mode 100644 DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4800A.json create mode 100644 DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-5200A.json create mode 100644 DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-5600A.json create mode 100644 DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-6000A.json create mode 100644 DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-6400A.json diff --git a/DRAMSys/library/resources/configs/amconfigs/am_ddr5_2x4x1Gbx8_dimm_p1KB_rbc.json b/DRAMSys/library/resources/configs/amconfigs/am_ddr5_2x4x1Gbx8_dimm_p1KB_rbc.json new file mode 100644 index 00000000..7e02f877 --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_ddr5_2x4x1Gbx8_dimm_p1KB_rbc.json @@ -0,0 +1,49 @@ +{ + "CONGEN": { + "BYTE_BIT": [ + 0, + 1 + ], + "COLUMN_BIT": [ + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11 + ], + "BANKGROUP_BIT": [ + 12, + 13, + 14 + ], + "BANK_BIT": [ + 15 + ], + "ROW_BIT": [ + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31 + ], + "CHANNEL_BIT": [ + 32 + ] + } +} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-3200A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-3200A.json new file mode 100644 index 00000000..3febbed0 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-3200A.json @@ -0,0 +1,68 @@ +{ + "memspec": { + "memarchitecturespec": { + "burstLength": 16, + "dataRate": 2, + "nbrOfBankGroups": 8, + "nbrOfBanks": 16, + "nbrOfColumns": 1024, + "nbrOfRanks": 1, + "nbrOfDIMMRanks": 1, + "nbrOfPhysicalRanks": 1, + "nbrOfLogicalRanks": 1, + "nbrOfRows": 65536, + "width": 8, + "nbrOfDevicesOnDIMM": 4, + "nbrOfChannels": 2, + "cmdMode": 1 + }, + "memoryId": "JEDEC_2x4x1Gbx8_DDR5-3200A", + "memoryType": "DDR5", + "memtimingspec": { + "RCD": 22, + "PPD": 2, + "RP": 22, + "RAS": 52, + "RL": 22, + "RTP": 12, + "RPRE": 1, + "RPST": 0, + "RDDQS": 0, + "WL": 20, + "WPRE": 2, + "WPST": 0, + "WR": 48, + "CCD_L_slr": 8, + "CCD_L_WR_slr": 16, + "CCD_S_slr": 8, + "CCD_S_WR_slr": 8, + "CCD_dlr": 0, + "CCD_WR_dlr": 0, + "CCD_WR_dpr": 0, + "RRD_L_slr": 8, + "RRD_S_slr": 8, + "RRD_dlr": 0, + "FAW_slr": 32, + "FAW_dlr": 0, + "WTR_L": 16, + "WTR_S": 4, + "RFC_slr": 312, + "RFC_dlr": 0, + "RFC_dpr": 0, + "RFCsb_slr": 184, + "RFCsb_dlr": 0, + "REFI": 6240, + "REFISB": 1560, + "REFSBRD_slr": 48, + "REFSBRD_dlr": 0, + "RTRS": 2, + "CPDED": 8, + "PD": 12, + "XP": 12, + "ACTPDEN": 2, + "PRPDEN": 2, + "REFPDEN": 2, + "clkMhz": 1600 + } + } +} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-3600A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-3600A.json new file mode 100644 index 00000000..90e37faf --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-3600A.json @@ -0,0 +1,68 @@ +{ + "memspec": { + "memarchitecturespec": { + "burstLength": 16, + "dataRate": 2, + "nbrOfBankGroups": 8, + "nbrOfBanks": 16, + "nbrOfColumns": 1024, + "nbrOfRanks": 1, + "nbrOfDIMMRanks": 1, + "nbrOfPhysicalRanks": 1, + "nbrOfLogicalRanks": 1, + "nbrOfRows": 65536, + "width": 8, + "nbrOfDevicesOnDIMM": 4, + "nbrOfChannels": 2, + "cmdMode": 1 + }, + "memoryId": "JEDEC_2x4x1Gbx8_DDR5-3600A", + "memoryType": "DDR5", + "memtimingspec": { + "RCD": 26, + "PPD": 2, + "RP": 26, + "RAS": 58, + "RL": 26, + "RTP": 14, + "RPRE": 1, + "RPST": 0, + "RDDQS": 0, + "WL": 24, + "WPRE": 2, + "WPST": 0, + "WR": 54, + "CCD_L_slr": 9, + "CCD_L_WR_slr": 18, + "CCD_S_slr": 8, + "CCD_S_WR_slr": 8, + "CCD_dlr": 0, + "CCD_WR_dlr": 0, + "CCD_WR_dpr": 0, + "RRD_L_slr": 9, + "RRD_S_slr": 8, + "RRD_dlr": 0, + "FAW_slr": 32, + "FAW_dlr": 0, + "WTR_L": 18, + "WTR_S": 5, + "RFC_slr": 351, + "RFC_dlr": 0, + "RFC_dpr": 0, + "RFCsb_slr": 207, + "RFCsb_dlr": 0, + "REFI": 7020, + "REFISB": 1755, + "REFSBRD_slr": 54, + "REFSBRD_dlr": 0, + "RTRS": 2, + "CPDED": 9, + "PD": 14, + "XP": 14, + "ACTPDEN": 2, + "PRPDEN": 2, + "REFPDEN": 2, + "clkMhz": 1800 + } + } +} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4000A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4000A.json new file mode 100644 index 00000000..687e6295 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4000A.json @@ -0,0 +1,68 @@ +{ + "memspec": { + "memarchitecturespec": { + "burstLength": 16, + "dataRate": 2, + "nbrOfBankGroups": 8, + "nbrOfBanks": 16, + "nbrOfColumns": 1024, + "nbrOfRanks": 1, + "nbrOfDIMMRanks": 1, + "nbrOfPhysicalRanks": 1, + "nbrOfLogicalRanks": 1, + "nbrOfRows": 65536, + "width": 8, + "nbrOfDevicesOnDIMM": 4, + "nbrOfChannels": 2, + "cmdMode": 1 + }, + "memoryId": "JEDEC_2x4x1Gbx8_DDR5-4000A", + "memoryType": "DDR5", + "memtimingspec": { + "RCD": 28, + "PPD": 2, + "RP": 28, + "RAS": 64, + "RL": 28, + "RTP": 15, + "RPRE": 1, + "RPST": 0, + "RDDQS": 0, + "WL": 26, + "WPRE": 2, + "WPST": 0, + "WR": 60, + "CCD_L_slr": 10, + "CCD_L_WR_slr": 20, + "CCD_S_slr": 8, + "CCD_S_WR_slr": 8, + "CCD_dlr": 0, + "CCD_WR_dlr": 0, + "CCD_WR_dpr": 0, + "RRD_L_slr": 10, + "RRD_S_slr": 8, + "RRD_dlr": 0, + "FAW_slr": 32, + "FAW_dlr": 0, + "WTR_L": 20, + "WTR_S": 5, + "RFC_slr": 390, + "RFC_dlr": 0, + "RFC_dpr": 0, + "RFCsb_slr": 230, + "RFCsb_dlr": 0, + "REFI": 7800, + "REFISB": 1950, + "REFSBRD_slr": 60, + "REFSBRD_dlr": 0, + "RTRS": 2, + "CPDED": 10, + "PD": 15, + "XP": 15, + "ACTPDEN": 2, + "PRPDEN": 2, + "REFPDEN": 2, + "clkMhz": 2000 + } + } +} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4400A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4400A.json new file mode 100644 index 00000000..19c05cbf --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4400A.json @@ -0,0 +1,68 @@ +{ + "memspec": { + "memarchitecturespec": { + "burstLength": 16, + "dataRate": 2, + "nbrOfBankGroups": 8, + "nbrOfBanks": 16, + "nbrOfColumns": 1024, + "nbrOfRanks": 1, + "nbrOfDIMMRanks": 1, + "nbrOfPhysicalRanks": 1, + "nbrOfLogicalRanks": 1, + "nbrOfRows": 65536, + "width": 8, + "nbrOfDevicesOnDIMM": 4, + "nbrOfChannels": 2, + "cmdMode": 1 + }, + "memoryId": "JEDEC_2x4x1Gbx8_DDR5-4400A", + "memoryType": "DDR5", + "memtimingspec": { + "RCD": 32, + "PPD": 2, + "RP": 32, + "RAS": 71, + "RL": 32, + "RTP": 17, + "RPRE": 1, + "RPST": 0, + "RDDQS": 0, + "WL": 30, + "WPRE": 2, + "WPST": 0, + "WR": 66, + "CCD_L_slr": 11, + "CCD_L_WR_slr": 22, + "CCD_S_slr": 8, + "CCD_S_WR_slr": 8, + "CCD_dlr": 0, + "CCD_WR_dlr": 0, + "CCD_WR_dpr": 0, + "RRD_L_slr": 11, + "RRD_S_slr": 8, + "RRD_dlr": 0, + "FAW_slr": 32, + "FAW_dlr": 0, + "WTR_L": 22, + "WTR_S": 6, + "RFC_slr": 429, + "RFC_dlr": 0, + "RFC_dpr": 0, + "RFCsb_slr": 253, + "RFCsb_dlr": 0, + "REFI": 8580, + "REFISB": 2145, + "REFSBRD_slr": 66, + "REFSBRD_dlr": 0, + "RTRS": 2, + "CPDED": 11, + "PD": 17, + "XP": 17, + "ACTPDEN": 2, + "PRPDEN": 2, + "REFPDEN": 2, + "clkMhz": 2200 + } + } +} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4800A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4800A.json new file mode 100644 index 00000000..56d7a6b3 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4800A.json @@ -0,0 +1,68 @@ +{ + "memspec": { + "memarchitecturespec": { + "burstLength": 16, + "dataRate": 2, + "nbrOfBankGroups": 8, + "nbrOfBanks": 16, + "nbrOfColumns": 1024, + "nbrOfRanks": 1, + "nbrOfDIMMRanks": 1, + "nbrOfPhysicalRanks": 1, + "nbrOfLogicalRanks": 1, + "nbrOfRows": 65536, + "width": 8, + "nbrOfDevicesOnDIMM": 4, + "nbrOfChannels": 2, + "cmdMode": 1 + }, + "memoryId": "JEDEC_2x4x1Gbx8_DDR5-4800A", + "memoryType": "DDR5", + "memtimingspec": { + "RCD": 34, + "PPD": 2, + "RP": 34, + "RAS": 77, + "RL": 34, + "RTP": 18, + "RPRE": 1, + "RPST": 0, + "RDDQS": 0, + "WL": 32, + "WPRE": 2, + "WPST": 0, + "WR": 72, + "CCD_L_slr": 12, + "CCD_L_WR_slr": 24, + "CCD_S_slr": 8, + "CCD_S_WR_slr": 8, + "CCD_dlr": 0, + "CCD_WR_dlr": 0, + "CCD_WR_dpr": 0, + "RRD_L_slr": 12, + "RRD_S_slr": 8, + "RRD_dlr": 0, + "FAW_slr": 32, + "FAW_dlr": 0, + "WTR_L": 24, + "WTR_S": 6, + "RFC_slr": 468, + "RFC_dlr": 0, + "RFC_dpr": 0, + "RFCsb_slr": 276, + "RFCsb_dlr": 0, + "REFI": 9360, + "REFISB": 2340, + "REFSBRD_slr": 72, + "REFSBRD_dlr": 0, + "RTRS": 2, + "CPDED": 12, + "PD": 18, + "XP": 18, + "ACTPDEN": 2, + "PRPDEN": 2, + "REFPDEN": 2, + "clkMhz": 2400 + } + } +} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-5200A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-5200A.json new file mode 100644 index 00000000..40fe0283 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-5200A.json @@ -0,0 +1,68 @@ +{ + "memspec": { + "memarchitecturespec": { + "burstLength": 16, + "dataRate": 2, + "nbrOfBankGroups": 8, + "nbrOfBanks": 16, + "nbrOfColumns": 1024, + "nbrOfRanks": 1, + "nbrOfDIMMRanks": 1, + "nbrOfPhysicalRanks": 1, + "nbrOfLogicalRanks": 1, + "nbrOfRows": 65536, + "width": 8, + "nbrOfDevicesOnDIMM": 4, + "nbrOfChannels": 2, + "cmdMode": 1 + }, + "memoryId": "JEDEC_2x4x1Gbx8_DDR5-5200A", + "memoryType": "DDR5", + "memtimingspec": { + "RCD": 38, + "PPD": 2, + "RP": 38, + "RAS": 84, + "RL": 38, + "RTP": 20, + "RPRE": 1, + "RPST": 0, + "RDDQS": 0, + "WL": 36, + "WPRE": 2, + "WPST": 0, + "WR": 78, + "CCD_L_slr": 13, + "CCD_L_WR_slr": 26, + "CCD_S_slr": 8, + "CCD_S_WR_slr": 8, + "CCD_dlr": 0, + "CCD_WR_dlr": 0, + "CCD_WR_dpr": 0, + "RRD_L_slr": 13, + "RRD_S_slr": 8, + "RRD_dlr": 0, + "FAW_slr": 32, + "FAW_dlr": 0, + "WTR_L": 26, + "WTR_S": 7, + "RFC_slr": 507, + "RFC_dlr": 0, + "RFC_dpr": 0, + "RFCsb_slr": 299, + "RFCsb_dlr": 0, + "REFI": 10140, + "REFISB": 2535, + "REFSBRD_slr": 78, + "REFSBRD_dlr": 0, + "RTRS": 2, + "CPDED": 13, + "PD": 20, + "XP": 20, + "ACTPDEN": 2, + "PRPDEN": 2, + "REFPDEN": 2, + "clkMhz": 2600 + } + } +} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-5600A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-5600A.json new file mode 100644 index 00000000..5ed3f965 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-5600A.json @@ -0,0 +1,68 @@ +{ + "memspec": { + "memarchitecturespec": { + "burstLength": 16, + "dataRate": 2, + "nbrOfBankGroups": 8, + "nbrOfBanks": 16, + "nbrOfColumns": 1024, + "nbrOfRanks": 1, + "nbrOfDIMMRanks": 1, + "nbrOfPhysicalRanks": 1, + "nbrOfLogicalRanks": 1, + "nbrOfRows": 65536, + "width": 8, + "nbrOfDevicesOnDIMM": 4, + "nbrOfChannels": 2, + "cmdMode": 1 + }, + "memoryId": "JEDEC_2x4x1Gbx8_DDR5-5600A", + "memoryType": "DDR5", + "memtimingspec": { + "RCD": 40, + "PPD": 2, + "RP": 40, + "RAS": 90, + "RL": 40, + "RTP": 21, + "RPRE": 1, + "RPST": 0, + "RDDQS": 0, + "WL": 38, + "WPRE": 2, + "WPST": 0, + "WR": 84, + "CCD_L_slr": 14, + "CCD_L_WR_slr": 28, + "CCD_S_slr": 8, + "CCD_S_WR_slr": 8, + "CCD_dlr": 0, + "CCD_WR_dlr": 0, + "CCD_WR_dpr": 0, + "RRD_L_slr": 14, + "RRD_S_slr": 8, + "RRD_dlr": 0, + "FAW_slr": 32, + "FAW_dlr": 0, + "WTR_L": 28, + "WTR_S": 7, + "RFC_slr": 546, + "RFC_dlr": 0, + "RFC_dpr": 0, + "RFCsb_slr": 322, + "RFCsb_dlr": 0, + "REFI": 10920, + "REFISB": 2730, + "REFSBRD_slr": 84, + "REFSBRD_dlr": 0, + "RTRS": 2, + "CPDED": 14, + "PD": 21, + "XP": 21, + "ACTPDEN": 2, + "PRPDEN": 2, + "REFPDEN": 2, + "clkMhz": 2800 + } + } +} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-6000A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-6000A.json new file mode 100644 index 00000000..878a99ec --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-6000A.json @@ -0,0 +1,68 @@ +{ + "memspec": { + "memarchitecturespec": { + "burstLength": 16, + "dataRate": 2, + "nbrOfBankGroups": 8, + "nbrOfBanks": 16, + "nbrOfColumns": 1024, + "nbrOfRanks": 1, + "nbrOfDIMMRanks": 1, + "nbrOfPhysicalRanks": 1, + "nbrOfLogicalRanks": 1, + "nbrOfRows": 65536, + "width": 8, + "nbrOfDevicesOnDIMM": 4, + "nbrOfChannels": 2, + "cmdMode": 1 + }, + "memoryId": "JEDEC_2x4x1Gbx8_DDR5-6000A", + "memoryType": "DDR5", + "memtimingspec": { + "RCD": 42, + "PPD": 2, + "RP": 42, + "RAS": 96, + "RL": 42, + "RTP": 23, + "RPRE": 1, + "RPST": 0, + "RDDQS": 0, + "WL": 40, + "WPRE": 2, + "WPST": 0, + "WR": 90, + "CCD_L_slr": 15, + "CCD_L_WR_slr": 30, + "CCD_S_slr": 8, + "CCD_S_WR_slr": 8, + "CCD_dlr": 0, + "CCD_WR_dlr": 0, + "CCD_WR_dpr": 0, + "RRD_L_slr": 15, + "RRD_S_slr": 8, + "RRD_dlr": 0, + "FAW_slr": 32, + "FAW_dlr": 0, + "WTR_L": 30, + "WTR_S": 8, + "RFC_slr": 585, + "RFC_dlr": 0, + "RFC_dpr": 0, + "RFCsb_slr": 345, + "RFCsb_dlr": 0, + "REFI": 11700, + "REFISB": 2925, + "REFSBRD_slr": 90, + "REFSBRD_dlr": 0, + "RTRS": 2, + "CPDED": 15, + "PD": 23, + "XP": 23, + "ACTPDEN": 2, + "PRPDEN": 2, + "REFPDEN": 2, + "clkMhz": 3000 + } + } +} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-6400A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-6400A.json new file mode 100644 index 00000000..6f291b49 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-6400A.json @@ -0,0 +1,68 @@ +{ + "memspec": { + "memarchitecturespec": { + "burstLength": 16, + "dataRate": 2, + "nbrOfBankGroups": 8, + "nbrOfBanks": 16, + "nbrOfColumns": 1024, + "nbrOfRanks": 1, + "nbrOfDIMMRanks": 1, + "nbrOfPhysicalRanks": 1, + "nbrOfLogicalRanks": 1, + "nbrOfRows": 65536, + "width": 8, + "nbrOfDevicesOnDIMM": 4, + "nbrOfChannels": 2, + "cmdMode": 1 + }, + "memoryId": "JEDEC_2x4x1Gbx8_DDR5-6400A", + "memoryType": "DDR5", + "memtimingspec": { + "RCD": 46, + "PPD": 2, + "RP": 46, + "RAS": 103, + "RL": 46, + "RTP": 24, + "RPRE": 1, + "RPST": 0, + "RDDQS": 0, + "WL": 44, + "WPRE": 2, + "WPST": 0, + "WR": 96, + "CCD_L_slr": 16, + "CCD_L_WR_slr": 32, + "CCD_S_slr": 8, + "CCD_S_WR_slr": 8, + "CCD_dlr": 0, + "CCD_WR_dlr": 0, + "CCD_WR_dpr": 0, + "RRD_L_slr": 16, + "RRD_S_slr": 8, + "RRD_dlr": 0, + "FAW_slr": 32, + "FAW_dlr": 0, + "WTR_L": 32, + "WTR_S": 8, + "RFC_slr": 624, + "RFC_dlr": 0, + "RFC_dpr": 0, + "RFCsb_slr": 368, + "RFCsb_dlr": 0, + "REFI": 12480, + "REFISB": 3120, + "REFSBRD_slr": 96, + "REFSBRD_dlr": 0, + "RTRS": 2, + "CPDED": 16, + "PD": 24, + "XP": 24, + "ACTPDEN": 2, + "PRPDEN": 2, + "REFPDEN": 2, + "clkMhz": 3200 + } + } +} \ No newline at end of file