diff --git a/DRAMSys/library/src/controller/core/configuration/MemSpec.h b/DRAMSys/library/src/controller/core/configuration/MemSpec.h index e043404b..b43df8e1 100644 --- a/DRAMSys/library/src/controller/core/configuration/MemSpec.h +++ b/DRAMSys/library/src/controller/core/configuration/MemSpec.h @@ -90,7 +90,7 @@ struct MemSpec sc_time tAL; // additive delay (delayed execution in dram) sc_time tCKE; // min time in pdna or pdnp sc_time tCKESR; // min time in sref - //sc_time tCL; // unused? + sc_time tCL; // unused, will be used in the future sc_time tDQSCK; sc_time tRAS; // active-time (act -> pre same bank) sc_time tRC; // RAS-cycle-time (min time bw 2 succesive ACT to same bank) diff --git a/DRAMSys/library/src/simulation/Dram.cpp b/DRAMSys/library/src/simulation/Dram.cpp index 65a7ebbe..a380ceea 100644 --- a/DRAMSys/library/src/simulation/Dram.cpp +++ b/DRAMSys/library/src/simulation/Dram.cpp @@ -69,110 +69,6 @@ Dram::Dram(sc_module_name) : tSocket("socket") tSocket.register_nb_transport_fw(this, &Dram::nb_transport_fw); tSocket.register_transport_dbg(this, &Dram::transport_dbg); - - // Parameters for DRAMPower - sc_time clk = Configuration::getInstance().memSpec->clk; - - MemArchitectureSpec memArchSpec; - memArchSpec.burstLength = - Configuration::getInstance().memSpec->BurstLength; - memArchSpec.dataRate = Configuration::getInstance().memSpec->DataRate; - memArchSpec.nbrOfRows = - Configuration::getInstance().memSpec->NumberOfRows; - memArchSpec.nbrOfBanks = - Configuration::getInstance().memSpec->NumberOfBanks; - memArchSpec.nbrOfColumns = - Configuration::getInstance().memSpec->NumberOfColumns; - memArchSpec.nbrOfRanks = - Configuration::getInstance().memSpec->NumberOfRanks; - memArchSpec.width = Configuration::getInstance().memSpec->bitWidth; - memArchSpec.nbrOfBankGroups = - Configuration::getInstance().memSpec->NumberOfBankGroups; - memArchSpec.twoVoltageDomains = (Configuration::getInstance().memSpec->vDD2 == 0 - ? false : true); - memArchSpec.dll = Configuration::getInstance().memSpec->DLL; - - MemTimingSpec memTimingSpec; - memTimingSpec.FAWB = Configuration::getInstance().tfawbclk; - memTimingSpec.RASB = Configuration::getInstance().trasbclk; - memTimingSpec.RCB = Configuration::getInstance().trcbclk; - memTimingSpec.RPB = Configuration::getInstance().trpbclk; - memTimingSpec.RRDB = Configuration::getInstance().trrdblclk; - memTimingSpec.RRDB_L = Configuration::getInstance().trrdblclk; - memTimingSpec.RRDB_S = Configuration::getInstance().trrdblclk; - memTimingSpec.AL = Configuration::getInstance().memSpec->tAL / clk; - memTimingSpec.CCD = Configuration::getInstance().memSpec->tCCD_S / clk; - memTimingSpec.CCD_L = Configuration::getInstance().memSpec->tCCD_L / clk; - memTimingSpec.CCD_S = Configuration::getInstance().memSpec->tCCD_S / clk; - memTimingSpec.CKE = Configuration::getInstance().memSpec->tCKE / clk; - memTimingSpec.CKESR = Configuration::getInstance().memSpec->tCKESR / clk; - memTimingSpec.clkMhz = Configuration::getInstance().memSpec->clkMHz; - // See also MemTimingSpec.cc in DRAMPower - memTimingSpec.clkPeriod = 1000.0 / Configuration::getInstance().memSpec->clkMHz; - memTimingSpec.DQSCK = Configuration::getInstance().memSpec->tDQSCK / clk; - memTimingSpec.FAW = Configuration::getInstance().memSpec->tNAW / clk; - memTimingSpec.RAS = Configuration::getInstance().memSpec->tRAS / clk; - memTimingSpec.RC = Configuration::getInstance().memSpec->tRC / clk; - memTimingSpec.RCD = Configuration::getInstance().memSpec->tRCD / clk; - memTimingSpec.REFI = Configuration::getInstance().memSpec->tREFI / clk; - auto m = Configuration::getInstance().getRefMode(); - if (m == 4) - memTimingSpec.RFC = Configuration::getInstance().memSpec->tRFC4 / clk; - else if (m == 2) - memTimingSpec.RFC = Configuration::getInstance().memSpec->tRFC2 / clk; - else - memTimingSpec.RFC = Configuration::getInstance().memSpec->tRFC / clk; - memTimingSpec.RL = Configuration::getInstance().memSpec->tRL / clk; - memTimingSpec.RP = Configuration::getInstance().memSpec->tRP / clk; - memTimingSpec.RRD = Configuration::getInstance().memSpec->tRRD_S / clk; - memTimingSpec.RRD_L = Configuration::getInstance().memSpec->tRRD_L / clk; - memTimingSpec.RRD_S = Configuration::getInstance().memSpec->tRRD_S / clk; - memTimingSpec.RTP = Configuration::getInstance().memSpec->tRTP / clk; - memTimingSpec.TAW = Configuration::getInstance().memSpec->tNAW / clk; - memTimingSpec.WL = Configuration::getInstance().memSpec->tWL / clk; - memTimingSpec.WR = Configuration::getInstance().memSpec->tWR / clk; - memTimingSpec.WTR = Configuration::getInstance().memSpec->tWTR_S / clk; - memTimingSpec.WTR_L = Configuration::getInstance().memSpec->tWTR_L / clk; - memTimingSpec.WTR_S = Configuration::getInstance().memSpec->tWTR_S / clk; - memTimingSpec.XP = Configuration::getInstance().memSpec->tXP / clk; - memTimingSpec.XPDLL = Configuration::getInstance().memSpec->tXPDLL / clk; - memTimingSpec.XS = Configuration::getInstance().memSpec->tXSR / clk; - memTimingSpec.XSDLL = Configuration::getInstance().memSpec->tXSRDLL / clk; - - MemPowerSpec memPowerSpec; - memPowerSpec.idd0 = Configuration::getInstance().memSpec->iDD0; - memPowerSpec.idd02 = Configuration::getInstance().memSpec->iDD02; - memPowerSpec.idd2p0 = Configuration::getInstance().memSpec->iDD2P0; - memPowerSpec.idd2p02 = Configuration::getInstance().memSpec->iDD2P02; - memPowerSpec.idd2p1 = Configuration::getInstance().memSpec->iDD2P1; - memPowerSpec.idd2p12 = Configuration::getInstance().memSpec->iDD2P12; - memPowerSpec.idd2n = Configuration::getInstance().memSpec->iDD2N; - memPowerSpec.idd2n2 = Configuration::getInstance().memSpec->iDD2N2; - memPowerSpec.idd3p0 = Configuration::getInstance().memSpec->iDD3P0; - memPowerSpec.idd3p02 = Configuration::getInstance().memSpec->iDD3P02; - memPowerSpec.idd3p1 = Configuration::getInstance().memSpec->iDD3P1; - memPowerSpec.idd3p12 = Configuration::getInstance().memSpec->iDD3P12; - memPowerSpec.idd3n = Configuration::getInstance().memSpec->iDD3N; - memPowerSpec.idd3n2 = Configuration::getInstance().memSpec->iDD3N2; - memPowerSpec.idd4r = Configuration::getInstance().memSpec->iDD4R; - memPowerSpec.idd4r2 = Configuration::getInstance().memSpec->iDD4R2; - memPowerSpec.idd4w = Configuration::getInstance().memSpec->iDD4W; - memPowerSpec.idd4w2 = Configuration::getInstance().memSpec->iDD4W2; - memPowerSpec.idd5 = Configuration::getInstance().memSpec->iDD5; - memPowerSpec.idd52 = Configuration::getInstance().memSpec->iDD52; - memPowerSpec.idd6 = Configuration::getInstance().memSpec->iDD6; - memPowerSpec.idd62 = Configuration::getInstance().memSpec->iDD62; - memPowerSpec.vdd = Configuration::getInstance().memSpec->vDD; - memPowerSpec.vdd2 = Configuration::getInstance().memSpec->vDD2; - - MemorySpecification memSpec; - memSpec.id = Configuration::getInstance().memSpec->MemoryId; - memSpec.memoryType = Configuration::getInstance().memSpec->MemoryType; - memSpec.memTimingSpec = memTimingSpec; - memSpec.memPowerSpec = memPowerSpec; - memSpec.memArchSpec = memArchSpec; - - DRAMPower = new libDRAMPower(memSpec, 0); } Dram::~Dram() diff --git a/DRAMSys/library/src/simulation/DramDDR3.cpp b/DRAMSys/library/src/simulation/DramDDR3.cpp index 2eff2592..8453a6da 100644 --- a/DRAMSys/library/src/simulation/DramDDR3.cpp +++ b/DRAMSys/library/src/simulation/DramDDR3.cpp @@ -37,9 +37,111 @@ #include "Dram.h" #include "../controller/core/configuration/Configuration.h" +#include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" DramDDR3::DramDDR3(sc_module_name name) : Dram(name) { if (StoreMode == StorageMode::ErrorModel) SC_REPORT_FATAL("DramDDR3", "Error Model not supported for DDR3"); + + // Parameters for DRAMPower + MemSpecDDR3 *memSpec = dynamic_cast(Configuration::getInstance().memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("DramDDR4", "Wrong MemSpec chosen"); + + sc_time clk = memSpec->clk; + + MemArchitectureSpec memArchSpec; + memArchSpec.burstLength = memSpec->BurstLength; + memArchSpec.dataRate = memSpec->DataRate; + memArchSpec.nbrOfRows = memSpec->NumberOfRows; + memArchSpec.nbrOfBanks = memSpec->NumberOfBanks; + memArchSpec.nbrOfColumns = memSpec->NumberOfColumns; + memArchSpec.nbrOfRanks = memSpec->NumberOfRanks; + memArchSpec.width = memSpec->bitWidth; + memArchSpec.nbrOfBankGroups = memSpec->NumberOfBankGroups; + memArchSpec.twoVoltageDomains = ((memSpec->vDD2 == 0) ? false : true); + memArchSpec.dll = memSpec->DLL; + + MemTimingSpec memTimingSpec; + memTimingSpec.FAWB = Configuration::getInstance().tfawbclk; + memTimingSpec.RASB = Configuration::getInstance().trasbclk; + memTimingSpec.RCB = Configuration::getInstance().trcbclk; + memTimingSpec.RPB = Configuration::getInstance().trpbclk; + memTimingSpec.RRDB = Configuration::getInstance().trrdblclk; + memTimingSpec.RRDB_L = Configuration::getInstance().trrdblclk; + memTimingSpec.RRDB_S = Configuration::getInstance().trrdblclk; + memTimingSpec.AL = memSpec->tAL / clk; + memTimingSpec.CCD = memSpec->tCCD_S / clk; + memTimingSpec.CCD_L = memSpec->tCCD_L / clk; + memTimingSpec.CCD_S = memSpec->tCCD_S / clk; + memTimingSpec.CKE = memSpec->tCKE / clk; + memTimingSpec.CKESR = memSpec->tCKESR / clk; + memTimingSpec.clkMhz = memSpec->clkMHz; + // See also MemTimingSpec.cc in DRAMPower + memTimingSpec.clkPeriod = 1000.0 / memSpec->clkMHz; + memTimingSpec.DQSCK = memSpec->tDQSCK / clk; + memTimingSpec.FAW = memSpec->tNAW / clk; + memTimingSpec.RAS = memSpec->tRAS / clk; + memTimingSpec.RC = memSpec->tRC / clk; + memTimingSpec.RCD = memSpec->tRCD / clk; + memTimingSpec.REFI = memSpec->tREFI / clk; + unsigned m = Configuration::getInstance().getRefMode(); + if (m == 4) + memTimingSpec.RFC = memSpec->tRFC4 / clk; + else if (m == 2) + memTimingSpec.RFC = memSpec->tRFC2 / clk; + else + memTimingSpec.RFC = memSpec->tRFC / clk; + memTimingSpec.RL = memSpec->tRL / clk; + memTimingSpec.RP = memSpec->tRP / clk; + memTimingSpec.RRD = memSpec->tRRD_S / clk; + memTimingSpec.RRD_L = memSpec->tRRD_L / clk; + memTimingSpec.RRD_S = memSpec->tRRD_S / clk; + memTimingSpec.RTP = memSpec->tRTP / clk; + memTimingSpec.TAW = memSpec->tNAW / clk; + memTimingSpec.WL = memSpec->tWL / clk; + memTimingSpec.WR = memSpec->tWR / clk; + memTimingSpec.WTR = memSpec->tWTR_S / clk; + memTimingSpec.WTR_L = memSpec->tWTR_L / clk; + memTimingSpec.WTR_S = memSpec->tWTR_S / clk; + memTimingSpec.XP = memSpec->tXP / clk; + memTimingSpec.XPDLL = memSpec->tXPDLL / clk; + memTimingSpec.XS = memSpec->tXSR / clk; + memTimingSpec.XSDLL = memSpec->tXSRDLL / clk; + + MemPowerSpec memPowerSpec; + memPowerSpec.idd0 = memSpec->iDD0; + memPowerSpec.idd02 = memSpec->iDD02; + memPowerSpec.idd2p0 = memSpec->iDD2P0; + memPowerSpec.idd2p02 = memSpec->iDD2P02; + memPowerSpec.idd2p1 = memSpec->iDD2P1; + memPowerSpec.idd2p12 = memSpec->iDD2P12; + memPowerSpec.idd2n = memSpec->iDD2N; + memPowerSpec.idd2n2 = memSpec->iDD2N2; + memPowerSpec.idd3p0 = memSpec->iDD3P0; + memPowerSpec.idd3p02 = memSpec->iDD3P02; + memPowerSpec.idd3p1 = memSpec->iDD3P1; + memPowerSpec.idd3p12 = memSpec->iDD3P12; + memPowerSpec.idd3n = memSpec->iDD3N; + memPowerSpec.idd3n2 = memSpec->iDD3N2; + memPowerSpec.idd4r = memSpec->iDD4R; + memPowerSpec.idd4r2 = memSpec->iDD4R2; + memPowerSpec.idd4w = memSpec->iDD4W; + memPowerSpec.idd4w2 = memSpec->iDD4W2; + memPowerSpec.idd5 = memSpec->iDD5; + memPowerSpec.idd52 = memSpec->iDD52; + memPowerSpec.idd6 = memSpec->iDD6; + memPowerSpec.idd62 = memSpec->iDD62; + memPowerSpec.vdd = memSpec->vDD; + memPowerSpec.vdd2 = memSpec->vDD2; + + MemorySpecification powerSpec; + powerSpec.id = memSpec->MemoryId; + powerSpec.memoryType = memSpec->MemoryType; + powerSpec.memTimingSpec = memTimingSpec; + powerSpec.memPowerSpec = memPowerSpec; + powerSpec.memArchSpec = memArchSpec; + + DRAMPower = new libDRAMPower(powerSpec, 0); } diff --git a/DRAMSys/library/src/simulation/DramDDR4.cpp b/DRAMSys/library/src/simulation/DramDDR4.cpp index 1fc81d81..bf768f29 100644 --- a/DRAMSys/library/src/simulation/DramDDR4.cpp +++ b/DRAMSys/library/src/simulation/DramDDR4.cpp @@ -37,9 +37,111 @@ #include "Dram.h" #include "../controller/core/configuration/Configuration.h" +#include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" DramDDR4::DramDDR4(sc_module_name name) : Dram(name) { if (StoreMode == StorageMode::ErrorModel) SC_REPORT_FATAL("DramDDR4", "Error Model not supported for DDR4"); + + // Parameters for DRAMPower + MemSpecDDR4 *memSpec = dynamic_cast(Configuration::getInstance().memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("DramDDR4", "Wrong MemSpec chosen"); + + sc_time clk = memSpec->clk; + + MemArchitectureSpec memArchSpec; + memArchSpec.burstLength = memSpec->BurstLength; + memArchSpec.dataRate = memSpec->DataRate; + memArchSpec.nbrOfRows = memSpec->NumberOfRows; + memArchSpec.nbrOfBanks = memSpec->NumberOfBanks; + memArchSpec.nbrOfColumns = memSpec->NumberOfColumns; + memArchSpec.nbrOfRanks = memSpec->NumberOfRanks; + memArchSpec.width = memSpec->bitWidth; + memArchSpec.nbrOfBankGroups = memSpec->NumberOfBankGroups; + memArchSpec.twoVoltageDomains = ((memSpec->vDD2 == 0) ? false : true); + memArchSpec.dll = memSpec->DLL; + + MemTimingSpec memTimingSpec; + memTimingSpec.FAWB = Configuration::getInstance().tfawbclk; + memTimingSpec.RASB = Configuration::getInstance().trasbclk; + memTimingSpec.RCB = Configuration::getInstance().trcbclk; + memTimingSpec.RPB = Configuration::getInstance().trpbclk; + memTimingSpec.RRDB = Configuration::getInstance().trrdblclk; + memTimingSpec.RRDB_L = Configuration::getInstance().trrdblclk; + memTimingSpec.RRDB_S = Configuration::getInstance().trrdblclk; + memTimingSpec.AL = memSpec->tAL / clk; + memTimingSpec.CCD = memSpec->tCCD_S / clk; + memTimingSpec.CCD_L = memSpec->tCCD_L / clk; + memTimingSpec.CCD_S = memSpec->tCCD_S / clk; + memTimingSpec.CKE = memSpec->tCKE / clk; + memTimingSpec.CKESR = memSpec->tCKESR / clk; + memTimingSpec.clkMhz = memSpec->clkMHz; + // See also MemTimingSpec.cc in DRAMPower + memTimingSpec.clkPeriod = 1000.0 / memSpec->clkMHz; + memTimingSpec.DQSCK = memSpec->tDQSCK / clk; + memTimingSpec.FAW = memSpec->tNAW / clk; + memTimingSpec.RAS = memSpec->tRAS / clk; + memTimingSpec.RC = memSpec->tRC / clk; + memTimingSpec.RCD = memSpec->tRCD / clk; + memTimingSpec.REFI = memSpec->tREFI / clk; + unsigned m = Configuration::getInstance().getRefMode(); + if (m == 4) + memTimingSpec.RFC = memSpec->tRFC4 / clk; + else if (m == 2) + memTimingSpec.RFC = memSpec->tRFC2 / clk; + else + memTimingSpec.RFC = memSpec->tRFC / clk; + memTimingSpec.RL = memSpec->tRL / clk; + memTimingSpec.RP = memSpec->tRP / clk; + memTimingSpec.RRD = memSpec->tRRD_S / clk; + memTimingSpec.RRD_L = memSpec->tRRD_L / clk; + memTimingSpec.RRD_S = memSpec->tRRD_S / clk; + memTimingSpec.RTP = memSpec->tRTP / clk; + memTimingSpec.TAW = memSpec->tNAW / clk; + memTimingSpec.WL = memSpec->tWL / clk; + memTimingSpec.WR = memSpec->tWR / clk; + memTimingSpec.WTR = memSpec->tWTR_S / clk; + memTimingSpec.WTR_L = memSpec->tWTR_L / clk; + memTimingSpec.WTR_S = memSpec->tWTR_S / clk; + memTimingSpec.XP = memSpec->tXP / clk; + memTimingSpec.XPDLL = memSpec->tXPDLL / clk; + memTimingSpec.XS = memSpec->tXSR / clk; + memTimingSpec.XSDLL = memSpec->tXSRDLL / clk; + + MemPowerSpec memPowerSpec; + memPowerSpec.idd0 = memSpec->iDD0; + memPowerSpec.idd02 = memSpec->iDD02; + memPowerSpec.idd2p0 = memSpec->iDD2P0; + memPowerSpec.idd2p02 = memSpec->iDD2P02; + memPowerSpec.idd2p1 = memSpec->iDD2P1; + memPowerSpec.idd2p12 = memSpec->iDD2P12; + memPowerSpec.idd2n = memSpec->iDD2N; + memPowerSpec.idd2n2 = memSpec->iDD2N2; + memPowerSpec.idd3p0 = memSpec->iDD3P0; + memPowerSpec.idd3p02 = memSpec->iDD3P02; + memPowerSpec.idd3p1 = memSpec->iDD3P1; + memPowerSpec.idd3p12 = memSpec->iDD3P12; + memPowerSpec.idd3n = memSpec->iDD3N; + memPowerSpec.idd3n2 = memSpec->iDD3N2; + memPowerSpec.idd4r = memSpec->iDD4R; + memPowerSpec.idd4r2 = memSpec->iDD4R2; + memPowerSpec.idd4w = memSpec->iDD4W; + memPowerSpec.idd4w2 = memSpec->iDD4W2; + memPowerSpec.idd5 = memSpec->iDD5; + memPowerSpec.idd52 = memSpec->iDD52; + memPowerSpec.idd6 = memSpec->iDD6; + memPowerSpec.idd62 = memSpec->iDD62; + memPowerSpec.vdd = memSpec->vDD; + memPowerSpec.vdd2 = memSpec->vDD2; + + MemorySpecification powerSpec; + powerSpec.id = memSpec->MemoryId; + powerSpec.memoryType = memSpec->MemoryType; + powerSpec.memTimingSpec = memTimingSpec; + powerSpec.memPowerSpec = memPowerSpec; + powerSpec.memArchSpec = memArchSpec; + + DRAMPower = new libDRAMPower(powerSpec, 0);; } diff --git a/DRAMSys/library/src/simulation/DramWideIO.cpp b/DRAMSys/library/src/simulation/DramWideIO.cpp index 9b3655cb..93f80c06 100644 --- a/DRAMSys/library/src/simulation/DramWideIO.cpp +++ b/DRAMSys/library/src/simulation/DramWideIO.cpp @@ -40,6 +40,7 @@ #include "Dram.h" #include "../controller/core/configuration/Configuration.h" #include "../error/errormodel.h" +#include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" using namespace tlm; @@ -60,6 +61,107 @@ DramWideIO::DramWideIO(sc_module_name name) : Dram(name) ememory.push_back(em); } } + + // Parameters for DRAMPower + MemSpecWideIO *memSpec = dynamic_cast(Configuration::getInstance().memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("DramWideIO", "Wrong MemSpec chosen"); + + sc_time clk = memSpec->clk; + + MemArchitectureSpec memArchSpec; + memArchSpec.burstLength = memSpec->BurstLength; + memArchSpec.dataRate = memSpec->DataRate; + memArchSpec.nbrOfRows = memSpec->NumberOfRows; + memArchSpec.nbrOfBanks = memSpec->NumberOfBanks; + memArchSpec.nbrOfColumns = memSpec->NumberOfColumns; + memArchSpec.nbrOfRanks = memSpec->NumberOfRanks; + memArchSpec.width = memSpec->bitWidth; + memArchSpec.nbrOfBankGroups = memSpec->NumberOfBankGroups; + memArchSpec.twoVoltageDomains = ((memSpec->vDD2 == 0) ? false : true); + memArchSpec.dll = memSpec->DLL; + + MemTimingSpec memTimingSpec; + memTimingSpec.FAWB = Configuration::getInstance().tfawbclk; + memTimingSpec.RASB = Configuration::getInstance().trasbclk; + memTimingSpec.RCB = Configuration::getInstance().trcbclk; + memTimingSpec.RPB = Configuration::getInstance().trpbclk; + memTimingSpec.RRDB = Configuration::getInstance().trrdblclk; + memTimingSpec.RRDB_L = Configuration::getInstance().trrdblclk; + memTimingSpec.RRDB_S = Configuration::getInstance().trrdblclk; + memTimingSpec.AL = memSpec->tAL / clk; + memTimingSpec.CCD = memSpec->tCCD_S / clk; + memTimingSpec.CCD_L = memSpec->tCCD_L / clk; + memTimingSpec.CCD_S = memSpec->tCCD_S / clk; + memTimingSpec.CKE = memSpec->tCKE / clk; + memTimingSpec.CKESR = memSpec->tCKESR / clk; + memTimingSpec.clkMhz = memSpec->clkMHz; + // See also MemTimingSpec.cc in DRAMPower + memTimingSpec.clkPeriod = 1000.0 / memSpec->clkMHz; + memTimingSpec.DQSCK = memSpec->tDQSCK / clk; + memTimingSpec.FAW = memSpec->tNAW / clk; + memTimingSpec.RAS = memSpec->tRAS / clk; + memTimingSpec.RC = memSpec->tRC / clk; + memTimingSpec.RCD = memSpec->tRCD / clk; + memTimingSpec.REFI = memSpec->tREFI / clk; + unsigned m = Configuration::getInstance().getRefMode(); + if (m == 4) + memTimingSpec.RFC = memSpec->tRFC4 / clk; + else if (m == 2) + memTimingSpec.RFC = memSpec->tRFC2 / clk; + else + memTimingSpec.RFC = memSpec->tRFC / clk; + memTimingSpec.RL = memSpec->tRL / clk; + memTimingSpec.RP = memSpec->tRP / clk; + memTimingSpec.RRD = memSpec->tRRD_S / clk; + memTimingSpec.RRD_L = memSpec->tRRD_L / clk; + memTimingSpec.RRD_S = memSpec->tRRD_S / clk; + memTimingSpec.RTP = memSpec->tRTP / clk; + memTimingSpec.TAW = memSpec->tNAW / clk; + memTimingSpec.WL = memSpec->tWL / clk; + memTimingSpec.WR = memSpec->tWR / clk; + memTimingSpec.WTR = memSpec->tWTR_S / clk; + memTimingSpec.WTR_L = memSpec->tWTR_L / clk; + memTimingSpec.WTR_S = memSpec->tWTR_S / clk; + memTimingSpec.XP = memSpec->tXP / clk; + memTimingSpec.XPDLL = memSpec->tXPDLL / clk; + memTimingSpec.XS = memSpec->tXSR / clk; + memTimingSpec.XSDLL = memSpec->tXSRDLL / clk; + + MemPowerSpec memPowerSpec; + memPowerSpec.idd0 = memSpec->iDD0; + memPowerSpec.idd02 = memSpec->iDD02; + memPowerSpec.idd2p0 = memSpec->iDD2P0; + memPowerSpec.idd2p02 = memSpec->iDD2P02; + memPowerSpec.idd2p1 = memSpec->iDD2P1; + memPowerSpec.idd2p12 = memSpec->iDD2P12; + memPowerSpec.idd2n = memSpec->iDD2N; + memPowerSpec.idd2n2 = memSpec->iDD2N2; + memPowerSpec.idd3p0 = memSpec->iDD3P0; + memPowerSpec.idd3p02 = memSpec->iDD3P02; + memPowerSpec.idd3p1 = memSpec->iDD3P1; + memPowerSpec.idd3p12 = memSpec->iDD3P12; + memPowerSpec.idd3n = memSpec->iDD3N; + memPowerSpec.idd3n2 = memSpec->iDD3N2; + memPowerSpec.idd4r = memSpec->iDD4R; + memPowerSpec.idd4r2 = memSpec->iDD4R2; + memPowerSpec.idd4w = memSpec->iDD4W; + memPowerSpec.idd4w2 = memSpec->iDD4W2; + memPowerSpec.idd5 = memSpec->iDD5; + memPowerSpec.idd52 = memSpec->iDD52; + memPowerSpec.idd6 = memSpec->iDD6; + memPowerSpec.idd62 = memSpec->iDD62; + memPowerSpec.vdd = memSpec->vDD; + memPowerSpec.vdd2 = memSpec->vDD2; + + MemorySpecification powerSpec; + powerSpec.id = memSpec->MemoryId; + powerSpec.memoryType = memSpec->MemoryType; + powerSpec.memTimingSpec = memTimingSpec; + powerSpec.memPowerSpec = memPowerSpec; + powerSpec.memArchSpec = memArchSpec; + + DRAMPower = new libDRAMPower(powerSpec, 0); } DramWideIO::~DramWideIO()