diff --git a/benches/CMakeLists.txt b/benches/CMakeLists.txt index f7fedd64..3c6ed571 100644 --- a/benches/CMakeLists.txt +++ b/benches/CMakeLists.txt @@ -41,6 +41,7 @@ project(benches_dramsys) add_executable(${PROJECT_NAME} main.cpp + simulation.cpp addressdecoder.cpp ) @@ -49,7 +50,8 @@ set_target_properties(${PROJECT_NAME} PROPERTIES FOLDER benches) target_link_libraries(${PROJECT_NAME} DRAMSys::util DRAMSys::libdramsys - SystemC::systemc + DRAMSys::simulator + SystemC::systemc benchmark ) diff --git a/benches/configs/ddr3-example.json b/benches/configs/ddr3-example.json new file mode 100644 index 00000000..c9d51a95 --- /dev/null +++ b/benches/configs/ddr3-example.json @@ -0,0 +1,156 @@ +{ + "simulation": { + "addressmapping": { + "BANK_BIT": [ + [13, 16], + 14, + 15 + ], + "BYTE_BIT": [ + 0, + 1, + 2 + ], + "COLUMN_BIT": [ + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12 + ], + "ROW_BIT": [ + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29 + ], + "RANK_BIT": [ + 30 + ] + }, + "mcconfig": { + "PagePolicy": "Open", + "Scheduler": "FrFcfsGrp", + "RequestBufferSize": 8, + "CmdMux": "Oldest", + "RespQueue": "Fifo", + "RefreshPolicy": "Rankwise", + "RefreshMaxPostponed": 0, + "RefreshMaxPulledin": 0, + "PowerDownPolicy": "Staggered", + "PowerDownTimeout": 100 + }, + "memspec": { + "memarchitecturespec": { + "burstLength": 8, + "dataRate": 2, + "nbrOfBanks": 8, + "nbrOfColumns": 1024, + "nbrOfRanks": 2, + "nbrOfChannels": 1, + "nbrOfRows": 16384, + "width": 64, + "nbrOfDevices": 1 + }, + "memoryId": "MICRON_2GB_DDR3-1066_64bit_D_SODIMM", + "memoryType": "DDR3", + "mempowerspec": { + "idd0": 720.0, + "idd2n": 400.0, + "idd2p0": 80.0, + "idd2p1": 200.0, + "idd3n": 440.0, + "idd3p0": 240.0, + "idd3p1": 240.0, + "idd4r": 1200.0, + "idd4w": 1200.0, + "idd5": 1760.0, + "idd6": 48.0, + "vdd": 1.5 + }, + "memtimingspec": { + "AL": 0, + "CCD": 4, + "CKE": 3, + "CKESR": 4, + "CL": 7, + "DQSCK": 0, + "FAW": 20, + "RAS": 20, + "RC": 27, + "RCD": 7, + "REFI": 4160, + "RFC": 59, + "RL": 7, + "RP": 7, + "RRD": 4, + "RTP": 4, + "WL": 6, + "WR": 8, + "WTR": 4, + "XP": 4, + "XPDLL": 13, + "XS": 64, + "XSDLL": 512, + "ACTPDEN": 1, + "PRPDEN": 1, + "REFPDEN": 1, + "RTRS": 1, + "clkMhz": 533 + } + }, + "simconfig": { + "AddressOffset": 0, + "CheckTLM2Protocol": false, + "DatabaseRecording": true, + "Debug": false, + "ECCControllerMode": "Disabled", + "EnableWindowing": false, + "ErrorCSVFile": "", + "ErrorChipSeed": 42, + "PowerAnalysis": true, + "SimulationName": "ddr3", + "SimulationProgressBar": true, + "StoreMode": "NoStorage", + "ThermalSimulation": false, + "UseMalloc": false, + "WindowSize": 1000 + }, + "simulationid": "ddr3-dual-rank", + "tracesetup": [ + { + "clkMhz": 2000, + "type": "generator", + "name": "gen0", + "numRequests": 2000, + "rwRatio": 0.85, + "addressDistribution": "sequential", + "addressIncrement": 256, + }, + { + "clkMhz": 2000, + "type": "generator", + "name": "gen1", + "numRequests": 2000, + "rwRatio": 0.85, + "addressDistribution": "random", + "seed": 123456, + } + ] + } +} diff --git a/benches/simulation.cpp b/benches/simulation.cpp new file mode 100644 index 00000000..8153dfa7 --- /dev/null +++ b/benches/simulation.cpp @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2023, RPTU Kaiserslautern-Landau + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Derek Christ + */ + +#include + +#include +#include + +static void ddr3Simulation(benchmark::State& state) +{ + auto rdbuf = std::cout.rdbuf(nullptr); + + for (auto _ : state) + { + sc_core::sc_get_curr_simcontext()->reset(); + + std::filesystem::path configFile("configs/ddr3-example.json"); + std::filesystem::path resourceDirectory("configs"); + + DRAMSys::Config::Configuration configuration = DRAMSys::Config::from_path(configFile.c_str()); + + Simulator simulator(std::move(configuration), std::move(resourceDirectory)); + Simulator::run(); + } + + std::cout.rdbuf(rdbuf); +} + +BENCHMARK(ddr3Simulation); diff --git a/src/simulator/CMakeLists.txt b/src/simulator/CMakeLists.txt index a485bbd8..91a9fc47 100644 --- a/src/simulator/CMakeLists.txt +++ b/src/simulator/CMakeLists.txt @@ -55,6 +55,8 @@ target_link_libraries(${PROJECT_NAME} DRAMSys::libdramsys ) +add_library(DRAMSys::simulator ALIAS ${PROJECT_NAME}) + add_executable(DRAMSys main.cpp )