diff --git a/extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp b/extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp
index 181409a5..b2400ef2 100644
--- a/extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp
+++ b/extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp
@@ -441,7 +441,7 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, const tlm_generic
             }
         }
 
-        if (memSpec->requiresReadModifyWrite(payload)) // second WR requires RMW
+        if (memSpec->requiresMaskedWrite(payload)) // second WR requires RMW
         {
             lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank];
             if (lastCommandStart != scMaxTime)
@@ -517,7 +517,7 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, const tlm_generic
             }
         }
 
-        if (memSpec->requiresReadModifyWrite(payload)) // second WR requires RMW
+        if (memSpec->requiresMaskedWrite(payload)) // second WR requires RMW
         {
             lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankGroup];
             if (lastCommandStart != scMaxTime)