diff --git a/analyzer/analyzer/businessObjects/phases/phase.cpp b/analyzer/analyzer/businessObjects/phases/phase.cpp
index a3e467f4..71ebdcf3 100644
--- a/analyzer/analyzer/businessObjects/phases/phase.cpp
+++ b/analyzer/analyzer/businessObjects/phases/phase.cpp
@@ -28,7 +28,13 @@ void Phase::draw(QPainter *painter, const QwtScaleMap &xMap, const QwtScaleMap &
         painter->setPen(pen);
     }
 
-    drawPhaseSymbol(span.Begin(), span.End(), getYVal(drawingProperties), drawingProperties.drawText,getPhaseSymbol(), painter, xMap, yMap);
+    if(!isBankwise())
+    {
+        for(unsigned int i=0; i<drawingProperties.numberOfBanks;i++)
+        drawPhaseSymbol(span.Begin(), span.End(), i, drawingProperties.drawText,getPhaseSymbol(), painter, xMap, yMap);
+    }
+    else
+        drawPhaseSymbol(span.Begin(), span.End(), getYVal(drawingProperties), drawingProperties.drawText,getPhaseSymbol(), painter, xMap, yMap);
 
     for(Timespan span: spansOnCommandBus)
     {
diff --git a/analyzer/analyzer/businessObjects/phases/phase.h b/analyzer/analyzer/businessObjects/phases/phase.h
index 5d827512..5b2be3de 100644
--- a/analyzer/analyzer/businessObjects/phases/phase.h
+++ b/analyzer/analyzer/businessObjects/phases/phase.h
@@ -25,6 +25,7 @@ public:
     const Timespan& Span() const {return span;}
     ID Id() const {return id;}
     virtual QString Name() const = 0;
+    virtual bool isBankwise() const {return true;}
 
 protected:
     ID id;
@@ -136,6 +137,24 @@ protected:
                                                   }
 };
 
+class REFA : public AUTO_REFRESH
+{
+public:
+    using AUTO_REFRESH::AUTO_REFRESH;
+protected:
+    virtual QString Name() const override {return "REFA";}
+    virtual bool isBankwise() const {return false;}
+};
+
+class REFB : public AUTO_REFRESH
+{
+public:
+    using AUTO_REFRESH::AUTO_REFRESH;
+protected:
+    virtual QString Name() const override {return "REFB";}
+};
+
+
 class PRECHARGE_ALL : public Phase
 {
 public:
diff --git a/analyzer/analyzer/businessObjects/phases/phasefactory.cpp b/analyzer/analyzer/businessObjects/phases/phasefactory.cpp
index 37da7a93..f5ebd1a4 100644
--- a/analyzer/analyzer/businessObjects/phases/phasefactory.cpp
+++ b/analyzer/analyzer/businessObjects/phases/phasefactory.cpp
@@ -22,8 +22,10 @@ shared_ptr<Phase> PhaseFactory::CreatePhase(ID id, const QString& dbPhaseName,co
         return shared_ptr<Phase>(new ACT(id, span,trans,{Timespan(span.Begin(),span.Begin()+clk)},std::shared_ptr<Timespan>()));
     else if(dbPhaseName == "PRE_ALL")
         return shared_ptr<Phase>(new PRECHARGE_ALL(id,span,trans,{Timespan(span.Begin(),span.Begin()+clk)},std::shared_ptr<Timespan>()));
-    else if(dbPhaseName == "AUTO_REFRESH")
-        return shared_ptr<Phase>(new AUTO_REFRESH(id, span,trans,{Timespan(span.Begin(),span.Begin()+clk)},std::shared_ptr<Timespan>()));
+    else if(dbPhaseName == "REFA")
+        return shared_ptr<Phase>(new REFA(id, span,trans,{Timespan(span.Begin(),span.Begin()+clk)},std::shared_ptr<Timespan>()));
+    else if(dbPhaseName == "REFB")
+        return shared_ptr<Phase>(new REFB(id, span,trans,{Timespan(span.Begin(),span.Begin()+clk)},std::shared_ptr<Timespan>()));
 
     else if(dbPhaseName == "RD")
         return shared_ptr<Phase>(new RD(id, span,trans,{Timespan(span.Begin(),span.Begin()+clk)},std::shared_ptr<Timespan>(new Timespan(trans->SpanOnDataStrobe()))));
diff --git a/dram/dramSys/dramSys.pro b/dram/dramSys/dramSys.pro
index f0052a93..6e5bbe27 100644
--- a/dram/dramSys/dramSys.pro
+++ b/dram/dramSys/dramSys.pro
@@ -8,24 +8,24 @@ LIBS += -L/opt/systemc/lib-linux64 -lsystemc
 LIBS += -L/opt/boost/lib -lboost_filesystem -lboost_system
 LIBS += -L/opt/sqlite3/lib -lsqlite3
 LIBS += -lpthread
-LIBS += -lxerces-c
-LIBS += -L../src/common/third_party/DRAMPower/src/ -ldrampowerxml
-LIBS += -L../src/common/third_party/DRAMPower/src/ -ldrampower
+#LIBS += -lxerces-c
+#LIBS += -L../src/common/third_party/DRAMPower/src/ -ldrampowerxml
+#LIBS += -L../src/common/third_party/DRAMPower/src/ -ldrampower
 
 INCLUDEPATH += /opt/systemc/include
 INCLUDEPATH += /opt/boost/include
 INCLUDEPATH += /opt/sqlite3/include
-INCLUDEPATH += ../src/common/third_party/DRAMPower/src
-INCLUDEPATH += ../src/common/third_party/DRAMPower/src/libdrampower
+#INCLUDEPATH += ../src/common/third_party/DRAMPower/src
+#INCLUDEPATH += ../src/common/third_party/DRAMPower/src/libdrampower
 
 DEFINES += TIXML_USE_STL
 DEFINES += SC_INCLUDE_DYNAMIC_PROCESSES
-DEFINES += USE_XERCES=1
+#DEFINES += USE_XERCES=1
 
 QMAKE_CXXFLAGS += -std=c++11
 QMAKE_CXXFLAGS += -isystem /opt/systemc/include
 QMAKE_CXXFLAGS += -isystem /opt/boost/include
-QMAKE_CXXFLAGS += -iquote ../src/common/third_party/DRAMPower/src/
+#QMAKE_CXXFLAGS += -iquote ../src/common/third_party/DRAMPower/src/
 
 SOURCES += \
     ../src/common/third_party/tinyxml2.cpp \
diff --git a/dram/resources/configs/memconfigs/fifo.xml b/dram/resources/configs/memconfigs/fifo.xml
index 2e23e330..603049f2 100644
--- a/dram/resources/configs/memconfigs/fifo.xml
+++ b/dram/resources/configs/memconfigs/fifo.xml
@@ -1,6 +1,6 @@
 <memspec>
   <memconfig>
-    <parameter id="bankwiseLogic" type="bool" value="0" />
+    <parameter id="bankwiseLogic" type="bool" value="1" />
     <parameter id="openPagePolicy" type="bool" value="1" />
     <parameter id="adaptiveOpenPagePolicy" type="bool" value="0" />
     <parameter id="refreshAwareScheduling" type="bool" value="0" />
diff --git a/dram/resources/simulations/sim-batch.xml b/dram/resources/simulations/sim-batch.xml
index 7b793ec0..f1c7c731 100644
--- a/dram/resources/simulations/sim-batch.xml
+++ b/dram/resources/simulations/sim-batch.xml
@@ -16,7 +16,7 @@
 
 
 <trace-setup id="media">
-      <device clkMhz="800">mediabench-epic_32.stl</device> 
+      <device clkMhz="800">chstone-sha_32.stl</device> 
 </trace-setup>
     
   </trace-setups>
diff --git a/dram/src/common/TlmRecorder.cpp b/dram/src/common/TlmRecorder.cpp
index e6bad2d4..089f24db 100644
--- a/dram/src/common/TlmRecorder.cpp
+++ b/dram/src/common/TlmRecorder.cpp
@@ -191,7 +191,8 @@ void TlmRecorder::createTables(string pathToURI)
 void TlmRecorder::setUpTransactionTerminatingPhases()
 {
     transactionTerminatingPhases.push_back(tlm::END_RESP);
-    transactionTerminatingPhases.push_back(static_cast<const tlm::tlm_phase>(END_AUTO_REFRESH));
+    transactionTerminatingPhases.push_back(static_cast<const tlm::tlm_phase>(END_REFA));
+    transactionTerminatingPhases.push_back(static_cast<const tlm::tlm_phase>(END_REFB));
     transactionTerminatingPhases.push_back(static_cast<const tlm::tlm_phase>(END_PDNP));
     transactionTerminatingPhases.push_back(static_cast<const tlm::tlm_phase>(END_PDNA));
     transactionTerminatingPhases.push_back(static_cast<const tlm::tlm_phase>(END_SREF));
diff --git a/dram/src/common/protocol.h b/dram/src/common/protocol.h
index 41e5daeb..8cebad64 100755
--- a/dram/src/common/protocol.h
+++ b/dram/src/common/protocol.h
@@ -11,8 +11,11 @@ DECLARE_EXTENDED_PHASE(END_PRE_ALL);
 DECLARE_EXTENDED_PHASE(BEGIN_ACT);
 DECLARE_EXTENDED_PHASE(END_ACT);
 
-DECLARE_EXTENDED_PHASE(BEGIN_AUTO_REFRESH);
-DECLARE_EXTENDED_PHASE(END_AUTO_REFRESH);
+DECLARE_EXTENDED_PHASE(BEGIN_REFA);
+DECLARE_EXTENDED_PHASE(END_REFA);
+
+DECLARE_EXTENDED_PHASE(BEGIN_REFB);
+DECLARE_EXTENDED_PHASE(END_REFB);
 
 
 // Phases for Read and Write
diff --git a/dram/src/controller/Controller.h b/dram/src/controller/Controller.h
index 34a1c4e8..c8462a44 100644
--- a/dram/src/controller/Controller.h
+++ b/dram/src/controller/Controller.h
@@ -164,7 +164,13 @@ void Controller<BUSWIDTH>::send(const ScheduledCommand &command, tlm_generic_pay
         controllerCorePEQ.notify(payload, BEGIN_WRA, command.getStart() - sc_time_stamp());
         break;
     case Command::AutoRefresh:
-        controllerCorePEQ.notify(payload, BEGIN_AUTO_REFRESH, command.getStart() - sc_time_stamp());
+        if(!Configuration::getInstance().BankwiseLogic)
+        {
+            if(command.getBank() == Bank(0))
+                controllerCorePEQ.notify(payload, BEGIN_REFA, command.getStart() - sc_time_stamp());
+        }
+        else
+            controllerCorePEQ.notify(payload, BEGIN_REFB, command.getStart() - sc_time_stamp());
         break;
     case Command::Activate:
         controllerCorePEQ.notify(payload, BEGIN_ACT, command.getStart() - sc_time_stamp());
@@ -238,8 +244,10 @@ void Controller<BUSWIDTH>::controllerCorePEQCallback(tlm_generic_payload &payloa
 
         if (phase == BEGIN_RD || phase == BEGIN_WR)
             scheduleNextPayload();
-        else if (phase == BEGIN_AUTO_REFRESH)
-            printDebugMessage("Entering auto refresh on bank " + to_string(bank.ID()));
+        else if (phase == BEGIN_REFB)
+            printDebugMessage("Entering REFB on bank " + to_string(bank.ID()));
+        else if (phase == BEGIN_REFA)
+            printDebugMessage("Entering REFA");
         else if (containsPhase(phase, { BEGIN_PDNA, BEGIN_PDNP, BEGIN_SREF }))
             printDebugMessage("Entering PowerDown " + phaseNameToString(phase) + " on bank " + to_string(bank.ID()));
         else if (containsPhase(phase, { END_PDNA, END_PDNP, END_SREF }))
@@ -396,7 +404,7 @@ void Controller<BUSWIDTH>::dramPEQCallback(tlm_generic_payload &payload, const t
         sendToFrontend(payload, BEGIN_RESP, SC_ZERO_TIME);
         scheduleNextPayload();
     }
-    else if (phase == END_AUTO_REFRESH)
+    else if (phase == END_REFA || phase == END_REFB)//TODO send all to sleep for REFA??
     {
         printDebugMessage("Finished auto refresh on bank " + to_string(bank.ID()));
         if(numberOfPayloadsInSystem[bank] == 0)
diff --git a/dram/src/simulation/Dram.h b/dram/src/simulation/Dram.h
index 69c882ba..0770e22a 100644
--- a/dram/src/simulation/Dram.h
+++ b/dram/src/simulation/Dram.h
@@ -19,38 +19,38 @@
 #include "../common/protocol.h"
 #include "../common/Utils.h"
 #include "../common/TlmRecorder.h"
-#include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
-#include "../common/third_party/DRAMPower/src/xmlparser/MemSpecParser.h"
-#include "../common/third_party/DRAMPower/src/MemorySpecification.h"
-#include "../common/third_party/DRAMPower/src/MemCommand.h"
+//#include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
+//#include "../common/third_party/DRAMPower/src/xmlparser/MemSpecParser.h"
+//#include "../common/third_party/DRAMPower/src/MemorySpecification.h"
+//#include "../common/third_party/DRAMPower/src/MemCommand.h"
 
 using namespace std;
 using namespace tlm;
 using namespace core;
-using namespace Data;
+//using namespace Data;
 
 template<unsigned int BUSWIDTH = 128, unsigned int WORDS = 4096, bool STORE = true, bool FIXED_BL = false,
         unsigned int FIXED_BL_VALUE = 0>
 struct Dram: sc_module
 {
     tlm_utils::simple_target_socket<Dram, BUSWIDTH, tlm::tlm_base_protocol_types> tSocket;
-    libDRAMPower *DRAMPower;
+    //libDRAMPower *DRAMPower;
 
     SC_CTOR(Dram) : tSocket("socket")
     {
         tSocket.register_nb_transport_fw(this, &Dram::nb_transport_fw);
 
-        MemorySpecification memSpec(MemSpecParser::getMemSpecFromXML(Configuration::getInstance().memspecUri));
-        //MemorySpecification::getMemSpecFromXML(Configuration::getInstance().memspecUri));
-        DRAMPower = new libDRAMPower( memSpec, 1,1,1,0,0 );
+//        MemorySpecification memSpec(MemSpecParser::getMemSpecFromXML(Configuration::getInstance().memspecUri));
+//        MemorySpecification::getMemSpecFromXML(Configuration::getInstance().memspecUri));
+//        DRAMPower = new libDRAMPower( memSpec, 1,1,1,0,0 );
     }
 
     ~Dram()
     {
-        DRAMPower->updateCounters(true);
-        DRAMPower->getEnergy();
-        cout << "Total Energy" << "\t" << DRAMPower->mpm.energy.total_energy << endl;
-        cout << "Average Power" << "\t" << DRAMPower->mpm.power.average_power << endl;
+//        DRAMPower->updateCounters(true);
+//        DRAMPower->getEnergy();
+//        cout << "Total Energy" << "\t" << DRAMPower->mpm.energy.total_energy << endl;
+//        cout << "Average Power" << "\t" << DRAMPower->mpm.power.average_power << endl;
     }
 
     virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& payload, tlm::tlm_phase& phase, sc_time& delay)
@@ -63,43 +63,49 @@ struct Dram: sc_module
 
         if (phase == BEGIN_PRE)
         {
-            DRAMPower->doCommand(MemCommand::PRE, bank, cycle);
+            //DRAMPower->doCommand(MemCommand::PRE, bank, cycle);
             sendToController(payload, END_PRE, delay + getExecutionTime(Command::Precharge, payload));
         }
         else if (phase == BEGIN_PRE_ALL)
         {
-            DRAMPower->doCommand(MemCommand::PREA, bank, cycle);
+            //DRAMPower->doCommand(MemCommand::PREA, bank, cycle);
             sendToController(payload, END_PRE_ALL,delay +  getExecutionTime(Command::PrechargeAll, payload));
         }
         else if (phase == BEGIN_ACT)
         {
-            DRAMPower->doCommand(MemCommand::ACT, bank, cycle);
+            //DRAMPower->doCommand(MemCommand::ACT, bank, cycle);
             sendToController(payload, END_ACT, delay +  getExecutionTime(Command::Activate, payload));
         }
         else if (phase == BEGIN_WR)
         {
-            DRAMPower->doCommand(MemCommand::WR, bank, cycle);
+            //DRAMPower->doCommand(MemCommand::WR, bank, cycle);
             sendToController(payload, END_WR, delay +  getExecutionTime(Command::Write, payload));
         }
         else if (phase == BEGIN_RD)
         {
-            DRAMPower->doCommand(MemCommand::RD, bank, cycle);
+            //DRAMPower->doCommand(MemCommand::RD, bank, cycle);
             sendToController(payload, END_RD, delay +  getExecutionTime(Command::Read, payload));
         }
         else if (phase == BEGIN_WRA)
         {
-            DRAMPower->doCommand(MemCommand::WRA, bank, cycle);
+            //DRAMPower->doCommand(MemCommand::WRA, bank, cycle);
             sendToController(payload, END_WRA, delay +  getExecutionTime(Command::WriteA, payload));
         }
         else if (phase == BEGIN_RDA)
         {
-            DRAMPower->doCommand(MemCommand::RDA, bank, cycle);
+            //DRAMPower->doCommand(MemCommand::RDA, bank, cycle);
             sendToController(payload, END_RDA, delay +  getExecutionTime(Command::ReadA, payload));
         }
-        else if (phase == BEGIN_AUTO_REFRESH)
+        else if (phase == BEGIN_REFA)
         {
-            DRAMPower->doCommand(MemCommand::REF, bank, cycle);
-            sendToController(payload, END_AUTO_REFRESH, delay +  getExecutionTime(Command::AutoRefresh, payload));
+            //DRAMPower->doCommand(MemCommand::REF, bank, cycle);
+            sendToController(payload, END_REFA, delay +  getExecutionTime(Command::AutoRefresh, payload));
+        }
+
+        else if (phase == BEGIN_REFB)
+        {
+            //DRAMPower->doCommand(MemCommand::REF, bank, cycle);
+            sendToController(payload, END_REFB, delay +  getExecutionTime(Command::AutoRefresh, payload));
         }
 
         //Powerdown phases have to be started and ended by the controller, because they do not have a fixed length
@@ -109,7 +115,7 @@ struct Dram: sc_module
             {
                 if(bank == 0)
                 {
-                    DRAMPower->doCommand(MemCommand::PDN_S_PRE, bank, cycle);
+                    //DRAMPower->doCommand(MemCommand::PDN_S_PRE, bank, cycle);
                 }
             }
         }
@@ -119,7 +125,7 @@ struct Dram: sc_module
             {
                 if(bank == 0)
                 {
-                    DRAMPower->doCommand(MemCommand::PUP_PRE, bank, cycle);
+                    //DRAMPower->doCommand(MemCommand::PUP_PRE, bank, cycle);
                 }
             }
         }
@@ -129,7 +135,7 @@ struct Dram: sc_module
             {
                 if(bank == 0)
                 {
-                    DRAMPower->doCommand(MemCommand::PDN_S_ACT, bank, cycle);
+                    //DRAMPower->doCommand(MemCommand::PDN_S_ACT, bank, cycle);
                 }
             }
         }
@@ -139,17 +145,17 @@ struct Dram: sc_module
             {
                 if(bank == 0)
                 {
-                    DRAMPower->doCommand(MemCommand::PUP_ACT, bank, cycle);
+                    //DRAMPower->doCommand(MemCommand::PUP_ACT, bank, cycle);
                 }
             }
         }
         else if (phase == BEGIN_SREF)
         {
-            DRAMPower->doCommand(MemCommand::SREN, bank, cycle);
+            //DRAMPower->doCommand(MemCommand::SREN, bank, cycle);
         }
         else if (phase == END_SREF)
         {
-            DRAMPower->doCommand(MemCommand::SREX, bank, cycle);
+            //DRAMPower->doCommand(MemCommand::SREX, bank, cycle);
         }
         else
         {
@@ -172,4 +178,6 @@ struct Dram: sc_module
 
 };
 
+
+
 #endif /* DRAM_H_ */