From c88486d842689bc2fa27abdc1875529493e7200a Mon Sep 17 00:00:00 2001 From: Janik Schlemminger Date: Tue, 5 Aug 2014 00:07:22 +0200 Subject: [PATCH 1/5] memcpy bug --- dram/dramSys/dramSys.pro | 3 ++- dram/resources/configs/memconfigs/fifo.xml | 2 +- dram/resources/simulations/sim-batch.xml | 2 +- dram/src/simulation/Dram.h | 3 ++- dram/src/simulation/main.cpp | 1 + 5 files changed, 7 insertions(+), 4 deletions(-) diff --git a/dram/dramSys/dramSys.pro b/dram/dramSys/dramSys.pro index 61f4c916..c4693944 100644 --- a/dram/dramSys/dramSys.pro +++ b/dram/dramSys/dramSys.pro @@ -8,13 +8,14 @@ LIBS += -L/opt/systemc/lib-linux64 -lsystemc LIBS += -L/opt/boost/lib -lboost_filesystem -lboost_system LIBS += -L/opt/sqlite3/lib -lsqlite3 LIBS += -lpthread -LIBS += -lxerces-c +LIBS += -L/opt/xerces-c-3.1.1/lib -lxerces-c LIBS += -L../src/common/third_party/DRAMPower/src/ -ldrampowerxml LIBS += -L../src/common/third_party/DRAMPower/src/ -ldrampower INCLUDEPATH += /opt/systemc/include INCLUDEPATH += /opt/boost/include INCLUDEPATH += /opt/sqlite3/include +INCLUDEPATH += /opt/xerces-c-3.1.1/include INCLUDEPATH += ../src/common/third_party/DRAMPower/src INCLUDEPATH += ../src/common/third_party/DRAMPower/src/libdrampower diff --git a/dram/resources/configs/memconfigs/fifo.xml b/dram/resources/configs/memconfigs/fifo.xml index 603049f2..2e23e330 100644 --- a/dram/resources/configs/memconfigs/fifo.xml +++ b/dram/resources/configs/memconfigs/fifo.xml @@ -1,6 +1,6 @@ - + diff --git a/dram/resources/simulations/sim-batch.xml b/dram/resources/simulations/sim-batch.xml index f1c7c731..89adea06 100644 --- a/dram/resources/simulations/sim-batch.xml +++ b/dram/resources/simulations/sim-batch.xml @@ -16,7 +16,7 @@ - chstone-sha_32.stl + small.stl diff --git a/dram/src/simulation/Dram.h b/dram/src/simulation/Dram.h index bdb70e99..42ca1880 100644 --- a/dram/src/simulation/Dram.h +++ b/dram/src/simulation/Dram.h @@ -56,7 +56,7 @@ class column column(int bytes) { - bytes = bytes; + this->bytes = bytes; data = new unsigned char[bytes]; } @@ -68,6 +68,7 @@ class column void set(unsigned char * payloadDataPtr) { printf("Dest: %p Source: %p\n",data,payloadDataPtr); + printf("Bytes: %i\n",bytes); cout << "mem" ; memcpy(data, payloadDataPtr, bytes); // XXX hier knallts cout << "copy" << endl; diff --git a/dram/src/simulation/main.cpp b/dram/src/simulation/main.cpp index c064bc67..00797a88 100644 --- a/dram/src/simulation/main.cpp +++ b/dram/src/simulation/main.cpp @@ -32,6 +32,7 @@ int main(int argc, char **argv) int sc_main(int argc, char **argv) { + cout<<"hello"< Date: Tue, 5 Aug 2014 00:22:03 +0200 Subject: [PATCH 2/5] destructor --- dram/src/simulation/Dram.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/dram/src/simulation/Dram.h b/dram/src/simulation/Dram.h index 42ca1880..7ff6e630 100644 --- a/dram/src/simulation/Dram.h +++ b/dram/src/simulation/Dram.h @@ -62,7 +62,7 @@ class column ~column() { - //delete data; + delete data; } void set(unsigned char * payloadDataPtr) From 609e568fbca28d0a4c9e1b5ef6ca427898148740 Mon Sep 17 00:00:00 2001 From: Matthias Jung Date: Tue, 5 Aug 2014 16:58:15 +0200 Subject: [PATCH 3/5] Added the tRAS timing constraint into the precharge checker --- .../core/scheduling/checker/PrechargeChecker.cpp | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/dram/src/controller/core/scheduling/checker/PrechargeChecker.cpp b/dram/src/controller/core/scheduling/checker/PrechargeChecker.cpp index f8fd5a42..204e5ead 100644 --- a/dram/src/controller/core/scheduling/checker/PrechargeChecker.cpp +++ b/dram/src/controller/core/scheduling/checker/PrechargeChecker.cpp @@ -14,6 +14,7 @@ void PrechargeChecker::delayToSatisfyConstraints(ScheduledCommand& command) cons { sc_assert(command.getCommand() == Command::Precharge); + ScheduledCommand lastCommand = state.getLastScheduledCommand(command.getBank()); if (lastCommand.isValidCommand()) @@ -34,6 +35,13 @@ void PrechargeChecker::delayToSatisfyConstraints(ScheduledCommand& command) cons reportFatal("Precharge Checker", "Precharge can not follow " + commandToString(lastCommand.getCommand())); } + ScheduledCommand lastActivate = state.getLastCommand(Command::Activate, command.getBank()); + if (lastActivate.isValidCommand()) + { + command.delayToMeetConstraint(lastActivate.getStart(), config.Timings.tRAS); + } + + state.bus.moveCommandToNextFreeSlot(command); } From 327608b691a954705fbdb1335a06025c20723210 Mon Sep 17 00:00:00 2001 From: Matthias Jung Date: Tue, 5 Aug 2014 16:59:22 +0200 Subject: [PATCH 4/5] commented out the saving part --- dram/src/simulation/Dram.h | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/dram/src/simulation/Dram.h b/dram/src/simulation/Dram.h index bdb70e99..49725c46 100644 --- a/dram/src/simulation/Dram.h +++ b/dram/src/simulation/Dram.h @@ -56,21 +56,19 @@ class column column(int bytes) { - bytes = bytes; + this->bytes = bytes; data = new unsigned char[bytes]; } ~column() { - //delete data; + delete data; } void set(unsigned char * payloadDataPtr) { - printf("Dest: %p Source: %p\n",data,payloadDataPtr); - cout << "mem" ; - memcpy(data, payloadDataPtr, bytes); // XXX hier knallts - cout << "copy" << endl; + //printf("Dest: %p Source: %p\n",data,payloadDataPtr); + memcpy(data, payloadDataPtr, bytes); } void get(unsigned char * payloadDataPtr) @@ -134,9 +132,9 @@ struct Dram: sc_module sendToController(payload, END_WR, delay + getExecutionTime(Command::Write, payload)); // Save: - column * c = new column(16); - c->set(payload.get_data_ptr()); // <-- hier drin knallts - memory[payload.get_address()] = c; + //column * c = new column(16); + //c->set(payload.get_data_ptr()); + //memory[payload.get_address()] = c; } else if (phase == BEGIN_RD) { From 15f07b00176e084ae535af13e8b2ca88bf176445 Mon Sep 17 00:00:00 2001 From: Janik Schlemminger Date: Tue, 5 Aug 2014 19:33:16 +0200 Subject: [PATCH 5/5] precharge allchecker tRas, simulation memory --- dram/resources/simulations/sim-batch.xml | 3 +- .../checker/PrechargeAllChecker.cpp | 6 ++ dram/src/simulation/Dram.h | 67 ++++--------------- 3 files changed, 21 insertions(+), 55 deletions(-) diff --git a/dram/resources/simulations/sim-batch.xml b/dram/resources/simulations/sim-batch.xml index 89adea06..b1f47a18 100644 --- a/dram/resources/simulations/sim-batch.xml +++ b/dram/resources/simulations/sim-batch.xml @@ -16,7 +16,8 @@ - small.stl + + chstone-sha_32.stl diff --git a/dram/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp b/dram/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp index 112d4f90..92820e76 100644 --- a/dram/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp +++ b/dram/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp @@ -53,6 +53,12 @@ void PrechargeAllChecker::delayToSatisfyConstraints(ScheduledCommand& command) c } } + ScheduledCommand lastActivate = state.getLastCommand(Command::Activate, command.getBank()); + if (lastActivate.isValidCommand()) + { + command.delayToMeetConstraint(lastActivate.getStart(), config.Timings.tRAS); + } + state.bus.moveCommandToNextFreeSlot(command); } diff --git a/dram/src/simulation/Dram.h b/dram/src/simulation/Dram.h index 22e48d74..ba252c55 100644 --- a/dram/src/simulation/Dram.h +++ b/dram/src/simulation/Dram.h @@ -30,7 +30,7 @@ using namespace core; using namespace Data; -#define POWER +#define POWER //not better to define in simulation xml? also flag for storage simulation #ifdef POWER #define IFPOW(x) x @@ -39,43 +39,6 @@ using namespace Data; #endif -class column -{ - private: - - unsigned char * data; - unsigned int bytes; - - public: - - column() - { - bytes = 0; - data = NULL; - } - - column(int bytes) - { - this->bytes = bytes; - data = new unsigned char[bytes]; - } - - ~column() - { - delete data; - } - - void set(unsigned char * payloadDataPtr) - { - memcpy(data, payloadDataPtr, bytes); - } - - void get(unsigned char * payloadDataPtr) - { - memcpy(payloadDataPtr, data, bytes); - } -}; - template struct Dram: sc_module @@ -83,7 +46,7 @@ struct Dram: sc_module tlm_utils::simple_target_socket tSocket; IFPOW(libDRAMPower *DRAMPower); - map< unsigned long int, column * > memory; + map< unsigned long int, unsigned char[BUSWIDTH/2] > memory; SC_CTOR(Dram) : tSocket("socket") { @@ -128,28 +91,24 @@ struct Dram: sc_module else if (phase == BEGIN_WR) { IFPOW(DRAMPower->doCommand(MemCommand::WR, bank, cycle)); + //save data: + memcpy(&memory[payload.get_address()], payload.get_data_ptr(), BUSWIDTH/8); sendToController(payload, END_WR, delay + getExecutionTime(Command::Write, payload)); - - // Save: - //column * c = new column(16); - //c->set(payload.get_data_ptr()); - //memory[payload.get_address()] = c; } else if (phase == BEGIN_RD) { IFPOW(DRAMPower->doCommand(MemCommand::RD, bank, cycle)); sendToController(payload, END_RD, delay + getExecutionTime(Command::Read, payload)); - // Load: - //if(memory.count(payload.get_address()) == 1) - //{ - // column * c = memory[payload.get_address()]; - // c->get(payload.get_data_ptr()); - //} - //else - //{ - // SC_REPORT_WARNING ("DRAM", "Reading from an empty memory location"); - //} + // Load data: + if(memory.count(payload.get_address()) == 1) + { + memcpy(payload.get_data_ptr(), &memory[payload.get_address()], BUSWIDTH/8); + } + else + { + SC_REPORT_WARNING ("DRAM", "Reading from an empty memory location."); + } } else if (phase == BEGIN_WRA) {