diff --git a/dram/dramSys/dramSys.pro b/dram/dramSys/dramSys.pro index b521d493..78ebe06a 100644 --- a/dram/dramSys/dramSys.pro +++ b/dram/dramSys/dramSys.pro @@ -15,6 +15,7 @@ LIBS += -L../src/common/third_party/DRAMPower/src/ -ldrampower INCLUDEPATH += /opt/systemc/include INCLUDEPATH += /opt/boost/include INCLUDEPATH += /opt/sqlite3/include +INCLUDEPATH += /opt/xerces-c-3.1.1/include INCLUDEPATH += ../src/common/third_party/DRAMPower/src INCLUDEPATH += ../src/common/third_party/DRAMPower/src/libdrampower diff --git a/dram/resources/configs/memconfigs/fifo.xml b/dram/resources/configs/memconfigs/fifo.xml index 603049f2..2e23e330 100644 --- a/dram/resources/configs/memconfigs/fifo.xml +++ b/dram/resources/configs/memconfigs/fifo.xml @@ -1,6 +1,6 @@ - + diff --git a/dram/resources/simulations/sim-batch.xml b/dram/resources/simulations/sim-batch.xml index f0aa5a30..a5a1c593 100644 --- a/dram/resources/simulations/sim-batch.xml +++ b/dram/resources/simulations/sim-batch.xml @@ -10,7 +10,7 @@ - mediabench-epic_32.stl + mediabench-epic_32.stl diff --git a/dram/src/controller/Controller.h b/dram/src/controller/Controller.h index ea8adc02..a7505976 100644 --- a/dram/src/controller/Controller.h +++ b/dram/src/controller/Controller.h @@ -116,7 +116,7 @@ template void Controller::buildScheduler() { string selectedScheduler = Configuration::getInstance().Scheduler; - //selectedScheduler == "ReadWriteGrouper"; + selectedScheduler = "ReadWriteGrouper"; if (selectedScheduler == "FR_FCFS") { diff --git a/dram/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp b/dram/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp index 112d4f90..92820e76 100644 --- a/dram/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp +++ b/dram/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp @@ -53,6 +53,12 @@ void PrechargeAllChecker::delayToSatisfyConstraints(ScheduledCommand& command) c } } + ScheduledCommand lastActivate = state.getLastCommand(Command::Activate, command.getBank()); + if (lastActivate.isValidCommand()) + { + command.delayToMeetConstraint(lastActivate.getStart(), config.Timings.tRAS); + } + state.bus.moveCommandToNextFreeSlot(command); } diff --git a/dram/src/controller/core/scheduling/checker/PrechargeChecker.cpp b/dram/src/controller/core/scheduling/checker/PrechargeChecker.cpp index f8fd5a42..204e5ead 100644 --- a/dram/src/controller/core/scheduling/checker/PrechargeChecker.cpp +++ b/dram/src/controller/core/scheduling/checker/PrechargeChecker.cpp @@ -14,6 +14,7 @@ void PrechargeChecker::delayToSatisfyConstraints(ScheduledCommand& command) cons { sc_assert(command.getCommand() == Command::Precharge); + ScheduledCommand lastCommand = state.getLastScheduledCommand(command.getBank()); if (lastCommand.isValidCommand()) @@ -34,6 +35,13 @@ void PrechargeChecker::delayToSatisfyConstraints(ScheduledCommand& command) cons reportFatal("Precharge Checker", "Precharge can not follow " + commandToString(lastCommand.getCommand())); } + ScheduledCommand lastActivate = state.getLastCommand(Command::Activate, command.getBank()); + if (lastActivate.isValidCommand()) + { + command.delayToMeetConstraint(lastActivate.getStart(), config.Timings.tRAS); + } + + state.bus.moveCommandToNextFreeSlot(command); } diff --git a/dram/src/controller/scheduler/Scheduler.cpp b/dram/src/controller/scheduler/Scheduler.cpp index b7bbbbb4..f86a59d0 100644 --- a/dram/src/controller/scheduler/Scheduler.cpp +++ b/dram/src/controller/scheduler/Scheduler.cpp @@ -1,12 +1,16 @@ #include "Scheduler.h" #include "../../common/DebugManager.h" +#include + +using namespace std; using namespace scheduler; std::string Scheduler::sendername = "scheduler"; void Scheduler::printDebugMessage(std::string message) { - DebugManager::getInstance().printDebugMessage(Scheduler::sendername, message); + cout << "scheduler: " << message << std::endl; + //DebugManager::getInstance().printDebugMessage(Scheduler::sendername, message); } diff --git a/dram/src/controller/scheduler/readwritegrouper.cpp b/dram/src/controller/scheduler/readwritegrouper.cpp index b28057db..6c2d9306 100644 --- a/dram/src/controller/scheduler/readwritegrouper.cpp +++ b/dram/src/controller/scheduler/readwritegrouper.cpp @@ -20,12 +20,13 @@ ReadWriteGrouper::~ReadWriteGrouper() void ReadWriteGrouper::schedule(gp *payload) { tlm_command command = payload->get_command(); - printDebugMessage("Scheduling new payload"); if(batches.size() > 2) { if(command == TLM_READ_COMMAND) { + //printDebugMessage("Scheduling read"); + if(schedulingReadCausesHazardWithQueuedWrite(payload)) { printDebugMessage("Scheduling read causes hazard with queued write"); @@ -37,6 +38,7 @@ void ReadWriteGrouper::schedule(gp *payload) } else if(command == TLM_WRITE_COMMAND) { + //printDebugMessage("Scheduling write"); getLatestWriteBatch().schedule(payload); } } @@ -44,6 +46,8 @@ void ReadWriteGrouper::schedule(gp *payload) { if(command == TLM_READ_COMMAND) { + //printDebugMessage("Scheduling read"); + if(getLatestReadBatch().hasPayloads() && schedulingReadCausesHazardWithQueuedWrite(payload)) { printDebugMessage("Scheduling read causes hazard with queued write"); @@ -52,6 +56,7 @@ void ReadWriteGrouper::schedule(gp *payload) } else if(!getLatestReadBatch().hasPayloads() && getLatestWriteBatch().hasPayloads()) { + printDebugMessage("Scheduling read, but there are writes to be processed first"); batches.erase(batches.begin()); batches.push_back(shared_ptr(new FR_FCFS(controllerCore,true,false))); batches.push_back(shared_ptr(new FR_FCFS(controllerCore,true,false))); @@ -61,6 +66,7 @@ void ReadWriteGrouper::schedule(gp *payload) } else if(command == TLM_WRITE_COMMAND) { + //printDebugMessage("Scheduling write"); getLatestWriteBatch().schedule(payload); } } diff --git a/dram/src/simulation/Dram.h b/dram/src/simulation/Dram.h index bdb70e99..9b306f27 100644 --- a/dram/src/simulation/Dram.h +++ b/dram/src/simulation/Dram.h @@ -30,7 +30,7 @@ using namespace core; using namespace Data; -#define POWER +#define POWER //not better to define in simulation xml? also flag for storage simulation #ifdef POWER #define IFPOW(x) x @@ -39,46 +39,6 @@ using namespace Data; #endif -class column -{ - private: - - unsigned char * data; - unsigned int bytes; - - public: - - column() - { - bytes = 0; - data = NULL; - } - - column(int bytes) - { - bytes = bytes; - data = new unsigned char[bytes]; - } - - ~column() - { - //delete data; - } - - void set(unsigned char * payloadDataPtr) - { - printf("Dest: %p Source: %p\n",data,payloadDataPtr); - cout << "mem" ; - memcpy(data, payloadDataPtr, bytes); // XXX hier knallts - cout << "copy" << endl; - } - - void get(unsigned char * payloadDataPtr) - { - memcpy(payloadDataPtr, data, bytes); - } -}; - template struct Dram: sc_module @@ -86,7 +46,7 @@ struct Dram: sc_module tlm_utils::simple_target_socket tSocket; IFPOW(libDRAMPower *DRAMPower); - map< unsigned long int, column * > memory; + map< unsigned long int, unsigned char[BUSWIDTH/2] > memory; SC_CTOR(Dram) : tSocket("socket") { @@ -131,28 +91,24 @@ struct Dram: sc_module else if (phase == BEGIN_WR) { IFPOW(DRAMPower->doCommand(MemCommand::WR, bank, cycle)); + //save data: + memcpy(&memory[payload.get_address()], payload.get_data_ptr(), BUSWIDTH/8); sendToController(payload, END_WR, delay + getExecutionTime(Command::Write, payload)); - - // Save: - column * c = new column(16); - c->set(payload.get_data_ptr()); // <-- hier drin knallts - memory[payload.get_address()] = c; } else if (phase == BEGIN_RD) { IFPOW(DRAMPower->doCommand(MemCommand::RD, bank, cycle)); sendToController(payload, END_RD, delay + getExecutionTime(Command::Read, payload)); - // Load: - //if(memory.count(payload.get_address()) == 1) - //{ - // column * c = memory[payload.get_address()]; - // c->get(payload.get_data_ptr()); - //} - //else - //{ - // SC_REPORT_WARNING ("DRAM", "Reading from an empty memory location"); - //} + // Load data: + if(memory.count(payload.get_address()) == 1) + { + memcpy(payload.get_data_ptr(), &memory[payload.get_address()], BUSWIDTH/8); + } + else + { + //SC_REPORT_WARNING ("DRAM", "Reading from an empty memory location."); + } } else if (phase == BEGIN_WRA) { diff --git a/dram/src/simulation/SimulationManager.cpp b/dram/src/simulation/SimulationManager.cpp index 83173b8b..fa394f78 100644 --- a/dram/src/simulation/SimulationManager.cpp +++ b/dram/src/simulation/SimulationManager.cpp @@ -1,4 +1,4 @@ -/* + /* * SimulationManager.cpp * * Created on: Apr 12, 2014 diff --git a/dram/src/simulation/TracePlayer.h b/dram/src/simulation/TracePlayer.h index 5581ed6c..0e604822 100644 --- a/dram/src/simulation/TracePlayer.h +++ b/dram/src/simulation/TracePlayer.h @@ -115,15 +115,15 @@ void TracePlayer::generateNextPayload() payload->set_command(TLM_WRITE_COMMAND); // Parse and set data - file >> data; - unsigned int counter = 0; - for(int i = 0; i < 16*2-2; i=i+2) // TODO column / burst breite - { - std::string byteString = "0x"; - byteString.append(data.substr(i+2, 2)); - //cout << byteString << " " << std::stoi(byteString.c_str(), 0, 16) << endl; - dataElement[counter++] = std::stoi(byteString.c_str(), 0, 16); - } +// file >> data; +// unsigned int counter = 0; +// for(int i = 0; i < 16*2-2; i=i+2) // TODO column / burst breite +// { +// std::string byteString = "0x"; +// byteString.append(data.substr(i+2, 2)); +// //cout << byteString << " " << std::stoi(byteString.c_str(), 0, 16) << endl; +// dataElement[counter++] = std::stoi(byteString.c_str(), 0, 16); +// } } else { diff --git a/dram/src/simulation/main.cpp b/dram/src/simulation/main.cpp index c064bc67..00797a88 100644 --- a/dram/src/simulation/main.cpp +++ b/dram/src/simulation/main.cpp @@ -32,6 +32,7 @@ int main(int argc, char **argv) int sc_main(int argc, char **argv) { + cout<<"hello"<