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all constraints implemented

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This commit is contained in:
robert
2014-03-30 12:52:12 +02:00
parent e13f2b0868
commit 75a5dca81e
26 changed files with 471 additions and 146 deletions
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41
dram/src/core/ControllerState.cpp
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@@ -6,6 +6,7 @@
*/
#include "ControllerState.h"
#include <algorithm>
namespace core {
@@ -27,7 +28,7 @@ const ScheduledCommand ControllerState::getLastCommand(Command command)
return max;
}
const ScheduledCommand ControllerState::getLastCommand(Bank bank)
const ScheduledCommand ControllerState::getLastScheduledCommand(Bank bank)
{
ScheduledCommand lastCommand;
for (std::map<Command, std::map<Bank, ScheduledCommand> >::iterator it =
@@ -42,23 +43,39 @@ const ScheduledCommand ControllerState::getLastCommand(Bank bank)
void ControllerState::change(const ScheduledCommand& scheduledCommand)
{
pendingBusCommands.insert(scheduledCommand.getStart());
bus.blockSlot(scheduledCommand.getStart());
lastCommandsOnBus[scheduledCommand.getCommand()][scheduledCommand.getBank()] = scheduledCommand;
lastCommandsOnBus[scheduledCommand.getCommand()][scheduledCommand.getBank()].invalidateTransaction();
switch (scheduledCommand.getCommand())
{
case Command::Read:
lastDataStrobeCommands.emplace_back(scheduledCommand);
break;
case Command::ReadA:
bankStates.closeRowBuffer(scheduledCommand.getBank());
lastDataStrobeCommands.emplace_back(scheduledCommand);
break;
case Command::Write:
lastDataStrobeCommands.emplace_back(scheduledCommand);
break;
case Command::WriteA:
bankStates.closeRowBuffer(scheduledCommand.getBank());
lastDataStrobeCommands.emplace_back(scheduledCommand);
break;
case Command::AutoRefresh:
break;
case Command::Activate:
bankStates.openRowInRowBuffer(scheduledCommand.getBank(), scheduledCommand.getRow());
nActivateWindow.put(scheduledCommand.getStart());
activates.blockSlots(scheduledCommand.getStart() - config->Timings.tRRD,
scheduledCommand.getStart() + config->Timings.tRRD, true);
break;
case Command::Precharge:
bankStates.closeRowBuffer(scheduledCommand.getBank());
break;
case Command::PrechargeAll:
bankStates.closeAllRowBuffers();
bankStates.closeAllRowBuffers();
break;
default:
break;
@@ -66,5 +83,21 @@ void ControllerState::change(const ScheduledCommand& scheduledCommand)
}
} /* namespace controller */
void ControllerState::cleanUp(sc_time time)
{
bus.cleanUpSlots(time);
activates.cleanUpSlots(time);
//remove_if(lastDataStrobeCommands.begin(),lastDataStrobeCommands.end(), [&](ScheduledCommand command){return command.getEnd() < time;});
vector<ScheduledCommand> tmp;
for(ScheduledCommand& command: lastDataStrobeCommands)
{
if(command.getEnd() >= time )
{
tmp.emplace_back(command);
}
}
lastDataStrobeCommands = tmp;
}
} /* namespace controller */