diff --git a/DRAMSys/gem5/README.md b/DRAMSys/gem5/README.md
index 31cff150..4d2e1c1a 100644
--- a/DRAMSys/gem5/README.md
+++ b/DRAMSys/gem5/README.md
@@ -153,7 +153,7 @@ build/ARM/gem5.opt configs/example/se.py \
 
 An overview of the architcture being simulated is presented below:
 
-![arch](DRAMSys/docs/images/gem5_se_mode_arch.png)
+![arch](images/gem5_se_mode_arch.png)
 
 **Note**: this is a gem5 generated file, therefore DRAMSys is omitted. DRAMSys is
 direct connected as external tlm slave.
@@ -405,7 +405,7 @@ This is an example for running an elastic trace:
 
 An overview of the architcture being simulated is presented below:
 
-![arch](DRAMSys/docs/images/singleElasticTraceReplay.png)
+![arch](images/singleElasticTraceReplay.png)
 
 Note that the address offset is usually zero for elastic traces.
 
@@ -423,7 +423,7 @@ If two elastic traces should be used run the simulation with the following examp
 
 An overview of the architcture being simulated is presented below:
 
-![arch](DRAMSys/docs/images/dualElasticTraceReplay.png)
+![arch](images/dualElasticTraceReplay.png)
 
 For more spophisticated setups, even with l2 caches the proper ini file should be created.
 If you need help please contact Matthias Jung.
@@ -670,15 +670,11 @@ Note: the port may vary, gem5 prints it during initialization. Example:
 system.terminal: Listening for connections on port 3456
 ```
 
-[1] System Simulation with gem5 and SystemC: The Keystone for Full
-Interoperability C. Menard, M. Jung, J. Castrillon, N. Wehn. IEEE International
-Conference on Embedded Computer Systems Architectures Modeling and Simulation
-(SAMOS), July, 2017, Samos Island, Greece.
+[1] System Simulation with gem5 and SystemC: The Keystone for Full Interoperability  
+C. Menard, M. Jung, J. Castrillon, N. Wehn. IEEE International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS), July, 2017, Samos Island, Greece.
 
-[2] Exploring System Performance using Elastic Traces: Fast, Accurate and
-Portable Radhika Jagtap, Stephan Diestelhorst, Andreas Hansson, Matthias Jung
-and Norbert Wehn, IEEE International Conference on Embedded Computer Systems
-Architectures Modeling and Simulation (SAMOS), 2016, Samos Island, Greece.
+[2] Exploring System Performance using Elastic Traces: Fast, Accurate and Portable  
+R. Jagtap, S. Diestelhorst, A. Hansson, M. Jung, N. Wehn, IEEE International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS), 2016, Samos Island, Greece.
 
 [gem5.TnT]: https://github.com/tukl-msd/gem5.TnT
 [gem5ilva.sh]: DRAMSys/library/resources/scripts/DRAMSylva/gem5ilva.sh
diff --git a/README.md b/README.md
index 178c8365..40e87557 100644
--- a/README.md
+++ b/README.md
@@ -482,21 +482,20 @@ $ ./DRAMSys ../../DRAMSys/library/resources/simulations/wideio-thermal.json
 
 ## References
 
-[1] TLM Modelling of 3D Stacked Wide I/O DRAM Subsystems, A Virtual Platform for Memory Controller Design Space Exploration
+[1] TLM Modelling of 3D Stacked Wide I/O DRAM Subsystems, A Virtual Platform for Memory Controller Design Space Exploration  
 M. Jung, C. Weis, N. Wehn, K. Chandrasekar. International Conference on High-Performance and Embedded Architectures and Compilers 2013 (HiPEAC), Workshop on: Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO), January, 2013, Berlin.
 
-[2] DRAMSys: A flexible DRAM Subsystem Design Space Exploration Framework
+[2] DRAMSys: A flexible DRAM Subsystem Design Space Exploration Framework  
 M. Jung, C. Weis, N. Wehn. IPSJ Transactions on System LSI Design Methodology (T-SLDM), October, 2015.
 
-[3] DRAMSys4.0: A Fast and Cycle-Accurate SystemC/TLM-Based DRAM Simulator
+[3] DRAMSys4.0: A Fast and Cycle-Accurate SystemC/TLM-Based DRAM Simulator  
 L. Steiner, M. Jung, F. S. Prado, K. Bykov, N. Wehn. International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), July, 2020, Samos Island, Greece.
 
-[4] DRAMPower: Open-source DRAM Power & Energy Estimation Tool
-K. Chandrasekar, C. Weis, Y. Li, S. Goossens, M. Jung, O. Naji, B. Akesson, N. Wehn, K. Goossens
-URL: http://www.drampower.info
+[4] DRAMPower: Open-source DRAM Power & Energy Estimation Tool  
+K. Chandrasekar, C. Weis, Y. Li, S. Goossens, M. Jung, O. Naji, B. Akesson, N. Wehn, K. Goossens. URL: http://www.drampower.info
 
-[5] Optimized Active and Power-Down Mode Refresh Control in 3D-DRAMs
+[5] Optimized Active and Power-Down Mode Refresh Control in 3D-DRAMs  
 M. Jung, M. Sadri, C. Weis, N. Wehn, L. Benini. VLSI-SoC, October, 2014, Playa del Carmen, Mexico.
 
-[6] Retention Time Measurements and Modelling of Bit Error Rates of WIDE-I/O DRAM in MPSoCs
-C. Weis, M. Jung, P. Ehses, C. Santos, P. Vivet, S. Goossens, M. Koedam, N. Wehn. IEEE Conference Design, Automation and Test in Europe (DATE), March, 2015, Grenoble, France
+[6] Retention Time Measurements and Modelling of Bit Error Rates of WIDE-I/O DRAM in MPSoCs  
+C. Weis, M. Jung, P. Ehses, C. Santos, P. Vivet, S. Goossens, M. Koedam, N. Wehn. IEEE Conference Design, Automation and Test in Europe (DATE), March, 2015, Grenoble, France.