diff --git a/DRAMSys/library/resources/configs/amconfigs/congen_extended.json b/DRAMSys/library/resources/configs/amconfigs/congen_extended.json
index 80e3450f..04f585b7 100644
--- a/DRAMSys/library/resources/configs/amconfigs/congen_extended.json
+++ b/DRAMSys/library/resources/configs/amconfigs/congen_extended.json
@@ -1,5 +1,5 @@
 {
-	"CONGEN": [{
+	"CONGEN": {
 			"XOR":[
 				{
 					"FIRST":13,
@@ -46,5 +46,4 @@
 			],
 			"ID": 0
 		}
-	]
 }
diff --git a/DRAMSys/library/resources/configs/amconfigs/congen_extended_solution.json b/DRAMSys/library/resources/configs/amconfigs/congen_extended_solution.json
new file mode 100644
index 00000000..a0e8c181
--- /dev/null
+++ b/DRAMSys/library/resources/configs/amconfigs/congen_extended_solution.json
@@ -0,0 +1,98 @@
+{
+	"CONGEN": 
+		{"SOLUTION":[{
+			"XOR":[
+				{
+					"FIRST":13,
+					"SECOND":16
+				}
+			],
+			"BYTE_BIT": [
+				0,
+				1,
+				2
+			],
+			"COLUMN_BIT": [
+				3,
+				4,
+				5,
+				6,
+				7,
+				8,
+				9,
+				10,
+				11,
+				12
+			],
+			"BANK_BIT": [
+				13,
+				14,
+				15
+			],
+			"ROW_BIT": [
+				16,
+				17,
+				18,
+				19,
+				20,
+				21,
+				22,
+				23,
+				24,
+				25,
+				26,
+				27,
+				28,
+				29
+			],
+			"ID": 0
+		},
+		{
+			"XOR":[
+				{
+					"FIRST":13,
+					"SECOND":16
+				}
+			],
+			"BYTE_BIT": [
+				0,
+				1,
+				2
+			],
+			"COLUMN_BIT": [
+				3,
+				4,
+				5,
+				6,
+				7,
+				8,
+				9,
+				10,
+				11,
+				12
+			],
+			"BANK_BIT": [
+				13,
+				14,
+				15
+			],
+			"ROW_BIT": [
+				16,
+				17,
+				18,
+				19,
+				20,
+				21,
+				22,
+				23,
+				24,
+				25,
+				26,
+				27,
+				28,
+				29
+			],
+			"ID": 1
+		}]
+	}	
+}
diff --git a/DRAMSys/library/resources/simulations/ddr3-example.xml b/DRAMSys/library/resources/simulations/ddr3-example.xml
index afdc7781..3e06bb4f 100644
--- a/DRAMSys/library/resources/simulations/ddr3-example.xml
+++ b/DRAMSys/library/resources/simulations/ddr3-example.xml
@@ -8,7 +8,7 @@
     <!-- Memory Device Specification: Which Device is on the DDR3 DIMM -->
     <memspec src="MICRON_1Gb_DDR3-1600_8bit_G.json"></memspec>
     <!-- Addressmapping Configuration of the Memory Controller -->
-    <addressmapping src="congen_extended.json"></addressmapping>
+    <addressmapping src="congen_extended_solution.json"></addressmapping>
     <!-- Memory Controller Configuration: -->
     <mcconfig src="fifoStrict.json"/>
     <!--
diff --git a/DRAMSys/library/src/common/AddressDecoder.cpp b/DRAMSys/library/src/common/AddressDecoder.cpp
index 69a0aa3f..5b67f96f 100644
--- a/DRAMSys/library/src/common/AddressDecoder.cpp
+++ b/DRAMSys/library/src/common/AddressDecoder.cpp
@@ -25,11 +25,8 @@ unsigned int AddressDecoder::getUnsignedAttrFromJson(nlohmann::json obj, std::st
                      "Attribute " + strName + " is empty or not found");
          return (unsigned)(-1);
     }
-
 }
 
-
-
  std::vector<unsigned> AddressDecoder::getAttrToVectorFromJson(nlohmann::json obj,
                                                      std::string strName)
 {
@@ -52,34 +49,38 @@ unsigned int AddressDecoder::getUnsignedAttrFromJson(nlohmann::json obj, std::st
 AddressDecoder::AddressDecoder(std::string pathToAddressMapping)
 {
     json AddrFile = json::parse(std::ifstream(pathToAddressMapping));
-
+    json j;
     if (AddrFile["CONGEN"].empty())
         reportFatal("AddressDecorder",
                     "Root node name differs from \"CONGEN\". File format not supported.");
 
     // Load address mapping
-     for ( auto it: AddrFile["CONGEN"].items()){
-         json j= it.value();
-         if (getUnsignedAttrFromJson(j, "ID") == 0){
-             ID=true;
-             for ( auto xorItem: j["XOR"].items() ){
-                 auto value = xorItem.value();
-                 if (!value.empty())
-                     vXor.push_back(std::pair<unsigned, unsigned>(getUnsignedAttrFromJson(value, "FIRST"),
-                                                                  getUnsignedAttrFromJson(value, "SECOND")));
-             }
-             vChannelBits = getAttrToVectorFromJson(j,"CHANNEL_BIT");
-             vRankBits = getAttrToVectorFromJson(j,"RANK_BIT");
-             vBankGroupBits = getAttrToVectorFromJson(j,"BANKGROUP_BIT");
-             vBankBits = getAttrToVectorFromJson(j,"BANK_BIT");
-             vRowBits = getAttrToVectorFromJson(j,"ROW_BIT");
-             vColumnBits = getAttrToVectorFromJson(j,"COLUMN_BIT");
-             vByteBits = getAttrToVectorFromJson(j,"BYTE_BIT");
-         }
-     }
+    if (!AddrFile["CONGEN"]["SOLUTION"].empty()) {
+         for ( auto it: AddrFile["CONGEN"]["SOLUTION"].items()){
+             if (getUnsignedAttrFromJson(it.value(), "ID") == 0){
+                ID=true;
+                j = it.value();
+            }
+        }
+        if (ID != true)
+            SC_REPORT_FATAL("AddressDecoder", "No mapping with ID 0 was found.");
+   }
+   else
+        j = AddrFile["CONGEN"];
 
-     if (ID != true)
-         SC_REPORT_FATAL("AddressDecoder", "No mapping with ID 0 was found.");
+   for ( auto xorItem: j["XOR"].items() ){
+        auto value = xorItem.value();
+        if (!value.empty())
+            vXor.push_back(std::pair<unsigned, unsigned>(getUnsignedAttrFromJson(value, "FIRST"),
+                                                         getUnsignedAttrFromJson(value, "SECOND")));
+   }
+   vChannelBits = getAttrToVectorFromJson(j,"CHANNEL_BIT");
+   vRankBits = getAttrToVectorFromJson(j,"RANK_BIT");
+   vBankGroupBits = getAttrToVectorFromJson(j,"BANKGROUP_BIT");
+   vBankBits = getAttrToVectorFromJson(j,"BANK_BIT");
+   vRowBits = getAttrToVectorFromJson(j,"ROW_BIT");
+   vColumnBits = getAttrToVectorFromJson(j,"COLUMN_BIT");
+   vByteBits = getAttrToVectorFromJson(j,"BYTE_BIT");
 
     unsigned channels = pow(2.0, vChannelBits.size());
     unsigned ranks = pow(2.0, vRankBits.size());